diff options
Diffstat (limited to 'src/SubcircuitLibrary/diac')
| -rw-r--r-- | src/SubcircuitLibrary/diac/analysis | 1 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac-cache.lib | 67 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.bak | 138 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.cir | 13 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.cir.ckt | 9 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.cir.out | 21 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.cir.out~ | 24 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.pro | 45 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.sch | 148 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.sub | 15 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac.sub~ | 18 | ||||
| -rw-r--r-- | src/SubcircuitLibrary/diac/diac_Previous_Values.xml | 1 |
12 files changed, 500 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/diac/analysis b/src/SubcircuitLibrary/diac/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/src/SubcircuitLibrary/diac/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/diac-cache.lib b/src/SubcircuitLibrary/diac/diac-cache.lib new file mode 100644 index 00000000..b15fdeec --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac-cache.lib @@ -0,0 +1,67 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# aswitch +# +DEF aswitch U 0 40 Y Y 1 F N +F0 "U" 450 300 60 H V C CNN +F1 "aswitch" 450 200 60 H V C CNN +F2 "" 450 100 60 H V C CNN +F3 "" 450 100 60 H V C CNN +DRAW +S 200 250 650 100 0 1 0 N +X ~ 2 0 150 200 R 50 50 1 1 O +X ~ 3 850 150 200 L 50 50 1 1 O +X ~ 1_IN 450 -100 200 U 50 20 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/src/SubcircuitLibrary/diac/diac.bak b/src/SubcircuitLibrary/diac/diac.bak new file mode 100644 index 00000000..16009984 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.bak @@ -0,0 +1,138 @@ +EESchema Schematic File Version 2 date 09/22/14 16:36:31
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:analogSpice
+LIBS:analogXSpice
+LIBS:convergenceAidSpice
+LIBS:converterSpice
+LIBS:digitalSpice
+LIBS:digitalXSpice
+LIBS:linearSpice
+LIBS:measurementSpice
+LIBS:portSpice
+LIBS:sourcesSpice
+LIBS:diac-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11700 8267
+encoding utf-8
+Sheet 1 1
+Title ""
+Date "22 sep 2014"
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+Wire Wire Line
+ 4150 2750 4150 3450
+Connection ~ 4400 3750
+Wire Wire Line
+ 4900 4250 4900 4450
+Wire Wire Line
+ 4900 4450 4400 4450
+Wire Wire Line
+ 4400 4450 4400 3450
+Wire Wire Line
+ 5200 3400 5200 4050
+Connection ~ 4600 3400
+Wire Wire Line
+ 4600 4050 4600 2750
+Wire Wire Line
+ 4600 2750 4150 2750
+Wire Wire Line
+ 4150 3250 4150 3600
+Wire Wire Line
+ 4400 3450 4150 3450
+Connection ~ 4150 3450
+Wire Wire Line
+ 4400 3750 4900 3750
+Wire Wire Line
+ 4900 3750 4900 3600
+Wire Wire Line
+ 4150 4100 4150 4300
+$Comp
+L PWR_FLAG #FLG01
+U 1 1 5417D647
+P 4150 4300
+F 0 "#FLG01" H 4150 4570 30 0001 C CNN
+F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN
+ 1 4150 4300
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U3
+U 2 1 5417D62C
+P 5450 3400
+F 0 "U3" H 5450 3350 30 0000 C CNN
+F 1 "PORT" H 5450 3400 30 0000 C CNN
+ 2 5450 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U3
+U 1 1 5417D624
+P 4150 2500
+F 0 "U3" H 4150 2450 30 0000 C CNN
+F 1 "PORT" H 4150 2500 30 0000 C CNN
+ 1 4150 2500
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 5417D5DC
+P 4150 4300
+F 0 "#PWR02" H 4150 4300 30 0001 C CNN
+F 1 "GND" H 4150 4230 30 0001 C CNN
+ 1 4150 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L ANALOGSWITCH U2
+U 1 1 5417D537
+P 4900 4050
+F 0 "U2" H 4700 4100 30 0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 4050 30 0000 C CNN
+ 1 4900 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L ANALOGSWITCH U1
+U 1 1 5417D530
+P 4900 3400
+F 0 "U1" H 4700 3450 30 0000 C CNN
+F 1 "ANALOGSWITCH" H 4900 3400 30 0000 C CNN
+ 1 4900 3400
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/diac/diac.cir b/src/SubcircuitLibrary/diac/diac.cir new file mode 100644 index 00000000..91629b91 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir @@ -0,0 +1,13 @@ +* /opt/eSim/src/SubcircuitLibrary/diac/diac.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Tue Dec 8 15:35:49 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 1 2 PORT +U1 1 1 2 aswitch +U2 1 1 2 aswitch + +.end diff --git a/src/SubcircuitLibrary/diac/diac.cir.ckt b/src/SubcircuitLibrary/diac/diac.cir.ckt new file mode 100644 index 00000000..e89f9cfb --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.ckt @@ -0,0 +1,9 @@ +* eeschema netlist version 1.1 (spice format) creation date: 09/22/14 16:36:23
+
+u3 1 2 port
+* Analog Switch analogswitch
+* Analog Switch analogswitch
+a1 1 (1 2) u2
+.model u2 aswitch(cntl_on=-25 cntl_off=-0.1 r_on=0.0125 r_off=1000000)
+a2 1 (1 2) u1
+.model u1 aswitch(cntl_on=25 cntl_off=0.1 r_on=0.0125 r_off=1000000)
diff --git a/src/SubcircuitLibrary/diac/diac.cir.out b/src/SubcircuitLibrary/diac/diac.cir.out new file mode 100644 index 00000000..a1e31f14 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.out @@ -0,0 +1,21 @@ +* /opt/esim/src/subcircuitlibrary/diac/diac.cir + +* u3 1 2 port +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/diac/diac.cir.out~ b/src/SubcircuitLibrary/diac/diac.cir.out~ new file mode 100644 index 00000000..89cc8142 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.cir.out~ @@ -0,0 +1,24 @@ +* /opt/esim/src/subcircuitlibrary/diac/diac.cir + +* u3 1 2 port +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 [1 2 ] u1 +a2 1 [1 2 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/src/SubcircuitLibrary/diac/diac.pro b/src/SubcircuitLibrary/diac/diac.pro new file mode 100644 index 00000000..c8563047 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.pro @@ -0,0 +1,45 @@ +update=Tue Dec 8 14:06:36 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=analogSpice +LibName32=eSim_Analog +LibName33=eSim_Devices +LibName34=eSim_Digital +LibName35=eSim_Hybrid +LibName36=eSim_Miscellaneous +LibName37=eSim_Sources +LibName38=eSim_Subckt +LibName39=eSim_User diff --git a/src/SubcircuitLibrary/diac/diac.sch b/src/SubcircuitLibrary/diac/diac.sch new file mode 100644 index 00000000..163665e7 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sch @@ -0,0 +1,148 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:analogSpice +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "22 sep 2014" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 4150 2750 4150 4300 +Connection ~ 4400 3750 +Wire Wire Line + 4400 4450 5050 4450 +Wire Wire Line + 4400 4450 4400 3450 +Wire Wire Line + 5500 3350 5500 4050 +Connection ~ 4600 3400 +Wire Wire Line + 4600 4050 4600 2750 +Wire Wire Line + 4600 2750 4150 2750 +Wire Wire Line + 4400 3450 4150 3450 +Connection ~ 4150 3450 +Wire Wire Line + 4400 3750 5050 3750 +$Comp +L PWR_FLAG #FLG01 +U 1 1 5417D647 +P 4150 4300 +F 0 "#FLG01" H 4150 4570 30 0001 C CNN +F 1 "PWR_FLAG" H 4150 4530 30 0000 C CNN +F 2 "" H 4150 4300 60 0001 C CNN +F 3 "" H 4150 4300 60 0001 C CNN + 1 4150 4300 + 0 1 1 0 +$EndComp +$Comp +L PORT U3 +U 2 1 5417D62C +P 5750 3350 +F 0 "U3" H 5750 3300 30 0000 C CNN +F 1 "PORT" H 5750 3350 30 0000 C CNN +F 2 "" H 5750 3350 60 0001 C CNN +F 3 "" H 5750 3350 60 0001 C CNN + 2 5750 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U3 +U 1 1 5417D624 +P 4150 2500 +F 0 "U3" H 4150 2450 30 0000 C CNN +F 1 "PORT" H 4150 2500 30 0000 C CNN +F 2 "" H 4150 2500 60 0001 C CNN +F 3 "" H 4150 2500 60 0001 C CNN + 1 4150 2500 + 0 1 1 0 +$EndComp +$Comp +L GND #PWR02 +U 1 1 5417D5DC +P 4150 4300 +F 0 "#PWR02" H 4150 4300 30 0001 C CNN +F 1 "GND" H 4150 4230 30 0001 C CNN +F 2 "" H 4150 4300 60 0001 C CNN +F 3 "" H 4150 4300 60 0001 C CNN + 1 4150 4300 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U1 +U 1 1 56669812 +P 4600 3550 +F 0 "U1" H 5050 3850 60 0000 C CNN +F 1 "aswitch" H 5050 3750 60 0000 C CNN +F 2 "" H 5050 3650 60 0000 C CNN +F 3 "" H 5050 3650 60 0000 C CNN + 1 4600 3550 + 1 0 0 -1 +$EndComp +$Comp +L aswitch U2 +U 1 1 5666987C +P 4600 4200 +F 0 "U2" H 5050 4500 60 0000 C CNN +F 1 "aswitch" H 5050 4400 60 0000 C CNN +F 2 "" H 5050 4300 60 0000 C CNN +F 3 "" H 5050 4300 60 0000 C CNN + 1 4600 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 4450 5050 4300 +Wire Wire Line + 5050 3750 5050 3650 +Wire Wire Line + 5500 4050 5450 4050 +Wire Wire Line + 5500 3400 5450 3400 +Connection ~ 5500 3400 +$EndSCHEMATC diff --git a/src/SubcircuitLibrary/diac/diac.sub b/src/SubcircuitLibrary/diac/diac.sub new file mode 100644 index 00000000..7f28ecc2 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sub @@ -0,0 +1,15 @@ +* Subcircuit diac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 (1 2) u1 +a2 1 (1 2) u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) + +* Control Statements + +.ends diac diff --git a/src/SubcircuitLibrary/diac/diac.sub~ b/src/SubcircuitLibrary/diac/diac.sub~ new file mode 100644 index 00000000..43c2d279 --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac.sub~ @@ -0,0 +1,18 @@ +* Subcircuit diac +.subckt diac 1 2 +* /opt/esim/src/subcircuitlibrary/diac/diac.cir +* u1 1 1 2 aswitch +* u2 1 1 2 aswitch +a1 1 [1 2 ] u1 +a2 1 [1 2 ] u2 +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=25 r_on=0.0125 r_off=1000000 ) +* Schematic Name: aswitch, NgSpice Name: aswitch +.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-25 r_on=0.0125 r_off=1000000 ) +* Control Statements + +.ends diac
\ No newline at end of file diff --git a/src/SubcircuitLibrary/diac/diac_Previous_Values.xml b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml new file mode 100644 index 00000000..96df431c --- /dev/null +++ b/src/SubcircuitLibrary/diac/diac_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">aswitch<field1 name="Enter Log (default=TRUE)" /><field2 name="Enter Control OFF value (default=0.0)">0.1</field2><field3 name="Enter OFF Resistance (default=1.0e12)">1000000</field3><field4 name="Enter ON Resistance (default=1.0)">0.0125</field4><field5 name="Enter Control ON value(default=1.0)">25</field5></u1><u2 name="type">aswitch<field6 name="Enter Log (default=TRUE)" /><field7 name="Enter Control OFF value (default=0.0)">-0.1</field7><field8 name="Enter OFF Resistance (default=1.0e12)">1000000</field8><field9 name="Enter ON Resistance (default=1.0)">0.0125</field9><field10 name="Enter Control ON value(default=1.0)">-25</field10></u2></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |