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-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR-cache.lib126
-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR.cir28
-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR.cir.out48
-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR.pro90
-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR.sch300
-rw-r--r--src/SubcircuitLibrary/4_OR/4_OR.sub34
6 files changed, 313 insertions, 313 deletions
diff --git a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
index a3c1c972..155f5e60 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
+++ b/src/SubcircuitLibrary/4_OR/4_OR-cache.lib
@@ -1,63 +1,63 @@
-EESchema-LIBRARY Version 2.3
-#encoding utf-8
-#
-# PORT
-#
-DEF PORT U 0 40 Y Y 26 F N
-F0 "U" 50 100 30 H V C CNN
-F1 "PORT" 0 0 30 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
-A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
-S -100 50 100 -50 0 1 0 N
-X ~ 1 250 0 100 L 30 30 1 1 B
-X ~ 2 250 0 100 L 30 30 2 1 B
-X ~ 3 250 0 100 L 30 30 3 1 B
-X ~ 4 250 0 100 L 30 30 4 1 B
-X ~ 5 250 0 100 L 30 30 5 1 B
-X ~ 6 250 0 100 L 30 30 6 1 B
-X ~ 7 250 0 100 L 30 30 7 1 B
-X ~ 8 250 0 100 L 30 30 8 1 B
-X ~ 9 250 0 100 L 30 30 9 1 B
-X ~ 10 250 0 100 L 30 30 10 1 B
-X ~ 11 250 0 100 L 30 30 11 1 B
-X ~ 12 250 0 100 L 30 30 12 1 B
-X ~ 13 250 0 100 L 30 30 13 1 B
-X ~ 14 250 0 100 L 30 30 14 1 B
-X ~ 15 250 0 100 L 30 30 15 1 B
-X ~ 16 250 0 100 L 30 30 16 1 B
-X ~ 17 250 0 100 L 30 30 17 1 B
-X ~ 18 250 0 100 L 30 30 18 1 B
-X ~ 19 250 0 100 L 30 30 19 1 B
-X ~ 20 250 0 100 L 30 30 20 1 B
-X ~ 21 250 0 100 L 30 30 21 1 B
-X ~ 22 250 0 100 L 30 30 22 1 B
-X ~ 23 250 0 100 L 30 30 23 1 B
-X ~ 24 250 0 100 L 30 30 24 1 B
-X ~ 25 250 0 100 L 30 30 25 1 B
-X ~ 26 250 0 100 L 30 30 26 1 B
-ENDDRAW
-ENDDEF
-#
-# d_or
-#
-DEF d_or U 0 40 Y Y 1 F N
-F0 "U" 0 0 60 H V C CNN
-F1 "d_or" 0 100 60 H V C CNN
-F2 "" 0 0 60 H V C CNN
-F3 "" 0 0 60 H V C CNN
-DRAW
-A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
-A -25 -124 325 574 323 0 1 0 N 150 150 250 50
-A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
-P 2 0 1 0 -250 -50 150 -50 N
-P 2 0 1 0 -250 150 150 150 N
-X IN1 1 -450 100 215 R 50 50 1 1 I
-X IN2 2 -450 0 215 R 50 50 1 1 I
-X OUT 3 450 50 200 L 50 50 1 1 O
-ENDDRAW
-ENDDEF
-#
-#End Library
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir b/src/SubcircuitLibrary/4_OR/4_OR.cir
index 7adbf177..b338b7b5 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir
+++ b/src/SubcircuitLibrary/4_OR/4_OR.cir
@@ -1,14 +1,14 @@
-* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
-U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
-U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
-U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
-
-.end
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.cir.out b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
index 4388b975..adb6b01b 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.cir.out
+++ b/src/SubcircuitLibrary/4_OR/4_OR.cir.out
@@ -1,24 +1,24 @@
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-.tran 0e-00 0e-00 0e-00
-
-* Control Statements
-.control
-run
-print allv > plot_data_v.txt
-print alli > plot_data_i.txt
-.endc
-.end
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.pro b/src/SubcircuitLibrary/4_OR/4_OR.pro
index 1e19b3a7..9daf26bc 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.pro
+++ b/src/SubcircuitLibrary/4_OR/4_OR.pro
@@ -1,45 +1,45 @@
-update=06/01/19 12:36:09
-version=1
-last_client=eeschema
-[general]
-version=1
-RootSch=
-BoardNm=
-[pcbnew]
-version=1
-LastNetListRead=
-UseCmpFile=1
-PadDrill=0.600000000000
-PadDrillOvalY=0.600000000000
-PadSizeH=1.500000000000
-PadSizeV=1.500000000000
-PcbTextSizeV=1.500000000000
-PcbTextSizeH=1.500000000000
-PcbTextThickness=0.300000000000
-ModuleTextSizeV=1.000000000000
-ModuleTextSizeH=1.000000000000
-ModuleTextSizeThickness=0.150000000000
-SolderMaskClearance=0.000000000000
-SolderMaskMinWidth=0.000000000000
-DrawSegmentWidth=0.200000000000
-BoardOutlineThickness=0.100000000000
-ModuleOutlineThickness=0.150000000000
-[cvpcb]
-version=1
-NetIExt=net
-[eeschema]
-version=1
-LibDir=../../../kicadSchematicLibrary
-[eeschema/libraries]
-LibName1=power
-LibName2=eSim_Analog
-LibName3=eSim_Devices
-LibName4=eSim_Digital
-LibName5=eSim_Hybrid
-LibName6=eSim_Miscellaneous
-LibName7=eSim_Plot
-LibName8=eSim_Power
-LibName9=eSim_PSpice
-LibName10=eSim_Sources
-LibName11=eSim_Subckt
-LibName12=eSim_User
+update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_PSpice
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
+LibName12=eSim_User
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sch b/src/SubcircuitLibrary/4_OR/4_OR.sch
index 2f28896c..11896865 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.sch
+++ b/src/SubcircuitLibrary/4_OR/4_OR.sch
@@ -1,150 +1,150 @@
-EESchema Schematic File Version 2
-LIBS:power
-LIBS:eSim_Analog
-LIBS:eSim_Devices
-LIBS:eSim_Digital
-LIBS:eSim_Hybrid
-LIBS:eSim_Miscellaneous
-LIBS:eSim_Plot
-LIBS:eSim_Power
-LIBS:eSim_PSpice
-LIBS:eSim_Sources
-LIBS:eSim_Subckt
-LIBS:eSim_User
-EELAYER 25 0
-EELAYER END
-$Descr A4 11693 8268
-encoding utf-8
-Sheet 1 1
-Title ""
-Date ""
-Rev ""
-Comp ""
-Comment1 ""
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-Comment4 ""
-$EndDescr
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-F 1 "d_or" H 4300 3050 60 0000 C CNN
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- 1 0 0 -1
-$EndComp
-$Comp
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-F 2 "" H 5250 3150 60 0000 C CNN
-F 3 "" H 5250 3150 60 0000 C CNN
- 1 5250 3150
- 1 0 0 -1
-$EndComp
-Wire Wire Line
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- 5700 3100 6200 3100
-$Comp
-L PORT U1
-U 1 1 5C9D01F4
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-F 2 "" H 3100 2850 60 0000 C CNN
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-F 2 "" H 3100 3000 60 0000 C CNN
-F 3 "" H 3100 3000 60 0000 C CNN
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- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 3 1 5C9D0271
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-F 2 "" H 3100 3250 60 0000 C CNN
-F 3 "" H 3100 3250 60 0000 C CNN
- 3 3100 3250
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 4 1 5C9D0299
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-F 0 "U1" H 3150 3500 30 0000 C CNN
-F 1 "PORT" H 3100 3400 30 0000 C CNN
-F 2 "" H 3100 3400 60 0000 C CNN
-F 3 "" H 3100 3400 60 0000 C CNN
- 4 3100 3400
- 1 0 0 -1
-$EndComp
-$Comp
-L PORT U1
-U 5 1 5C9D02C2
-P 6450 3100
-F 0 "U1" H 6500 3200 30 0000 C CNN
-F 1 "PORT" H 6450 3100 30 0000 C CNN
-F 2 "" H 6450 3100 60 0000 C CNN
-F 3 "" H 6450 3100 60 0000 C CNN
- 5 6450 3100
- -1 0 0 1
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-Text Notes 3450 2850 0 60 ~ 12
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-in3
-Text Notes 3450 3400 0 60 ~ 12
-in4
-Text Notes 5800 3100 0 60 ~ 12
-out
-$EndSCHEMATC
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
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+Comment4 ""
+$EndDescr
+$Comp
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+U 1 1 5C9D00E1
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+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
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+U 1 1 5C9D011F
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+ 1 4300 3350
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+$EndComp
+$Comp
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+U 1 1 5C9D0141
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+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
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+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
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+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
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+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/4_OR/4_OR.sub b/src/SubcircuitLibrary/4_OR/4_OR.sub
index 53fc8b33..d1fd3a24 100644
--- a/src/SubcircuitLibrary/4_OR/4_OR.sub
+++ b/src/SubcircuitLibrary/4_OR/4_OR.sub
@@ -1,18 +1,18 @@
-* Subcircuit 4_OR
-.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
-* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
-* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
-* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
-* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
-a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
-a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
-a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Schematic Name: d_or, NgSpice Name: d_or
-.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
-* Control Statements
-
+* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
.ends 4_OR \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-20 07:33:39 +0000