8 files changed, 526 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/4002/4002-cache.lib b/src/SubcircuitLibrary/4002/4002-cache.lib
new file mode 100644
index 00000000..677411a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002-cache.lib
@@ -0,0 +1,82 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/4002/4002.cir b/src/SubcircuitLibrary/4002/4002.cir
new file mode 100644
index 00000000..5d5c1ed7
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.cir
@@ -0,0 +1,17 @@
+* C:\Users\Bhargav\eSim\src\SubcircuitLibrary\4002\4002.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 09:36:54
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2  Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad3_ d_or		
+U3  Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or		
+U6  Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad1_ d_nor		
+U1  Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ ? ? ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT		
+U4  Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U4-Pad3_ d_or		
+U5  Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U5-Pad3_ d_or		
+U7  Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U1-Pad13_ d_nor		
+
+.end
diff --git a/src/SubcircuitLibrary/4002/4002.cir.out b/src/SubcircuitLibrary/4002/4002.cir.out
new file mode 100644
index 00000000..e9cc6862
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.cir.out
@@ -0,0 +1,36 @@
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/4002/4002.pro b/src/SubcircuitLibrary/4002/4002.pro
new file mode 100644
index 00000000..225ef82a
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.pro
@@ -0,0 +1,44 @@
+update=05/31/19 09:35:41
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Analog
+LibName2=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Devices
+LibName3=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Digital
+LibName4=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Hybrid
+LibName5=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Miscellaneous
+LibName6=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Plot
+LibName7=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Power
+LibName8=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Sources
+LibName9=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_Subckt
+LibName10=C:/Users/Bhargav/eSim/kicadSchematicLibrary/eSim_User
+LibName11=power
diff --git a/src/SubcircuitLibrary/4002/4002.sch b/src/SubcircuitLibrary/4002/4002.sch
new file mode 100644
index 00000000..545f46fe
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.sch
@@ -0,0 +1,315 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5CEE059A
+P 4750 2900
+F 0 "U2" H 4750 2900 60  0000 C CNN
+F 1 "d_or" H 4750 3000 60  0000 C CNN
+F 2 "" H 4750 2900 60  0000 C CNN
+F 3 "" H 4750 2900 60  0000 C CNN
+	1    4750 2900
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5CEE0629
+P 4750 3450
+F 0 "U3" H 4750 3450 60  0000 C CNN
+F 1 "d_or" H 4750 3550 60  0000 C CNN
+F 2 "" H 4750 3450 60  0000 C CNN
+F 3 "" H 4750 3450 60  0000 C CNN
+	1    4750 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CEE0663
+P 6000 3100
+F 0 "U6" H 6000 3100 60  0000 C CNN
+F 1 "d_nor" H 6050 3200 60  0000 C CNN
+F 2 "" H 6000 3100 60  0000 C CNN
+F 3 "" H 6000 3100 60  0000 C CNN
+	1    6000 3100
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5200 2850 5400 2850
+Wire Wire Line
+	5400 2850 5400 3000
+Wire Wire Line
+	5400 3000 5550 3000
+Wire Wire Line
+	5200 3400 5400 3400
+Wire Wire Line
+	5400 3400 5400 3100
+Wire Wire Line
+	5400 3100 5550 3100
+Wire Wire Line
+	5650 5350 6050 5350
+Wire Wire Line
+	5650 5550 6050 5550
+Wire Wire Line
+	5650 5800 6050 5800
+Wire Wire Line
+	5650 6000 6050 6000
+NoConn ~ 5650 5350
+NoConn ~ 5650 5550
+NoConn ~ 5650 5800
+NoConn ~ 5650 6000
+$Comp
+L PORT U1
+U 2 1 5CEE1C41
+P 3850 2800
+F 0 "U1" H 3900 2900 30  0000 C CNN
+F 1 "PORT" H 3850 2800 30  0000 C CNN
+F 2 "" H 3850 2800 60  0000 C CNN
+F 3 "" H 3850 2800 60  0000 C CNN
+	2    3850 2800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CEE22EE
+P 3900 3050
+F 0 "U1" H 3950 3150 30  0000 C CNN
+F 1 "PORT" H 3900 3050 30  0000 C CNN
+F 2 "" H 3900 3050 60  0000 C CNN
+F 3 "" H 3900 3050 60  0000 C CNN
+	3    3900 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5CEE2322
+P 3900 3250
+F 0 "U1" H 3950 3350 30  0000 C CNN
+F 1 "PORT" H 3900 3250 30  0000 C CNN
+F 2 "" H 3900 3250 60  0000 C CNN
+F 3 "" H 3900 3250 60  0000 C CNN
+	5    3900 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CEE2351
+P 3900 3550
+F 0 "U1" H 3950 3650 30  0000 C CNN
+F 1 "PORT" H 3900 3550 30  0000 C CNN
+F 2 "" H 3900 3550 60  0000 C CNN
+F 3 "" H 3900 3550 60  0000 C CNN
+	4    3900 3550
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CEE2387
+P 6950 3050
+F 0 "U1" H 7000 3150 30  0000 C CNN
+F 1 "PORT" H 6950 3050 30  0000 C CNN
+F 2 "" H 6950 3050 60  0000 C CNN
+F 3 "" H 6950 3050 60  0000 C CNN
+	1    6950 3050
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4100 2800 4300 2800
+Wire Wire Line
+	4150 3050 4150 2900
+Wire Wire Line
+	4150 2900 4300 2900
+Wire Wire Line
+	4150 3250 4300 3250
+Wire Wire Line
+	4300 3250 4300 3350
+Wire Wire Line
+	4150 3550 4150 3450
+Wire Wire Line
+	4150 3450 4300 3450
+Wire Wire Line
+	6700 3050 6450 3050
+$Comp
+L d_or U4
+U 1 1 5CEE4ED7
+P 4900 4100
+F 0 "U4" H 4900 4100 60  0000 C CNN
+F 1 "d_or" H 4900 4200 60  0000 C CNN
+F 2 "" H 4900 4100 60  0000 C CNN
+F 3 "" H 4900 4100 60  0000 C CNN
+	1    4900 4100
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_or U5
+U 1 1 5CEE4EDD
+P 4900 4650
+F 0 "U5" H 4900 4650 60  0000 C CNN
+F 1 "d_or" H 4900 4750 60  0000 C CNN
+F 2 "" H 4900 4650 60  0000 C CNN
+F 3 "" H 4900 4650 60  0000 C CNN
+	1    4900 4650
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CEE4EE3
+P 6150 4300
+F 0 "U7" H 6150 4300 60  0000 C CNN
+F 1 "d_nor" H 6200 4400 60  0000 C CNN
+F 2 "" H 6150 4300 60  0000 C CNN
+F 3 "" H 6150 4300 60  0000 C CNN
+	1    6150 4300
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	5350 4050 5550 4050
+Wire Wire Line
+	5550 4050 5550 4200
+Wire Wire Line
+	5550 4200 5700 4200
+Wire Wire Line
+	5350 4600 5550 4600
+Wire Wire Line
+	5550 4600 5550 4300
+Wire Wire Line
+	5550 4300 5700 4300
+$Comp
+L PORT U1
+U 9 1 5CEE4EEF
+P 4000 4000
+F 0 "U1" H 4050 4100 30  0000 C CNN
+F 1 "PORT" H 4000 4000 30  0000 C CNN
+F 2 "" H 4000 4000 60  0000 C CNN
+F 3 "" H 4000 4000 60  0000 C CNN
+	9    4000 4000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CEE4EF5
+P 4050 4250
+F 0 "U1" H 4100 4350 30  0000 C CNN
+F 1 "PORT" H 4050 4250 30  0000 C CNN
+F 2 "" H 4050 4250 60  0000 C CNN
+F 3 "" H 4050 4250 60  0000 C CNN
+	10   4050 4250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CEE4EFB
+P 4050 4450
+F 0 "U1" H 4100 4550 30  0000 C CNN
+F 1 "PORT" H 4050 4450 30  0000 C CNN
+F 2 "" H 4050 4450 60  0000 C CNN
+F 3 "" H 4050 4450 60  0000 C CNN
+	11   4050 4450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CEE4F01
+P 4050 4750
+F 0 "U1" H 4100 4850 30  0000 C CNN
+F 1 "PORT" H 4050 4750 30  0000 C CNN
+F 2 "" H 4050 4750 60  0000 C CNN
+F 3 "" H 4050 4750 60  0000 C CNN
+	12   4050 4750
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CEE4F07
+P 7100 4250
+F 0 "U1" H 7150 4350 30  0000 C CNN
+F 1 "PORT" H 7100 4250 30  0000 C CNN
+F 2 "" H 7100 4250 60  0000 C CNN
+F 3 "" H 7100 4250 60  0000 C CNN
+	13   7100 4250
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	4250 4000 4450 4000
+Wire Wire Line
+	4300 4250 4300 4100
+Wire Wire Line
+	4300 4100 4450 4100
+Wire Wire Line
+	4300 4450 4450 4450
+Wire Wire Line
+	4450 4450 4450 4550
+Wire Wire Line
+	4300 4750 4300 4650
+Wire Wire Line
+	4300 4650 4450 4650
+Wire Wire Line
+	6850 4250 6600 4250
+$Comp
+L PORT U1
+U 6 1 5CEE51A5
+P 6300 5350
+F 0 "U1" H 6350 5450 30  0000 C CNN
+F 1 "PORT" H 6300 5350 30  0000 C CNN
+F 2 "" H 6300 5350 60  0000 C CNN
+F 3 "" H 6300 5350 60  0000 C CNN
+	6    6300 5350
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CEE522C
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+F 0 "U1" H 6350 5650 30  0000 C CNN
+F 1 "PORT" H 6300 5550 30  0000 C CNN
+F 2 "" H 6300 5550 60  0000 C CNN
+F 3 "" H 6300 5550 60  0000 C CNN
+	7    6300 5550
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 8 1 5CEE5276
+P 6300 5800
+F 0 "U1" H 6350 5900 30  0000 C CNN
+F 1 "PORT" H 6300 5800 30  0000 C CNN
+F 2 "" H 6300 5800 60  0000 C CNN
+F 3 "" H 6300 5800 60  0000 C CNN
+	8    6300 5800
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CEE52C5
+P 6300 6000
+F 0 "U1" H 6350 6100 30  0000 C CNN
+F 1 "PORT" H 6300 6000 30  0000 C CNN
+F 2 "" H 6300 6000 60  0000 C CNN
+F 3 "" H 6300 6000 60  0000 C CNN
+	14   6300 6000
+	-1   0    0    1   
+$EndComp
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diff --git a/src/SubcircuitLibrary/4002/4002.sub b/src/SubcircuitLibrary/4002/4002.sub
new file mode 100644
index 00000000..b9726625
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002.sub
@@ -0,0 +1,30 @@
+* Subcircuit 4002
+.subckt 4002 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ? ? ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? 
+* c:\users\bhargav\esim\src\subcircuitlibrary\4002\4002.cir
+* u2  net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad3_ d_or
+* u3  net-_u1-pad5_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u6  net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad1_ d_nor
+* u4  net-_u1-pad9_ net-_u1-pad10_ net-_u4-pad3_ d_or
+* u5  net-_u1-pad11_ net-_u1-pad12_ net-_u5-pad3_ d_or
+* u7  net-_u4-pad3_ net-_u5-pad3_ net-_u1-pad13_ d_nor
+a1 [net-_u1-pad2_ net-_u1-pad3_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad1_ u6
+a4 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u4-pad3_ u4
+a5 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u5-pad3_ u5
+a6 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u1-pad13_ u7
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4002
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/4002_Previous_Values.xml b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
new file mode 100644
index 00000000..75360e5e
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/4002_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u6 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_or<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u5><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/4002/analysis b/src/SubcircuitLibrary/4002/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/src/SubcircuitLibrary/4002/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00
\ No newline at end of file