diff options
Diffstat (limited to 'library')
481 files changed, 60286 insertions, 2 deletions
diff --git a/library/SubcircuitLibrary/74F350/3_and-cache.lib b/library/SubcircuitLibrary/74F350/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/3_and.cir b/library/SubcircuitLibrary/74F350/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.cir.out b/library/SubcircuitLibrary/74F350/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/3_and.pro b/library/SubcircuitLibrary/74F350/3_and.pro new file mode 100644 index 00000000..00597a5a --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:26:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_User +LibName9=eSim_Sources +LibName10=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/3_and.sch b/library/SubcircuitLibrary/74F350/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/3_and.sub b/library/SubcircuitLibrary/74F350/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/74F350/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350-cache.lib b/library/SubcircuitLibrary/74F350/74F350-cache.lib new file mode 100644 index 00000000..8256d8a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350-cache.lib @@ -0,0 +1,112 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74F350/74F350.cir b/library/SubcircuitLibrary/74F350/74F350.cir new file mode 100644 index 00000000..87560c28 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\74F350\74F350.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:58:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X16 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad7_ Net-_U16-Pad1_ 3_and +X15 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U16-Pad2_ 3_and +X14 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad5_ Net-_U13-Pad1_ 3_and +X13 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U13-Pad2_ 3_and +X12 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad6_ Net-_U12-Pad1_ 3_and +X11 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U12-Pad2_ 3_and +X10 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U9-Pad1_ 3_and +X9 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U9-Pad2_ 3_and +X8 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad5_ Net-_U8-Pad1_ 3_and +X7 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U8-Pad2_ 3_and +X6 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad3_ Net-_U6-Pad1_ 3_and +X5 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U6-Pad2_ 3_and +X4 Net-_U24-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad1_ 3_and +X3 Net-_U25-Pad2_ Net-_U22-Pad2_ Net-_U1-Pad3_ Net-_U4-Pad2_ 3_and +X2 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad2_ Net-_U2-Pad1_ 3_and +X1 Net-_U25-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad1_ Net-_U2-Pad2_ 3_and +U26 Net-_U1-Pad13_ Net-_U10-Pad1_ d_inverter +U24 Net-_U1-Pad10_ Net-_U24-Pad2_ d_inverter +U22 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U25-Pad2_ d_inverter +U23 Net-_U22-Pad2_ Net-_U23-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +U20 Net-_U10-Pad1_ Net-_U14-Pad3_ Net-_U1-Pad15_ d_and +U15 Net-_U10-Pad1_ Net-_U11-Pad3_ Net-_U1-Pad14_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U1-Pad12_ d_and +U5 Net-_U10-Pad1_ Net-_U3-Pad3_ Net-_U1-Pad11_ d_and +U14 Net-_U14-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U7 Net-_U7-Pad1_ Net-_U6-Pad3_ Net-_U10-Pad2_ d_or +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U3-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ Net-_U14-Pad1_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U11-Pad1_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U11-Pad2_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U7-Pad1_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ d_or +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad1_ d_or +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.cir.out b/library/SubcircuitLibrary/74F350/74F350.cir.out new file mode 100644 index 00000000..b90caa5e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.cir.out @@ -0,0 +1,113 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir + +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74F350/74F350.pro b/library/SubcircuitLibrary/74F350/74F350.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/74F350/74F350.sch b/library/SubcircuitLibrary/74F350/74F350.sch new file mode 100644 index 00000000..989985a6 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sch @@ -0,0 +1,1000 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:74F350-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and X16 +U 1 1 679DB336 +P 15400 7400 +F 0 "X16" H 15500 7350 60 0000 C CNN +F 1 "3_and" H 15550 7550 60 0000 C CNN +F 2 "" H 15400 7400 60 0000 C CNN +F 3 "" H 15400 7400 60 0000 C CNN + 1 15400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X15 +U 1 1 679DB473 +P 14650 7400 +F 0 "X15" H 14750 7350 60 0000 C CNN +F 1 "3_and" H 14800 7550 60 0000 C CNN +F 2 "" H 14650 7400 60 0000 C CNN +F 3 "" H 14650 7400 60 0000 C CNN + 1 14650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X14 +U 1 1 679DB4EB +P 14050 7400 +F 0 "X14" H 14150 7350 60 0000 C CNN +F 1 "3_and" H 14200 7550 60 0000 C CNN +F 2 "" H 14050 7400 60 0000 C CNN +F 3 "" H 14050 7400 60 0000 C CNN + 1 14050 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X13 +U 1 1 679DB4F1 +P 13300 7400 +F 0 "X13" H 13400 7350 60 0000 C CNN +F 1 "3_and" H 13450 7550 60 0000 C CNN +F 2 "" H 13300 7400 60 0000 C CNN +F 3 "" H 13300 7400 60 0000 C CNN + 1 13300 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X12 +U 1 1 679DB5C3 +P 12750 7400 +F 0 "X12" H 12850 7350 60 0000 C CNN +F 1 "3_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12750 7400 60 0000 C CNN +F 3 "" H 12750 7400 60 0000 C CNN + 1 12750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X11 +U 1 1 679DB5C9 +P 12000 7400 +F 0 "X11" H 12100 7350 60 0000 C CNN +F 1 "3_and" H 12150 7550 60 0000 C CNN +F 2 "" H 12000 7400 60 0000 C CNN +F 3 "" H 12000 7400 60 0000 C CNN + 1 12000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X10 +U 1 1 679DB5CF +P 11400 7400 +F 0 "X10" H 11500 7350 60 0000 C CNN +F 1 "3_and" H 11550 7550 60 0000 C CNN +F 2 "" H 11400 7400 60 0000 C CNN +F 3 "" H 11400 7400 60 0000 C CNN + 1 11400 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X9 +U 1 1 679DB5D5 +P 10650 7400 +F 0 "X9" H 10750 7350 60 0000 C CNN +F 1 "3_and" H 10800 7550 60 0000 C CNN +F 2 "" H 10650 7400 60 0000 C CNN +F 3 "" H 10650 7400 60 0000 C CNN + 1 10650 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X8 +U 1 1 679DB885 +P 10100 7400 +F 0 "X8" H 10200 7350 60 0000 C CNN +F 1 "3_and" H 10250 7550 60 0000 C CNN +F 2 "" H 10100 7400 60 0000 C CNN +F 3 "" H 10100 7400 60 0000 C CNN + 1 10100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X7 +U 1 1 679DB88B +P 9350 7400 +F 0 "X7" H 9450 7350 60 0000 C CNN +F 1 "3_and" H 9500 7550 60 0000 C CNN +F 2 "" H 9350 7400 60 0000 C CNN +F 3 "" H 9350 7400 60 0000 C CNN + 1 9350 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X6 +U 1 1 679DB891 +P 8750 7400 +F 0 "X6" H 8850 7350 60 0000 C CNN +F 1 "3_and" H 8900 7550 60 0000 C CNN +F 2 "" H 8750 7400 60 0000 C CNN +F 3 "" H 8750 7400 60 0000 C CNN + 1 8750 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X5 +U 1 1 679DB897 +P 8000 7400 +F 0 "X5" H 8100 7350 60 0000 C CNN +F 1 "3_and" H 8150 7550 60 0000 C CNN +F 2 "" H 8000 7400 60 0000 C CNN +F 3 "" H 8000 7400 60 0000 C CNN + 1 8000 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X4 +U 1 1 679DB89D +P 7450 7400 +F 0 "X4" H 7550 7350 60 0000 C CNN +F 1 "3_and" H 7600 7550 60 0000 C CNN +F 2 "" H 7450 7400 60 0000 C CNN +F 3 "" H 7450 7400 60 0000 C CNN + 1 7450 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X3 +U 1 1 679DB8A3 +P 6700 7400 +F 0 "X3" H 6800 7350 60 0000 C CNN +F 1 "3_and" H 6850 7550 60 0000 C CNN +F 2 "" H 6700 7400 60 0000 C CNN +F 3 "" H 6700 7400 60 0000 C CNN + 1 6700 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X2 +U 1 1 679DB8A9 +P 6100 7400 +F 0 "X2" H 6200 7350 60 0000 C CNN +F 1 "3_and" H 6250 7550 60 0000 C CNN +F 2 "" H 6100 7400 60 0000 C CNN +F 3 "" H 6100 7400 60 0000 C CNN + 1 6100 7400 + 0 1 1 0 +$EndComp +$Comp +L 3_and X1 +U 1 1 679DB8AF +P 5350 7400 +F 0 "X1" H 5450 7350 60 0000 C CNN +F 1 "3_and" H 5500 7550 60 0000 C CNN +F 2 "" H 5350 7400 60 0000 C CNN +F 3 "" H 5350 7400 60 0000 C CNN + 1 5350 7400 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U26 +U 1 1 679DBBC7 +P 17700 3200 +F 0 "U26" H 17700 3100 60 0000 C CNN +F 1 "d_inverter" H 17700 3350 60 0000 C CNN +F 2 "" H 17750 3150 60 0000 C CNN +F 3 "" H 17750 3150 60 0000 C CNN + 1 17700 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U24 +U 1 1 679DBC88 +P 16900 3200 +F 0 "U24" H 16900 3100 60 0000 C CNN +F 1 "d_inverter" H 16900 3350 60 0000 C CNN +F 2 "" H 16950 3150 60 0000 C CNN +F 3 "" H 16950 3150 60 0000 C CNN + 1 16900 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U22 +U 1 1 679DBCDF +P 16150 3200 +F 0 "U22" H 16150 3100 60 0000 C CNN +F 1 "d_inverter" H 16150 3350 60 0000 C CNN +F 2 "" H 16200 3150 60 0000 C CNN +F 3 "" H 16200 3150 60 0000 C CNN + 1 16150 3200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U25 +U 1 1 679DBD6D +P 16900 4200 +F 0 "U25" H 16900 4100 60 0000 C CNN +F 1 "d_inverter" H 16900 4350 60 0000 C CNN +F 2 "" H 16950 4150 60 0000 C CNN +F 3 "" H 16950 4150 60 0000 C CNN + 1 16900 4200 + 0 1 1 0 +$EndComp +$Comp +L d_inverter U23 +U 1 1 679DBD73 +P 16150 4200 +F 0 "U23" H 16150 4100 60 0000 C CNN +F 1 "d_inverter" H 16150 4350 60 0000 C CNN +F 2 "" H 16200 4150 60 0000 C CNN +F 3 "" H 16200 4150 60 0000 C CNN + 1 16150 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 679EA80D +P 17700 2050 +F 0 "U1" H 17750 2150 30 0000 C CNN +F 1 "PORT" H 17700 2050 30 0000 C CNN +F 2 "" H 17700 2050 60 0000 C CNN +F 3 "" H 17700 2050 60 0000 C CNN + 13 17700 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 679EAA26 +P 16900 2050 +F 0 "U1" H 16950 2150 30 0000 C CNN +F 1 "PORT" H 16900 2050 30 0000 C CNN +F 2 "" H 16900 2050 60 0000 C CNN +F 3 "" H 16900 2050 60 0000 C CNN + 10 16900 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679EAAAF +P 16150 2100 +F 0 "U1" H 16200 2200 30 0000 C CNN +F 1 "PORT" H 16150 2100 30 0000 C CNN +F 2 "" H 16150 2100 60 0000 C CNN +F 3 "" H 16150 2100 60 0000 C CNN + 9 16150 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 679EAB54 +P 15350 2150 +F 0 "U1" H 15400 2250 30 0000 C CNN +F 1 "PORT" H 15350 2150 30 0000 C CNN +F 2 "" H 15350 2150 60 0000 C CNN +F 3 "" H 15350 2150 60 0000 C CNN + 7 15350 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 679EAD32 +P 14600 2150 +F 0 "U1" H 14650 2250 30 0000 C CNN +F 1 "PORT" H 14600 2150 30 0000 C CNN +F 2 "" H 14600 2150 60 0000 C CNN +F 3 "" H 14600 2150 60 0000 C CNN + 6 14600 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 679EAD38 +P 14000 2150 +F 0 "U1" H 14050 2250 30 0000 C CNN +F 1 "PORT" H 14000 2150 30 0000 C CNN +F 2 "" H 14000 2150 60 0000 C CNN +F 3 "" H 14000 2150 60 0000 C CNN + 5 14000 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 679EAD3E +P 13250 2150 +F 0 "U1" H 13300 2250 30 0000 C CNN +F 1 "PORT" H 13250 2150 30 0000 C CNN +F 2 "" H 13250 2150 60 0000 C CNN +F 3 "" H 13250 2150 60 0000 C CNN + 4 13250 2150 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 679EB065 +P 10600 2300 +F 0 "U1" H 10650 2400 30 0000 C CNN +F 1 "PORT" H 10600 2300 30 0000 C CNN +F 2 "" H 10600 2300 60 0000 C CNN +F 3 "" H 10600 2300 60 0000 C CNN + 3 10600 2300 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 679EB06B +P 7950 2200 +F 0 "U1" H 8000 2300 30 0000 C CNN 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+F 3 "" H 11900 12050 60 0000 C CNN + 1 11900 12050 + 0 1 1 0 +$EndComp +$Comp +L d_and U10 +U 1 1 679F0140 +P 9200 12200 +F 0 "U10" H 9200 12200 60 0000 C CNN +F 1 "d_and" H 9250 12300 60 0000 C CNN +F 2 "" H 9200 12200 60 0000 C CNN +F 3 "" H 9200 12200 60 0000 C CNN + 1 9200 12200 + 0 1 1 0 +$EndComp +$Comp +L d_and U5 +U 1 1 679F01D7 +P 6550 12200 +F 0 "U5" H 6550 12200 60 0000 C CNN +F 1 "d_and" H 6600 12300 60 0000 C CNN +F 2 "" H 6550 12200 60 0000 C CNN +F 3 "" H 6550 12200 60 0000 C CNN + 1 6550 12200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6600 12750 6600 12650 +Wire Wire Line + 9250 12700 9250 12650 +Wire Wire Line + 17700 11300 15050 11300 +Wire Wire Line + 15050 10850 15050 11600 +Wire Wire Line + 15050 11600 14650 11600 +Wire Wire Line + 7100 10850 15050 10850 +Wire Wire Line + 12300 11600 12000 11600 +Connection ~ 15050 11300 +Wire Wire Line + 9950 11750 9300 11750 +Connection ~ 12300 10850 +Wire Wire Line + 7100 11750 6650 11750 +Connection ~ 9950 10850 +$Comp +L d_or U14 +U 1 1 67A37333 +P 14500 10350 +F 0 "U14" H 14500 10350 60 0000 C CNN +F 1 "d_or" H 14500 10450 60 0000 C CNN +F 2 "" H 14500 10350 60 0000 C CNN +F 3 "" H 14500 10350 60 0000 C CNN + 1 14500 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U11 +U 1 1 67A375DC +P 11850 10350 +F 0 "U11" H 11850 10350 60 0000 C CNN +F 1 "d_or" H 11850 10450 60 0000 C CNN +F 2 "" H 11850 10350 60 0000 C CNN +F 3 "" H 11850 10350 60 0000 C CNN + 1 11850 10350 + 0 1 1 0 +$EndComp +$Comp +L d_or U7 +U 1 1 67A376D5 +P 9150 10450 +F 0 "U7" H 9150 10450 60 0000 C CNN +F 1 "d_or" H 9150 10550 60 0000 C CNN +F 2 "" H 9150 10450 60 0000 C CNN +F 3 "" H 9150 10450 60 0000 C CNN + 1 9150 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U3 +U 1 1 67A377D6 +P 6500 10450 +F 0 "U3" H 6500 10450 60 0000 C CNN +F 1 "d_or" H 6500 10550 60 0000 C CNN +F 2 "" H 6500 10450 60 0000 C CNN +F 3 "" H 6500 10450 60 0000 C CNN + 1 6500 10450 + 0 1 1 0 +$EndComp +$Comp +L d_or U16 +U 1 1 67A37A21 +P 15150 8950 +F 0 "U16" H 15150 8950 60 0000 C CNN +F 1 "d_or" H 15150 9050 60 0000 C CNN +F 2 "" H 15150 8950 60 0000 C CNN +F 3 "" H 15150 8950 60 0000 C CNN + 1 15150 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U13 +U 1 1 67A37ADA +P 13700 8950 +F 0 "U13" H 13700 8950 60 0000 C CNN +F 1 "d_or" H 13700 9050 60 0000 C CNN +F 2 "" H 13700 8950 60 0000 C CNN +F 3 "" H 13700 8950 60 0000 C CNN + 1 13700 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U12 +U 1 1 67A37C7D +P 12500 8950 +F 0 "U12" H 12500 8950 60 0000 C CNN +F 1 "d_or" H 12500 9050 60 0000 C CNN +F 2 "" H 12500 8950 60 0000 C CNN +F 3 "" H 12500 8950 60 0000 C CNN + 1 12500 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U9 +U 1 1 67A37CFE +P 11050 8950 +F 0 "U9" H 11050 8950 60 0000 C CNN +F 1 "d_or" H 11050 9050 60 0000 C CNN +F 2 "" H 11050 8950 60 0000 C CNN +F 3 "" H 11050 8950 60 0000 C CNN + 1 11050 8950 + 0 1 1 0 +$EndComp +$Comp +L d_or U8 +U 1 1 67A37DF9 +P 9800 9050 +F 0 "U8" H 9800 9050 60 0000 C CNN +F 1 "d_or" H 9800 9150 60 0000 C CNN +F 2 "" H 9800 9050 60 0000 C CNN +F 3 "" H 9800 9050 60 0000 C CNN + 1 9800 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U6 +U 1 1 67A37FCE +P 8350 9050 +F 0 "U6" H 8350 9050 60 0000 C CNN +F 1 "d_or" H 8350 9150 60 0000 C CNN +F 2 "" H 8350 9050 60 0000 C CNN +F 3 "" H 8350 9050 60 0000 C CNN + 1 8350 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U4 +U 1 1 67A38059 +P 7150 9050 +F 0 "U4" H 7150 9050 60 0000 C CNN +F 1 "d_or" H 7150 9150 60 0000 C CNN +F 2 "" H 7150 9050 60 0000 C CNN +F 3 "" H 7150 9050 60 0000 C CNN + 1 7150 9050 + 0 1 1 0 +$EndComp +$Comp +L d_or U2 +U 1 1 67A38154 +P 5700 9050 +F 0 "U2" H 5700 9050 60 0000 C CNN +F 1 "d_or" H 5700 9150 60 0000 C CNN +F 2 "" H 5700 9050 60 0000 C CNN +F 3 "" H 5700 9050 60 0000 C CNN + 1 5700 9050 + 0 1 1 0 +$EndComp +Wire Wire Line + 12300 11600 12300 10850 +Wire Wire Line + 9950 11750 9950 10850 +Wire Wire Line + 7100 10850 7100 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74F350/74F350.sub b/library/SubcircuitLibrary/74F350/74F350.sub new file mode 100644 index 00000000..39ba9abb --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350.sub @@ -0,0 +1,107 @@ +* Subcircuit 74F350 +.subckt 74F350 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\74f350\74f350.cir +.include 3_and.sub +x16 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad7_ net-_u16-pad1_ 3_and +x15 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u16-pad2_ 3_and +x14 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad5_ net-_u13-pad1_ 3_and +x13 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u13-pad2_ 3_and +x12 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad6_ net-_u12-pad1_ 3_and +x11 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u12-pad2_ 3_and +x10 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u9-pad1_ 3_and +x9 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u9-pad2_ 3_and +x8 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad5_ net-_u8-pad1_ 3_and +x7 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u8-pad2_ 3_and +x6 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad3_ net-_u6-pad1_ 3_and +x5 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u6-pad2_ 3_and +x4 net-_u24-pad2_ net-_u22-pad2_ net-_u1-pad4_ net-_u4-pad1_ 3_and +x3 net-_u25-pad2_ net-_u22-pad2_ net-_u1-pad3_ net-_u4-pad2_ 3_and +x2 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad2_ net-_u2-pad1_ 3_and +x1 net-_u25-pad2_ net-_u23-pad2_ net-_u1-pad1_ net-_u2-pad2_ 3_and +* u26 net-_u1-pad13_ net-_u10-pad1_ d_inverter +* u24 net-_u1-pad10_ net-_u24-pad2_ d_inverter +* u22 net-_u1-pad9_ net-_u22-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u25-pad2_ d_inverter +* u23 net-_u22-pad2_ net-_u23-pad2_ d_inverter +* u20 net-_u10-pad1_ net-_u14-pad3_ net-_u1-pad15_ d_and +* u15 net-_u10-pad1_ net-_u11-pad3_ net-_u1-pad14_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u1-pad12_ d_and +* u5 net-_u10-pad1_ net-_u3-pad3_ net-_u1-pad11_ d_and +* u14 net-_u14-pad1_ net-_u13-pad3_ net-_u14-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u7 net-_u7-pad1_ net-_u6-pad3_ net-_u10-pad2_ d_or +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u3-pad3_ d_or +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u14-pad1_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u11-pad1_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u11-pad2_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u7-pad1_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ d_or +* u4 net-_u4-pad1_ net-_u4-pad2_ net-_u3-pad1_ d_or +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_or +a1 net-_u1-pad13_ net-_u10-pad1_ u26 +a2 net-_u1-pad10_ net-_u24-pad2_ u24 +a3 net-_u1-pad9_ net-_u22-pad2_ u22 +a4 net-_u24-pad2_ net-_u25-pad2_ u25 +a5 net-_u22-pad2_ net-_u23-pad2_ u23 +a6 [net-_u10-pad1_ net-_u14-pad3_ ] net-_u1-pad15_ u20 +a7 [net-_u10-pad1_ net-_u11-pad3_ ] net-_u1-pad14_ u15 +a8 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u1-pad12_ u10 +a9 [net-_u10-pad1_ net-_u3-pad3_ ] net-_u1-pad11_ u5 +a10 [net-_u14-pad1_ net-_u13-pad3_ ] net-_u14-pad3_ u14 +a11 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a12 [net-_u7-pad1_ net-_u6-pad3_ ] net-_u10-pad2_ u7 +a13 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u3-pad3_ u3 +a14 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u14-pad1_ u16 +a15 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u11-pad1_ u12 +a17 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u11-pad2_ u9 +a18 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u7-pad1_ u8 +a19 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u6-pad3_ u6 +a20 [net-_u4-pad1_ net-_u4-pad2_ ] net-_u3-pad1_ u4 +a21 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 74F350
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml new file mode 100644 index 00000000..bc7f0ee5 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/74F350_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u26 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u26><u24 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u22 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u25><u23 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u23><u21 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u21><u17 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u16><u12 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u13><u11 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u11><u7 name="type">d_nor<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nor<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_nor<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u6><u2 name="type">d_nor<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_nor<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u3><u20 name="type">d_tristate<field52 name="Enter Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Enable Load (default=1.0e-12)" /></u20><u15 name="type">d_tristate<field55 name="Enter Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Enable Load (default=1.0e-12)" /></u15><u10 name="type">d_tristate<field58 name="Enter Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Enable Load (default=1.0e-12)" /></u10><u5 name="type">d_tristate<field61 name="Enter Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Enable Load (default=1.0e-12)" /></u5><u4 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u9><u14 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u14><u19 name="type">d_inverter<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u19><u10 name="type">d_nand<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_nand<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u9><u5 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u5><u4 name="type">d_nand<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u4><u20 name="type">d_and<field64 name="Enter Input Load (default=1.0e-12)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u20><u15 name="type">d_and<field67 name="Enter Input Load (default=1.0e-12)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u15><u10 name="type">d_and<field70 name="Enter Input Load (default=1.0e-12)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u10><u5 name="type">d_and<field73 name="Enter Input Load (default=1.0e-12)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u5><u14 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u14><u11 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u11><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u3 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u3><u16 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u16><u13 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u13><u12 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u12><u9 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u8 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u8><u6 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u6><u4 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u4><u2 name="type">d_or<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x10><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x15><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x4><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x7><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x16></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74F350/analysis b/library/SubcircuitLibrary/74F350/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74F350/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib new file mode 100644 index 00000000..57dd9d9b --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir new file mode 100644 index 00000000..00f7b56f --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir @@ -0,0 +1,35 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4078B_IC\CD4078B_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/18/24 16:43:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad9_ Net-_U11-Pad1_ d_inverter +U4 Net-_U2-Pad10_ Net-_U11-Pad2_ d_inverter +U5 Net-_U2-Pad11_ Net-_U12-Pad1_ d_inverter +U6 Net-_U2-Pad12_ Net-_U12-Pad2_ d_inverter +U7 Net-_U2-Pad13_ Net-_U13-Pad1_ d_inverter +U8 Net-_U2-Pad14_ Net-_U13-Pad2_ d_inverter +U9 Net-_U2-Pad15_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U21 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ d_nor +U22 Net-_U21-Pad3_ Net-_U22-Pad2_ d_inverter +U24 Net-_U22-Pad2_ Net-_U24-Pad2_ d_inverter +U23 Net-_U21-Pad3_ Net-_U23-Pad2_ d_inverter +U25 Net-_U24-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad10_ Net-_U1-Pad9_ dac_bridge_2 +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8 +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand +U15 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U16 Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U16-Pad3_ d_nand +U19 Net-_U15-Pad3_ Net-_U16-Pad3_ Net-_U19-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_nand +U14 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_nand +U17 Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_nand +U18 Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U18-Pad3_ d_nand +U20 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U20-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out new file mode 100644 index 00000000..30c56474 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.cir.out @@ -0,0 +1,108 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir + +* u3 net-_u2-pad9_ net-_u11-pad1_ d_inverter +* u4 net-_u2-pad10_ net-_u11-pad2_ d_inverter +* u5 net-_u2-pad11_ net-_u12-pad1_ d_inverter +* u6 net-_u2-pad12_ net-_u12-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u13-pad1_ d_inverter +* u8 net-_u2-pad14_ net-_u13-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u21 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_u24-pad2_ d_inverter +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2 +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand +* u20 net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ port +a1 net-_u2-pad9_ net-_u11-pad1_ u3 +a2 net-_u2-pad10_ net-_u11-pad2_ u4 +a3 net-_u2-pad11_ net-_u12-pad1_ u5 +a4 net-_u2-pad12_ net-_u12-pad2_ u6 +a5 net-_u2-pad13_ net-_u13-pad1_ u7 +a6 net-_u2-pad14_ net-_u13-pad2_ u8 +a7 net-_u2-pad15_ net-_u14-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a10 net-_u21-pad3_ net-_u22-pad2_ u22 +a11 net-_u22-pad2_ net-_u24-pad2_ u24 +a12 net-_u21-pad3_ net-_u23-pad2_ u23 +a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25 +a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18 +a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch new file mode 100644 index 00000000..9436e506 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sch @@ -0,0 +1,700 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4078B_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 66716575 +P 7850 6350 +F 0 "U3" H 7850 6250 60 0000 C CNN +F 1 "d_inverter" H 7850 6500 60 0000 C CNN +F 2 "" H 7900 6300 60 0000 C CNN +F 3 "" H 7900 6300 60 0000 C CNN + 1 7850 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 66716576 +P 7850 6850 +F 0 "U4" H 7850 6750 60 0000 C CNN +F 1 "d_inverter" H 7850 7000 60 0000 C CNN +F 2 "" H 7900 6800 60 0000 C CNN +F 3 "" H 7900 6800 60 0000 C CNN + 1 7850 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 66716577 +P 7850 7350 +F 0 "U5" H 7850 7250 60 0000 C CNN +F 1 "d_inverter" H 7850 7500 60 0000 C CNN +F 2 "" H 7900 7300 60 0000 C CNN +F 3 "" H 7900 7300 60 0000 C CNN + 1 7850 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 66716578 +P 7850 7950 +F 0 "U6" H 7850 7850 60 0000 C CNN +F 1 "d_inverter" H 7850 8100 60 0000 C CNN +F 2 "" H 7900 7900 60 0000 C CNN +F 3 "" H 7900 7900 60 0000 C CNN + 1 7850 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 66716579 +P 7850 8750 +F 0 "U7" H 7850 8650 60 0000 C CNN +F 1 "d_inverter" H 7850 8900 60 0000 C CNN +F 2 "" H 7900 8700 60 0000 C CNN +F 3 "" H 7900 8700 60 0000 C CNN + 1 7850 8750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 6671657A +P 7850 9250 +F 0 "U8" H 7850 9150 60 0000 C CNN +F 1 "d_inverter" H 7850 9400 60 0000 C CNN +F 2 "" H 7900 9200 60 0000 C CNN +F 3 "" H 7900 9200 60 0000 C CNN + 1 7850 9250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 6671657B +P 7850 9750 +F 0 "U9" H 7850 9650 60 0000 C CNN +F 1 "d_inverter" H 7850 9900 60 0000 C CNN +F 2 "" H 7900 9700 60 0000 C CNN +F 3 "" H 7900 9700 60 0000 C CNN + 1 7850 9750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 6671657C +P 7850 10350 +F 0 "U10" H 7850 10250 60 0000 C CNN +F 1 "d_inverter" H 7850 10500 60 0000 C CNN +F 2 "" H 7900 10300 60 0000 C CNN +F 3 "" H 7900 10300 60 0000 C CNN + 1 7850 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U21 +U 1 1 6671657D +P 14350 8200 +F 0 "U21" H 14350 8200 60 0000 C CNN +F 1 "d_nor" H 14400 8300 60 0000 C CNN +F 2 "" H 14350 8200 60 0000 C CNN +F 3 "" H 14350 8200 60 0000 C CNN + 1 14350 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6671657E +P 15350 8150 +F 0 "U22" H 15350 8050 60 0000 C CNN +F 1 "d_inverter" H 15350 8300 60 0000 C CNN +F 2 "" H 15400 8100 60 0000 C CNN +F 3 "" H 15400 8100 60 0000 C CNN + 1 15350 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U24 +U 1 1 6671657F +P 16150 8150 +F 0 "U24" H 16150 8050 60 0000 C CNN +F 1 "d_inverter" H 16150 8300 60 0000 C CNN +F 2 "" H 16200 8100 60 0000 C CNN +F 3 "" H 16200 8100 60 0000 C CNN + 1 16150 8150 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 66716580 +P 15450 8850 +F 0 "U23" H 15450 8750 60 0000 C CNN +F 1 "d_inverter" H 15450 9000 60 0000 C CNN +F 2 "" H 15500 8800 60 0000 C CNN +F 3 "" H 15500 8800 60 0000 C CNN + 1 15450 8850 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_2 U25 +U 1 1 66716581 +P 17350 8350 +F 0 "U25" H 17350 8350 60 0000 C CNN +F 1 "dac_bridge_2" H 17400 8500 60 0000 C CNN +F 2 "" H 17350 8350 60 0000 C CNN +F 3 "" H 17350 8350 60 0000 C CNN + 1 17350 8350 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_8 U2 +U 1 1 66716584 +P 5500 8050 +F 0 "U2" H 5500 8050 60 0000 C CNN +F 1 "adc_bridge_8" H 5500 8200 60 0000 C CNN +F 2 "" H 5500 8050 60 0000 C CNN +F 3 "" H 5500 8050 60 0000 C CNN + 1 5500 8050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8150 6350 8800 6350 +Wire Wire Line + 8800 6350 8800 6950 +Wire Wire Line + 8800 6950 9100 6950 +Wire Wire Line + 8150 6850 8700 6850 +Wire Wire Line + 8700 6850 8700 7050 +Wire Wire Line + 8700 7050 9250 7050 +Wire Wire Line + 8150 7350 8700 7350 +Wire Wire Line + 8700 7350 8700 7150 +Wire Wire Line + 8700 7150 9700 7150 +Wire Wire Line + 8150 7950 8800 7950 +Wire Wire Line + 8800 7950 8800 7250 +Wire Wire Line + 8800 7250 9600 7250 +Wire Wire Line + 8150 8750 8750 8750 +Wire Wire Line + 8750 8750 8750 9250 +Wire Wire Line + 8750 9250 9150 9250 +Wire Wire Line + 8150 9250 8650 9250 +Wire Wire Line + 8650 9250 8650 9350 +Wire Wire Line + 8650 9350 9300 9350 +Wire Wire Line + 8150 9750 8650 9750 +Wire Wire Line + 8650 9750 8650 9450 +Wire Wire Line + 8650 9450 9350 9450 +Wire Wire Line + 8150 10350 8750 10350 +Wire Wire Line + 8750 10350 8750 9550 +Wire Wire Line + 8750 9550 9300 9550 +Wire Wire Line + 13700 8200 13900 8200 +Wire Wire Line + 15050 8150 14800 8150 +Wire Wire Line + 15650 8150 15850 8150 +Wire Wire Line + 15150 8850 14950 8850 +Wire Wire Line + 14950 8850 14950 8150 +Connection ~ 14950 8150 +Wire Wire Line + 16450 8150 16800 8150 +Wire Wire Line + 16800 8150 16800 8300 +Wire Wire Line + 16800 8300 16900 8300 +Wire Wire Line + 15750 8850 16750 8850 +Wire Wire Line + 16750 8850 16750 8400 +Wire Wire Line + 16750 8400 16900 8400 +Wire Wire Line + 6050 8000 6800 8000 +Wire Wire Line + 6800 8000 6800 6350 +Wire Wire Line + 6800 6350 7550 6350 +Wire Wire Line + 7550 6850 6900 6850 +Wire Wire Line + 6900 6850 6900 8100 +Wire Wire Line + 6900 8100 6050 8100 +Wire Wire Line + 6050 8200 7150 8200 +Wire Wire Line + 7150 8200 7150 7350 +Wire Wire Line + 7150 7350 7550 7350 +Wire Wire Line + 7550 7950 7250 7950 +Wire Wire Line + 7250 7950 7250 8300 +Wire Wire Line + 7250 8300 6050 8300 +Wire Wire Line + 6050 8400 7300 8400 +Wire Wire Line + 7300 8400 7300 8750 +Wire Wire Line + 7300 8750 7550 8750 +Wire Wire Line + 6050 8500 7200 8500 +Wire Wire Line + 7200 8500 7200 9250 +Wire Wire Line + 7200 9250 7550 9250 +Wire Wire Line + 6050 8600 7050 8600 +Wire Wire Line + 7050 8600 7050 9750 +Wire Wire Line + 7050 9750 7550 9750 +Wire Wire Line + 6050 8700 6950 8700 +Wire Wire Line + 6950 8700 6950 10350 +Wire Wire Line + 6950 10350 7550 10350 +$Comp +L d_nand U11 +U 1 1 6671659D +P 10250 7000 +F 0 "U11" H 10250 7000 60 0000 C CNN +F 1 "d_nand" H 10300 7100 60 0000 C CNN +F 2 "" H 10250 7000 60 0000 C CNN +F 3 "" H 10250 7000 60 0000 C CNN + 1 10250 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 6671659E +P 10250 7500 +F 0 "U12" H 10250 7500 60 0000 C CNN +F 1 "d_nand" H 10300 7600 60 0000 C CNN +F 2 "" H 10250 7500 60 0000 C CNN +F 3 "" H 10250 7500 60 0000 C CNN + 1 10250 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 6671659F +P 11550 7000 +F 0 "U15" H 11550 7000 60 0000 C CNN +F 1 "d_nand" H 11600 7100 60 0000 C CNN +F 2 "" H 11550 7000 60 0000 C CNN +F 3 "" H 11550 7000 60 0000 C CNN + 1 11550 7000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 667165A0 +P 11550 7500 +F 0 "U16" H 11550 7500 60 0000 C CNN +F 1 "d_nand" H 11600 7600 60 0000 C CNN +F 2 "" H 11550 7500 60 0000 C CNN +F 3 "" H 11550 7500 60 0000 C CNN + 1 11550 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 667165A1 +P 12750 7200 +F 0 "U19" H 12750 7200 60 0000 C CNN +F 1 "d_nand" H 12800 7300 60 0000 C CNN +F 2 "" H 12750 7200 60 0000 C CNN +F 3 "" H 12750 7200 60 0000 C CNN + 1 12750 7200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 6900 11000 6900 +Wire Wire Line + 11000 6900 11000 7000 +Wire Wire Line + 11000 7000 11100 7000 +Wire Wire Line + 11100 7400 11000 7400 +Wire Wire Line + 11000 7400 11000 7500 +Wire Wire Line + 11000 7500 11100 7500 +Wire Wire Line + 10700 6950 11000 6950 +Connection ~ 11000 6950 +Wire Wire Line + 10700 7450 11000 7450 +Connection ~ 11000 7450 +Wire Wire Line + 12000 6950 12150 6950 +Wire Wire Line + 12150 6950 12150 7100 +Wire Wire Line + 12150 7100 12300 7100 +Wire Wire Line + 12000 7450 12150 7450 +Wire Wire Line + 12150 7450 12150 7200 +Wire Wire Line + 12150 7200 12300 7200 +Wire Wire Line + 9100 6950 9100 6900 +Wire Wire Line + 9100 6900 9800 6900 +Wire Wire Line + 9250 7050 9250 7000 +Wire Wire Line + 9250 7000 9800 7000 +Wire Wire Line + 9700 7150 9700 7400 +Wire Wire Line + 9700 7400 9800 7400 +Wire Wire Line + 9600 7250 9600 7500 +Wire Wire Line + 9600 7500 9800 7500 +$Comp +L d_nand U13 +U 1 1 667165A2 +P 10250 9300 +F 0 "U13" H 10250 9300 60 0000 C CNN +F 1 "d_nand" H 10300 9400 60 0000 C CNN +F 2 "" H 10250 9300 60 0000 C CNN +F 3 "" H 10250 9300 60 0000 C CNN + 1 10250 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 667165A3 +P 10250 9800 +F 0 "U14" H 10250 9800 60 0000 C CNN +F 1 "d_nand" H 10300 9900 60 0000 C CNN +F 2 "" H 10250 9800 60 0000 C CNN +F 3 "" H 10250 9800 60 0000 C CNN + 1 10250 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 667165A4 +P 11550 9300 +F 0 "U17" H 11550 9300 60 0000 C CNN +F 1 "d_nand" H 11600 9400 60 0000 C CNN +F 2 "" H 11550 9300 60 0000 C CNN +F 3 "" H 11550 9300 60 0000 C CNN + 1 11550 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 667165A5 +P 11550 9800 +F 0 "U18" H 11550 9800 60 0000 C CNN +F 1 "d_nand" H 11600 9900 60 0000 C CNN +F 2 "" H 11550 9800 60 0000 C CNN +F 3 "" H 11550 9800 60 0000 C CNN + 1 11550 9800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11100 9200 11000 9200 +Wire Wire Line + 11000 9200 11000 9300 +Wire Wire Line + 11000 9300 11100 9300 +Wire Wire Line + 11100 9700 11000 9700 +Wire Wire Line + 11000 9700 11000 9800 +Wire Wire Line + 11000 9800 11100 9800 +Wire Wire Line + 10700 9250 11000 9250 +Connection ~ 11000 9250 +Wire Wire Line + 10700 9750 11000 9750 +Connection ~ 11000 9750 +Wire Wire Line + 9800 9200 9150 9200 +Wire Wire Line + 9150 9200 9150 9250 +Wire Wire Line + 9300 9350 9300 9300 +Wire Wire Line + 9300 9300 9800 9300 +Wire Wire Line + 9350 9450 9350 9700 +Wire Wire Line + 9350 9700 9800 9700 +Wire Wire Line + 9300 9550 9300 9800 +Wire Wire Line + 9300 9800 9800 9800 +$Comp +L d_nand U20 +U 1 1 667165A6 +P 12950 9500 +F 0 "U20" H 12950 9500 60 0000 C CNN +F 1 "d_nand" H 13000 9600 60 0000 C CNN +F 2 "" H 12950 9500 60 0000 C CNN +F 3 "" H 12950 9500 60 0000 C CNN + 1 12950 9500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 12000 9250 12350 9250 +Wire Wire Line + 12350 9250 12350 9400 +Wire Wire Line + 12350 9400 12500 9400 +Wire Wire Line + 12000 9750 12350 9750 +Wire Wire Line + 12350 9750 12350 9500 +Wire Wire Line + 12350 9500 12500 9500 +Wire Wire Line + 13700 8200 13700 9450 +Wire Wire Line + 13700 9450 13400 9450 +Wire Wire Line + 13900 8100 13700 8100 +Wire Wire Line + 13700 8100 13700 7150 +Wire Wire Line + 13700 7150 13200 7150 +$Comp +L PORT U1 +U 1 1 6671678E +P 4050 7700 +F 0 "U1" H 4100 7800 30 0000 C CNN +F 1 "PORT" H 4050 7700 30 0000 C CNN +F 2 "" H 4050 7700 60 0000 C CNN +F 3 "" H 4050 7700 60 0000 C CNN + 1 4050 7700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 66716827 +P 4050 7900 +F 0 "U1" H 4100 8000 30 0000 C CNN +F 1 "PORT" H 4050 7900 30 0000 C CNN +F 2 "" H 4050 7900 60 0000 C CNN +F 3 "" H 4050 7900 60 0000 C CNN + 2 4050 7900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 667168B8 +P 4050 8100 +F 0 "U1" H 4100 8200 30 0000 C CNN +F 1 "PORT" H 4050 8100 30 0000 C CNN +F 2 "" H 4050 8100 60 0000 C CNN +F 3 "" H 4050 8100 60 0000 C CNN + 3 4050 8100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6671693B +P 4050 8300 +F 0 "U1" H 4100 8400 30 0000 C CNN +F 1 "PORT" H 4050 8300 30 0000 C CNN +F 2 "" H 4050 8300 60 0000 C CNN +F 3 "" H 4050 8300 60 0000 C CNN + 4 4050 8300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 667169A8 +P 4050 8500 +F 0 "U1" H 4100 8600 30 0000 C CNN +F 1 "PORT" H 4050 8500 30 0000 C CNN +F 2 "" H 4050 8500 60 0000 C CNN +F 3 "" H 4050 8500 60 0000 C CNN + 5 4050 8500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 66716A2D +P 4050 8700 +F 0 "U1" H 4100 8800 30 0000 C CNN +F 1 "PORT" H 4050 8700 30 0000 C CNN +F 2 "" H 4050 8700 60 0000 C CNN +F 3 "" H 4050 8700 60 0000 C CNN + 6 4050 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 66716AB0 +P 4050 8900 +F 0 "U1" H 4100 9000 30 0000 C CNN +F 1 "PORT" H 4050 8900 30 0000 C CNN +F 2 "" H 4050 8900 60 0000 C CNN +F 3 "" H 4050 8900 60 0000 C CNN + 7 4050 8900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 66716B2F +P 4050 9100 +F 0 "U1" H 4100 9200 30 0000 C CNN +F 1 "PORT" H 4050 9100 30 0000 C CNN +F 2 "" H 4050 9100 60 0000 C CNN +F 3 "" H 4050 9100 60 0000 C CNN + 8 4050 9100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 7700 4800 7700 +Wire Wire Line + 4800 7700 4800 8000 +Wire Wire Line + 4800 8000 4900 8000 +Wire Wire Line + 4300 7900 4750 7900 +Wire Wire Line + 4750 7900 4750 8100 +Wire Wire Line + 4750 8100 4900 8100 +Wire Wire Line + 4300 8100 4650 8100 +Wire Wire Line + 4650 8100 4650 8200 +Wire Wire Line + 4650 8200 4900 8200 +Wire Wire Line + 4300 8300 4900 8300 +Wire Wire Line + 4300 8500 4750 8500 +Wire Wire Line + 4750 8500 4750 8400 +Wire Wire Line + 4750 8400 4900 8400 +Wire Wire Line + 4300 8700 4800 8700 +Wire Wire Line + 4800 8700 4800 8500 +Wire Wire Line + 4800 8500 4900 8500 +Wire Wire Line + 4300 8900 4850 8900 +Wire Wire Line + 4850 8900 4850 8600 +Wire Wire Line + 4850 8600 4900 8600 +Wire Wire Line + 4300 9100 4900 9100 +Wire Wire Line + 4900 9100 4900 8700 +$Comp +L PORT U1 +U 9 1 667175F2 +P 18450 8450 +F 0 "U1" H 18500 8550 30 0000 C CNN +F 1 "PORT" H 18450 8450 30 0000 C CNN +F 2 "" H 18450 8450 60 0000 C CNN +F 3 "" H 18450 8450 60 0000 C CNN + 9 18450 8450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6671766D +P 18450 8300 +F 0 "U1" H 18500 8400 30 0000 C CNN +F 1 "PORT" H 18450 8300 30 0000 C CNN +F 2 "" H 18450 8300 60 0000 C CNN +F 3 "" H 18450 8300 60 0000 C CNN + 10 18450 8300 + -1 0 0 1 +$EndComp +Wire Wire Line + 18200 8300 17900 8300 +Wire Wire Line + 18200 8450 17900 8450 +Wire Wire Line + 17900 8450 17900 8400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub new file mode 100644 index 00000000..7800040c --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC.sub @@ -0,0 +1,102 @@ +* Subcircuit CD4078B_IC +.subckt CD4078B_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ +* d:\fossee\esim\library\subcircuitlibrary\cd4078b_ic\cd4078b_ic.cir +* u3 net-_u2-pad9_ net-_u11-pad1_ d_inverter +* u4 net-_u2-pad10_ net-_u11-pad2_ d_inverter +* u5 net-_u2-pad11_ net-_u12-pad1_ d_inverter +* u6 net-_u2-pad12_ net-_u12-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u13-pad1_ d_inverter +* u8 net-_u2-pad14_ net-_u13-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u21 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u21-pad3_ net-_u22-pad2_ d_inverter +* u24 net-_u22-pad2_ net-_u24-pad2_ d_inverter +* u23 net-_u21-pad3_ net-_u23-pad2_ d_inverter +* u25 net-_u24-pad2_ net-_u23-pad2_ net-_u1-pad10_ net-_u1-pad9_ dac_bridge_2 +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u12-pad3_ net-_u16-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad3_ net-_u19-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u14-pad1_ net-_u10-pad2_ net-_u14-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u14-pad3_ net-_u18-pad3_ d_nand +* u20 net-_u17-pad3_ net-_u18-pad3_ net-_u20-pad3_ d_nand +a1 net-_u2-pad9_ net-_u11-pad1_ u3 +a2 net-_u2-pad10_ net-_u11-pad2_ u4 +a3 net-_u2-pad11_ net-_u12-pad1_ u5 +a4 net-_u2-pad12_ net-_u12-pad2_ u6 +a5 net-_u2-pad13_ net-_u13-pad1_ u7 +a6 net-_u2-pad14_ net-_u13-pad2_ u8 +a7 net-_u2-pad15_ net-_u14-pad1_ u9 +a8 net-_u10-pad1_ net-_u10-pad2_ u10 +a9 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u21-pad3_ u21 +a10 net-_u21-pad3_ net-_u22-pad2_ u22 +a11 net-_u22-pad2_ net-_u24-pad2_ u24 +a12 net-_u21-pad3_ net-_u23-pad2_ u23 +a13 [net-_u24-pad2_ net-_u23-pad2_ ] [net-_u1-pad10_ net-_u1-pad9_ ] u25 +a14 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a15 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a17 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a18 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u16-pad3_ u16 +a19 [net-_u15-pad3_ net-_u16-pad3_ ] net-_u19-pad3_ u19 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a22 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a23 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u18-pad3_ u18 +a24 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u25 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends CD4078B_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml new file mode 100644 index 00000000..821bf547 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/CD4078B_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u10><u21 name="type">d_nor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u22><u24 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u24><u23 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u23><u25 name="type">dac_bridge<field37 name="Enter value for out_low (default=0.0)" /><field38 name="Enter value for out_high (default=5.0)" /><field39 name="Enter value for out_undef (default=0.5)" /><field40 name="Enter value for input load (default=1.0e-12)" /><field41 name="Enter the Rise Time (default=1.0e-9)" /><field42 name="Enter the Fall Time (default=1.0e-9)" /></u25><u2 name="type">adc_bridge<field43 name="Enter value for in_low (default=1.0)" /><field44 name="Enter value for in_high (default=2.0)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /><field46 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">d_nand<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u12><u15 name="type">d_nand<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_nand<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u16><u19 name="type">d_nand<field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /><field61 name="Enter Input Load (default=1.0e-12)" /></u19><u13 name="type">d_nand<field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /><field64 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /><field67 name="Enter Input Load (default=1.0e-12)" /></u14><u17 name="type">d_nand<field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /><field70 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nand<field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /><field73 name="Enter Input Load (default=1.0e-12)" /></u18><u20 name="type">d_nand<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u20></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4078B_sub/analysis b/library/SubcircuitLibrary/CD4078B_sub/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4078B_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and-cache.lib b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir b/library/SubcircuitLibrary/CD4532B/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.cir.out b/library/SubcircuitLibrary/CD4532B/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/3_and.pro b/library/SubcircuitLibrary/CD4532B/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sch b/library/SubcircuitLibrary/CD4532B/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/3_and.sub b/library/SubcircuitLibrary/CD4532B/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib new file mode 100644 index 00000000..155f5e60 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir b/library/SubcircuitLibrary/CD4532B/4_OR.cir new file mode 100644 index 00000000..b338b7b5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or +U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or +U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.cir.out b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out new file mode 100644 index 00000000..adb6b01b --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.pro b/library/SubcircuitLibrary/CD4532B/4_OR.pro new file mode 100644 index 00000000..881563eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=power +LibName2=eSim_Analog +LibName3=eSim_Devices +LibName4=eSim_Digital +LibName5=eSim_Hybrid +LibName6=eSim_Miscellaneous +LibName7=eSim_Plot +LibName8=eSim_Power +LibName9=eSim_User +LibName10=eSim_Sources +LibName11=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sch b/library/SubcircuitLibrary/CD4532B/4_OR.sch new file mode 100644 index 00000000..11896865 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_or U2 +U 1 1 5C9D00E1 +P 4300 2950 +F 0 "U2" H 4300 2950 60 0000 C CNN +F 1 "d_or" H 4300 3050 60 0000 C CNN +F 2 "" H 4300 2950 60 0000 C CNN +F 3 "" H 4300 2950 60 0000 C CNN + 1 4300 2950 + 1 0 0 -1 +$EndComp +$Comp +L d_or U3 +U 1 1 5C9D011F +P 4300 3350 +F 0 "U3" H 4300 3350 60 0000 C CNN +F 1 "d_or" H 4300 3450 60 0000 C CNN +F 2 "" H 4300 3350 60 0000 C CNN +F 3 "" H 4300 3350 60 0000 C CNN + 1 4300 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U4 +U 1 1 5C9D0141 +P 5250 3150 +F 0 "U4" H 5250 3150 60 0000 C CNN +F 1 "d_or" H 5250 3250 60 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 3050 4800 2900 +Wire Wire Line + 4800 2900 4750 2900 +Wire Wire Line + 4800 3150 4800 3300 +Wire Wire Line + 4800 3300 4750 3300 +Wire Wire Line + 3350 2850 3850 2850 +Wire Wire Line + 3850 2950 3600 2950 +Wire Wire Line + 3850 3250 3350 3250 +Wire Wire Line + 3600 2950 3600 3000 +Wire Wire Line + 3600 3000 3350 3000 +Wire Wire Line + 3850 3350 3850 3400 +Wire Wire Line + 3850 3400 3350 3400 +Wire Wire Line + 5700 3100 6200 3100 +$Comp +L PORT U1 +U 1 1 5C9D01F4 +P 3100 2850 +F 0 "U1" H 3150 2950 30 0000 C CNN +F 1 "PORT" H 3100 2850 30 0000 C CNN +F 2 "" H 3100 2850 60 0000 C CNN +F 3 "" H 3100 2850 60 0000 C CNN + 1 3100 2850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9D022F +P 3100 3000 +F 0 "U1" H 3150 3100 30 0000 C CNN +F 1 "PORT" H 3100 3000 30 0000 C CNN +F 2 "" H 3100 3000 60 0000 C CNN +F 3 "" H 3100 3000 60 0000 C CNN + 2 3100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9D0271 +P 3100 3250 +F 0 "U1" H 3150 3350 30 0000 C CNN +F 1 "PORT" H 3100 3250 30 0000 C CNN +F 2 "" H 3100 3250 60 0000 C CNN +F 3 "" H 3100 3250 60 0000 C CNN + 3 3100 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9D0299 +P 3100 3400 +F 0 "U1" H 3150 3500 30 0000 C CNN +F 1 "PORT" H 3100 3400 30 0000 C CNN +F 2 "" H 3100 3400 60 0000 C CNN +F 3 "" H 3100 3400 60 0000 C CNN + 4 3100 3400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9D02C2 +P 6450 3100 +F 0 "U1" H 6500 3200 30 0000 C CNN +F 1 "PORT" H 6450 3100 30 0000 C CNN +F 2 "" H 6450 3100 60 0000 C CNN +F 3 "" H 6450 3100 60 0000 C CNN + 5 6450 3100 + -1 0 0 1 +$EndComp +Text Notes 3450 2850 0 60 ~ 12 +in1 +Text Notes 3450 3000 0 60 ~ 12 +in2 +Text Notes 3450 3250 0 60 ~ 12 +in3 +Text Notes 3450 3400 0 60 ~ 12 +in4 +Text Notes 5800 3100 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_OR.sub b/library/SubcircuitLibrary/CD4532B/4_OR.sub new file mode 100644 index 00000000..d1fd3a24 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR +.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or +* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and-cache.lib b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir b/library/SubcircuitLibrary/CD4532B/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.cir.out b/library/SubcircuitLibrary/CD4532B/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/4_and.pro b/library/SubcircuitLibrary/CD4532B/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sch b/library/SubcircuitLibrary/CD4532B/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/4_and.sub b/library/SubcircuitLibrary/CD4532B/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib new file mode 100644 index 00000000..fbb8d926 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir b/library/SubcircuitLibrary/CD4532B/CD4532B.cir new file mode 100644 index 00000000..cd581690 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir @@ -0,0 +1,54 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\CD4532B\CD4532B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 20:14:54 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad11_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U4 Net-_U1-Pad13_ Net-_U4-Pad2_ d_inverter +U5 Net-_U1-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U1-Pad2_ Net-_U12-Pad1_ d_inverter +U8 Net-_U1-Pad3_ Net-_U13-Pad1_ d_inverter +U6 Net-_U1-Pad4_ Net-_U6-Pad2_ d_inverter +U9 Net-_U1-Pad5_ Net-_U14-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +X1 Net-_U2-Pad2_ Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U13-Pad2_ Net-_X1-Pad5_ 4_OR +X2 Net-_U13-Pad2_ Net-_U11-Pad2_ Net-_U4-Pad2_ ? Net-_X2-Pad5_ 4_OR +X3 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X3-Pad5_ 4_OR +X4 Net-_U4-Pad2_ Net-_U11-Pad2_ Net-_U12-Pad2_ ? Net-_X4-Pad5_ 4_OR +U22 Net-_U22-Pad1_ Net-_U16-Pad1_ d_inverter +U23 Net-_U23-Pad1_ Net-_U15-Pad1_ d_inverter +U24 Net-_U16-Pad1_ Net-_U15-Pad1_ Net-_U24-Pad3_ d_nand +X5 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U19-Pad3_ Net-_U6-Pad2_ Net-_U25-Pad1_ 4_and +X6 Net-_X3-Pad5_ Net-_X4-Pad5_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U27-Pad1_ 4_and +X7 Net-_U11-Pad1_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U6-Pad2_ Net-_U26-Pad1_ 4_and +U25 Net-_U25-Pad1_ Net-_U25-Pad2_ d_inverter +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ d_inverter +U26 Net-_U26-Pad1_ Net-_U26-Pad2_ d_inverter +U29 Net-_U25-Pad2_ Net-_U14-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U27-Pad2_ Net-_U14-Pad2_ Net-_U30-Pad3_ d_nand +U31 Net-_U26-Pad2_ Net-_U14-Pad2_ Net-_U31-Pad3_ d_nand +U32 Net-_U24-Pad3_ Net-_U1-Pad5_ Net-_U32-Pad3_ d_nand +U34 Net-_U29-Pad3_ Net-_U1-Pad9_ d_inverter +U33 Net-_U30-Pad3_ Net-_U1-Pad7_ d_inverter +U36 Net-_U31-Pad3_ Net-_U1-Pad6_ d_inverter +U37 Net-_U32-Pad3_ Net-_U1-Pad14_ d_inverter +U35 Net-_U20-Pad3_ Net-_U1-Pad15_ d_inverter +U19 Net-_U13-Pad2_ Net-_U12-Pad1_ Net-_U19-Pad3_ d_or +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT +X8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U22-Pad1_ 4_OR +X9 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U23-Pad1_ 4_OR +U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter +U17 Net-_U1-Pad5_ Net-_U17-Pad2_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U18 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_or +U20 Net-_U18-Pad3_ Net-_U17-Pad2_ Net-_U20-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out new file mode 100644 index 00000000..40e32465 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.cir.out @@ -0,0 +1,159 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir + +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.pro b/library/SubcircuitLibrary/CD4532B/CD4532B.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sch b/library/SubcircuitLibrary/CD4532B/CD4532B.sch new file mode 100644 index 00000000..626b76df --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sch @@ -0,0 +1,1074 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:CD4532B-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U2 +U 1 1 67A4FD25 +P 7050 4200 +F 0 "U2" H 7050 4100 60 0000 C CNN +F 1 "d_inverter" H 7050 4350 60 0000 C CNN +F 2 "" H 7100 4150 60 0000 C CNN +F 3 "" H 7100 4150 60 0000 C CNN + 1 7050 4200 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 67A4FD58 +P 7050 4850 +F 0 "U3" H 7050 4750 60 0000 C CNN +F 1 "d_inverter" H 7050 5000 60 0000 C CNN +F 2 "" H 7100 4800 60 0000 C CNN +F 3 "" H 7100 4800 60 0000 C CNN + 1 7050 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 67A4FD79 +P 7050 6350 +F 0 "U4" H 7050 6250 60 0000 C CNN +F 1 "d_inverter" H 7050 6500 60 0000 C CNN +F 2 "" H 7100 6300 60 0000 C CNN +F 3 "" H 7100 6300 60 0000 C CNN + 1 7050 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 67A4FDA4 +P 7050 7350 +F 0 "U5" H 7050 7250 60 0000 C CNN +F 1 "d_inverter" H 7050 7500 60 0000 C CNN +F 2 "" H 7100 7300 60 0000 C CNN +F 3 "" H 7100 7300 60 0000 C CNN + 1 7050 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 67A4FE34 +P 7100 8050 +F 0 "U7" H 7100 7950 60 0000 C CNN +F 1 "d_inverter" H 7100 8200 60 0000 C CNN +F 2 "" H 7150 8000 60 0000 C CNN +F 3 "" H 7150 8000 60 0000 C CNN + 1 7100 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U8 +U 1 1 67A4FE3A +P 7100 8700 +F 0 "U8" H 7100 8600 60 0000 C CNN +F 1 "d_inverter" H 7100 8850 60 0000 C CNN +F 2 "" H 7150 8650 60 0000 C CNN +F 3 "" H 7150 8650 60 0000 C CNN + 1 7100 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 67A4FE40 +P 7050 9300 +F 0 "U6" H 7050 9200 60 0000 C CNN +F 1 "d_inverter" H 7050 9450 60 0000 C CNN +F 2 "" H 7100 9250 60 0000 C CNN +F 3 "" H 7100 9250 60 0000 C CNN + 1 7050 9300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67A4FE4F +P 7150 11450 +F 0 "U9" H 7150 11350 60 0000 C CNN +F 1 "d_inverter" H 7150 11600 60 0000 C CNN +F 2 "" H 7200 11400 60 0000 C CNN +F 3 "" H 7200 11400 60 0000 C CNN + 1 7150 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U10 +U 1 1 67A4FF04 +P 8400 4850 +F 0 "U10" H 8400 4750 60 0000 C CNN +F 1 "d_inverter" H 8400 5000 60 0000 C CNN +F 2 "" H 8450 4800 60 0000 C CNN +F 3 "" H 8450 4800 60 0000 C CNN + 1 8400 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U11 +U 1 1 67A4FF41 +P 8400 7350 +F 0 "U11" H 8400 7250 60 0000 C CNN +F 1 "d_inverter" H 8400 7500 60 0000 C CNN +F 2 "" H 8450 7300 60 0000 C CNN +F 3 "" H 8450 7300 60 0000 C CNN + 1 8400 7350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U12 +U 1 1 67A4FF6C +P 8400 8050 +F 0 "U12" H 8400 7950 60 0000 C CNN +F 1 "d_inverter" H 8400 8200 60 0000 C CNN +F 2 "" H 8450 8000 60 0000 C CNN +F 3 "" H 8450 8000 60 0000 C CNN + 1 8400 8050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U13 +U 1 1 67A4FF9D +P 8400 8700 +F 0 "U13" H 8400 8600 60 0000 C CNN +F 1 "d_inverter" H 8400 8850 60 0000 C CNN +F 2 "" H 8450 8650 60 0000 C CNN +F 3 "" H 8450 8650 60 0000 C CNN + 1 8400 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U14 +U 1 1 67A4FFE2 +P 8550 11450 +F 0 "U14" H 8550 11350 60 0000 C CNN +F 1 "d_inverter" H 8550 11600 60 0000 C CNN +F 2 "" H 8600 11400 60 0000 C CNN +F 3 "" H 8600 11400 60 0000 C CNN + 1 8550 11450 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X1 +U 1 1 67A500F9 +P 10400 4300 +F 0 "X1" H 10550 4200 60 0000 C CNN +F 1 "4_OR" H 10550 4400 60 0000 C CNN +F 2 "" H 10400 4300 60 0000 C CNN +F 3 "" H 10400 4300 60 0000 C CNN + 1 10400 4300 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X2 +U 1 1 67A5B522 +P 10400 5150 +F 0 "X2" H 10550 5050 60 0000 C CNN +F 1 "4_OR" H 10550 5250 60 0000 C CNN +F 2 "" H 10400 5150 60 0000 C CNN +F 3 "" H 10400 5150 60 0000 C CNN + 1 10400 5150 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X3 +U 1 1 67A5B8C6 +P 10400 7350 +F 0 "X3" H 10550 7250 60 0000 C CNN +F 1 "4_OR" H 10550 7450 60 0000 C CNN +F 2 "" H 10400 7350 60 0000 C CNN +F 3 "" H 10400 7350 60 0000 C CNN + 1 10400 7350 + 1 0 0 -1 +$EndComp +$Comp +L 4_OR X4 +U 1 1 67A5B911 +P 10400 8400 +F 0 "X4" H 10550 8300 60 0000 C CNN +F 1 "4_OR" H 10550 8500 60 0000 C CNN +F 2 "" H 10400 8400 60 0000 C CNN +F 3 "" H 10400 8400 60 0000 C CNN + 1 10400 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A5BD44 +P 11550 9600 +F 0 "U22" H 11550 9500 60 0000 C CNN +F 1 "d_inverter" H 11550 9750 60 0000 C CNN +F 2 "" H 11600 9550 60 0000 C CNN +F 3 "" H 11600 9550 60 0000 C CNN + 1 11550 9600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A5BDD7 +P 11650 10300 +F 0 "U23" H 11650 10200 60 0000 C CNN +F 1 "d_inverter" H 11650 10450 60 0000 C CNN +F 2 "" H 11700 10250 60 0000 C CNN +F 3 "" H 11700 10250 60 0000 C CNN + 1 11650 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U24 +U 1 1 67A5BEDF +P 13350 9650 +F 0 "U24" H 13350 9650 60 0000 C CNN +F 1 "d_nand" H 13400 9750 60 0000 C CNN +F 2 "" H 13350 9650 60 0000 C CNN +F 3 "" H 13350 9650 60 0000 C CNN + 1 13350 9650 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X5 +U 1 1 67A5BF59 +P 12500 4600 +F 0 "X5" H 12550 4550 60 0000 C CNN +F 1 "4_and" H 12600 4700 60 0000 C CNN +F 2 "" H 12500 4600 60 0000 C CNN +F 3 "" H 12500 4600 60 0000 C CNN + 1 12500 4600 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X6 +U 1 1 67A5BFC2 +P 12550 6050 +F 0 "X6" H 12600 6000 60 0000 C CNN +F 1 "4_and" H 12650 6150 60 0000 C CNN +F 2 "" H 12550 6050 60 0000 C CNN +F 3 "" H 12550 6050 60 0000 C CNN + 1 12550 6050 + 1 0 0 -1 +$EndComp +$Comp +L 4_and X7 +U 1 1 67A5C035 +P 12550 7900 +F 0 "X7" H 12600 7850 60 0000 C CNN +F 1 "4_and" H 12650 8000 60 0000 C CNN +F 2 "" H 12550 7900 60 0000 C CNN +F 3 "" H 12550 7900 60 0000 C CNN + 1 12550 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U25 +U 1 1 67A5C183 +P 13500 4600 +F 0 "U25" H 13500 4500 60 0000 C CNN +F 1 "d_inverter" H 13500 4750 60 0000 C CNN +F 2 "" H 13550 4550 60 0000 C CNN +F 3 "" H 13550 4550 60 0000 C CNN + 1 13500 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 67A5C189 +P 13650 6050 +F 0 "U27" H 13650 5950 60 0000 C CNN +F 1 "d_inverter" H 13650 6200 60 0000 C CNN +F 2 "" H 13700 6000 60 0000 C CNN +F 3 "" H 13700 6000 60 0000 C CNN + 1 13650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U26 +U 1 1 67A5C18F +P 13600 7900 +F 0 "U26" H 13600 7800 60 0000 C CNN +F 1 "d_inverter" H 13600 8050 60 0000 C CNN +F 2 "" H 13650 7850 60 0000 C CNN +F 3 "" H 13650 7850 60 0000 C CNN + 1 13600 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U29 +U 1 1 67A5C873 +P 15300 4900 +F 0 "U29" H 15300 4900 60 0000 C CNN +F 1 "d_nand" H 15350 5000 60 0000 C CNN +F 2 "" H 15300 4900 60 0000 C CNN +F 3 "" H 15300 4900 60 0000 C CNN + 1 15300 4900 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U30 +U 1 1 67A5C90C +P 15300 6800 +F 0 "U30" H 15300 6800 60 0000 C CNN +F 1 "d_nand" H 15350 6900 60 0000 C CNN +F 2 "" H 15300 6800 60 0000 C CNN +F 3 "" H 15300 6800 60 0000 C CNN + 1 15300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 67A5C99B +P 15350 8550 +F 0 "U31" H 15350 8550 60 0000 C CNN +F 1 "d_nand" H 15400 8650 60 0000 C CNN +F 2 "" H 15350 8550 60 0000 C CNN +F 3 "" H 15350 8550 60 0000 C CNN + 1 15350 8550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 67A5CA32 +P 15400 10350 +F 0 "U32" H 15400 10350 60 0000 C CNN +F 1 "d_nand" H 15450 10450 60 0000 C CNN +F 2 "" H 15400 10350 60 0000 C CNN +F 3 "" H 15400 10350 60 0000 C CNN + 1 15400 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67A5CB45 +P 16750 4850 +F 0 "U34" H 16750 4750 60 0000 C CNN +F 1 "d_inverter" H 16750 5000 60 0000 C CNN +F 2 "" H 16800 4800 60 0000 C CNN +F 3 "" H 16800 4800 60 0000 C CNN + 1 16750 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U33 +U 1 1 67A5CB4B +P 16700 6750 +F 0 "U33" H 16700 6650 60 0000 C CNN +F 1 "d_inverter" H 16700 6900 60 0000 C CNN +F 2 "" H 16750 6700 60 0000 C CNN +F 3 "" H 16750 6700 60 0000 C CNN + 1 16700 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67A5CB51 +P 16800 8500 +F 0 "U36" H 16800 8400 60 0000 C CNN +F 1 "d_inverter" H 16800 8650 60 0000 C CNN +F 2 "" H 16850 8450 60 0000 C CNN +F 3 "" H 16850 8450 60 0000 C CNN + 1 16800 8500 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 67A5CB57 +P 16800 10300 +F 0 "U37" H 16800 10200 60 0000 C CNN +F 1 "d_inverter" H 16800 10450 60 0000 C CNN +F 2 "" H 16850 10250 60 0000 C CNN +F 3 "" H 16850 10250 60 0000 C CNN + 1 16800 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U35 +U 1 1 67A5CB5D +P 16750 10900 +F 0 "U35" H 16750 10800 60 0000 C CNN +F 1 "d_inverter" H 16750 11050 60 0000 C CNN +F 2 "" H 16800 10850 60 0000 C CNN +F 3 "" H 16800 10850 60 0000 C CNN + 1 16750 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A5EBCA +P 10650 6200 +F 0 "U19" H 10650 6200 60 0000 C CNN +F 1 "d_or" H 10650 6300 60 0000 C CNN +F 2 "" H 10650 6200 60 0000 C CNN +F 3 "" H 10650 6200 60 0000 C CNN + 1 10650 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 4200 4450 4200 +Wire Wire Line + 6750 4850 4400 4850 +Wire Wire Line + 6750 6350 4350 6350 +Wire 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-1 +$EndComp +$Comp +L PORT U1 +U 12 1 67A671AB +P 4150 4850 +F 0 "U1" H 4200 4950 30 0000 C CNN +F 1 "PORT" H 4150 4850 30 0000 C CNN +F 2 "" H 4150 4850 60 0000 C CNN +F 3 "" H 4150 4850 60 0000 C CNN + 12 4150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67A673CE +P 4100 6350 +F 0 "U1" H 4150 6450 30 0000 C CNN +F 1 "PORT" H 4100 6350 30 0000 C CNN +F 2 "" H 4100 6350 60 0000 C CNN +F 3 "" H 4100 6350 60 0000 C CNN + 13 4100 6350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67A675BD +P 4050 7350 +F 0 "U1" H 4100 7450 30 0000 C CNN +F 1 "PORT" H 4050 7350 30 0000 C CNN +F 2 "" H 4050 7350 60 0000 C CNN +F 3 "" H 4050 7350 60 0000 C CNN + 1 4050 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67A67752 +P 3950 8050 +F 0 "U1" H 4000 8150 30 0000 C CNN +F 1 "PORT" H 3950 8050 30 0000 C CNN +F 2 "" H 3950 8050 60 0000 C CNN +F 3 "" H 3950 8050 60 0000 C CNN + 2 3950 8050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67A67986 +P 3950 8700 +F 0 "U1" H 4000 8800 30 0000 C CNN +F 1 "PORT" H 3950 8700 30 0000 C CNN +F 2 "" H 3950 8700 60 0000 C CNN +F 3 "" H 3950 8700 60 0000 C CNN + 3 3950 8700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67A67BC3 +P 3950 9300 +F 0 "U1" H 4000 9400 30 0000 C CNN +F 1 "PORT" H 3950 9300 30 0000 C CNN +F 2 "" H 3950 9300 60 0000 C CNN +F 3 "" H 3950 9300 60 0000 C CNN + 4 3950 9300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67A67DDA +P 3400 10500 +F 0 "U1" H 3450 10600 30 0000 C CNN +F 1 "PORT" H 3400 10500 30 0000 C CNN +F 2 "" H 3400 10500 60 0000 C CNN +F 3 "" H 3400 10500 60 0000 C CNN + 10 3400 10500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67A67EF9 +P 3200 11450 +F 0 "U1" H 3250 11550 30 0000 C CNN +F 1 "PORT" H 3200 11450 30 0000 C CNN +F 2 "" H 3200 11450 60 0000 C CNN +F 3 "" H 3200 11450 60 0000 C CNN + 5 3200 11450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67A681F4 +P 18200 4850 +F 0 "U1" H 18250 4950 30 0000 C CNN +F 1 "PORT" H 18200 4850 30 0000 C CNN +F 2 "" H 18200 4850 60 0000 C CNN +F 3 "" H 18200 4850 60 0000 C CNN + 9 18200 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 67A68454 +P 18750 6750 +F 0 "U1" H 18800 6850 30 0000 C CNN +F 1 "PORT" H 18750 6750 30 0000 C CNN +F 2 "" H 18750 6750 60 0000 C CNN +F 3 "" H 18750 6750 60 0000 C CNN + 7 18750 6750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 67A68779 +P 18800 8500 +F 0 "U1" H 18850 8600 30 0000 C CNN +F 1 "PORT" H 18800 8500 30 0000 C CNN +F 2 "" H 18800 8500 60 0000 C CNN +F 3 "" H 18800 8500 60 0000 C CNN + 6 18800 8500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 67A68A78 +P 18850 10300 +F 0 "U1" H 18900 10400 30 0000 C CNN +F 1 "PORT" H 18850 10300 30 0000 C CNN +F 2 "" H 18850 10300 60 0000 C CNN +F 3 "" H 18850 10300 60 0000 C CNN + 14 18850 10300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 15 1 67A68BEF +P 18850 10900 +F 0 "U1" H 18900 11000 30 0000 C CNN +F 1 "PORT" H 18850 10900 30 0000 C CNN +F 2 "" H 18850 10900 60 0000 C CNN +F 3 "" H 18850 10900 60 0000 C CNN + 15 18850 10900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67A68CDF +P 18650 9150 +F 0 "U1" H 18700 9250 30 0000 C CNN +F 1 "PORT" H 18650 9150 30 0000 C CNN +F 2 "" H 18650 9150 60 0000 C CNN +F 3 "" H 18650 9150 60 0000 C CNN + 8 18650 9150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67A68D6C +P 18650 9350 +F 0 "U1" H 18700 9450 30 0000 C CNN +F 1 "PORT" H 18650 9350 30 0000 C CNN +F 2 "" H 18650 9350 60 0000 C CNN +F 3 "" H 18650 9350 60 0000 C CNN + 16 18650 9350 + 1 0 0 -1 +$EndComp +NoConn ~ 18900 9150 +NoConn ~ 18900 9350 +$Comp +L 4_OR X8 +U 1 1 67AA119F +P 10550 9600 +F 0 "X8" H 10700 9500 60 0000 C CNN +F 1 "4_OR" H 10700 9700 60 0000 C CNN +F 2 "" H 10550 9600 60 0000 C CNN +F 3 "" H 10550 9600 60 0000 C CNN + 1 10550 9600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10200 9700 10200 9650 +Wire Wire Line + 10200 9800 10200 9750 +$Comp +L 4_OR X9 +U 1 1 67AA15F9 +P 10600 10300 +F 0 "X9" H 10750 10200 60 0000 C CNN +F 1 "4_OR" H 10750 10400 60 0000 C CNN +F 2 "" H 10600 10300 60 0000 C CNN +F 3 "" H 10600 10300 60 0000 C CNN + 1 10600 10300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10250 10350 10100 10350 +Wire Wire Line + 10100 10350 10100 10400 +Wire Wire Line + 10250 10500 10250 10450 +Wire Wire Line + 11250 9600 11100 9600 +Wire Wire Line + 11350 10300 11150 10300 +$Comp +L d_inverter U16 +U 1 1 67AA23A3 +P 12750 10700 +F 0 "U16" H 12750 10600 60 0000 C CNN +F 1 "d_inverter" H 12750 10850 60 0000 C CNN +F 2 "" H 12800 10650 60 0000 C CNN +F 3 "" H 12800 10650 60 0000 C CNN + 1 12750 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U17 +U 1 1 67AA2430 +P 12750 11050 +F 0 "U17" H 12750 10950 60 0000 C CNN +F 1 "d_inverter" H 12750 11200 60 0000 C CNN +F 2 "" H 12800 11000 60 0000 C CNN +F 3 "" H 12800 11000 60 0000 C CNN + 1 12750 11050 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U15 +U 1 1 67AA24BF +P 12750 10350 +F 0 "U15" H 12750 10250 60 0000 C CNN +F 1 "d_inverter" H 12750 10500 60 0000 C CNN +F 2 "" H 12800 10300 60 0000 C CNN +F 3 "" H 12800 10300 60 0000 C CNN + 1 12750 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67AA2582 +P 13650 10500 +F 0 "U18" H 13650 10500 60 0000 C CNN +F 1 "d_or" H 13650 10600 60 0000 C CNN +F 2 "" H 13650 10500 60 0000 C CNN +F 3 "" H 13650 10500 60 0000 C CNN + 1 13650 10500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67AA2694 +P 14200 10950 +F 0 "U20" H 14200 10950 60 0000 C CNN +F 1 "d_or" H 14200 11050 60 0000 C CNN +F 2 "" H 14200 10950 60 0000 C CNN +F 3 "" H 14200 10950 60 0000 C CNN + 1 14200 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 10450 14200 10450 +Wire Wire Line + 14200 10450 14200 10700 +Wire Wire Line + 14200 10700 13650 10700 +Wire Wire Line + 13650 10700 13650 10850 +Wire Wire Line + 13650 10850 13750 10850 +Wire Wire Line + 13050 10350 13200 10350 +Wire Wire Line + 13200 10350 13200 10400 +Wire Wire Line + 13200 10500 13200 10700 +Wire Wire Line + 13200 10700 13050 10700 +Wire Wire Line + 13050 11050 13650 11050 +Wire Wire Line + 13650 11050 13650 10950 +Wire Wire Line + 13650 10950 13750 10950 +Wire Wire Line + 6400 11050 12450 11050 +Wire Wire Line + 6400 11050 6400 11450 +Wire Wire Line + 11950 11050 11950 11250 +Wire Wire Line + 11950 11250 14800 11250 +Connection ~ 11950 11050 +Wire Wire Line + 14950 10350 14800 10350 +Wire Wire Line + 14800 10350 14800 11250 +Wire Wire Line + 11850 9600 12300 9600 +Wire Wire Line + 12300 9600 12300 9550 +Wire Wire Line + 12300 9550 12900 9550 +Wire Wire Line + 11950 10300 12250 10300 +Wire Wire Line + 12250 9950 12250 10350 +Wire Wire Line + 12250 9950 12650 9950 +Wire Wire Line + 12650 9950 12650 9650 +Wire Wire Line + 12650 9650 12900 9650 +Wire Wire Line + 12250 10350 12450 10350 +Connection ~ 12250 10300 +Wire Wire Line + 12100 9600 12100 10700 +Wire Wire Line + 12100 10700 12450 10700 +Connection ~ 12100 9600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B.sub b/library/SubcircuitLibrary/CD4532B/CD4532B.sub new file mode 100644 index 00000000..4f812629 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B.sub @@ -0,0 +1,153 @@ +* Subcircuit CD4532B +.subckt CD4532B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\cd4532b\cd4532b.cir +.include 4_and.sub +.include 4_OR.sub +* u2 net-_u1-pad11_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u4 net-_u1-pad13_ net-_u4-pad2_ d_inverter +* u5 net-_u1-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u1-pad2_ net-_u12-pad1_ d_inverter +* u8 net-_u1-pad3_ net-_u13-pad1_ d_inverter +* u6 net-_u1-pad4_ net-_u6-pad2_ d_inverter +* u9 net-_u1-pad5_ net-_u14-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +x1 net-_u2-pad2_ net-_u10-pad2_ net-_u11-pad2_ net-_u13-pad2_ net-_x1-pad5_ 4_OR +x2 net-_u13-pad2_ net-_u11-pad2_ net-_u4-pad2_ ? net-_x2-pad5_ 4_OR +x3 net-_u10-pad1_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x3-pad5_ 4_OR +x4 net-_u4-pad2_ net-_u11-pad2_ net-_u12-pad2_ ? net-_x4-pad5_ 4_OR +* u22 net-_u22-pad1_ net-_u16-pad1_ d_inverter +* u23 net-_u23-pad1_ net-_u15-pad1_ d_inverter +* u24 net-_u16-pad1_ net-_u15-pad1_ net-_u24-pad3_ d_nand +x5 net-_x1-pad5_ net-_x2-pad5_ net-_u19-pad3_ net-_u6-pad2_ net-_u25-pad1_ 4_and +x6 net-_x3-pad5_ net-_x4-pad5_ net-_u13-pad1_ net-_u6-pad2_ net-_u27-pad1_ 4_and +x7 net-_u11-pad1_ net-_u12-pad1_ net-_u13-pad1_ net-_u6-pad2_ net-_u26-pad1_ 4_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u29 net-_u25-pad2_ net-_u14-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u27-pad2_ net-_u14-pad2_ net-_u30-pad3_ d_nand +* u31 net-_u26-pad2_ net-_u14-pad2_ net-_u31-pad3_ d_nand +* u32 net-_u24-pad3_ net-_u1-pad5_ net-_u32-pad3_ d_nand +* u34 net-_u29-pad3_ net-_u1-pad9_ d_inverter +* u33 net-_u30-pad3_ net-_u1-pad7_ d_inverter +* u36 net-_u31-pad3_ net-_u1-pad6_ d_inverter +* u37 net-_u32-pad3_ net-_u1-pad14_ d_inverter +* u35 net-_u20-pad3_ net-_u1-pad15_ d_inverter +* u19 net-_u13-pad2_ net-_u12-pad1_ net-_u19-pad3_ d_or +x8 net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad2_ net-_u1-pad1_ net-_u22-pad1_ 4_OR +x9 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad10_ net-_u23-pad1_ 4_OR +* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter +* u17 net-_u1-pad5_ net-_u17-pad2_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u18 net-_u15-pad2_ net-_u16-pad2_ net-_u18-pad3_ d_or +* u20 net-_u18-pad3_ net-_u17-pad2_ net-_u20-pad3_ d_or +a1 net-_u1-pad11_ net-_u2-pad2_ u2 +a2 net-_u1-pad12_ net-_u10-pad1_ u3 +a3 net-_u1-pad13_ net-_u4-pad2_ u4 +a4 net-_u1-pad1_ net-_u11-pad1_ u5 +a5 net-_u1-pad2_ net-_u12-pad1_ u7 +a6 net-_u1-pad3_ net-_u13-pad1_ u8 +a7 net-_u1-pad4_ net-_u6-pad2_ u6 +a8 net-_u1-pad5_ net-_u14-pad1_ u9 +a9 net-_u10-pad1_ net-_u10-pad2_ u10 +a10 net-_u11-pad1_ net-_u11-pad2_ u11 +a11 net-_u12-pad1_ net-_u12-pad2_ u12 +a12 net-_u13-pad1_ net-_u13-pad2_ u13 +a13 net-_u14-pad1_ net-_u14-pad2_ u14 +a14 net-_u22-pad1_ net-_u16-pad1_ u22 +a15 net-_u23-pad1_ net-_u15-pad1_ u23 +a16 [net-_u16-pad1_ net-_u15-pad1_ ] net-_u24-pad3_ u24 +a17 net-_u25-pad1_ net-_u25-pad2_ u25 +a18 net-_u27-pad1_ net-_u27-pad2_ u27 +a19 net-_u26-pad1_ net-_u26-pad2_ u26 +a20 [net-_u25-pad2_ net-_u14-pad2_ ] net-_u29-pad3_ u29 +a21 [net-_u27-pad2_ net-_u14-pad2_ ] net-_u30-pad3_ u30 +a22 [net-_u26-pad2_ net-_u14-pad2_ ] net-_u31-pad3_ u31 +a23 [net-_u24-pad3_ net-_u1-pad5_ ] net-_u32-pad3_ u32 +a24 net-_u29-pad3_ net-_u1-pad9_ u34 +a25 net-_u30-pad3_ net-_u1-pad7_ u33 +a26 net-_u31-pad3_ net-_u1-pad6_ u36 +a27 net-_u32-pad3_ net-_u1-pad14_ u37 +a28 net-_u20-pad3_ net-_u1-pad15_ u35 +a29 [net-_u13-pad2_ net-_u12-pad1_ ] net-_u19-pad3_ u19 +a30 net-_u16-pad1_ net-_u16-pad2_ u16 +a31 net-_u1-pad5_ net-_u17-pad2_ u17 +a32 net-_u15-pad1_ net-_u15-pad2_ u15 +a33 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a34 [net-_u18-pad3_ net-_u17-pad2_ ] net-_u20-pad3_ u20 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends CD4532B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml new file mode 100644 index 00000000..cd7a8a8d --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/CD4532B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_inverter<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Rise Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Rise Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Rise Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_inverter<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Rise Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_inverter<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Rise Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u6 name="type">d_inverter<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Rise Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Rise Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Rise Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Rise Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Rise Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_inverter<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Rise Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u16><u22 name="type">d_inverter<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u22><u17 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u18><u23 name="type">d_inverter<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Rise Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u27 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Rise Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u27><u26 name="type">d_inverter<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Rise Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u26><u28 name="type">d_inverter<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Rise Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_nand<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u32><u34 name="type">d_inverter<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u34><u33 name="type">d_inverter<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u33><u36 name="type">d_inverter<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u36><u37 name="type">d_inverter<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u37><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u35><u19 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_or<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u21><u38 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u16 name="type">d_inverter<field88 name="Enter Input Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_inverter<field91 name="Enter Input Load (default=1.0e-12)" /><field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u17><u15 name="type">d_inverter<field94 name="Enter Input Load (default=1.0e-12)" /><field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x8><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x3><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x5><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x9><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x6></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4532B/analysis b/library/SubcircuitLibrary/CD4532B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4532B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib new file mode 100644 index 00000000..cca13acf --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir new file mode 100644 index 00000000..dc30556f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir @@ -0,0 +1,57 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4556BMS_IC\CD4556BMS_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/24 15:55:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad4_ Net-_U10-Pad1_ d_inverter +U4 Net-_U2-Pad5_ Net-_U4-Pad2_ d_inverter +U5 Net-_U2-Pad6_ Net-_U16-Pad2_ d_inverter +U6 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U4-Pad2_ Net-_U10-Pad2_ d_inverter +U8 Net-_U10-Pad1_ Net-_U4-Pad2_ Net-_U12-Pad1_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad1_ Net-_U12-Pad3_ d_nand +U16 Net-_U12-Pad3_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand +U9 Net-_U11-Pad1_ Net-_U4-Pad2_ Net-_U13-Pad1_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad1_ Net-_U13-Pad3_ d_nand +U17 Net-_U13-Pad3_ Net-_U16-Pad2_ Net-_U17-Pad3_ d_nand +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U14 Net-_U10-Pad3_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_nand +U18 Net-_U14-Pad3_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nand +U15 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U19 Net-_U15-Pad3_ Net-_U16-Pad2_ Net-_U19-Pad3_ d_nand +U20 Net-_U16-Pad3_ Net-_U20-Pad2_ d_inverter +U21 Net-_U17-Pad3_ Net-_U21-Pad2_ d_inverter +U22 Net-_U18-Pad3_ Net-_U22-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U23-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ adc_bridge_3 +U24 Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ dac_bridge_4 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U26 Net-_U25-Pad4_ Net-_U26-Pad2_ d_inverter +U27 Net-_U25-Pad5_ Net-_U27-Pad2_ d_inverter +U28 Net-_U25-Pad6_ Net-_U28-Pad2_ d_inverter +U29 Net-_U26-Pad2_ Net-_U29-Pad2_ d_inverter +U30 Net-_U27-Pad2_ Net-_U30-Pad2_ d_inverter +U31 Net-_U26-Pad2_ Net-_U27-Pad2_ Net-_U31-Pad3_ d_nand +U35 Net-_U31-Pad3_ Net-_U31-Pad3_ Net-_U35-Pad3_ d_nand +U39 Net-_U35-Pad3_ Net-_U28-Pad2_ Net-_U39-Pad3_ d_nand +U32 Net-_U29-Pad2_ Net-_U27-Pad2_ Net-_U32-Pad3_ d_nand +U36 Net-_U32-Pad3_ Net-_U32-Pad3_ Net-_U36-Pad3_ d_nand +U40 Net-_U36-Pad3_ Net-_U28-Pad2_ Net-_U40-Pad3_ d_nand +U33 Net-_U26-Pad2_ Net-_U30-Pad2_ Net-_U33-Pad3_ d_nand +U37 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U37-Pad3_ d_nand +U41 Net-_U37-Pad3_ Net-_U28-Pad2_ Net-_U41-Pad3_ d_nand +U34 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U34-Pad3_ d_nand +U38 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U38-Pad3_ d_nand +U42 Net-_U38-Pad3_ Net-_U28-Pad2_ Net-_U42-Pad3_ d_nand +U43 Net-_U39-Pad3_ Net-_U43-Pad2_ d_inverter +U44 Net-_U40-Pad3_ Net-_U44-Pad2_ d_inverter +U45 Net-_U41-Pad3_ Net-_U45-Pad2_ d_inverter +U46 Net-_U42-Pad3_ Net-_U46-Pad2_ d_inverter +U25 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U25-Pad4_ Net-_U25-Pad5_ Net-_U25-Pad6_ adc_bridge_3 +U47 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U46-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ dac_bridge_4 + +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out new file mode 100644 index 00000000..d1117c7b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out @@ -0,0 +1,196 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir + +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch new file mode 100644 index 00000000..7cdf8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch @@ -0,0 +1,1129 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4556BMS-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 6672B0FB +P 4050 4000 +F 0 "U3" H 4050 3900 60 0000 C CNN +F 1 "d_inverter" H 4050 4150 60 0000 C CNN +F 2 "" H 4100 3950 60 0000 C CNN +F 3 "" H 4100 3950 60 0000 C CNN + 1 4050 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6672B0FC +P 4050 4650 +F 0 "U4" H 4050 4550 60 0000 C CNN +F 1 "d_inverter" H 4050 4800 60 0000 C CNN +F 2 "" H 4100 4600 60 0000 C CNN +F 3 "" H 4100 4600 60 0000 C CNN + 1 4050 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6672B0FD +P 4050 6450 +F 0 "U5" H 4050 6350 60 0000 C CNN +F 1 "d_inverter" H 4050 6600 60 0000 C CNN +F 2 "" H 4100 6400 60 0000 C CNN +F 3 "" H 4100 6400 60 0000 C CNN + 1 4050 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6672B0FE +P 5000 4000 +F 0 "U6" H 5000 3900 60 0000 C CNN +F 1 "d_inverter" H 5000 4150 60 0000 C CNN +F 2 "" H 5050 3950 60 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5000 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6672B0FF +P 5050 4650 +F 0 "U7" H 5050 4550 60 0000 C CNN +F 1 "d_inverter" H 5050 4800 60 0000 C CNN +F 2 "" H 5100 4600 60 0000 C CNN +F 3 "" H 5100 4600 60 0000 C CNN + 1 5050 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4000 4700 4000 +Wire Wire Line + 4350 4650 4750 4650 +$Comp +L d_nand U8 +U 1 1 6672B100 +P 6600 4050 +F 0 "U8" H 6600 4050 60 0000 C CNN +F 1 "d_nand" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 6672B101 +P 7800 4050 +F 0 "U12" H 7800 4050 60 0000 C CNN +F 1 "d_nand" H 7850 4150 60 0000 C CNN +F 2 "" H 7800 4050 60 0000 C CNN +F 3 "" H 7800 4050 60 0000 C CNN + 1 7800 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 6672B102 +P 9000 4150 +F 0 "U16" H 9000 4150 60 0000 C CNN +F 1 "d_nand" H 9050 4250 60 0000 C CNN +F 2 "" H 9000 4150 60 0000 C CNN +F 3 "" H 9000 4150 60 0000 C CNN + 1 9000 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 4050 8500 4050 +Wire Wire Line + 8500 4050 8500 4000 +Wire Wire Line + 8500 4000 8250 4000 +Wire Wire Line + 7350 3950 7250 3950 +Wire Wire Line + 7250 3950 7250 4050 +Wire Wire Line + 7250 4050 7350 4050 +Wire Wire Line + 7050 4000 7250 4000 +Connection ~ 7250 4000 +$Comp +L d_nand U9 +U 1 1 6672B103 +P 6600 4650 +F 0 "U9" H 6600 4650 60 0000 C CNN +F 1 "d_nand" H 6650 4750 60 0000 C CNN +F 2 "" H 6600 4650 60 0000 C CNN +F 3 "" H 6600 4650 60 0000 C CNN + 1 6600 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 6672B104 +P 7800 4650 +F 0 "U13" H 7800 4650 60 0000 C CNN +F 1 "d_nand" H 7850 4750 60 0000 C CNN +F 2 "" H 7800 4650 60 0000 C CNN +F 3 "" H 7800 4650 60 0000 C CNN + 1 7800 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 6672B105 +P 9000 4750 +F 0 "U17" H 9000 4750 60 0000 C CNN +F 1 "d_nand" H 9050 4850 60 0000 C CNN +F 2 "" H 9000 4750 60 0000 C CNN +F 3 "" H 9000 4750 60 0000 C CNN + 1 9000 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 4650 8500 4650 +Wire Wire Line + 8500 4650 8500 4600 +Wire Wire Line + 8500 4600 8250 4600 +Wire Wire Line + 7350 4550 7250 4550 +Wire Wire Line + 7250 4550 7250 4650 +Wire Wire Line + 7250 4650 7350 4650 +Wire Wire Line + 7050 4600 7250 4600 +Connection ~ 7250 4600 +$Comp +L d_nand U10 +U 1 1 6672B106 +P 6600 5350 +F 0 "U10" H 6600 5350 60 0000 C CNN +F 1 "d_nand" H 6650 5450 60 0000 C CNN +F 2 "" H 6600 5350 60 0000 C CNN +F 3 "" H 6600 5350 60 0000 C CNN + 1 6600 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 6672B107 +P 7800 5350 +F 0 "U14" H 7800 5350 60 0000 C CNN +F 1 "d_nand" H 7850 5450 60 0000 C CNN +F 2 "" H 7800 5350 60 0000 C CNN +F 3 "" H 7800 5350 60 0000 C CNN + 1 7800 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 6672B108 +P 9000 5450 +F 0 "U18" H 9000 5450 60 0000 C CNN +F 1 "d_nand" H 9050 5550 60 0000 C CNN +F 2 "" H 9000 5450 60 0000 C CNN +F 3 "" H 9000 5450 60 0000 C CNN + 1 9000 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 5350 8500 5350 +Wire Wire Line + 8500 5350 8500 5300 +Wire Wire Line + 8500 5300 8250 5300 +Wire Wire Line + 7350 5250 7250 5250 +Wire Wire Line + 7250 5250 7250 5350 +Wire Wire Line + 7250 5350 7350 5350 +Wire Wire Line + 7050 5300 7250 5300 +Connection ~ 7250 5300 +$Comp +L d_nand U11 +U 1 1 6672B109 +P 6600 6050 +F 0 "U11" H 6600 6050 60 0000 C CNN +F 1 "d_nand" H 6650 6150 60 0000 C CNN +F 2 "" H 6600 6050 60 0000 C CNN +F 3 "" H 6600 6050 60 0000 C CNN + 1 6600 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 6672B10A +P 7800 6050 +F 0 "U15" H 7800 6050 60 0000 C CNN +F 1 "d_nand" H 7850 6150 60 0000 C CNN +F 2 "" H 7800 6050 60 0000 C CNN +F 3 "" H 7800 6050 60 0000 C CNN + 1 7800 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 6672B10B +P 9000 6150 +F 0 "U19" H 9000 6150 60 0000 C CNN +F 1 "d_nand" H 9050 6250 60 0000 C CNN +F 2 "" H 9000 6150 60 0000 C CNN +F 3 "" H 9000 6150 60 0000 C CNN + 1 9000 6150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 6050 8500 6050 +Wire Wire Line + 8500 6050 8500 6000 +Wire Wire Line + 8500 6000 8250 6000 +Wire Wire Line + 7350 5950 7250 5950 +Wire Wire Line + 7250 5950 7250 6050 +Wire Wire Line + 7250 6050 7350 6050 +Wire Wire Line + 7050 6000 7250 6000 +Connection ~ 7250 6000 +Wire Wire Line + 6150 3950 5900 3950 +Wire Wire Line + 5900 3950 5900 3800 +Wire Wire Line + 5900 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6150 4050 5750 4050 +Wire Wire Line + 5750 4050 5750 4350 +Connection ~ 5750 4350 +Wire Wire Line + 6150 5350 5800 5350 +Connection ~ 5800 5350 +$Comp +L d_inverter U20 +U 1 1 6672B10C +P 10050 4100 +F 0 "U20" H 10050 4000 60 0000 C CNN +F 1 "d_inverter" H 10050 4250 60 0000 C CNN +F 2 "" H 10100 4050 60 0000 C CNN +F 3 "" H 10100 4050 60 0000 C CNN + 1 10050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6672B10D +P 10050 4700 +F 0 "U21" H 10050 4600 60 0000 C CNN +F 1 "d_inverter" H 10050 4850 60 0000 C CNN +F 2 "" H 10100 4650 60 0000 C CNN +F 3 "" H 10100 4650 60 0000 C CNN + 1 10050 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6672B10E +P 10050 5400 +F 0 "U22" H 10050 5300 60 0000 C CNN +F 1 "d_inverter" H 10050 5550 60 0000 C CNN +F 2 "" H 10100 5350 60 0000 C CNN +F 3 "" H 10100 5350 60 0000 C CNN + 1 10050 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6672B10F +P 10050 6100 +F 0 "U23" H 10050 6000 60 0000 C CNN +F 1 "d_inverter" H 10050 6250 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Line + 16450 3900 16800 3900 +Wire Wire Line + 16450 4550 16850 4550 +$Comp +L d_nand U31 +U 1 1 6672C780 +P 18700 3950 +F 0 "U31" H 18700 3950 60 0000 C CNN +F 1 "d_nand" H 18750 4050 60 0000 C CNN +F 2 "" H 18700 3950 60 0000 C CNN +F 3 "" H 18700 3950 60 0000 C CNN + 1 18700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 6672C786 +P 19900 3950 +F 0 "U35" H 19900 3950 60 0000 C CNN +F 1 "d_nand" H 19950 4050 60 0000 C CNN +F 2 "" H 19900 3950 60 0000 C CNN +F 3 "" H 19900 3950 60 0000 C CNN + 1 19900 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U39 +U 1 1 6672C78C +P 21100 4050 +F 0 "U39" H 21100 4050 60 0000 C CNN +F 1 "d_nand" H 21150 4150 60 0000 C CNN +F 2 "" H 21100 4050 60 0000 C CNN +F 3 "" H 21100 4050 60 0000 C CNN + 1 21100 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 3950 20600 3950 +Wire Wire Line + 20600 3950 20600 3900 +Wire Wire Line + 20600 3900 20350 3900 +Wire Wire Line + 19450 3850 19350 3850 +Wire Wire Line + 19350 3850 19350 3950 +Wire Wire Line + 19350 3950 19450 3950 +Wire Wire Line + 19150 3900 19350 3900 +Connection ~ 19350 3900 +$Comp +L d_nand U32 +U 1 1 6672C79A +P 18700 4550 +F 0 "U32" H 18700 4550 60 0000 C CNN +F 1 "d_nand" H 18750 4650 60 0000 C CNN +F 2 "" H 18700 4550 60 0000 C CNN +F 3 "" H 18700 4550 60 0000 C CNN + 1 18700 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U36 +U 1 1 6672C7A0 +P 19900 4550 +F 0 "U36" H 19900 4550 60 0000 C CNN +F 1 "d_nand" H 19950 4650 60 0000 C CNN +F 2 "" H 19900 4550 60 0000 C CNN +F 3 "" H 19900 4550 60 0000 C CNN + 1 19900 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U40 +U 1 1 6672C7A6 +P 21100 4650 +F 0 "U40" H 21100 4650 60 0000 C CNN +F 1 "d_nand" H 21150 4750 60 0000 C CNN +F 2 "" H 21100 4650 60 0000 C CNN +F 3 "" H 21100 4650 60 0000 C CNN + 1 21100 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 4550 20600 4550 +Wire Wire Line + 20600 4550 20600 4500 +Wire Wire Line + 20600 4500 20350 4500 +Wire Wire Line + 19450 4450 19350 4450 +Wire Wire Line + 19350 4450 19350 4550 +Wire Wire Line + 19350 4550 19450 4550 +Wire Wire Line + 19150 4500 19350 4500 +Connection ~ 19350 4500 +$Comp +L d_nand U33 +U 1 1 6672C7B4 +P 18700 5250 +F 0 "U33" H 18700 5250 60 0000 C CNN +F 1 "d_nand" H 18750 5350 60 0000 C CNN +F 2 "" H 18700 5250 60 0000 C CNN +F 3 "" H 18700 5250 60 0000 C CNN + 1 18700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U37 +U 1 1 6672C7BA +P 19900 5250 +F 0 "U37" H 19900 5250 60 0000 C CNN +F 1 "d_nand" H 19950 5350 60 0000 C CNN +F 2 "" H 19900 5250 60 0000 C CNN +F 3 "" H 19900 5250 60 0000 C CNN + 1 19900 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U41 +U 1 1 6672C7C0 +P 21100 5350 +F 0 "U41" H 21100 5350 60 0000 C CNN +F 1 "d_nand" H 21150 5450 60 0000 C CNN +F 2 "" H 21100 5350 60 0000 C CNN +F 3 "" H 21100 5350 60 0000 C CNN + 1 21100 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 5250 20600 5250 +Wire Wire Line + 20600 5250 20600 5200 +Wire Wire Line + 20600 5200 20350 5200 +Wire Wire Line + 19450 5150 19350 5150 +Wire Wire Line + 19350 5150 19350 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5450 60 0000 C CNN +F 2 "" H 22200 5250 60 0000 C CNN +F 3 "" H 22200 5250 60 0000 C CNN + 1 22150 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 6672C81E +P 22150 6000 +F 0 "U46" H 22150 5900 60 0000 C CNN +F 1 "d_inverter" H 22150 6150 60 0000 C CNN +F 2 "" H 22200 5950 60 0000 C CNN +F 3 "" H 22200 5950 60 0000 C CNN + 1 22150 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 21550 4000 21850 4000 +Wire Wire Line + 21550 4600 21850 4600 +Wire Wire Line + 21550 5300 21850 5300 +Wire Wire Line + 21550 6000 21850 6000 +$Comp +L adc_bridge_3 U25 +U 1 1 6672C828 +P 14400 4850 +F 0 "U25" H 14400 4850 60 0000 C CNN +F 1 "adc_bridge_3" H 14400 5000 60 0000 C CNN +F 2 "" H 14400 4850 60 0000 C CNN +F 3 "" H 14400 4850 60 0000 C CNN + 1 14400 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14950 4800 15200 4800 +Wire Wire Line + 15200 4800 15200 3900 +Wire Wire Line + 15200 3900 15850 3900 +Wire Wire Line + 14950 4900 15500 4900 +Wire Wire Line + 15500 4900 15500 4550 +Wire Wire Line + 15500 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CNN +F 3 "" H 24800 4550 60 0000 C CNN + 11 24800 4550 + -1 0 0 1 +$EndComp +Wire Wire Line + 24550 4550 24400 4550 +Wire Wire Line + 24400 4550 24400 4750 +Wire Wire Line + 24400 4750 24300 4750 +$Comp +L PORT U1 +U 10 1 6672F27B +P 24850 4750 +F 0 "U1" H 24900 4850 30 0000 C CNN +F 1 "PORT" H 24850 4750 30 0000 C CNN +F 2 "" H 24850 4750 60 0000 C CNN +F 3 "" H 24850 4750 60 0000 C CNN + 10 24850 4750 + -1 0 0 1 +$EndComp +Wire Wire Line + 13650 4900 13800 4900 +$Comp +L PORT U1 +U 9 1 6672FB88 +P 24900 4900 +F 0 "U1" H 24950 5000 30 0000 C CNN +F 1 "PORT" H 24900 4900 30 0000 C CNN +F 2 "" H 24900 4900 60 0000 C CNN +F 3 "" H 24900 4900 60 0000 C CNN + 9 24900 4900 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 4650 13700 4800 +Wire Wire Line + 13700 4800 13800 4800 +$Comp +L PORT U1 +U 8 1 6672FD62 +P 24800 5050 +F 0 "U1" H 24850 5150 30 0000 C CNN +F 1 "PORT" H 24800 5050 30 0000 C CNN +F 2 "" H 24800 5050 60 0000 C CNN +F 3 "" H 24800 5050 60 0000 C CNN + 8 24800 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 5100 13700 5000 +Wire Wire Line + 13700 5000 13800 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub new file mode 100644 index 00000000..fdabce6f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub @@ -0,0 +1,190 @@ +* Subcircuit CD4556BMS_IC +.subckt CD4556BMS_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4556BMS_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml new file mode 100644 index 00000000..5d199ade --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u12 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u12><u16 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u16><u9 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u13 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u13><u17 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u17><u10 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u18><u11 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u15 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u19 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u23><u2 name="type">adc_bridge<field64 name="Enter value for in_low (default=1.0)" /><field65 name="Enter value for in_high (default=2.0)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /><field67 name="Enter Fall Delay (default=1.0e-9)" /></u2><u24 name="type">dac_bridge<field68 name="Enter value for out_low (default=0.0)" /><field69 name="Enter value for out_high (default=5.0)" /><field70 name="Enter value for out_undef (default=0.5)" /><field71 name="Enter value for input load (default=1.0e-12)" /><field72 name="Enter the Rise Time (default=1.0e-9)" /><field73 name="Enter the Fall Time (default=1.0e-9)" /></u24><u26 name="type">d_inverter<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_inverter<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u31><u35 name="type">d_nand<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u35><u39 name="type">d_nand<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u39><u32 name="type">d_nand<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u32><u36 name="type">d_nand<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u36><u40 name="type">d_nand<field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /><field106 name="Enter Input Load (default=1.0e-12)" /></u40><u33 name="type">d_nand<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">d_nand<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u37><u41 name="type">d_nand<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u41><u34 name="type">d_nand<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u34><u38 name="type">d_nand<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u38><u42 name="type">d_nand<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u42><u43 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u46><u25 name="type">adc_bridge<field137 name="Enter value for in_low (default=1.0)" /><field138 name="Enter value for in_high (default=2.0)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /></u25><u47 name="type">dac_bridge<field141 name="Enter value for out_low (default=0.0)" /><field142 name="Enter value for out_high (default=5.0)" /><field143 name="Enter value for out_undef (default=0.5)" /><field144 name="Enter value for input load (default=1.0e-12)" /><field145 name="Enter the Rise Time (default=1.0e-9)" /><field146 name="Enter the Fall Time (default=1.0e-9)" /></u47></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/analysis b/library/SubcircuitLibrary/CD4556BMS_sub/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DAC0800/D.lib b/library/SubcircuitLibrary/DAC0800/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib new file mode 100644 index 00000000..6184ddb3 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir new file mode 100644 index 00000000..242f8395 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir @@ -0,0 +1,92 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\DAC0800_Subcircuit\DAC0800_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/28/24 13:16:39
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U1 Net-_Q1-Pad2_ Net-_Q3-Pad2_ Net-_Q4-Pad2_ Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_Q11-Pad2_ Net-_Q16-Pad2_ Net-_Q21-Pad2_ Net-_Q26-Pad2_ Net-_Q32-Pad2_ Net-_Q37-Pad2_ Net-_Q42-Pad2_ Net-_Q47-Pad2_ Net-_Q14-Pad1_ Net-_Q12-Pad1_ PORT
+D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode
+D3 Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_Diode
+Q1 Net-_D1-Pad1_ Net-_Q1-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q3 Net-_Q2-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q2 Net-_Q2-Pad1_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN
+D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+Q4 Net-_D2-Pad1_ Net-_Q4-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q8 Net-_Q8-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q13 Net-_Q13-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q16 Net-_Q16-Pad1_ Net-_Q16-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q18 Net-_Q18-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q23 Net-_Q23-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q26 Net-_Q26-Pad1_ Net-_Q26-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q29 Net-_Q29-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q32 Net-_Q32-Pad1_ Net-_Q32-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q34 Net-_Q34-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q37 Net-_Q37-Pad1_ Net-_Q37-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q39 Net-_Q39-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q42 Net-_Q42-Pad1_ Net-_Q42-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q45 Net-_D5-Pad1_ Net-_D2-Pad1_ Net-_D2-Pad1_ eSim_PNP
+Q47 Net-_D6-Pad1_ Net-_Q47-Pad2_ Net-_D2-Pad1_ eSim_PNP
+Q9 Net-_Q14-Pad1_ Net-_Q8-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_Q11-Pad1_ Net-_Q10-Pad1_ eSim_NPN
+R2 Net-_Q8-Pad1_ Net-_D2-Pad1_ 800
+R4 Net-_Q11-Pad1_ Net-_D2-Pad1_ 800
+Q6 Net-_Q1-Pad2_ Net-_D2-Pad1_ Net-_Q5-Pad1_ eSim_NPN
+Q5 Net-_Q5-Pad1_ Net-_D1-Pad2_ Net-_Q5-Pad3_ eSim_NPN
+R1 Net-_Q5-Pad3_ Net-_D1-Pad2_ 5k
+Q14 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_Q14-Pad3_ eSim_NPN
+Q17 Net-_Q12-Pad1_ Net-_Q16-Pad1_ Net-_Q14-Pad3_ eSim_NPN
+R6 Net-_Q13-Pad1_ Net-_D2-Pad1_ 1.6k
+R8 Net-_Q16-Pad1_ Net-_D2-Pad1_ 1.6k
+Q19 Net-_Q14-Pad1_ Net-_Q18-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q22 Net-_Q12-Pad1_ Net-_Q21-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+R10 Net-_Q18-Pad1_ Net-_D2-Pad1_ 3.2k
+R12 Net-_Q21-Pad1_ Net-_D2-Pad1_ 3.2k
+Q24 Net-_Q14-Pad1_ Net-_Q23-Pad1_ Net-_Q24-Pad3_ eSim_NPN
+Q27 Net-_Q12-Pad1_ Net-_Q26-Pad1_ Net-_Q24-Pad3_ eSim_NPN
+R14 Net-_Q23-Pad1_ Net-_D2-Pad1_ 6.4k
+R17 Net-_Q26-Pad1_ Net-_D2-Pad1_ 6.4k
+Q30 Net-_Q14-Pad1_ Net-_Q29-Pad1_ Net-_Q30-Pad3_ eSim_NPN
+Q33 Net-_Q14-Pad1_ Net-_Q32-Pad1_ Net-_Q30-Pad3_ eSim_NPN
+R18 Net-_Q29-Pad1_ Net-_D2-Pad1_ 6.4k
+R20 Net-_Q32-Pad1_ Net-_D2-Pad1_ 6.4k
+Q35 Net-_Q14-Pad1_ Net-_Q34-Pad1_ Net-_Q35-Pad3_ eSim_NPN
+Q38 Net-_Q12-Pad1_ Net-_Q37-Pad1_ Net-_Q35-Pad3_ eSim_NPN
+R22 Net-_Q34-Pad1_ Net-_D2-Pad1_ 6.4k
+R23 Net-_Q37-Pad1_ Net-_D2-Pad1_ 6.4k
+Q40 Net-_Q14-Pad1_ Net-_Q39-Pad1_ Net-_Q40-Pad3_ eSim_NPN
+Q43 Net-_Q12-Pad1_ Net-_Q42-Pad1_ Net-_Q40-Pad3_ eSim_NPN
+R24 Net-_Q39-Pad1_ Net-_D2-Pad1_ 6.4k
+R25 Net-_Q42-Pad1_ Net-_D2-Pad1_ 6.4k
+Q44 Net-_Q14-Pad1_ Net-_D5-Pad1_ Net-_Q44-Pad3_ eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+D6 Net-_D6-Pad1_ Net-_D5-Pad2_ eSim_Diode
+R26 Net-_D5-Pad1_ Net-_D2-Pad1_ 6.4k
+R27 Net-_D6-Pad1_ Net-_D2-Pad1_ 6.4k
+Q48 Net-_Q12-Pad1_ Net-_D6-Pad1_ Net-_Q44-Pad3_ eSim_NPN
+D4 Net-_D2-Pad1_ Net-_D4-Pad2_ eSim_Diode
+Q10 Net-_Q10-Pad1_ Net-_D1-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q7 Net-_D1-Pad2_ Net-_D1-Pad2_ Net-_D4-Pad2_ eSim_PNP
+Q15 Net-_Q14-Pad3_ Net-_D1-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+Q20 Net-_Q19-Pad3_ Net-_D1-Pad2_ Net-_Q20-Pad3_ eSim_NPN
+Q25 Net-_Q24-Pad3_ Net-_D1-Pad2_ Net-_Q25-Pad3_ eSim_NPN
+Q31 Net-_Q30-Pad3_ Net-_D2-Pad1_ Net-_Q31-Pad3_ eSim_NPN
+Q36 Net-_Q35-Pad3_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q41 Net-_Q40-Pad3_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q46 Net-_D5-Pad2_ Net-_D2-Pad1_ Net-_Q36-Pad3_ eSim_NPN
+Q28 Net-_Q28-Pad1_ Net-_D1-Pad2_ Net-_Q28-Pad3_ eSim_NPN
+R3 Net-_Q10-Pad3_ Net-_D1-Pad2_ 10k
+R7 Net-_Q15-Pad3_ Net-_R5-Pad1_ 10k
+R11 Net-_Q20-Pad3_ Net-_R11-Pad2_ 10k
+R15 Net-_Q25-Pad3_ Net-_R13-Pad1_ 10k
+R19 Net-_Q31-Pad3_ Net-_Q28-Pad1_ 5k
+R16 Net-_Q28-Pad3_ Net-_R13-Pad1_ 10k
+R13 Net-_R13-Pad1_ Net-_R11-Pad2_ 5k
+R9 Net-_R11-Pad2_ Net-_R5-Pad1_ 5k
+R5 Net-_R5-Pad1_ Net-_D1-Pad2_ 5k
+R21 Net-_Q36-Pad3_ Net-_Q28-Pad1_ 5k
+
+.end
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out new file mode 100644 index 00000000..1f37ec14 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.cir.out @@ -0,0 +1,96 @@ +* c:\fossee\esim\library\subcircuitlibrary\dac0800_subcircuit\dac0800_subcircuit.cir
+
+.include PNP.lib
+.include D.lib
+.include NPN.lib
+* u1 net-_q1-pad2_ net-_q3-pad2_ net-_q4-pad2_ net-_d2-pad1_ net-_d3-pad2_ net-_d1-pad2_ net-_q11-pad2_ net-_q16-pad2_ net-_q21-pad2_ net-_q26-pad2_ net-_q32-pad2_ net-_q37-pad2_ net-_q42-pad2_ net-_q47-pad2_ net-_q14-pad1_ net-_q12-pad1_ port
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148
+q1 net-_d1-pad1_ net-_q1-pad2_ net-_d2-pad1_ Q2N2907A
+q3 net-_q2-pad1_ net-_q3-pad2_ net-_d2-pad1_ Q2N2907A
+q2 net-_q2-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q4 net-_d2-pad1_ net-_q4-pad2_ net-_d1-pad2_ Q2N2222
+q8 net-_q8-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d2-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q16 net-_q16-pad1_ net-_q16-pad2_ net-_d2-pad1_ Q2N2907A
+q18 net-_q18-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d2-pad1_ Q2N2907A
+q23 net-_q23-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q26 net-_q26-pad1_ net-_q26-pad2_ net-_d2-pad1_ Q2N2907A
+q29 net-_q29-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q32 net-_q32-pad1_ net-_q32-pad2_ net-_d2-pad1_ Q2N2907A
+q34 net-_q34-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q37 net-_q37-pad1_ net-_q37-pad2_ net-_d2-pad1_ Q2N2907A
+q39 net-_q39-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q42 net-_q42-pad1_ net-_q42-pad2_ net-_d2-pad1_ Q2N2907A
+q45 net-_d5-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q47 net-_d6-pad1_ net-_q47-pad2_ net-_d2-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q8-pad1_ net-_q10-pad1_ Q2N2222
+q12 net-_q12-pad1_ net-_q11-pad1_ net-_q10-pad1_ Q2N2222
+r2 net-_q8-pad1_ net-_d2-pad1_ 800
+r4 net-_q11-pad1_ net-_d2-pad1_ 800
+q6 net-_q1-pad2_ net-_d2-pad1_ net-_q5-pad1_ Q2N2222
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q5-pad3_ net-_d1-pad2_ 5k
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_q14-pad3_ Q2N2222
+q17 net-_q12-pad1_ net-_q16-pad1_ net-_q14-pad3_ Q2N2222
+r6 net-_q13-pad1_ net-_d2-pad1_ 1.6k
+r8 net-_q16-pad1_ net-_d2-pad1_ 1.6k
+q19 net-_q14-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222
+q22 net-_q12-pad1_ net-_q21-pad1_ net-_q19-pad3_ Q2N2222
+r10 net-_q18-pad1_ net-_d2-pad1_ 3.2k
+r12 net-_q21-pad1_ net-_d2-pad1_ 3.2k
+q24 net-_q14-pad1_ net-_q23-pad1_ net-_q24-pad3_ Q2N2222
+q27 net-_q12-pad1_ net-_q26-pad1_ net-_q24-pad3_ Q2N2222
+r14 net-_q23-pad1_ net-_d2-pad1_ 6.4k
+r17 net-_q26-pad1_ net-_d2-pad1_ 6.4k
+q30 net-_q14-pad1_ net-_q29-pad1_ net-_q30-pad3_ Q2N2222
+q33 net-_q14-pad1_ net-_q32-pad1_ net-_q30-pad3_ Q2N2222
+r18 net-_q29-pad1_ net-_d2-pad1_ 6.4k
+r20 net-_q32-pad1_ net-_d2-pad1_ 6.4k
+q35 net-_q14-pad1_ net-_q34-pad1_ net-_q35-pad3_ Q2N2222
+q38 net-_q12-pad1_ net-_q37-pad1_ net-_q35-pad3_ Q2N2222
+r22 net-_q34-pad1_ net-_d2-pad1_ 6.4k
+r23 net-_q37-pad1_ net-_d2-pad1_ 6.4k
+q40 net-_q14-pad1_ net-_q39-pad1_ net-_q40-pad3_ Q2N2222
+q43 net-_q12-pad1_ net-_q42-pad1_ net-_q40-pad3_ Q2N2222
+r24 net-_q39-pad1_ net-_d2-pad1_ 6.4k
+r25 net-_q42-pad1_ net-_d2-pad1_ 6.4k
+q44 net-_q14-pad1_ net-_d5-pad1_ net-_q44-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+d6 net-_d6-pad1_ net-_d5-pad2_ 1N4148
+r26 net-_d5-pad1_ net-_d2-pad1_ 6.4k
+r27 net-_d6-pad1_ net-_d2-pad1_ 6.4k
+q48 net-_q12-pad1_ net-_d6-pad1_ net-_q44-pad3_ Q2N2222
+d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d1-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad2_ net-_d4-pad2_ Q2N2907A
+q15 net-_q14-pad3_ net-_d1-pad2_ net-_q15-pad3_ Q2N2222
+q20 net-_q19-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2222
+q25 net-_q24-pad3_ net-_d1-pad2_ net-_q25-pad3_ Q2N2222
+q31 net-_q30-pad3_ net-_d2-pad1_ net-_q31-pad3_ Q2N2222
+q36 net-_q35-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q41 net-_q40-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q46 net-_d5-pad2_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q28 net-_q28-pad1_ net-_d1-pad2_ net-_q28-pad3_ Q2N2222
+r3 net-_q10-pad3_ net-_d1-pad2_ 10k
+r7 net-_q15-pad3_ net-_r5-pad1_ 10k
+r11 net-_q20-pad3_ net-_r11-pad2_ 10k
+r15 net-_q25-pad3_ net-_r13-pad1_ 10k
+r19 net-_q31-pad3_ net-_q28-pad1_ 5k
+r16 net-_q28-pad3_ net-_r13-pad1_ 10k
+r13 net-_r13-pad1_ net-_r11-pad2_ 5k
+r9 net-_r11-pad2_ net-_r5-pad1_ 5k
+r5 net-_r5-pad1_ net-_d1-pad2_ 5k
+r21 net-_q36-pad3_ net-_q28-pad1_ 5k
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch new file mode 100644 index 00000000..f083c62b --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sch @@ -0,0 +1,1690 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:DAC0800_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
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+F 2 "" H 1160 4820 29 0000 C CNN
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+ 1 960 4720
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 675E8E0C
+P -1440 3860
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+F 2 "" H -1440 3860 60 0000 C CNN
+F 3 "" H -1440 3860 60 0000 C CNN
+ 1 -1440 3860
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 675E9A7E
+P 760 5400
+F 0 "Q5" H 660 5450 50 0000 R CNN
+F 1 "eSim_NPN" H 710 5550 50 0000 R CNN
+F 2 "" H 960 5500 29 0000 C CNN
+F 3 "" H 760 5400 60 0000 C CNN
+ 1 760 5400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R1
+U 1 1 675E9D55
+P 810 5830
+F 0 "R1" H 860 5960 50 0000 C CNN
+F 1 "5k" H 860 5780 50 0000 C CNN
+F 2 "" H 860 5810 30 0000 C CNN
+F 3 "" V 860 5880 30 0000 C CNN
+ 1 810 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q14
+U 1 1 675EA672
+P 2850 3830
+F 0 "Q14" H 2750 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 2800 3980 50 0000 R CNN
+F 2 "" H 3050 3930 29 0000 C CNN
+F 3 "" H 2850 3830 60 0000 C CNN
+ 1 2850 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 675EA678
+P 3450 3830
+F 0 "Q17" H 3350 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 3400 3980 50 0000 R CNN
+F 2 "" H 3650 3930 29 0000 C CNN
+F 3 "" H 3450 3830 60 0000 C CNN
+ 1 3450 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 675EA685
+P 2600 4200
+F 0 "R6" H 2650 4330 50 0000 C CNN
+F 1 "1.6k" H 2650 4150 50 0000 C CNN
+F 2 "" H 2650 4180 30 0000 C CNN
+F 3 "" V 2650 4250 30 0000 C CNN
+ 1 2600 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R8
+U 1 1 675EA68B
+P 3600 4220
+F 0 "R8" H 3650 4350 50 0000 C CNN
+F 1 "1.6k" H 3650 4170 50 0000 C CNN
+F 2 "" H 3650 4200 30 0000 C CNN
+F 3 "" V 3650 4270 30 0000 C CNN
+ 1 3600 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 675EA8F7
+P 4150 3830
+F 0 "Q19" H 4050 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 4100 3980 50 0000 R CNN
+F 2 "" H 4350 3930 29 0000 C CNN
+F 3 "" H 4150 3830 60 0000 C CNN
+ 1 4150 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q22
+U 1 1 675EA8FD
+P 4750 3830
+F 0 "Q22" H 4650 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 4700 3980 50 0000 R CNN
+F 2 "" H 4950 3930 29 0000 C CNN
+F 3 "" H 4750 3830 60 0000 C CNN
+ 1 4750 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 675EA90A
+P 3900 4200
+F 0 "R10" H 3950 4330 50 0000 C CNN
+F 1 "3.2k" H 3950 4150 50 0000 C CNN
+F 2 "" H 3950 4180 30 0000 C CNN
+F 3 "" V 3950 4250 30 0000 C CNN
+ 1 3900 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 675EA910
+P 4900 4220
+F 0 "R12" H 4950 4350 50 0000 C CNN
+F 1 "3.2k" H 4950 4170 50 0000 C CNN
+F 2 "" H 4950 4200 30 0000 C CNN
+F 3 "" V 4950 4270 30 0000 C CNN
+ 1 4900 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q24
+U 1 1 675EB778
+P 5450 3830
+F 0 "Q24" H 5350 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 5400 3980 50 0000 R CNN
+F 2 "" H 5650 3930 29 0000 C CNN
+F 3 "" H 5450 3830 60 0000 C CNN
+ 1 5450 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q27
+U 1 1 675EB77E
+P 6050 3830
+F 0 "Q27" H 5950 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 6000 3980 50 0000 R CNN
+F 2 "" H 6250 3930 29 0000 C CNN
+F 3 "" H 6050 3830 60 0000 C CNN
+ 1 6050 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R14
+U 1 1 675EB78B
+P 5200 4200
+F 0 "R14" H 5250 4330 50 0000 C CNN
+F 1 "6.4k" H 5250 4150 50 0000 C CNN
+F 2 "" H 5250 4180 30 0000 C CNN
+F 3 "" V 5250 4250 30 0000 C CNN
+ 1 5200 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 675EB791
+P 6200 4220
+F 0 "R17" H 6250 4350 50 0000 C CNN
+F 1 "6.4k" H 6250 4170 50 0000 C CNN
+F 2 "" H 6250 4200 30 0000 C CNN
+F 3 "" V 6250 4270 30 0000 C CNN
+ 1 6200 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q30
+U 1 1 675EB799
+P 6750 3830
+F 0 "Q30" H 6650 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 6700 3980 50 0000 R CNN
+F 2 "" H 6950 3930 29 0000 C CNN
+F 3 "" H 6750 3830 60 0000 C CNN
+ 1 6750 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q33
+U 1 1 675EB79F
+P 7350 3830
+F 0 "Q33" H 7250 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 7300 3980 50 0000 R CNN
+F 2 "" H 7550 3930 29 0000 C CNN
+F 3 "" H 7350 3830 60 0000 C CNN
+ 1 7350 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R18
+U 1 1 675EB7AC
+P 6500 4200
+F 0 "R18" H 6550 4330 50 0000 C CNN
+F 1 "6.4k" H 6550 4150 50 0000 C CNN
+F 2 "" H 6550 4180 30 0000 C CNN
+F 3 "" V 6550 4250 30 0000 C CNN
+ 1 6500 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 675EB7B2
+P 7500 4220
+F 0 "R20" H 7550 4350 50 0000 C CNN
+F 1 "6.4k" H 7550 4170 50 0000 C CNN
+F 2 "" H 7550 4200 30 0000 C CNN
+F 3 "" V 7550 4270 30 0000 C CNN
+ 1 7500 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q35
+U 1 1 675EB7BA
+P 8150 3830
+F 0 "Q35" H 8050 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 8100 3980 50 0000 R CNN
+F 2 "" H 8350 3930 29 0000 C CNN
+F 3 "" H 8150 3830 60 0000 C CNN
+ 1 8150 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q38
+U 1 1 675EB7C0
+P 8750 3830
+F 0 "Q38" H 8650 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 8700 3980 50 0000 R CNN
+F 2 "" H 8950 3930 29 0000 C CNN
+F 3 "" H 8750 3830 60 0000 C CNN
+ 1 8750 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R22
+U 1 1 675EB7CD
+P 7900 4200
+F 0 "R22" H 7950 4330 50 0000 C CNN
+F 1 "6.4k" H 7950 4150 50 0000 C CNN
+F 2 "" H 7950 4180 30 0000 C CNN
+F 3 "" V 7950 4250 30 0000 C CNN
+ 1 7900 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R23
+U 1 1 675EB7D3
+P 8900 4220
+F 0 "R23" H 8950 4350 50 0000 C CNN
+F 1 "6.4k" H 8950 4170 50 0000 C CNN
+F 2 "" H 8950 4200 30 0000 C CNN
+F 3 "" V 8950 4270 30 0000 C CNN
+ 1 8900 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q40
+U 1 1 675EC029
+P 9400 3830
+F 0 "Q40" H 9300 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 9350 3980 50 0000 R CNN
+F 2 "" H 9600 3930 29 0000 C CNN
+F 3 "" H 9400 3830 60 0000 C CNN
+ 1 9400 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q43
+U 1 1 675EC02F
+P 10000 3830
+F 0 "Q43" H 9900 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 9950 3980 50 0000 R CNN
+F 2 "" H 10200 3930 29 0000 C CNN
+F 3 "" H 10000 3830 60 0000 C CNN
+ 1 10000 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L resistor R24
+U 1 1 675EC03C
+P 9150 4200
+F 0 "R24" H 9200 4330 50 0000 C CNN
+F 1 "6.4k" H 9200 4150 50 0000 C CNN
+F 2 "" H 9200 4180 30 0000 C CNN
+F 3 "" V 9200 4250 30 0000 C CNN
+ 1 9150 4200
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R25
+U 1 1 675EC042
+P 10150 4220
+F 0 "R25" H 10200 4350 50 0000 C CNN
+F 1 "6.4k" H 10200 4170 50 0000 C CNN
+F 2 "" H 10200 4200 30 0000 C CNN
+F 3 "" V 10200 4270 30 0000 C CNN
+ 1 10150 4220
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q44
+U 1 1 675EC36A
+P 10820 3830
+F 0 "Q44" H 10720 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 10770 3980 50 0000 R CNN
+F 2 "" H 11020 3930 29 0000 C CNN
+F 3 "" H 10820 3830 60 0000 C CNN
+ 1 10820 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D5
+U 1 1 675ED4D2
+P 11240 3830
+F 0 "D5" H 11240 3930 50 0000 C CNN
+F 1 "eSim_Diode" H 11240 3730 50 0000 C CNN
+F 2 "" H 11240 3830 60 0000 C CNN
+F 3 "" H 11240 3830 60 0000 C CNN
+ 1 11240 3830
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D6
+U 1 1 675EEB4B
+P 11790 3830
+F 0 "D6" H 11790 3930 50 0000 C CNN
+F 1 "eSim_Diode" H 11790 3730 50 0000 C CNN
+F 2 "" H 11790 3830 60 0000 C CNN
+F 3 "" H 11790 3830 60 0000 C CNN
+ 1 11790 3830
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R26
+U 1 1 675EFE6E
+P 10570 4230
+F 0 "R26" H 10620 4360 50 0000 C CNN
+F 1 "6.4k" H 10620 4180 50 0000 C CNN
+F 2 "" H 10620 4210 30 0000 C CNN
+F 3 "" V 10620 4280 30 0000 C CNN
+ 1 10570 4230
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R27
+U 1 1 675EFF87
+P 12330 4270
+F 0 "R27" H 12380 4400 50 0000 C CNN
+F 1 "6.4k" H 12380 4220 50 0000 C CNN
+F 2 "" H 12380 4250 30 0000 C CNN
+F 3 "" V 12380 4320 30 0000 C CNN
+ 1 12330 4270
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q48
+U 1 1 675F2477
+P 12180 3830
+F 0 "Q48" H 12080 3880 50 0000 R CNN
+F 1 "eSim_NPN" H 12130 3980 50 0000 R CNN
+F 2 "" H 12380 3930 29 0000 C CNN
+F 3 "" H 12180 3830 60 0000 C CNN
+ 1 12180 3830
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 675F37F6
+P 12900 3340
+F 0 "U1" H 12950 3440 30 0000 C CNN
+F 1 "PORT" H 12900 3340 30 0000 C CNN
+F 2 "" H 12900 3340 60 0000 C CNN
+F 3 "" H 12900 3340 60 0000 C CNN
+ 15 12900 3340
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 675F391A
+P 12900 3520
+F 0 "U1" H 12950 3620 30 0000 C CNN
+F 1 "PORT" H 12900 3520 30 0000 C CNN
+F 2 "" H 12900 3520 60 0000 C CNN
+F 3 "" H 12900 3520 60 0000 C CNN
+ 16 12900 3520
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 1700 2450 1700 2400
+Wire Wire Line
+ 1700 2400 2100 2400
+Wire Wire Line
+ 2100 2400 2100 2450
+Wire Wire Line
+ 1900 1080 1900 2400
+Wire Wire Line
+ 2450 2650 2400 2650
+Connection ~ 1900 2400
+Wire Wire Line
+ 2950 2450 2950 2400
+Wire Wire Line
+ 2950 2400 3350 2400
+Wire Wire Line
+ 3350 2400 3350 2450
+Wire Wire Line
+ 3150 1080 3150 2400
+Wire Wire Line
+ 3700 2650 3650 2650
+Connection ~ 3150 2400
+Wire Wire Line
+ 4250 2450 4250 2400
+Wire Wire Line
+ 4250 2400 4650 2400
+Wire Wire Line
+ 4450 1080 4450 2400
+Connection ~ 4450 2400
+Wire Wire Line
+ 5550 2450 5550 2400
+Wire Wire Line
+ 5550 2400 5950 2400
+Wire Wire Line
+ 5750 1080 5750 2400
+Connection ~ 5750 2400
+Wire Wire Line
+ 6850 2450 6850 2400
+Wire Wire Line
+ 6850 2400 7250 2400
+Wire Wire Line
+ 7050 1080 7050 2400
+Connection ~ 7050 2400
+Wire Wire Line
+ 8250 2450 8250 2400
+Wire Wire Line
+ 8250 2400 8650 2400
+Wire Wire Line
+ 8450 1080 8450 2400
+Connection ~ 8450 2400
+Wire Wire Line
+ 9500 2450 9500 2400
+Wire Wire Line
+ 9500 2400 9900 2400
+Wire Wire Line
+ 9700 1080 9700 2400
+Connection ~ 9700 2400
+Wire Wire Line
+ 4650 2400 4650 2450
+Wire Wire Line
+ 5950 2400 5950 2450
+Wire Wire Line
+ 7250 2400 7250 2450
+Wire Wire Line
+ 8650 2400 8650 2450
+Wire Wire Line
+ 9900 2400 9900 2450
+Wire Wire Line
+ 1270 1080 1270 2700
+Wire Wire Line
+ 1270 2650 1400 2650
+Wire Wire Line
+ 2650 2650 2600 2650
+Wire Wire Line
+ 2600 2650 2600 2150
+Connection ~ 2600 2150
+Wire Wire Line
+ 3950 2650 3850 2650
+Wire Wire Line
+ 3850 2650 3850 2150
+Connection ~ 3850 2150
+Wire Wire Line
+ 5250 2650 5150 2650
+Wire Wire Line
+ 5150 2650 5150 2150
+Connection ~ 5150 2150
+Wire Wire Line
+ 6550 2650 6450 2650
+Wire Wire Line
+ 6450 2650 6450 2150
+Connection ~ 6450 2150
+Wire Wire Line
+ 7950 2650 7850 2650
+Wire Wire Line
+ 7850 2650 7850 2150
+Connection ~ 7850 2150
+Wire Wire Line
+ 9200 2650 9100 2650
+Wire Wire Line
+ 9100 2650 9100 2150
+Connection ~ 9100 2150
+Wire Wire Line
+ 10350 2150 10350 2650
+Wire Wire Line
+ 10350 2650 10800 2650
+Wire Wire Line
+ 2450 650 2450 2650
+Wire Wire Line
+ 3700 2650 3700 700
+Wire Wire Line
+ 4950 2650 4950 700
+Wire Wire Line
+ 6250 700 6250 2650
+Wire Wire Line
+ 7600 2650 7550 2650
+Wire Wire Line
+ 7600 700 7600 2650
+Wire Wire Line
+ 8950 680 8950 2650
+Wire Wire Line
+ 10200 2650 10200 700
+Wire Wire Line
+ 1270 3000 1270 3090
+Wire Wire Line
+ 1270 3390 1270 3560
+Wire Wire Line
+ 1270 3560 770 3560
+Wire Wire Line
+ 770 3560 770 640
+Wire Wire Line
+ 11100 2450 11100 2360
+Wire Wire Line
+ 11100 2360 11890 2360
+Wire Wire Line
+ 11890 2360 11890 2440
+Connection ~ 1270 2650
+Wire Wire Line
+ 11500 1080 11500 2360
+Connection ~ 11500 2360
+Connection ~ 5750 1080
+Connection ~ 7050 1080
+Connection ~ 8450 1080
+Connection ~ 9700 1080
+Connection ~ 4450 1080
+Connection ~ 3150 1080
+Wire Wire Line
+ -380 1080 11500 1080
+Connection ~ 1900 1080
+Wire Wire Line
+ -580 4060 -180 4060
+Wire Wire Line
+ -380 630 -380 4060
+Connection ~ -380 4060
+Wire Wire Line
+ -180 4060 -180 4110
+Wire Wire Line
+ -580 4110 -580 4060
+Wire Wire Line
+ -180 4510 -180 5220
+Wire Wire Line
+ -580 4510 -580 5720
+Wire Wire Line
+ -580 5420 -480 5420
+Wire Wire Line
+ -1190 4990 80 4990
+Connection ~ -580 5420
+Wire Wire Line
+ -1190 4710 200 4710
+Wire Wire Line
+ 200 4710 200 4310
+Wire Wire Line
+ 200 4310 120 4310
+Connection ~ -380 1080
+Connection ~ 1270 1080
+Wire Wire Line
+ 380 4790 380 1080
+Connection ~ 380 1080
+Wire Wire Line
+ 1330 2150 1330 2650
+Connection ~ 1330 2650
+Wire Wire Line
+ 10350 2150 1330 2150
+Wire Wire Line
+ 1700 2850 1700 3150
+Wire Wire Line
+ 1700 3150 1400 3150
+Wire Wire Line
+ 1400 3150 1400 4100
+Wire Wire Line
+ 2400 3140 2400 4120
+Wire Wire Line
+ 2400 3140 2100 3140
+Wire Wire Line
+ 2100 3140 2100 2850
+Wire Wire Line
+ 1700 4030 2100 4030
+Connection ~ 1400 3830
+Connection ~ 2400 3830
+Wire Wire Line
+ 860 4520 860 3860
+Wire Wire Line
+ 860 3860 -1190 3860
+Wire Wire Line
+ -880 4310 -880 3860
+Connection ~ -880 3860
+Wire Wire Line
+ 860 4920 860 5200
+Wire Wire Line
+ 380 5190 380 6370
+Wire Wire Line
+ 860 5600 860 5730
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3650 3140 3650 4120
+Wire Wire Line
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+Wire Wire Line
+ 3350 3140 3350 2850
+Wire Wire Line
+ 2950 4030 3350 4030
+Connection ~ 2650 3830
+Connection ~ 3650 3830
+Wire Wire Line
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+Wire Wire Line
+ 4250 3150 3950 3150
+Wire Wire Line
+ 3950 3150 3950 4100
+Wire Wire Line
+ 4950 3140 4950 4120
+Wire Wire Line
+ 4950 3140 4650 3140
+Wire Wire Line
+ 4650 3140 4650 2850
+Wire Wire Line
+ 4250 4030 4650 4030
+Connection ~ 3950 3830
+Connection ~ 4950 3830
+Wire Wire Line
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+Wire Wire Line
+ 5550 3150 5250 3150
+Wire Wire Line
+ 5250 3150 5250 4100
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 5250 3830
+Connection ~ 6250 3830
+Wire Wire Line
+ 6850 2850 6850 3150
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 6550 3830
+Connection ~ 7550 3830
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 8650 3140 8650 2850
+Wire Wire Line
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+Connection ~ 7950 3830
+Connection ~ 8950 3830
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 10200 3830
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 10620 3830
+Wire Wire Line
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+Connection ~ 12380 3830
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2950 3340
+Wire Wire Line
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+Connection ~ 3350 3520
+Wire Wire Line
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+Connection ~ 4250 3340
+Wire Wire Line
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+Connection ~ 4650 3520
+Wire Wire Line
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+Connection ~ 5550 3340
+Wire Wire Line
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+Connection ~ 5950 3520
+Wire Wire Line
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+Connection ~ 6850 3340
+Wire Wire Line
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+Connection ~ 7250 3340
+Wire Wire Line
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+Connection ~ 8250 3340
+Wire Wire Line
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+Connection ~ 8650 3520
+Wire Wire Line
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+Connection ~ 9500 3340
+Wire Wire Line
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+Connection ~ 9900 3520
+Wire Wire Line
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+Connection ~ 10920 3340
+Wire Wire Line
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+Connection ~ 12080 3520
+Wire Wire Line
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+Wire Wire Line
+ 12380 4720 12380 4470
+Wire Wire Line
+ 1160 4720 12380 4720
+Wire Wire Line
+ 1400 4720 1400 4400
+$Comp
+L eSim_Diode D4
+U 1 1 675FA513
+P 1270 4970
+F 0 "D4" H 1270 5070 50 0000 C CNN
+F 1 "eSim_Diode" H 1270 4870 50 0000 C CNN
+F 2 "" H 1270 4970 60 0000 C CNN
+F 3 "" H 1270 4970 60 0000 C CNN
+ 1 1270 4970
+ 0 1 1 0
+$EndComp
+Connection ~ 1400 4720
+Connection ~ 1270 4720
+Wire Wire Line
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+Connection ~ 380 4080
+Wire Wire Line
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+Connection ~ 2400 4720
+Wire Wire Line
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+Connection ~ 2650 4720
+Wire Wire Line
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+Connection ~ 3650 4720
+Wire Wire Line
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+Connection ~ 3950 4720
+Wire Wire Line
+ 4950 4420 4950 4720
+Connection ~ 4950 4720
+Wire Wire Line
+ 5250 4400 5250 4720
+Connection ~ 5250 4720
+Wire Wire Line
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+Connection ~ 6250 4720
+Wire Wire Line
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+Connection ~ 6550 4720
+Wire Wire Line
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+Connection ~ 7550 4720
+Wire Wire Line
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+Connection ~ 7950 4720
+Wire Wire Line
+ 8950 4420 8950 4720
+Connection ~ 8950 4720
+Wire Wire Line
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+Connection ~ 9200 4720
+Wire Wire Line
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+Connection ~ 10200 4720
+Wire Wire Line
+ 10620 4430 10620 4720
+Connection ~ 10620 4720
+$Comp
+L eSim_NPN Q10
+U 1 1 675FEC98
+P 1790 5400
+F 0 "Q10" H 1690 5450 50 0000 R CNN
+F 1 "eSim_NPN" H 1740 5550 50 0000 R CNN
+F 2 "" H 1990 5500 29 0000 C CNN
+F 3 "" H 1790 5400 60 0000 C CNN
+ 1 1790 5400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1270 4080 1270 4820
+Wire Wire Line
+ 1270 5200 1270 5120
+Wire Wire Line
+ 380 5400 1590 5400
+Connection ~ 560 5400
+$Comp
+L eSim_PNP Q7
+U 1 1 676EC938
+P 1170 5400
+F 0 "Q7" H 1070 5450 50 0000 R CNN
+F 1 "eSim_PNP" H 1120 5550 50 0000 R CNN
+F 2 "" H 1370 5500 29 0000 C CNN
+F 3 "" H 1170 5400 60 0000 C CNN
+ 1 1170 5400
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 676ED46A
+P 3030 5420
+F 0 "Q15" H 2930 5470 50 0000 R CNN
+F 1 "eSim_NPN" H 2980 5570 50 0000 R CNN
+F 2 "" H 3230 5520 29 0000 C CNN
+F 3 "" H 3030 5420 60 0000 C CNN
+ 1 3030 5420
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 676ED630
+P 4340 5430
+F 0 "Q20" H 4240 5480 50 0000 R CNN
+F 1 "eSim_NPN" H 4290 5580 50 0000 R CNN
+F 2 "" H 4540 5530 29 0000 C CNN
+F 3 "" H 4340 5430 60 0000 C CNN
+ 1 4340 5430
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q25
+U 1 1 676ED636
+P 5630 5450
+F 0 "Q25" H 5530 5500 50 0000 R CNN
+F 1 "eSim_NPN" H 5580 5600 50 0000 R CNN
+F 2 "" H 5830 5550 29 0000 C CNN
+F 3 "" H 5630 5450 60 0000 C CNN
+ 1 5630 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q31
+U 1 1 676ED948
+P 6960 5450
+F 0 "Q31" H 6860 5500 50 0000 R CNN
+F 1 "eSim_NPN" H 6910 5600 50 0000 R CNN
+F 2 "" H 7160 5550 29 0000 C CNN
+F 3 "" H 6960 5450 60 0000 C CNN
+ 1 6960 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q36
+U 1 1 676ED94E
+P 8340 5470
+F 0 "Q36" H 8240 5520 50 0000 R CNN
+F 1 "eSim_NPN" H 8290 5620 50 0000 R CNN
+F 2 "" H 8540 5570 29 0000 C CNN
+F 3 "" H 8340 5470 60 0000 C CNN
+ 1 8340 5470
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q41
+U 1 1 676ED954
+P 9620 5480
+F 0 "Q41" H 9520 5530 50 0000 R CNN
+F 1 "eSim_NPN" H 9570 5630 50 0000 R CNN
+F 2 "" H 9820 5580 29 0000 C CNN
+F 3 "" H 9620 5480 60 0000 C CNN
+ 1 9620 5480
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q46
+U 1 1 676ED95A
+P 11420 5500
+F 0 "Q46" H 11320 5550 50 0000 R CNN
+F 1 "eSim_NPN" H 11370 5650 50 0000 R CNN
+F 2 "" H 11620 5600 29 0000 C CNN
+F 3 "" H 11420 5500 60 0000 C CNN
+ 1 11420 5500
+ 1 0 0 -1
+$EndComp
+Connection ~ 1890 4030
+Wire Wire Line
+ 3130 5220 3130 4030
+Connection ~ 3130 4030
+Wire Wire Line
+ 4440 5230 4440 4030
+Connection ~ 4440 4030
+Wire Wire Line
+ 5730 5250 5730 4030
+Connection ~ 5730 4030
+Wire Wire Line
+ 7060 5250 7060 4030
+Connection ~ 7060 4030
+Wire Wire Line
+ 8440 5270 8440 4030
+Connection ~ 8440 4030
+Wire Wire Line
+ 9720 5280 9720 4030
+Connection ~ 9720 4030
+Wire Wire Line
+ 11520 5300 11520 3830
+Connection ~ 11520 3830
+Wire Wire Line
+ 11220 5500 9420 5500
+Wire Wire Line
+ 9420 5500 9420 5480
+Wire Wire Line
+ 9420 5480 8140 5480
+Wire Wire Line
+ 8140 5480 8140 5470
+Wire Wire Line
+ 8140 5470 6760 5470
+Wire Wire Line
+ 6760 5470 6760 5450
+Wire Wire Line
+ 4140 5450 4140 5430
+Wire Wire Line
+ 4140 5430 2830 5430
+Wire Wire Line
+ 2830 5430 2830 5420
+Wire Wire Line
+ 2830 5420 1590 5420
+Wire Wire Line
+ 1590 5420 1590 5400
+Connection ~ 970 5400
+Wire Wire Line
+ 5430 5450 4140 5450
+Wire Wire Line
+ 6760 5450 6250 5450
+$Comp
+L eSim_NPN Q28
+U 1 1 676FA4E3
+P 6170 5980
+F 0 "Q28" H 6070 6030 50 0000 R CNN
+F 1 "eSim_NPN" H 6120 6130 50 0000 R CNN
+F 2 "" H 6370 6080 29 0000 C CNN
+F 3 "" H 6170 5980 60 0000 C CNN
+ 1 6170 5980
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5970 5980 5970 5490
+Wire Wire Line
+ 5970 5490 5430 5490
+Wire Wire Line
+ 5430 5490 5430 5450
+$Comp
+L resistor R3
+U 1 1 67702BB0
+P 1840 5830
+F 0 "R3" H 1890 5960 50 0000 C CNN
+F 1 "10k" H 1890 5780 50 0000 C CNN
+F 2 "" H 1890 5810 30 0000 C CNN
+F 3 "" V 1890 5880 30 0000 C CNN
+ 1 1840 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 677031F4
+P 3080 5830
+F 0 "R7" H 3130 5960 50 0000 C CNN
+F 1 "10k" H 3130 5780 50 0000 C CNN
+F 2 "" H 3130 5810 30 0000 C CNN
+F 3 "" V 3130 5880 30 0000 C CNN
+ 1 3080 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 67703574
+P 4390 5830
+F 0 "R11" H 4440 5960 50 0000 C CNN
+F 1 "10k" H 4440 5780 50 0000 C CNN
+F 2 "" H 4440 5810 30 0000 C CNN
+F 3 "" V 4440 5880 30 0000 C CNN
+ 1 4390 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R15
+U 1 1 6770357A
+P 5680 5830
+F 0 "R15" H 5730 5960 50 0000 C CNN
+F 1 "10k" H 5730 5780 50 0000 C CNN
+F 2 "" H 5730 5810 30 0000 C CNN
+F 3 "" V 5730 5880 30 0000 C CNN
+ 1 5680 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 677041F3
+P 7010 5830
+F 0 "R19" H 7060 5960 50 0000 C CNN
+F 1 "5k" H 7060 5780 50 0000 C CNN
+F 2 "" H 7060 5810 30 0000 C CNN
+F 3 "" V 7060 5880 30 0000 C CNN
+ 1 7010 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R16
+U 1 1 677049B7
+P 6040 6320
+F 0 "R16" H 6090 6450 50 0000 C CNN
+F 1 "10k" H 6090 6270 50 0000 C CNN
+F 2 "" H 6090 6300 30 0000 C CNN
+F 3 "" V 6090 6370 30 0000 C CNN
+ 1 6040 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 67704B20
+P 5170 6320
+F 0 "R13" H 5220 6450 50 0000 C CNN
+F 1 "5k" H 5220 6270 50 0000 C CNN
+F 2 "" H 5220 6300 30 0000 C CNN
+F 3 "" V 5220 6370 30 0000 C CNN
+ 1 5170 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R9
+U 1 1 67704CEE
+P 3810 6320
+F 0 "R9" H 3860 6450 50 0000 C CNN
+F 1 "5k" H 3860 6270 50 0000 C CNN
+F 2 "" H 3860 6300 30 0000 C CNN
+F 3 "" V 3860 6370 30 0000 C CNN
+ 1 3810 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67704F7E
+P 2590 6320
+F 0 "R5" H 2640 6450 50 0000 C CNN
+F 1 "5k" H 2640 6270 50 0000 C CNN
+F 2 "" H 2640 6300 30 0000 C CNN
+F 3 "" V 2640 6370 30 0000 C CNN
+ 1 2590 6320
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R21
+U 1 1 67705310
+P 7830 6320
+F 0 "R21" H 7880 6450 50 0000 C CNN
+F 1 "5k" H 7880 6270 50 0000 C CNN
+F 2 "" H 7880 6300 30 0000 C CNN
+F 3 "" V 7880 6370 30 0000 C CNN
+ 1 7830 6320
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ -580 6020 -580 6370
+Wire Wire Line
+ -580 6370 2390 6370
+Wire Wire Line
+ 2690 6370 3610 6370
+Wire Wire Line
+ 3910 6370 4970 6370
+Wire Wire Line
+ 5270 6370 5840 6370
+Wire Wire Line
+ 7930 6370 11520 6370
+Wire Wire Line
+ 11520 6370 11520 5700
+Wire Wire Line
+ 1890 5730 1890 5600
+Wire Wire Line
+ 3130 5730 3130 5620
+Wire Wire Line
+ 4440 5730 4440 5630
+Wire Wire Line
+ 5730 5730 5730 5650
+Wire Wire Line
+ 7060 5730 7060 5650
+Wire Wire Line
+ 1890 6030 1890 6370
+Connection ~ 1890 6370
+Wire Wire Line
+ 3130 6030 3130 6370
+Connection ~ 3130 6370
+Wire Wire Line
+ 4440 6030 4440 6370
+Connection ~ 4440 6370
+Wire Wire Line
+ 5730 6030 5730 6370
+Connection ~ 5730 6370
+Wire Wire Line
+ 6640 6370 7630 6370
+Wire Wire Line
+ 7060 6370 7060 6030
+Wire Wire Line
+ 6270 6180 6270 6370
+Wire Wire Line
+ 6270 6370 6140 6370
+Wire Wire Line
+ 6270 5780 6270 5740
+Wire Wire Line
+ 6270 5740 6640 5740
+Wire Wire Line
+ 6640 5740 6640 6370
+Connection ~ 7060 6370
+Wire Wire Line
+ 9720 5680 9720 6370
+Connection ~ 9720 6370
+Wire Wire Line
+ 8440 5670 8440 6370
+Connection ~ 8440 6370
+$Comp
+L PORT U1
+U 14 1 6770EB8E
+P 12190 440
+F 0 "U1" H 12240 540 30 0000 C CNN
+F 1 "PORT" H 12190 440 30 0000 C CNN
+F 2 "" H 12190 440 60 0000 C CNN
+F 3 "" H 12190 440 60 0000 C CNN
+ 14 12190 440
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 12190 2640 12190 690
+Wire Wire Line
+ -180 5620 -180 6370
+Connection ~ -180 6370
+Wire Wire Line
+ 860 6030 860 6370
+Connection ~ 860 6370
+$Comp
+L PORT U1
+U 6 1 67713869
+P 1270 6890
+F 0 "U1" H 1320 6990 30 0000 C CNN
+F 1 "PORT" H 1270 6890 30 0000 C CNN
+F 2 "" H 1270 6890 60 0000 C CNN
+F 3 "" H 1270 6890 60 0000 C CNN
+ 6 1270 6890
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 1270 5600 1270 6640
+Connection ~ 1270 6370
+Wire Wire Line
+ 1890 5200 1890 4030
+Connection ~ 380 6370
+Connection ~ 380 5400
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub new file mode 100644 index 00000000..b282b9c5 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit.sub @@ -0,0 +1,90 @@ +* Subcircuit DAC0800_Subcircuit
+.subckt DAC0800_Subcircuit net-_q1-pad2_ net-_q3-pad2_ net-_q4-pad2_ net-_d2-pad1_ net-_d3-pad2_ net-_d1-pad2_ net-_q11-pad2_ net-_q16-pad2_ net-_q21-pad2_ net-_q26-pad2_ net-_q32-pad2_ net-_q37-pad2_ net-_q42-pad2_ net-_q47-pad2_ net-_q14-pad1_ net-_q12-pad1_
+* c:\fossee\esim\library\subcircuitlibrary\dac0800_subcircuit\dac0800_subcircuit.cir
+.include PNP.lib
+.include D.lib
+.include NPN.lib
+d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148
+d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148
+q1 net-_d1-pad1_ net-_q1-pad2_ net-_d2-pad1_ Q2N2907A
+q3 net-_q2-pad1_ net-_q3-pad2_ net-_d2-pad1_ Q2N2907A
+q2 net-_q2-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222
+d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148
+q4 net-_d2-pad1_ net-_q4-pad2_ net-_d1-pad2_ Q2N2222
+q8 net-_q8-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d2-pad1_ Q2N2907A
+q13 net-_q13-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q16 net-_q16-pad1_ net-_q16-pad2_ net-_d2-pad1_ Q2N2907A
+q18 net-_q18-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q21 net-_q21-pad1_ net-_q21-pad2_ net-_d2-pad1_ Q2N2907A
+q23 net-_q23-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q26 net-_q26-pad1_ net-_q26-pad2_ net-_d2-pad1_ Q2N2907A
+q29 net-_q29-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q32 net-_q32-pad1_ net-_q32-pad2_ net-_d2-pad1_ Q2N2907A
+q34 net-_q34-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q37 net-_q37-pad1_ net-_q37-pad2_ net-_d2-pad1_ Q2N2907A
+q39 net-_q39-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q42 net-_q42-pad1_ net-_q42-pad2_ net-_d2-pad1_ Q2N2907A
+q45 net-_d5-pad1_ net-_d2-pad1_ net-_d2-pad1_ Q2N2907A
+q47 net-_d6-pad1_ net-_q47-pad2_ net-_d2-pad1_ Q2N2907A
+q9 net-_q14-pad1_ net-_q8-pad1_ net-_q10-pad1_ Q2N2222
+q12 net-_q12-pad1_ net-_q11-pad1_ net-_q10-pad1_ Q2N2222
+r2 net-_q8-pad1_ net-_d2-pad1_ 800
+r4 net-_q11-pad1_ net-_d2-pad1_ 800
+q6 net-_q1-pad2_ net-_d2-pad1_ net-_q5-pad1_ Q2N2222
+q5 net-_q5-pad1_ net-_d1-pad2_ net-_q5-pad3_ Q2N2222
+r1 net-_q5-pad3_ net-_d1-pad2_ 5k
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_q14-pad3_ Q2N2222
+q17 net-_q12-pad1_ net-_q16-pad1_ net-_q14-pad3_ Q2N2222
+r6 net-_q13-pad1_ net-_d2-pad1_ 1.6k
+r8 net-_q16-pad1_ net-_d2-pad1_ 1.6k
+q19 net-_q14-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222
+q22 net-_q12-pad1_ net-_q21-pad1_ net-_q19-pad3_ Q2N2222
+r10 net-_q18-pad1_ net-_d2-pad1_ 3.2k
+r12 net-_q21-pad1_ net-_d2-pad1_ 3.2k
+q24 net-_q14-pad1_ net-_q23-pad1_ net-_q24-pad3_ Q2N2222
+q27 net-_q12-pad1_ net-_q26-pad1_ net-_q24-pad3_ Q2N2222
+r14 net-_q23-pad1_ net-_d2-pad1_ 6.4k
+r17 net-_q26-pad1_ net-_d2-pad1_ 6.4k
+q30 net-_q14-pad1_ net-_q29-pad1_ net-_q30-pad3_ Q2N2222
+q33 net-_q14-pad1_ net-_q32-pad1_ net-_q30-pad3_ Q2N2222
+r18 net-_q29-pad1_ net-_d2-pad1_ 6.4k
+r20 net-_q32-pad1_ net-_d2-pad1_ 6.4k
+q35 net-_q14-pad1_ net-_q34-pad1_ net-_q35-pad3_ Q2N2222
+q38 net-_q12-pad1_ net-_q37-pad1_ net-_q35-pad3_ Q2N2222
+r22 net-_q34-pad1_ net-_d2-pad1_ 6.4k
+r23 net-_q37-pad1_ net-_d2-pad1_ 6.4k
+q40 net-_q14-pad1_ net-_q39-pad1_ net-_q40-pad3_ Q2N2222
+q43 net-_q12-pad1_ net-_q42-pad1_ net-_q40-pad3_ Q2N2222
+r24 net-_q39-pad1_ net-_d2-pad1_ 6.4k
+r25 net-_q42-pad1_ net-_d2-pad1_ 6.4k
+q44 net-_q14-pad1_ net-_d5-pad1_ net-_q44-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+d6 net-_d6-pad1_ net-_d5-pad2_ 1N4148
+r26 net-_d5-pad1_ net-_d2-pad1_ 6.4k
+r27 net-_d6-pad1_ net-_d2-pad1_ 6.4k
+q48 net-_q12-pad1_ net-_d6-pad1_ net-_q44-pad3_ Q2N2222
+d4 net-_d2-pad1_ net-_d4-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d1-pad2_ net-_q10-pad3_ Q2N2222
+q7 net-_d1-pad2_ net-_d1-pad2_ net-_d4-pad2_ Q2N2907A
+q15 net-_q14-pad3_ net-_d1-pad2_ net-_q15-pad3_ Q2N2222
+q20 net-_q19-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2222
+q25 net-_q24-pad3_ net-_d1-pad2_ net-_q25-pad3_ Q2N2222
+q31 net-_q30-pad3_ net-_d2-pad1_ net-_q31-pad3_ Q2N2222
+q36 net-_q35-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q41 net-_q40-pad3_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q46 net-_d5-pad2_ net-_d2-pad1_ net-_q36-pad3_ Q2N2222
+q28 net-_q28-pad1_ net-_d1-pad2_ net-_q28-pad3_ Q2N2222
+r3 net-_q10-pad3_ net-_d1-pad2_ 10k
+r7 net-_q15-pad3_ net-_r5-pad1_ 10k
+r11 net-_q20-pad3_ net-_r11-pad2_ 10k
+r15 net-_q25-pad3_ net-_r13-pad1_ 10k
+r19 net-_q31-pad3_ net-_q28-pad1_ 5k
+r16 net-_q28-pad3_ net-_r13-pad1_ 10k
+r13 net-_r13-pad1_ net-_r11-pad2_ 5k
+r9 net-_r11-pad2_ net-_r5-pad1_ 5k
+r5 net-_r5-pad1_ net-_d1-pad2_ 5k
+r21 net-_q36-pad3_ net-_q28-pad1_ 5k
+* Control Statements
+
+.ends DAC0800_Subcircuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml new file mode 100644 index 00000000..d4931ecc --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/DAC0800_Subcircuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q16><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q29><q32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q32><q34><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q34><q37><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q37><q39><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q39><q42><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q42><q45><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q47><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q47><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q33><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q35><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q35><q38><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q38><q40><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q43><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q43><q44><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q44><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q48><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31><q36><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q36><q41><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q41><q46><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q46><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/DAC0800/NPN.lib b/library/SubcircuitLibrary/DAC0800/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/DAC0800/PNP.lib b/library/SubcircuitLibrary/DAC0800/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/DAC0800/analysis b/library/SubcircuitLibrary/DAC0800/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/DAC0800/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib new file mode 100644 index 00000000..889b4267 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir new file mode 100644 index 00000000..e0c1478f --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\HD74LS152\HD74LS152.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/18/25 21:34:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U8 Net-_U1-Pad5_ Net-_U12-Pad2_ Net-_U24-Pad1_ d_and +U9 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U24-Pad2_ d_and +U10 Net-_U1-Pad4_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_and +U14 Net-_U1-Pad2_ Net-_U10-Pad2_ Net-_U14-Pad3_ d_and +U15 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U15-Pad3_ d_and +U16 Net-_U1-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_and +U17 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U1-Pad13_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U11-Pad1_ Net-_U17-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U1-Pad12_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U1-Pad11_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U23 Net-_U13-Pad1_ Net-_U17-Pad2_ Net-_U23-Pad3_ d_and +U32 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U32-Pad3_ d_or +U24 Net-_U24-Pad1_ Net-_U24-Pad2_ Net-_U24-Pad3_ d_and +U25 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U25-Pad3_ d_and +U26 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U14-Pad3_ Net-_U15-Pad3_ Net-_U27-Pad3_ d_and +U28 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U28-Pad3_ d_and +U29 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U29-Pad3_ d_and +U30 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U30-Pad3_ d_and +U31 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U31-Pad3_ d_and +U33 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U33-Pad3_ d_or +U35 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_or +U34 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_or +U36 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U36-Pad3_ d_or +U37 Net-_U35-Pad3_ Net-_U34-Pad3_ Net-_U37-Pad3_ d_or +U38 Net-_U36-Pad3_ Net-_U37-Pad3_ Net-_U38-Pad3_ d_or +U39 Net-_U38-Pad3_ Net-_U1-Pad6_ d_inverter +U4 Net-_U1-Pad10_ Net-_U12-Pad2_ d_inverter +U7 Net-_U12-Pad2_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad9_ Net-_U11-Pad1_ d_inverter +U5 Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter +U3 Net-_U1-Pad8_ Net-_U11-Pad2_ d_inverter +U6 Net-_U11-Pad2_ Net-_U17-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out new file mode 100644 index 00000000..db09e46d --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.cir.out @@ -0,0 +1,164 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir + +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch new file mode 100644 index 00000000..70c27f62 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sch @@ -0,0 +1,904 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:HD74LS152-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U8 +U 1 1 678A887C +P 11800 5150 +F 0 "U8" H 11800 5150 60 0000 C CNN +F 1 "d_and" H 11850 5250 60 0000 C CNN +F 2 "" H 11800 5150 60 0000 C CNN +F 3 "" H 11800 5150 60 0000 C CNN + 1 11800 5150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678A889E +P 11800 5400 +F 0 "U9" H 11800 5400 60 0000 C CNN +F 1 "d_and" H 11850 5500 60 0000 C CNN +F 2 "" H 11800 5400 60 0000 C CNN +F 3 "" H 11800 5400 60 0000 C CNN + 1 11800 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 678A88F4 +P 11800 5850 +F 0 "U10" H 11800 5850 60 0000 C CNN +F 1 "d_and" H 11850 5950 60 0000 C CNN +F 2 "" H 11800 5850 60 0000 C CNN +F 3 "" H 11800 5850 60 0000 C CNN + 1 11800 5850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 678A88FA +P 11800 6100 +F 0 "U11" H 11800 6100 60 0000 C CNN +F 1 "d_and" H 11850 6200 60 0000 C CNN +F 2 "" H 11800 6100 60 0000 C CNN +F 3 "" H 11800 6100 60 0000 C CNN + 1 11800 6100 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 678A8C48 +P 11800 6600 +F 0 "U12" H 11800 6600 60 0000 C CNN +F 1 "d_and" H 11850 6700 60 0000 C CNN +F 2 "" H 11800 6600 60 0000 C CNN +F 3 "" H 11800 6600 60 0000 C CNN + 1 11800 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 678A8C4E +P 11800 6850 +F 0 "U13" H 11800 6850 60 0000 C CNN +F 1 "d_and" H 11850 6950 60 0000 C CNN +F 2 "" H 11800 6850 60 0000 C CNN +F 3 "" H 11800 6850 60 0000 C CNN + 1 11800 6850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 678A8C54 +P 11800 7300 +F 0 "U14" H 11800 7300 60 0000 C CNN +F 1 "d_and" H 11850 7400 60 0000 C CNN +F 2 "" H 11800 7300 60 0000 C CNN +F 3 "" H 11800 7300 60 0000 C CNN + 1 11800 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 678A8C5A +P 11800 7550 +F 0 "U15" H 11800 7550 60 0000 C CNN +F 1 "d_and" H 11850 7650 60 0000 C CNN +F 2 "" H 11800 7550 60 0000 C CNN +F 3 "" H 11800 7550 60 0000 C CNN + 1 11800 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 678A8D88 +P 11800 8000 +F 0 "U16" H 11800 8000 60 0000 C CNN +F 1 "d_and" H 11850 8100 60 0000 C CNN +F 2 "" H 11800 8000 60 0000 C CNN +F 3 "" H 11800 8000 60 0000 C CNN + 1 11800 8000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 678A8D8E +P 11800 8250 +F 0 "U17" H 11800 8250 60 0000 C CNN +F 1 "d_and" H 11850 8350 60 0000 C CNN +F 2 "" H 11800 8250 60 0000 C CNN +F 3 "" H 11800 8250 60 0000 C CNN + 1 11800 8250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 678A8D94 +P 11800 8700 +F 0 "U18" H 11800 8700 60 0000 C CNN +F 1 "d_and" H 11850 8800 60 0000 C CNN +F 2 "" H 11800 8700 60 0000 C CNN +F 3 "" H 11800 8700 60 0000 C CNN + 1 11800 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678A8D9A +P 11800 8950 +F 0 "U19" H 11800 8950 60 0000 C CNN +F 1 "d_and" H 11850 9050 60 0000 C CNN +F 2 "" H 11800 8950 60 0000 C CNN +F 3 "" H 11800 8950 60 0000 C CNN + 1 11800 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_and U20 +U 1 1 678A8DA0 +P 11800 9450 +F 0 "U20" H 11800 9450 60 0000 C CNN +F 1 "d_and" H 11850 9550 60 0000 C CNN +F 2 "" H 11800 9450 60 0000 C CNN +F 3 "" H 11800 9450 60 0000 C CNN + 1 11800 9450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 678A8DA6 +P 11800 9700 +F 0 "U21" H 11800 9700 60 0000 C CNN +F 1 "d_and" H 11850 9800 60 0000 C CNN +F 2 "" H 11800 9700 60 0000 C CNN +F 3 "" H 11800 9700 60 0000 C CNN + 1 11800 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 678A8DAC +P 11800 10150 +F 0 "U22" H 11800 10150 60 0000 C CNN +F 1 "d_and" H 11850 10250 60 0000 C CNN +F 2 "" H 11800 10150 60 0000 C CNN +F 3 "" H 11800 10150 60 0000 C CNN + 1 11800 10150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 678A8DB2 +P 11800 10400 +F 0 "U23" H 11800 10400 60 0000 C CNN +F 1 "d_and" H 11850 10500 60 0000 C CNN +F 2 "" H 11800 10400 60 0000 C CNN +F 3 "" H 11800 10400 60 0000 C CNN + 1 11800 10400 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 678A8DCA +P 14800 5700 +F 0 "U32" H 14800 5700 60 0000 C CNN +F 1 "d_or" H 14800 5800 60 0000 C CNN +F 2 "" H 14800 5700 60 0000 C CNN +F 3 "" H 14800 5700 60 0000 C CNN + 1 14800 5700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 678A8E8A +P 12850 5300 +F 0 "U24" H 12850 5300 60 0000 C CNN +F 1 "d_and" H 12900 5400 60 0000 C CNN +F 2 "" H 12850 5300 60 0000 C CNN +F 3 "" H 12850 5300 60 0000 C CNN + 1 12850 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U25 +U 1 1 678A8FC4 +P 12850 6000 +F 0 "U25" H 12850 6000 60 0000 C CNN +F 1 "d_and" H 12900 6100 60 0000 C CNN +F 2 "" H 12850 6000 60 0000 C CNN +F 3 "" H 12850 6000 60 0000 C CNN + 1 12850 6000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U26 +U 1 1 678A920D +P 12850 6750 +F 0 "U26" H 12850 6750 60 0000 C CNN +F 1 "d_and" H 12900 6850 60 0000 C CNN +F 2 "" H 12850 6750 60 0000 C CNN +F 3 "" H 12850 6750 60 0000 C CNN + 1 12850 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U27 +U 1 1 678A94C5 +P 12850 7450 +F 0 "U27" H 12850 7450 60 0000 C CNN +F 1 "d_and" H 12900 7550 60 0000 C CNN +F 2 "" H 12850 7450 60 0000 C CNN +F 3 "" H 12850 7450 60 0000 C CNN + 1 12850 7450 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 678A94CB +P 12850 8200 +F 0 "U28" H 12850 8200 60 0000 C CNN +F 1 "d_and" H 12900 8300 60 0000 C CNN +F 2 "" H 12850 8200 60 0000 C CNN +F 3 "" H 12850 8200 60 0000 C CNN + 1 12850 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 678A98CF +P 12850 8850 +F 0 "U29" H 12850 8850 60 0000 C CNN +F 1 "d_and" H 12900 8950 60 0000 C CNN +F 2 "" H 12850 8850 60 0000 C CNN +F 3 "" H 12850 8850 60 0000 C CNN + 1 12850 8850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 678A98D5 +P 12850 9550 +F 0 "U30" H 12850 9550 60 0000 C CNN +F 1 "d_and" H 12900 9650 60 0000 C CNN +F 2 "" H 12850 9550 60 0000 C CNN +F 3 "" H 12850 9550 60 0000 C CNN + 1 12850 9550 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 678A98DB +P 12850 10300 +F 0 "U31" H 12850 10300 60 0000 C CNN +F 1 "d_and" H 12900 10400 60 0000 C CNN +F 2 "" H 12850 10300 60 0000 C CNN +F 3 "" H 12850 10300 60 0000 C CNN + 1 12850 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U33 +U 1 1 678A9B5E +P 14850 7100 +F 0 "U33" H 14850 7100 60 0000 C CNN +F 1 "d_or" H 14850 7200 60 0000 C CNN +F 2 "" H 14850 7100 60 0000 C CNN +F 3 "" H 14850 7100 60 0000 C CNN + 1 14850 7100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U35 +U 1 1 678A9BE6 +P 14900 8450 +F 0 "U35" H 14900 8450 60 0000 C CNN +F 1 "d_or" H 14900 8550 60 0000 C CNN +F 2 "" H 14900 8450 60 0000 C CNN +F 3 "" H 14900 8450 60 0000 C CNN + 1 14900 8450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U34 +U 1 1 678A9CC3 +P 14850 9750 +F 0 "U34" H 14850 9750 60 0000 C CNN +F 1 "d_or" H 14850 9850 60 0000 C CNN +F 2 "" H 14850 9750 60 0000 C CNN +F 3 "" H 14850 9750 60 0000 C CNN + 1 14850 9750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U36 +U 1 1 678A9D59 +P 16150 6650 +F 0 "U36" H 16150 6650 60 0000 C CNN +F 1 "d_or" H 16150 6750 60 0000 C CNN +F 2 "" H 16150 6650 60 0000 C CNN +F 3 "" H 16150 6650 60 0000 C CNN + 1 16150 6650 + 1 0 0 -1 +$EndComp +$Comp +L d_or U37 +U 1 1 678A9DEC +P 16200 9200 +F 0 "U37" H 16200 9200 60 0000 C CNN +F 1 "d_or" H 16200 9300 60 0000 C CNN +F 2 "" H 16200 9200 60 0000 C CNN +F 3 "" H 16200 9200 60 0000 C CNN + 1 16200 9200 + 1 0 0 -1 +$EndComp +$Comp +L d_or U38 +U 1 1 678A9E94 +P 17350 7850 +F 0 "U38" H 17350 7850 60 0000 C CNN +F 1 "d_or" H 17350 7950 60 0000 C CNN +F 2 "" H 17350 7850 60 0000 C CNN +F 3 "" H 17350 7850 60 0000 C CNN + 1 17350 7850 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678A9F5D +P 18300 7800 +F 0 "U39" H 18300 7700 60 0000 C CNN +F 1 "d_inverter" H 18300 7950 60 0000 C CNN +F 2 "" H 18350 7750 60 0000 C CNN +F 3 "" H 18350 7750 60 0000 C CNN + 1 18300 7800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 678AABC1 +P 6750 11250 +F 0 "U4" H 6750 11150 60 0000 C CNN +F 1 "d_inverter" H 6750 11400 60 0000 C CNN +F 2 "" H 6800 11200 60 0000 C CNN +F 3 "" H 6800 11200 60 0000 C CNN + 1 6750 11250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 678AACCC +P 8500 11250 +F 0 "U7" H 8500 11150 60 0000 C CNN +F 1 "d_inverter" H 8500 11400 60 0000 C CNN +F 2 "" H 8550 11200 60 0000 C CNN +F 3 "" H 8550 11200 60 0000 C CNN + 1 8500 11250 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U2 +U 1 1 678AADA6 +P 6700 11950 +F 0 "U2" H 6700 11850 60 0000 C CNN +F 1 "d_inverter" H 6700 12100 60 0000 C CNN +F 2 "" H 6750 11900 60 0000 C CNN +F 3 "" H 6750 11900 60 0000 C CNN + 1 6700 11950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 678AADAC +P 8450 11950 +F 0 "U5" H 8450 11850 60 0000 C CNN +F 1 "d_inverter" H 8450 12100 60 0000 C CNN +F 2 "" H 8500 11900 60 0000 C CNN +F 3 "" H 8500 11900 60 0000 C CNN + 1 8450 11950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U3 +U 1 1 678AAE38 +P 6700 12700 +F 0 "U3" H 6700 12600 60 0000 C CNN +F 1 "d_inverter" H 6700 12850 60 0000 C CNN +F 2 "" H 6750 12650 60 0000 C CNN +F 3 "" H 6750 12650 60 0000 C CNN + 1 6700 12700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 678AAE3E +P 8450 12700 +F 0 "U6" H 8450 12600 60 0000 C CNN +F 1 "d_inverter" H 8450 12850 60 0000 C CNN +F 2 "" H 8500 12650 60 0000 C CNN +F 3 "" H 8500 12650 60 0000 C CNN + 1 8450 12700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7000 12700 8150 12700 +Wire Wire Line + 8150 11950 7000 11950 +Wire Wire Line + 7050 11250 8200 11250 +Wire Wire Line + 7900 11250 7900 10750 +Wire Wire Line + 7900 10750 10300 10750 +Wire Wire Line + 10300 10750 10300 5150 +Wire Wire Line + 10300 9450 11350 9450 +Connection ~ 7900 11250 +Wire Wire Line + 10300 8000 11350 8000 +Connection ~ 10300 9450 +Wire Wire Line + 10300 6600 11350 6600 +Connection ~ 10300 8000 +Wire Wire Line + 10300 5150 11350 5150 +Connection ~ 10300 6600 +Wire Wire Line + 10500 11250 8800 11250 +Wire Wire Line + 10500 5850 10500 11250 +Wire Wire Line + 10500 10150 11350 10150 +Wire Wire Line + 10500 8700 11350 8700 +Connection ~ 10500 10150 +Wire Wire Line + 10500 7300 11350 7300 +Connection ~ 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7900 30 0000 C CNN +F 1 "PORT" H 19200 7800 30 0000 C CNN +F 2 "" H 19200 7800 60 0000 C CNN +F 3 "" H 19200 7800 60 0000 C CNN + 6 19200 7800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 678BA3D2 +P 6500 5050 +F 0 "U1" H 6550 5150 30 0000 C CNN +F 1 "PORT" H 6500 5050 30 0000 C CNN +F 2 "" H 6500 5050 60 0000 C CNN +F 3 "" H 6500 5050 60 0000 C CNN + 5 6500 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 678BA4DF +P 6450 5750 +F 0 "U1" H 6500 5850 30 0000 C CNN +F 1 "PORT" H 6450 5750 30 0000 C CNN +F 2 "" H 6450 5750 60 0000 C CNN +F 3 "" H 6450 5750 60 0000 C CNN + 4 6450 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 678BA54C +P 6450 6500 +F 0 "U1" H 6500 6600 30 0000 C CNN +F 1 "PORT" H 6450 6500 30 0000 C CNN +F 2 "" H 6450 6500 60 0000 C CNN +F 3 "" H 6450 6500 60 0000 C CNN + 3 6450 6500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 678BA63F +P 6450 7200 +F 0 "U1" H 6500 7300 30 0000 C CNN +F 1 "PORT" H 6450 7200 30 0000 C CNN +F 2 "" H 6450 7200 60 0000 C CNN +F 3 "" H 6450 7200 60 0000 C CNN + 2 6450 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 678BA760 +P 6450 7900 +F 0 "U1" H 6500 8000 30 0000 C CNN +F 1 "PORT" H 6450 7900 30 0000 C CNN +F 2 "" H 6450 7900 60 0000 C CNN +F 3 "" H 6450 7900 60 0000 C CNN + 1 6450 7900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 678BAA39 +P 6500 8600 +F 0 "U1" H 6550 8700 30 0000 C CNN +F 1 "PORT" H 6500 8600 30 0000 C CNN +F 2 "" H 6500 8600 60 0000 C CNN +F 3 "" H 6500 8600 60 0000 C CNN + 13 6500 8600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 678BAAB4 +P 6350 9350 +F 0 "U1" H 6400 9450 30 0000 C CNN +F 1 "PORT" H 6350 9350 30 0000 C CNN +F 2 "" H 6350 9350 60 0000 C CNN +F 3 "" H 6350 9350 60 0000 C CNN + 12 6350 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 678BAB2F +P 6350 10050 +F 0 "U1" H 6400 10150 30 0000 C CNN +F 1 "PORT" H 6350 10050 30 0000 C CNN +F 2 "" H 6350 10050 60 0000 C CNN +F 3 "" H 6350 10050 60 0000 C CNN + 11 6350 10050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 678BAD20 +P 5850 11250 +F 0 "U1" H 5900 11350 30 0000 C CNN +F 1 "PORT" H 5850 11250 30 0000 C CNN +F 2 "" H 5850 11250 60 0000 C CNN +F 3 "" H 5850 11250 60 0000 C CNN + 10 5850 11250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 678BAD9B +P 5850 11950 +F 0 "U1" H 5900 12050 30 0000 C CNN +F 1 "PORT" H 5850 11950 30 0000 C CNN +F 2 "" H 5850 11950 60 0000 C CNN +F 3 "" H 5850 11950 60 0000 C CNN + 9 5850 11950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 678BB0C4 +P 5850 12700 +F 0 "U1" H 5900 12800 30 0000 C CNN +F 1 "PORT" H 5850 12700 30 0000 C CNN +F 2 "" H 5850 12700 60 0000 C CNN +F 3 "" H 5850 12700 60 0000 C CNN + 8 5850 12700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 678BB437 +P 13400 11500 +F 0 "U1" H 13450 11600 30 0000 C CNN +F 1 "PORT" H 13400 11500 30 0000 C CNN +F 2 "" H 13400 11500 60 0000 C CNN +F 3 "" H 13400 11500 60 0000 C CNN + 7 13400 11500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 678BB54B +P 13400 11750 +F 0 "U1" H 13450 11850 30 0000 C CNN +F 1 "PORT" H 13400 11750 30 0000 C CNN +F 2 "" H 13400 11750 60 0000 C CNN +F 3 "" H 13400 11750 60 0000 C CNN + 14 13400 11750 + 1 0 0 -1 +$EndComp +NoConn ~ 13650 11500 +NoConn ~ 13650 11750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub new file mode 100644 index 00000000..3604a713 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152.sub @@ -0,0 +1,158 @@ +* Subcircuit HD74LS152 +.subckt HD74LS152 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\hd74ls152\hd74ls152.cir +* u8 net-_u1-pad5_ net-_u12-pad2_ net-_u24-pad1_ d_and +* u9 net-_u11-pad1_ net-_u11-pad2_ net-_u24-pad2_ d_and +* u10 net-_u1-pad4_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_and +* u14 net-_u1-pad2_ net-_u10-pad2_ net-_u14-pad3_ d_and +* u15 net-_u13-pad1_ net-_u11-pad2_ net-_u15-pad3_ d_and +* u16 net-_u1-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_and +* u17 net-_u11-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_and +* u18 net-_u1-pad13_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u19 net-_u11-pad1_ net-_u17-pad2_ net-_u19-pad3_ d_and +* u20 net-_u1-pad12_ net-_u12-pad2_ net-_u20-pad3_ d_and +* u21 net-_u13-pad1_ net-_u17-pad2_ net-_u21-pad3_ d_and +* u22 net-_u1-pad11_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u23 net-_u13-pad1_ net-_u17-pad2_ net-_u23-pad3_ d_and +* u32 net-_u24-pad3_ net-_u25-pad3_ net-_u32-pad3_ d_or +* u24 net-_u24-pad1_ net-_u24-pad2_ net-_u24-pad3_ d_and +* u25 net-_u10-pad3_ net-_u11-pad3_ net-_u25-pad3_ d_and +* u26 net-_u12-pad3_ net-_u13-pad3_ net-_u26-pad3_ d_and +* u27 net-_u14-pad3_ net-_u15-pad3_ net-_u27-pad3_ d_and +* u28 net-_u16-pad3_ net-_u17-pad3_ net-_u28-pad3_ d_and +* u29 net-_u18-pad3_ net-_u19-pad3_ net-_u29-pad3_ d_and +* u30 net-_u20-pad3_ net-_u21-pad3_ net-_u30-pad3_ d_and +* u31 net-_u22-pad3_ net-_u23-pad3_ net-_u31-pad3_ d_and +* u33 net-_u26-pad3_ net-_u27-pad3_ net-_u33-pad3_ d_or +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_or +* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_or +* u36 net-_u32-pad3_ net-_u33-pad3_ net-_u36-pad3_ d_or +* u37 net-_u35-pad3_ net-_u34-pad3_ net-_u37-pad3_ d_or +* u38 net-_u36-pad3_ net-_u37-pad3_ net-_u38-pad3_ d_or +* u39 net-_u38-pad3_ net-_u1-pad6_ d_inverter +* u4 net-_u1-pad10_ net-_u12-pad2_ d_inverter +* u7 net-_u12-pad2_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad9_ net-_u11-pad1_ d_inverter +* u5 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u1-pad8_ net-_u11-pad2_ d_inverter +* u6 net-_u11-pad2_ net-_u17-pad2_ d_inverter +a1 [net-_u1-pad5_ net-_u12-pad2_ ] net-_u24-pad1_ u8 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u24-pad2_ u9 +a3 [net-_u1-pad4_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a5 [net-_u1-pad3_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u1-pad2_ net-_u10-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u15-pad3_ u15 +a9 [net-_u1-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a11 [net-_u1-pad13_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a12 [net-_u11-pad1_ net-_u17-pad2_ ] net-_u19-pad3_ u19 +a13 [net-_u1-pad12_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a14 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u21-pad3_ u21 +a15 [net-_u1-pad11_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a16 [net-_u13-pad1_ net-_u17-pad2_ ] net-_u23-pad3_ u23 +a17 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u32-pad3_ u32 +a18 [net-_u24-pad1_ net-_u24-pad2_ ] net-_u24-pad3_ u24 +a19 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u26-pad3_ u26 +a21 [net-_u14-pad3_ net-_u15-pad3_ ] net-_u27-pad3_ u27 +a22 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u28-pad3_ u28 +a23 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u29-pad3_ u29 +a24 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u30-pad3_ u30 +a25 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u31-pad3_ u31 +a26 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u33-pad3_ u33 +a27 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a28 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34 +a29 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u36-pad3_ u36 +a30 [net-_u35-pad3_ net-_u34-pad3_ ] net-_u37-pad3_ u37 +a31 [net-_u36-pad3_ net-_u37-pad3_ ] net-_u38-pad3_ u38 +a32 net-_u38-pad3_ net-_u1-pad6_ u39 +a33 net-_u1-pad10_ net-_u12-pad2_ u4 +a34 net-_u12-pad2_ net-_u10-pad2_ u7 +a35 net-_u1-pad9_ net-_u11-pad1_ u2 +a36 net-_u11-pad1_ net-_u13-pad1_ u5 +a37 net-_u1-pad8_ net-_u11-pad2_ u3 +a38 net-_u11-pad2_ net-_u17-pad2_ u6 +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u33 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u35 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u34 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u36 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u37 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u38 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends HD74LS152
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml new file mode 100644 index 00000000..044e3a73 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/HD74LS152_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_and<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u8><u9 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u21><u22 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /></u22><u23 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /></u23><u32 name="type">d_or<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /></u32><u24 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /></u24><u25 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /></u25><u26 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u26><u27 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Fall Delay (default=1.0e-9)" /></u27><u28 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Fall Delay (default=1.0e-9)" /></u28><u29 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Fall Delay (default=1.0e-9)" /></u29><u30 name="type">d_and<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Fall Delay (default=1.0e-9)" /></u30><u31 name="type">d_and<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /></u31><u33 name="type">d_or<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /></u33><u35 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /></u35><u34 name="type">d_or<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /></u34><u36 name="type">d_or<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /></u36><u37 name="type">d_or<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u37><u38 name="type">d_or<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /></u38><u39 name="type">d_inverter<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /></u39><u4 name="type">d_inverter<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /></u4><u7 name="type">d_inverter<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /></u7><u2 name="type">d_inverter<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /></u2><u5 name="type">d_inverter<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /></u5><u3 name="type">d_inverter<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /></u3><u6 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/HD74LS152/analysis b/library/SubcircuitLibrary/HD74LS152/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/HD74LS152/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/D.lib b/library/SubcircuitLibrary/LF147_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib b/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib new file mode 100644 index 00000000..6e89a43f --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC-cache.lib @@ -0,0 +1,186 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_p +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir new file mode 100644 index 00000000..4b2bbf21 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir @@ -0,0 +1,67 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LF147_IC\LF147_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/12/24 14:21:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 80u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 400u +J1 Net-_I1-Pad2_ Net-_J1-Pad2_ Net-_D1-Pad1_ jfet_p +J3 Net-_I1-Pad2_ Net-_J3-Pad2_ Net-_C1-Pad2_ jfet_p +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R1 Net-_D1-Pad2_ Net-_Q11-Pad3_ 5k +Q1 Net-_C1-Pad2_ Net-_D1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +R3 Net-_Q1-Pad3_ Net-_Q11-Pad3_ 2k +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D3-Pad2_ Net-_C1-Pad1_ eSim_Diode +Q3 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q5 Net-_I1-Pad1_ Net-_D3-Pad1_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q11-Pad3_ Net-_C1-Pad1_ Net-_Q5-Pad3_ eSim_PNP +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +I5 Net-_I1-Pad1_ Net-_I5-Pad2_ 80u +I7 Net-_I1-Pad1_ Net-_D9-Pad1_ 400u +J5 Net-_I5-Pad2_ Net-_J5-Pad2_ Net-_D7-Pad1_ jfet_p +J7 Net-_I5-Pad2_ Net-_J7-Pad2_ Net-_C3-Pad2_ jfet_p +D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode +R5 Net-_D7-Pad2_ Net-_Q11-Pad3_ 5k +Q9 Net-_C3-Pad2_ Net-_D7-Pad1_ Net-_Q9-Pad3_ eSim_NPN +R7 Net-_Q9-Pad3_ Net-_Q11-Pad3_ 2k +D9 Net-_D9-Pad1_ Net-_D10-Pad1_ eSim_Diode +D10 Net-_D10-Pad1_ Net-_C3-Pad1_ eSim_Diode +Q11 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q13 Net-_I1-Pad1_ Net-_D9-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_Q11-Pad3_ Net-_C3-Pad1_ Net-_Q13-Pad3_ eSim_PNP +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10p +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 80u +I4 Net-_I1-Pad1_ Net-_D5-Pad1_ 400u +J2 Net-_I2-Pad2_ Net-_J2-Pad2_ Net-_D2-Pad1_ jfet_p +J4 Net-_I2-Pad2_ Net-_J4-Pad2_ Net-_C2-Pad2_ jfet_p +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R2 Net-_D2-Pad2_ Net-_Q11-Pad3_ 5k +Q2 Net-_C2-Pad2_ Net-_D2-Pad1_ Net-_Q2-Pad3_ eSim_NPN +R4 Net-_Q2-Pad3_ Net-_Q11-Pad3_ 2k +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D5-Pad2_ Net-_C2-Pad1_ eSim_Diode +Q4 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q7 Net-_I1-Pad1_ Net-_D5-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q8 Net-_Q11-Pad3_ Net-_C2-Pad1_ Net-_Q7-Pad3_ eSim_PNP +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10p +I6 Net-_I1-Pad1_ Net-_I6-Pad2_ 80u +I8 Net-_I1-Pad1_ Net-_D11-Pad1_ 400u +J6 Net-_I6-Pad2_ Net-_J6-Pad2_ Net-_D8-Pad1_ jfet_p +J8 Net-_I6-Pad2_ Net-_J8-Pad2_ Net-_C4-Pad2_ jfet_p +D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode +R6 Net-_D8-Pad2_ Net-_Q11-Pad3_ 5k +Q10 Net-_C4-Pad2_ Net-_D8-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R8 Net-_Q10-Pad3_ Net-_Q11-Pad3_ 2k +D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode +D12 Net-_D11-Pad2_ Net-_C4-Pad1_ eSim_Diode +Q12 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q15 Net-_I1-Pad1_ Net-_D11-Pad1_ Net-_Q15-Pad3_ eSim_NPN +Q16 Net-_Q11-Pad3_ Net-_C4-Pad1_ Net-_Q15-Pad3_ eSim_PNP +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 10p +U1 Net-_Q5-Pad3_ Net-_J1-Pad2_ Net-_J3-Pad2_ Net-_I1-Pad1_ Net-_J4-Pad2_ Net-_J2-Pad2_ Net-_Q7-Pad3_ Net-_Q15-Pad3_ Net-_J6-Pad2_ Net-_J8-Pad2_ Net-_Q11-Pad3_ Net-_J7-Pad2_ Net-_J5-Pad2_ Net-_Q13-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out new file mode 100644 index 00000000..44d64043 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.cir.out @@ -0,0 +1,72 @@ +* d:\fossee\esim\library\subcircuitlibrary\lf147_ic\lf147_ic.cir + +.include PNP.lib +.include D.lib +.include NPN.lib +.include PJF.lib +i1 net-_i1-pad1_ net-_i1-pad2_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 400u +j1 net-_i1-pad2_ net-_j1-pad2_ net-_d1-pad1_ J2N3820 +j3 net-_i1-pad2_ net-_j3-pad2_ net-_c1-pad2_ J2N3820 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_d1-pad2_ net-_q11-pad3_ 5k +q1 net-_c1-pad2_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q11-pad3_ 2k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_c1-pad1_ 1N4148 +q3 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_i1-pad1_ net-_d3-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q11-pad3_ net-_c1-pad1_ net-_q5-pad3_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +i5 net-_i1-pad1_ net-_i5-pad2_ 80u +i7 net-_i1-pad1_ net-_d9-pad1_ 400u +j5 net-_i5-pad2_ net-_j5-pad2_ net-_d7-pad1_ J2N3820 +j7 net-_i5-pad2_ net-_j7-pad2_ net-_c3-pad2_ J2N3820 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +r5 net-_d7-pad2_ net-_q11-pad3_ 5k +q9 net-_c3-pad2_ net-_d7-pad1_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_q11-pad3_ 2k +d9 net-_d9-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_c3-pad1_ 1N4148 +q11 net-_c3-pad1_ net-_c3-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_d9-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q11-pad3_ net-_c3-pad1_ net-_q13-pad3_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +i4 net-_i1-pad1_ net-_d5-pad1_ 400u +j2 net-_i2-pad2_ net-_j2-pad2_ net-_d2-pad1_ J2N3820 +j4 net-_i2-pad2_ net-_j4-pad2_ net-_c2-pad2_ J2N3820 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q11-pad3_ 5k +q2 net-_c2-pad2_ net-_d2-pad1_ net-_q2-pad3_ Q2N2222 +r4 net-_q2-pad3_ net-_q11-pad3_ 2k +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad2_ net-_c2-pad1_ 1N4148 +q4 net-_c2-pad1_ net-_c2-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_i1-pad1_ net-_d5-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q11-pad3_ net-_c2-pad1_ net-_q7-pad3_ Q2N2907A +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +i6 net-_i1-pad1_ net-_i6-pad2_ 80u +i8 net-_i1-pad1_ net-_d11-pad1_ 400u +j6 net-_i6-pad2_ net-_j6-pad2_ net-_d8-pad1_ J2N3820 +j8 net-_i6-pad2_ net-_j8-pad2_ net-_c4-pad2_ J2N3820 +d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148 +r6 net-_d8-pad2_ net-_q11-pad3_ 5k +q10 net-_c4-pad2_ net-_d8-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_q10-pad3_ net-_q11-pad3_ 2k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d12 net-_d11-pad2_ net-_c4-pad1_ 1N4148 +q12 net-_c4-pad1_ net-_c4-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_i1-pad1_ net-_d11-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q11-pad3_ net-_c4-pad1_ net-_q15-pad3_ Q2N2907A +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +* u1 net-_q5-pad3_ net-_j1-pad2_ net-_j3-pad2_ net-_i1-pad1_ net-_j4-pad2_ net-_j2-pad2_ net-_q7-pad3_ net-_q15-pad3_ net-_j6-pad2_ net-_j8-pad2_ net-_q11-pad3_ net-_j7-pad2_ net-_j5-pad2_ net-_q13-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro b/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch new file mode 100644 index 00000000..243f479c --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sch @@ -0,0 +1,1186 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LF147_simplified_circuit-cache +EELAYER 25 0 +EELAYER END +$Descr User 31496 23622 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I1 +U 1 1 6690E555 +P 4850 4800 +F 0 "I1" H 4650 4900 60 0000 C CNN +F 1 "80u" H 4650 4750 60 0000 C CNN +F 2 "R1" H 4550 4800 60 0000 C CNN +F 3 "" H 4850 4800 60 0000 C CNN + 1 4850 4800 + 1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 6690E556 +P 7350 4700 +F 0 "I3" H 7150 4800 60 0000 C CNN +F 1 "400u" H 7150 4650 60 0000 C CNN +F 2 "R1" H 7050 4700 60 0000 C CNN +F 3 "" H 7350 4700 60 0000 C CNN + 1 7350 4700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J1 +U 1 1 6690E557 +P 4400 5800 +F 0 "J1" H 4300 5850 50 0000 R CNN +F 1 "jfet_p" H 4350 5950 50 0000 R CNN +F 2 "" H 4600 5900 29 0000 C CNN +F 3 "" H 4400 5800 60 0000 C CNN + 1 4400 5800 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J3 +U 1 1 6690E558 +P 5450 5800 +F 0 "J3" H 5350 5850 50 0000 R CNN +F 1 "jfet_p" H 5400 5950 50 0000 R CNN +F 2 "" H 5650 5900 29 0000 C CNN +F 3 "" H 5450 5800 60 0000 C CNN + 1 5450 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6690E559 +P 4500 7050 +F 0 "D1" H 4500 7150 50 0000 C CNN +F 1 "eSim_Diode" H 4500 6950 50 0000 C CNN +F 2 "" H 4500 7050 60 0000 C CNN +F 3 "" H 4500 7050 60 0000 C CNN + 1 4500 7050 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6690E55A +P 4450 7500 +F 0 "R1" H 4500 7630 50 0000 C CNN +F 1 "5k" H 4500 7450 50 0000 C CNN +F 2 "" H 4500 7480 30 0000 C CNN +F 3 "" V 4500 7550 30 0000 C CNN + 1 4450 7500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6690E55B +P 5250 6800 +F 0 "Q1" H 5150 6850 50 0000 R CNN +F 1 "eSim_NPN" H 5200 6950 50 0000 R CNN +F 2 "" H 5450 6900 29 0000 C CNN +F 3 "" H 5250 6800 60 0000 C CNN + 1 5250 6800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6690E55C +P 5300 7500 +F 0 "R3" H 5350 7630 50 0000 C CNN +F 1 "2k" H 5350 7450 50 0000 C CNN +F 2 "" H 5350 7480 30 0000 C CNN +F 3 "" V 5350 7550 30 0000 C CNN + 1 5300 7500 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6690E55D +P 7350 5600 +F 0 "D3" H 7350 5700 50 0000 C CNN +F 1 "eSim_Diode" H 7350 5500 50 0000 C CNN +F 2 "" H 7350 5600 60 0000 C CNN +F 3 "" H 7350 5600 60 0000 C CNN + 1 7350 5600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6690E55E +P 7350 6000 +F 0 "D4" H 7350 6100 50 0000 C CNN +F 1 "eSim_Diode" H 7350 5900 50 0000 C CNN +F 2 "" H 7350 6000 60 0000 C CNN +F 3 "" H 7350 6000 60 0000 C CNN + 1 7350 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6690E55F +P 7250 7150 +F 0 "Q3" H 7150 7200 50 0000 R CNN +F 1 "eSim_NPN" H 7200 7300 50 0000 R CNN +F 2 "" H 7450 7250 29 0000 C CNN +F 3 "" H 7250 7150 60 0000 C CNN + 1 7250 7150 + 1 0 0 -1 +$EndComp +$Comp +L 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19500 17550 19500 17000 +Wire Wire Line + 11150 17550 23650 17550 +Wire Wire Line + 20350 17550 20350 17000 +Wire Wire Line + 20050 16100 19500 16100 +Connection ~ 19500 16100 +Wire Wire Line + 22350 15050 22350 15150 +Wire Wire Line + 22350 14450 22350 14750 +Wire Wire Line + 22350 17550 22350 16650 +Connection ~ 20350 17550 +Wire Wire Line + 22350 15450 22350 16250 +Wire Wire Line + 23650 13400 23650 14350 +Wire Wire Line + 14100 13400 23650 13400 +Wire Wire Line + 19850 13400 19850 13650 +Wire Wire Line + 22350 13550 22350 13400 +Connection ~ 22350 13400 +Wire Wire Line + 23650 14750 23650 15450 +Wire Wire Line + 23650 17550 23650 15850 +Connection ~ 22350 17550 +Connection ~ 21350 16450 +Connection ~ 19850 13400 +Connection ~ 19500 17550 +Wire Wire Line + 23650 15100 24800 15100 +Connection ~ 23650 15100 +Wire Wire Line + 23350 14550 22350 14550 +Connection ~ 22350 14550 +Wire Wire Line + 20650 15100 20950 15100 +Wire Wire Line + 23350 15650 22600 15650 +Wire Wire Line + 22600 15650 22600 16100 +Wire Wire Line + 22600 16100 22050 16100 +Connection ~ 22350 16100 +Wire Wire Line + 21750 16100 21350 16100 +Wire Wire Line + 21350 16100 21350 16450 +Wire Wire Line + 20700 16450 22050 16450 +Wire Wire Line + 20700 16450 20700 15600 +Wire Wire Line + 20700 15600 20350 15600 +Connection ~ 20350 15600 +Wire Wire Line + 18950 15100 19200 15100 +$Comp +L PORT U1 +U 2 1 66911BD9 +P 3700 5800 +F 0 "U1" H 3750 5900 30 0000 C CNN +F 1 "PORT" H 3700 5800 30 0000 C CNN +F 2 "" H 3700 5800 60 0000 C CNN +F 3 "" H 3700 5800 60 0000 C CNN + 2 3700 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6691217F +P 6200 5800 +F 0 "U1" H 6250 5900 30 0000 C CNN +F 1 "PORT" H 6200 5800 30 0000 C CNN +F 2 "" H 6200 5800 60 0000 C CNN +F 3 "" H 6200 5800 60 0000 C CNN + 3 6200 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 66912CA1 +P 10050 5800 +F 0 "U1" H 10100 5900 30 0000 C CNN +F 1 "PORT" H 10050 5800 30 0000 C CNN +F 2 "" H 10050 5800 60 0000 C CNN +F 3 "" H 10050 5800 60 0000 C CNN + 1 10050 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 6691397B +P 18350 5700 +F 0 "U1" H 18400 5800 30 0000 C CNN +F 1 "PORT" H 18350 5700 30 0000 C CNN +F 2 "" H 18350 5700 60 0000 C CNN +F 3 "" H 18350 5700 60 0000 C CNN + 13 18350 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 669150B9 +P 20850 5700 +F 0 "U1" H 20900 5800 30 0000 C CNN +F 1 "PORT" H 20850 5700 30 0000 C CNN +F 2 "" H 20850 5700 60 0000 C CNN +F 3 "" H 20850 5700 60 0000 C CNN + 12 20850 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 6691577B +P 24700 5700 +F 0 "U1" H 24750 5800 30 0000 C CNN +F 1 "PORT" H 24700 5700 30 0000 C CNN +F 2 "" H 24700 5700 60 0000 C CNN +F 3 "" H 24700 5700 60 0000 C CNN + 14 24700 5700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 669161F1 +P 10450 15650 +F 0 "U1" H 10500 15750 30 0000 C CNN +F 1 "PORT" H 10450 15650 30 0000 C CNN +F 2 "" H 10450 15650 60 0000 C CNN +F 3 "" H 10450 15650 60 0000 C CNN + 7 10450 15650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 66917212 +P 4100 15650 +F 0 "U1" H 4150 15750 30 0000 C CNN +F 1 "PORT" H 4100 15650 30 0000 C CNN +F 2 "" H 4100 15650 60 0000 C CNN +F 3 "" H 4100 15650 60 0000 C CNN + 6 4100 15650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6691775E +P 6600 15650 +F 0 "U1" H 6650 15750 30 0000 C CNN +F 1 "PORT" H 6600 15650 30 0000 C CNN +F 2 "" H 6600 15650 60 0000 C CNN +F 3 "" H 6600 15650 60 0000 C CNN + 5 6600 15650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 66918407 +P 25050 15100 +F 0 "U1" H 25100 15200 30 0000 C CNN +F 1 "PORT" H 25050 15100 30 0000 C CNN +F 2 "" H 25050 15100 60 0000 C CNN +F 3 "" H 25050 15100 60 0000 C CNN + 8 25050 15100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 669199DD +P 18700 15100 +F 0 "U1" H 18750 15200 30 0000 C CNN +F 1 "PORT" H 18700 15100 30 0000 C CNN +F 2 "" H 18700 15100 60 0000 C CNN +F 3 "" H 18700 15100 60 0000 C CNN + 9 18700 15100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6691A785 +P 21200 15100 +F 0 "U1" H 21250 15200 30 0000 C CNN +F 1 "PORT" H 21200 15100 30 0000 C CNN +F 2 "" H 21200 15100 60 0000 C CNN +F 3 "" H 21200 15100 60 0000 C CNN + 10 21200 15100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6691B2C4 +P 2650 8250 +F 0 "U1" H 2700 8350 30 0000 C CNN +F 1 "PORT" H 2650 8250 30 0000 C CNN +F 2 "" H 2650 8250 60 0000 C CNN +F 3 "" H 2650 8250 60 0000 C CNN + 11 2650 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 18450 8150 18450 8650 +Wire Wire Line + 18450 8650 4200 8650 +Wire Wire Line + 4200 8650 4200 8250 +Connection ~ 4200 8250 +Wire Wire Line + 11150 17550 11150 9350 +Wire Wire Line + 11150 9350 3900 9350 +Wire Wire Line + 3900 9350 3900 8250 +Connection ~ 3900 8250 +Wire Wire Line + 1900 18100 1900 8900 +Wire Wire Line + 1900 8900 3550 8900 +Wire Wire Line + 3550 8900 3550 8250 +Connection ~ 3550 8250 +Wire Wire Line + 1500 13950 1500 5400 +Wire Wire Line + 1500 5400 4250 5400 +Wire Wire Line + 4250 5400 4250 4100 +Connection ~ 4250 4100 +$Comp +L PORT U1 +U 4 1 669208AB +P 3200 4100 +F 0 "U1" H 3250 4200 30 0000 C CNN +F 1 "PORT" H 3200 4100 30 0000 C CNN +F 2 "" H 3200 4100 60 0000 C CNN +F 3 "" H 3200 4100 60 0000 C CNN + 4 3200 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14100 13400 14100 3200 +Wire Wire Line + 14100 3200 4100 3200 +Wire Wire Line + 4100 3200 4100 4100 +Connection ~ 4100 4100 +Wire Wire Line + 4150 4000 4150 4100 +Connection ~ 4150 4100 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub new file mode 100644 index 00000000..e4cccc57 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC.sub @@ -0,0 +1,66 @@ +* Subcircuit LF147_IC +.subckt LF147_IC net-_q5-pad3_ net-_j1-pad2_ net-_j3-pad2_ net-_i1-pad1_ net-_j4-pad2_ net-_j2-pad2_ net-_q7-pad3_ net-_q15-pad3_ net-_j6-pad2_ net-_j8-pad2_ net-_q11-pad3_ net-_j7-pad2_ net-_j5-pad2_ net-_q13-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\lf147_ic\lf147_ic.cir +.include PNP.lib +.include D.lib +.include NPN.lib +.include PJF.lib +i1 net-_i1-pad1_ net-_i1-pad2_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 400u +j1 net-_i1-pad2_ net-_j1-pad2_ net-_d1-pad1_ J2N3820 +j3 net-_i1-pad2_ net-_j3-pad2_ net-_c1-pad2_ J2N3820 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r1 net-_d1-pad2_ net-_q11-pad3_ 5k +q1 net-_c1-pad2_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q11-pad3_ 2k +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_c1-pad1_ 1N4148 +q3 net-_c1-pad1_ net-_c1-pad2_ net-_q11-pad3_ Q2N2222 +q5 net-_i1-pad1_ net-_d3-pad1_ net-_q5-pad3_ Q2N2222 +q6 net-_q11-pad3_ net-_c1-pad1_ net-_q5-pad3_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +i5 net-_i1-pad1_ net-_i5-pad2_ 80u +i7 net-_i1-pad1_ net-_d9-pad1_ 400u +j5 net-_i5-pad2_ net-_j5-pad2_ net-_d7-pad1_ J2N3820 +j7 net-_i5-pad2_ net-_j7-pad2_ net-_c3-pad2_ J2N3820 +d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148 +r5 net-_d7-pad2_ net-_q11-pad3_ 5k +q9 net-_c3-pad2_ net-_d7-pad1_ net-_q9-pad3_ Q2N2222 +r7 net-_q9-pad3_ net-_q11-pad3_ 2k +d9 net-_d9-pad1_ net-_d10-pad1_ 1N4148 +d10 net-_d10-pad1_ net-_c3-pad1_ 1N4148 +q11 net-_c3-pad1_ net-_c3-pad2_ net-_q11-pad3_ Q2N2222 +q13 net-_i1-pad1_ net-_d9-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_q11-pad3_ net-_c3-pad1_ net-_q13-pad3_ Q2N2907A +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +i4 net-_i1-pad1_ net-_d5-pad1_ 400u +j2 net-_i2-pad2_ net-_j2-pad2_ net-_d2-pad1_ J2N3820 +j4 net-_i2-pad2_ net-_j4-pad2_ net-_c2-pad2_ J2N3820 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r2 net-_d2-pad2_ net-_q11-pad3_ 5k +q2 net-_c2-pad2_ net-_d2-pad1_ net-_q2-pad3_ Q2N2222 +r4 net-_q2-pad3_ net-_q11-pad3_ 2k +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d5-pad2_ net-_c2-pad1_ 1N4148 +q4 net-_c2-pad1_ net-_c2-pad2_ net-_q11-pad3_ Q2N2222 +q7 net-_i1-pad1_ net-_d5-pad1_ net-_q7-pad3_ Q2N2222 +q8 net-_q11-pad3_ net-_c2-pad1_ net-_q7-pad3_ Q2N2907A +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +i6 net-_i1-pad1_ net-_i6-pad2_ 80u +i8 net-_i1-pad1_ net-_d11-pad1_ 400u +j6 net-_i6-pad2_ net-_j6-pad2_ net-_d8-pad1_ J2N3820 +j8 net-_i6-pad2_ net-_j8-pad2_ net-_c4-pad2_ J2N3820 +d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148 +r6 net-_d8-pad2_ net-_q11-pad3_ 5k +q10 net-_c4-pad2_ net-_d8-pad1_ net-_q10-pad3_ Q2N2222 +r8 net-_q10-pad3_ net-_q11-pad3_ 2k +d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148 +d12 net-_d11-pad2_ net-_c4-pad1_ 1N4148 +q12 net-_c4-pad1_ net-_c4-pad2_ net-_q11-pad3_ Q2N2222 +q15 net-_i1-pad1_ net-_d11-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q11-pad3_ net-_c4-pad1_ net-_q15-pad3_ Q2N2907A +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +* Control Statements + +.ends LF147_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml b/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml new file mode 100644 index 00000000..7232ccc1 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/LF147_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i1 name="Source type">80u</i1><i3 name="Source type">400u</i3><i5 name="Source type">80u</i5><i7 name="Source type">400u</i7><i2 name="Source type">80u</i2><i4 name="Source type">400u</i4><i6 name="Source type">80u</i6><i8 name="Source type">400u</i8></source><model /><devicemodel><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j1><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j3><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><j5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j5><j7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j7><d7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><d9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j2><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j4><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><d5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><j6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j6><j8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j8><d8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><d12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q16></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LF147_sub/NPN.lib b/library/SubcircuitLibrary/LF147_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LF147_sub/PJF.lib b/library/SubcircuitLibrary/LF147_sub/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/SubcircuitLibrary/LF147_sub/PNP.lib b/library/SubcircuitLibrary/LF147_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LF147_sub/analysis b/library/SubcircuitLibrary/LF147_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LF147_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib new file mode 100644 index 00000000..809d9541 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC-cache.lib @@ -0,0 +1,160 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir new file mode 100644 index 00000000..7de39320 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir @@ -0,0 +1,49 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM140L_IC\LM140L_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/01/24 22:06:45 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_J1-Pad1_ Net-_Q2-Pad3_ 418 +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +U1 Net-_J1-Pad2_ Net-_J1-Pad3_ zener +Q1 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad3_ Net-_Q1-Pad1_ Net-_Q2-Pad3_ eSim_PNP +U2 Net-_J1-Pad2_ Net-_Q1-Pad3_ zener +Q3 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q7 Net-_Q11-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q4-Pad3_ eSim_NPN +R2 Net-_Q4-Pad3_ Net-_Q8-Pad2_ 576 +R3 Net-_Q8-Pad2_ Net-_R3-Pad2_ 3.41k +R4 Net-_R3-Pad2_ Net-_Q10-Pad2_ 3.89k +Q5 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q5-Pad3_ Net-_J1-Pad2_ eSim_NPN +U3 Net-_R10-Pad1_ Net-_J1-Pad1_ zener +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 5k +U4 Net-_Q13-Pad2_ Net-_R10-Pad2_ zener +Q15 Net-_J1-Pad1_ Net-_Q11-Pad3_ Net-_Q12-Pad1_ eSim_NPN +Q9 Net-_Q11-Pad3_ Net-_Q8-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_Q8-Pad2_ Net-_Q4-Pad3_ eSim_PNP +R5 Net-_Q8-Pad1_ Net-_J1-Pad2_ 7.8k +Q16 Net-_J1-Pad1_ Net-_Q12-Pad1_ Net-_Q16-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q10-Pad1_ eSim_NPN +R6 Net-_Q12-Pad2_ Net-_R3-Pad2_ 13k +Q11 Net-_J1-Pad2_ Net-_C1-Pad1_ Net-_Q11-Pad3_ eSim_PNP +R8 Net-_Q11-Pad3_ Net-_C1-Pad1_ 5.76k +Q14 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R7 Net-_Q10-Pad3_ Net-_J1-Pad2_ 2.84k +R9 Net-_Q13-Pad3_ Net-_R13-Pad2_ 100 +R14 Net-_Q16-Pad3_ Net-_R13-Pad2_ 1.9 +R13 Net-_Q12-Pad1_ Net-_R13-Pad2_ 2.5k +R11 Net-_Q16-Pad3_ Net-_Q13-Pad2_ 100 +R15 Net-_R13-Pad2_ Net-_R12-Pad1_ 1.5k +R12 Net-_R12-Pad1_ Net-_C1-Pad2_ 15k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5u +R16 Net-_R12-Pad1_ Net-_J1-Pad2_ 2.23k +Q13 Net-_Q11-Pad3_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +U5 Net-_J1-Pad1_ Net-_R13-Pad2_ Net-_J1-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out new file mode 100644 index 00000000..68cd633e --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.cir.out @@ -0,0 +1,65 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm140l_ic\lm140l_ic.cir + +.include NJF.lib +.include NPN.lib +.include PNP.lib +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +* u2 net-_j1-pad2_ net-_q1-pad3_ zener +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q7 net-_q11-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q8-pad2_ 576 +r3 net-_q8-pad2_ net-_r3-pad2_ 3.41k +r4 net-_r3-pad2_ net-_q10-pad2_ 3.89k +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ net-_j1-pad2_ Q2N2222 +* u3 net-_r10-pad1_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u4 net-_q13-pad2_ net-_r10-pad2_ zener +q15 net-_j1-pad1_ net-_q11-pad3_ net-_q12-pad1_ Q2N2222 +q9 net-_q11-pad3_ net-_q8-pad1_ net-_j1-pad2_ Q2N2222 +q8 net-_q8-pad1_ net-_q8-pad2_ net-_q4-pad3_ Q2N2907A +r5 net-_q8-pad1_ net-_j1-pad2_ 7.8k +q16 net-_j1-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q10-pad1_ Q2N2222 +r6 net-_q12-pad2_ net-_r3-pad2_ 13k +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q11-pad3_ Q2N2907A +r8 net-_q11-pad3_ net-_c1-pad1_ 5.76k +q14 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_j1-pad2_ 2.84k +r9 net-_q13-pad3_ net-_r13-pad2_ 100 +r14 net-_q16-pad3_ net-_r13-pad2_ 1.9 +r13 net-_q12-pad1_ net-_r13-pad2_ 2.5k +r11 net-_q16-pad3_ net-_q13-pad2_ 100 +r15 net-_r13-pad2_ net-_r12-pad1_ 1.5k +r12 net-_r12-pad1_ net-_c1-pad2_ 15k +c1 net-_c1-pad1_ net-_c1-pad2_ 5u +r16 net-_r12-pad1_ net-_j1-pad2_ 2.23k +q13 net-_q11-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +* u5 net-_j1-pad1_ net-_r13-pad2_ net-_j1-pad2_ port +a1 net-_j1-pad2_ net-_j1-pad3_ u1 +a2 net-_j1-pad2_ net-_q1-pad3_ u2 +a3 net-_r10-pad1_ net-_j1-pad1_ u3 +a4 net-_q13-pad2_ net-_r10-pad2_ u4 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch new file mode 100644 index 00000000..fee2452b --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sch @@ -0,0 +1,732 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM140L_IC-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 666EB6C4 +P 2300 1550 +F 0 "R1" H 2350 1680 50 0000 C CNN +F 1 "418" H 2350 1500 50 0000 C CNN +F 2 "" H 2350 1530 30 0000 C CNN +F 3 "" V 2350 1600 30 0000 C CNN + 1 2300 1550 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J1 +U 1 1 666EB6C5 +P 1650 1800 +F 0 "J1" H 1550 1850 50 0000 R CNN +F 1 "jfet_n" H 1600 1950 50 0000 R CNN +F 2 "" H 1850 1900 29 0000 C CNN +F 3 "" H 1650 1800 60 0000 C CNN + 1 1650 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1750 1600 1750 1300 +Wire Wire Line + 1750 1300 7600 1300 +Wire Wire Line + 2350 1300 2350 1450 +$Comp +L zener U1 +U 1 1 666EB6C6 +P 1750 3600 +F 0 "U1" H 1700 3500 60 0000 C CNN +F 1 "zener" H 1750 3700 60 0000 C CNN +F 2 "" H 1800 3600 60 0000 C CNN +F 3 "" H 1800 3600 60 0000 C CNN + 1 1750 3600 + 0 1 -1 0 +$EndComp +Wire Wire Line + 1750 2000 1750 3300 +$Comp +L eSim_NPN Q1 +U 1 1 666EB6C7 +P 2000 2550 +F 0 "Q1" H 1900 2600 50 0000 R CNN +F 1 "eSim_NPN" H 1950 2700 50 0000 R CNN +F 2 "" H 2200 2650 29 0000 C CNN +F 3 "" H 2000 2550 60 0000 C CNN + 1 2000 2550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 666EB6C8 +P 2450 2000 +F 0 "Q2" H 2350 2050 50 0000 R CNN +F 1 "eSim_PNP" H 2400 2150 50 0000 R CNN +F 2 "" H 2650 2100 29 0000 C CNN +F 3 "" H 2450 2000 60 0000 C CNN + 1 2450 2000 + -1 0 0 1 +$EndComp +Wire Wire Line + 2350 1800 2350 1750 +$Comp +L zener U2 +U 1 1 666EB6C9 +P 2350 3600 +F 0 "U2" H 2300 3500 60 0000 C CNN +F 1 "zener" H 2350 3700 60 0000 C CNN +F 2 "" H 2400 3600 60 0000 C CNN +F 3 "" H 2400 3600 60 0000 C CNN + 1 2350 3600 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2350 2200 2350 3300 +$Comp +L eSim_PNP Q3 +U 1 1 666EB6CA +P 3050 2000 +F 0 "Q3" H 2950 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3000 2150 50 0000 R CNN +F 2 "" H 3250 2100 29 0000 C CNN +F 3 "" H 3050 2000 60 0000 C CNN + 1 3050 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 666EB6CB +P 3500 2000 +F 0 "Q7" H 3400 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3450 2150 50 0000 R CNN +F 2 "" H 3700 2100 29 0000 C CNN +F 3 "" H 3500 2000 60 0000 C CNN + 1 3500 2000 + 1 0 0 1 +$EndComp +Wire Wire Line + 2650 2000 3300 2000 +Wire Wire Line + 3150 1800 3600 1800 +Wire Wire Line + 3400 1300 3400 1800 +Connection ~ 2350 1300 +Connection ~ 3400 1800 +Connection ~ 2850 2000 +$Comp +L eSim_NPN Q4 +U 1 1 666EB6CC +P 3050 2700 +F 0 "Q4" H 2950 2750 50 0000 R CNN +F 1 "eSim_NPN" H 3000 2850 50 0000 R CNN +F 2 "" H 3250 2800 29 0000 C CNN +F 3 "" H 3050 2700 60 0000 C CNN + 1 3050 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 2200 3150 2500 +Wire Wire Line + 2750 2000 2750 2350 +Wire Wire Line + 2750 2350 3150 2350 +Connection ~ 3150 2350 +Connection ~ 2750 2000 +Wire Wire Line + 2200 2700 2850 2700 +Wire Wire Line + 2200 2700 2200 2750 +Wire Wire Line + 2200 2750 2100 2750 +Connection ~ 2350 2700 +Wire Wire Line + 2100 2350 2600 2350 +Wire Wire Line + 2600 2350 2600 2450 +Wire Wire Line + 2600 2450 3150 2450 +Connection ~ 3150 2450 +Wire Wire Line + 1800 2550 1750 2550 +Connection ~ 1750 2550 +$Comp +L resistor R2 +U 1 1 666EB6CD +P 3100 3150 +F 0 "R2" H 3150 3280 50 0000 C CNN +F 1 "576" H 3150 3100 50 0000 C CNN +F 2 "" H 3150 3130 30 0000 C CNN +F 3 "" V 3150 3200 30 0000 C CNN + 1 3100 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 666EB6CE +P 3100 3600 +F 0 "R3" H 3150 3730 50 0000 C CNN +F 1 "3.41k" H 3150 3550 50 0000 C CNN +F 2 "" H 3150 3580 30 0000 C CNN +F 3 "" V 3150 3650 30 0000 C CNN + 1 3100 3600 + 0 1 1 0 +$EndComp +Wire Wire Line + 3150 2900 3150 3050 +Wire Wire Line + 3150 3350 3150 3500 +$Comp +L resistor R4 +U 1 1 666EB6CF +P 3100 4300 +F 0 "R4" H 3150 4430 50 0000 C CNN +F 1 "3.89k" H 3150 4250 50 0000 C CNN +F 2 "" H 3150 4280 30 0000 C CNN +F 3 "" V 3150 4350 30 0000 C CNN + 1 3100 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 3150 3800 3150 4200 +$Comp +L eSim_NPN Q5 +U 1 1 666EB6D0 +P 3050 5000 +F 0 "Q5" H 2950 5050 50 0000 R CNN +F 1 "eSim_NPN" H 3000 5150 50 0000 R CNN +F 2 "" H 3250 5100 29 0000 C CNN +F 3 "" H 3050 5000 60 0000 C CNN + 1 3050 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 666EB6D1 +P 3050 5600 +F 0 "Q6" H 2950 5650 50 0000 R CNN +F 1 "eSim_NPN" H 3000 5750 50 0000 R CNN +F 2 "" H 3250 5700 29 0000 C CNN +F 3 "" H 3050 5600 60 0000 C CNN + 1 3050 5600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 4500 3150 4800 +Wire Wire Line + 3150 5200 3150 5400 +Wire Wire Line + 2750 5000 4500 5000 +Wire Wire Line + 2750 5000 2750 4700 +Wire Wire Line + 2750 4700 3150 4700 +Connection ~ 3150 4700 +Wire Wire Line + 2850 5600 2850 5350 +Wire Wire Line + 2850 5350 3150 5350 +Connection ~ 3150 5350 +Wire Wire Line + 1750 3800 1750 6000 +Wire Wire Line + 1250 6000 7250 6000 +Wire Wire Line + 3150 6000 3150 5800 +Wire Wire Line + 2350 3800 2350 6000 +Connection ~ 2350 6000 +Wire Wire Line + 1450 1800 1250 1800 +Wire Wire Line + 1250 1800 1250 6000 +Connection ~ 1750 6000 +$Comp +L zener U3 +U 1 1 666EB6D2 +P 5650 1650 +F 0 "U3" H 5600 1550 60 0000 C CNN +F 1 "zener" H 5650 1750 60 0000 C CNN +F 2 "" H 5700 1650 60 0000 C CNN +F 3 "" H 5700 1650 60 0000 C CNN + 1 5650 1650 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5650 1300 5650 1350 +Connection ~ 3400 1300 +$Comp +L resistor R10 +U 1 1 666EB6D3 +P 5600 2000 +F 0 "R10" H 5650 2130 50 0000 C CNN +F 1 "5k" H 5650 1950 50 0000 C CNN +F 2 "" H 5650 1980 30 0000 C CNN +F 3 "" V 5650 2050 30 0000 C CNN + 1 5600 2000 + 0 1 1 0 +$EndComp +$Comp +L zener U4 +U 1 1 666EB6D4 +P 5650 2700 +F 0 "U4" H 5600 2600 60 0000 C CNN +F 1 "zener" H 5650 2800 60 0000 C CNN +F 2 "" H 5700 2700 60 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 0 1 -1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 666EB6D5 +P 6250 2350 +F 0 "Q15" H 6150 2400 50 0000 R CNN +F 1 "eSim_NPN" H 6200 2500 50 0000 R CNN +F 2 "" H 6450 2450 29 0000 C CNN +F 3 "" H 6250 2350 60 0000 C CNN + 1 6250 2350 + 1 0 0 -1 +$EndComp +Connection ~ 5650 1300 +Wire Wire Line + 5650 1900 5650 1850 +Wire Wire Line + 6350 1300 6350 2150 +Wire Wire Line + 3600 2350 6050 2350 +Wire Wire Line + 3600 2350 3600 2200 +$Comp +L eSim_NPN Q9 +U 1 1 666EB6D6 +P 4150 4650 +F 0 "Q9" H 4050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 4100 4800 50 0000 R CNN +F 2 "" H 4350 4750 29 0000 C CNN +F 3 "" H 4150 4650 60 0000 C CNN + 1 4150 4650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 666EB6D7 +P 3650 3400 +F 0 "Q8" H 3550 3450 50 0000 R CNN +F 1 "eSim_PNP" H 3600 3550 50 0000 R CNN +F 2 "" H 3850 3500 29 0000 C CNN +F 3 "" H 3650 3400 60 0000 C CNN + 1 3650 3400 + 1 0 0 1 +$EndComp +Wire Wire Line + 3750 3200 3750 3000 +Wire Wire Line + 3750 3000 3150 3000 +Connection ~ 3150 3000 +Wire Wire Line + 3450 3400 3150 3400 +Connection ~ 3150 3400 +$Comp +L resistor R5 +U 1 1 666EB6D8 +P 3700 5000 +F 0 "R5" H 3750 5130 50 0000 C CNN +F 1 "7.8k" H 3750 4950 50 0000 C CNN +F 2 "" H 3750 4980 30 0000 C CNN +F 3 "" V 3750 5050 30 0000 C CNN + 1 3700 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3750 3600 3750 4900 +Wire Wire Line + 3750 6000 3750 5200 +Connection ~ 3150 6000 +Wire Wire Line + 3950 4650 3750 4650 +Connection ~ 3750 4650 +Wire Wire Line + 4250 4450 4250 2350 +Connection ~ 4250 2350 +Wire Wire Line + 4250 6000 4250 4850 +Connection ~ 3750 6000 +Wire Wire Line + 5650 2400 5650 2200 +$Comp +L eSim_NPN Q16 +U 1 1 666EB6D9 +P 7150 2700 +F 0 "Q16" H 7050 2750 50 0000 R CNN +F 1 "eSim_NPN" H 7100 2850 50 0000 R CNN +F 2 "" H 7350 2800 29 0000 C CNN +F 3 "" H 7150 2700 60 0000 C CNN + 1 7150 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 1300 7250 2500 +Connection ~ 6350 1300 +Wire Wire Line + 6350 2550 6350 2700 +Wire Wire Line + 6350 2700 6950 2700 +$Comp +L eSim_NPN Q12 +U 1 1 666EB6DA +P 4750 4000 +F 0 "Q12" H 4650 4050 50 0000 R CNN +F 1 "eSim_NPN" H 4700 4150 50 0000 R CNN +F 2 "" H 4950 4100 29 0000 C CNN +F 3 "" H 4750 4000 60 0000 C CNN + 1 4750 4000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 666EB6DB +P 4050 3950 +F 0 "R6" H 4100 4080 50 0000 C CNN +F 1 "13k" H 4100 3900 50 0000 C CNN +F 2 "" H 4100 3930 30 0000 C CNN +F 3 "" V 4100 4000 30 0000 C CNN + 1 4050 3950 + -1 0 0 1 +$EndComp +Wire Wire Line + 4550 4000 4150 4000 +Wire Wire Line + 3850 4000 3150 4000 +Connection ~ 3150 4000 +Wire Wire Line + 4850 3800 4850 3100 +Wire Wire Line + 4850 3100 6450 3100 +Wire Wire Line + 6450 3100 6450 2700 +Connection ~ 6450 2700 +$Comp +L eSim_PNP Q11 +U 1 1 666EB6DC +P 4750 2800 +F 0 "Q11" H 4650 2850 50 0000 R CNN +F 1 "eSim_PNP" H 4700 2950 50 0000 R CNN +F 2 "" H 4950 2900 29 0000 C CNN +F 3 "" H 4750 2800 60 0000 C CNN + 1 4750 2800 + -1 0 0 1 +$EndComp +Connection ~ 4250 6000 +$Comp +L resistor R8 +U 1 1 666EB6DD +P 5000 2500 +F 0 "R8" H 5050 2630 50 0000 C CNN +F 1 "5.76k" H 5050 2450 50 0000 C CNN +F 2 "" H 5050 2480 30 0000 C CNN +F 3 "" V 5050 2550 30 0000 C CNN + 1 5000 2500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4950 6000 4950 3000 +$Comp +L eSim_NPN Q14 +U 1 1 666EB6DE +P 5450 4000 +F 0 "Q14" H 5350 4050 50 0000 R CNN +F 1 "eSim_NPN" H 5400 4150 50 0000 R CNN +F 2 "" H 5650 4100 29 0000 C CNN +F 3 "" H 5450 4000 60 0000 C CNN + 1 5450 4000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4850 4200 5350 4200 +$Comp +L eSim_NPN Q10 +U 1 1 666EB6DF +P 4700 5000 +F 0 "Q10" H 4600 5050 50 0000 R CNN +F 1 "eSim_NPN" H 4650 5150 50 0000 R CNN +F 2 "" H 4900 5100 29 0000 C CNN +F 3 "" H 4700 5000 60 0000 C CNN + 1 4700 5000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4800 4800 4900 4800 +Wire Wire Line + 4900 4800 4900 4200 +Connection ~ 4900 4200 +Connection ~ 2850 5000 +$Comp +L resistor R7 +U 1 1 666EB6E0 +P 4750 5500 +F 0 "R7" H 4800 5630 50 0000 C CNN +F 1 "2.84k" H 4800 5450 50 0000 C CNN +F 2 "" H 4800 5480 30 0000 C CNN +F 3 "" V 4800 5550 30 0000 C CNN + 1 4750 5500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4800 5400 4800 5200 +Wire Wire Line + 4800 5700 4800 6000 +Connection ~ 4800 6000 +$Comp +L resistor R9 +U 1 1 666EB6E1 +P 5200 3350 +F 0 "R9" H 5250 3480 50 0000 C CNN +F 1 "100" H 5250 3300 50 0000 C CNN +F 2 "" H 5250 3330 30 0000 C CNN +F 3 "" V 5250 3400 30 0000 C CNN + 1 5200 3350 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 666EB6E2 +P 7200 3200 +F 0 "R14" H 7250 3330 50 0000 C CNN +F 1 "1.9" H 7250 3150 50 0000 C CNN +F 2 "" H 7250 3180 30 0000 C CNN +F 3 "" V 7250 3250 30 0000 C CNN + 1 7200 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 666EB6E3 +P 6700 3200 +F 0 "R13" H 6750 3330 50 0000 C CNN +F 1 "2.5k" H 6750 3150 50 0000 C CNN +F 2 "" H 6750 3180 30 0000 C CNN +F 3 "" V 6750 3250 30 0000 C CNN + 1 6700 3200 + 0 1 1 0 +$EndComp +Wire Wire Line + 6750 3100 6750 2700 +Connection ~ 6750 2700 +Wire Wire Line + 7250 2900 7250 3100 +$Comp +L resistor R11 +U 1 1 666EB6E4 +P 6150 2950 +F 0 "R11" H 6200 3080 50 0000 C CNN +F 1 "100" H 6200 2900 50 0000 C CNN +F 2 "" H 6200 2930 30 0000 C CNN +F 3 "" V 6200 3000 30 0000 C CNN + 1 6150 2950 + -1 0 0 1 +$EndComp +Wire Wire Line + 5550 3000 5950 3000 +Wire Wire Line + 6250 3000 7250 3000 +Connection ~ 7250 3000 +Wire Wire Line + 5250 3650 7950 3650 +Wire Wire Line + 7250 3400 7250 3900 +Wire Wire Line + 6750 3400 6750 3650 +Connection ~ 6750 3650 +$Comp +L resistor R15 +U 1 1 666EB6E5 +P 7200 4000 +F 0 "R15" H 7250 4130 50 0000 C CNN +F 1 "1.5k" H 7250 3950 50 0000 C CNN +F 2 "" H 7250 3980 30 0000 C CNN +F 3 "" V 7250 4050 30 0000 C CNN + 1 7200 4000 + 0 1 1 0 +$EndComp +Connection ~ 7250 3650 +Wire Wire Line + 6900 4000 6900 4450 +Wire Wire Line + 6900 4450 7250 4450 +Wire Wire Line + 7250 4200 7250 5100 +$Comp +L resistor R12 +U 1 1 666EB6E6 +P 6450 3950 +F 0 "R12" H 6500 4080 50 0000 C CNN +F 1 "15k" H 6500 3900 50 0000 C CNN +F 2 "" H 6500 3930 30 0000 C CNN +F 3 "" V 6500 4000 30 0000 C CNN + 1 6450 3950 + -1 0 0 1 +$EndComp +Wire Wire Line + 6550 4000 6900 4000 +Wire Wire Line + 5650 4000 6250 4000 +$Comp +L capacitor_polarised C1 +U 1 1 666EB6E7 +P 5850 3750 +F 0 "C1" H 5875 3850 50 0000 L CNN +F 1 "5u" H 5875 3650 50 0000 L CNN +F 2 "" H 5850 3750 50 0001 C CNN +F 3 "" H 5850 3750 50 0001 C CNN + 1 5850 3750 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6000 3750 6100 3750 +Wire Wire Line + 6100 3750 6100 4000 +Connection ~ 6100 4000 +Wire Wire Line + 5700 3750 5350 3750 +Connection ~ 5350 3750 +$Comp +L resistor R16 +U 1 1 666EB6E8 +P 7200 5200 +F 0 "R16" H 7250 5330 50 0000 C CNN +F 1 "2.23k" H 7250 5150 50 0000 C CNN +F 2 "" H 7250 5180 30 0000 C CNN +F 3 "" V 7250 5250 30 0000 C CNN + 1 7200 5200 + 0 1 1 0 +$EndComp +Connection ~ 7250 4450 +Wire Wire Line + 7250 5400 7250 6250 +Connection ~ 4950 6000 +Wire Wire Line + 5350 3700 5350 3800 +Wire Wire Line + 5050 3700 5350 3700 +Wire Wire Line + 5050 2700 5050 3700 +Wire Wire Line + 5050 2400 5050 2350 +Connection ~ 5050 2350 +Wire Wire Line + 4950 2800 5050 2800 +Connection ~ 5050 2800 +Wire Wire Line + 4650 2600 4650 2350 +Connection ~ 4650 2350 +Wire Wire Line + 4950 3000 4650 3000 +$Comp +L eSim_NPN Q13 +U 1 1 666EB6E9 +P 5350 3000 +F 0 "Q13" H 5250 3050 50 0000 R CNN +F 1 "eSim_NPN" H 5300 3150 50 0000 R CNN +F 2 "" H 5550 3100 29 0000 C CNN +F 3 "" H 5350 3000 60 0000 C CNN + 1 5350 3000 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5250 2800 5250 2350 +Connection ~ 5250 2350 +Wire Wire Line + 5650 2900 5650 3000 +Connection ~ 5650 3000 +Wire Wire Line + 5250 3250 5250 3200 +Wire Wire Line + 5250 3550 5250 3650 +Connection ~ 7250 1300 +Connection ~ 7250 6000 +Wire Wire Line + 7950 3650 7950 3550 +$Comp +L PORT U5 +U 1 1 666EBC17 +P 7850 1300 +F 0 "U5" H 7900 1400 30 0000 C CNN +F 1 "PORT" H 7850 1300 30 0000 C CNN +F 2 "" H 7850 1300 60 0000 C CNN +F 3 "" H 7850 1300 60 0000 C CNN + 1 7850 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 2 1 666EC091 +P 8200 3550 +F 0 "U5" H 8250 3650 30 0000 C CNN +F 1 "PORT" H 8200 3550 30 0000 C CNN +F 2 "" H 8200 3550 60 0000 C CNN +F 3 "" H 8200 3550 60 0000 C CNN + 2 8200 3550 + -1 0 0 1 +$EndComp +$Comp +L PORT U5 +U 3 1 666EC2BD +P 7250 6500 +F 0 "U5" H 7300 6600 30 0000 C CNN +F 1 "PORT" H 7250 6500 30 0000 C CNN +F 2 "" H 7250 6500 60 0000 C CNN +F 3 "" H 7250 6500 60 0000 C CNN + 3 7250 6500 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub new file mode 100644 index 00000000..c8bd59c9 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC.sub @@ -0,0 +1,59 @@ +* Subcircuit LM140L_IC +.subckt LM140L_IC net-_j1-pad1_ net-_r13-pad2_ net-_j1-pad2_ +* d:\fossee\esim\library\subcircuitlibrary\lm140l_ic\lm140l_ic.cir +.include NJF.lib +.include NPN.lib +.include PNP.lib +r1 net-_j1-pad1_ net-_q2-pad3_ 418 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +* u1 net-_j1-pad2_ net-_j1-pad3_ zener +q1 net-_q1-pad1_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q2 net-_q1-pad3_ net-_q1-pad1_ net-_q2-pad3_ Q2N2907A +* u2 net-_j1-pad2_ net-_q1-pad3_ zener +q3 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q7 net-_q11-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q1-pad1_ net-_q1-pad3_ net-_q4-pad3_ Q2N2222 +r2 net-_q4-pad3_ net-_q8-pad2_ 576 +r3 net-_q8-pad2_ net-_r3-pad2_ 3.41k +r4 net-_r3-pad2_ net-_q10-pad2_ 3.89k +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q5-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q5-pad3_ net-_j1-pad2_ Q2N2222 +* u3 net-_r10-pad1_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 5k +* u4 net-_q13-pad2_ net-_r10-pad2_ zener +q15 net-_j1-pad1_ net-_q11-pad3_ net-_q12-pad1_ Q2N2222 +q9 net-_q11-pad3_ net-_q8-pad1_ net-_j1-pad2_ Q2N2222 +q8 net-_q8-pad1_ net-_q8-pad2_ net-_q4-pad3_ Q2N2907A +r5 net-_q8-pad1_ net-_j1-pad2_ 7.8k +q16 net-_j1-pad1_ net-_q12-pad1_ net-_q16-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q10-pad1_ Q2N2222 +r6 net-_q12-pad2_ net-_r3-pad2_ 13k +q11 net-_j1-pad2_ net-_c1-pad1_ net-_q11-pad3_ Q2N2907A +r8 net-_q11-pad3_ net-_c1-pad1_ 5.76k +q14 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad1_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_j1-pad2_ 2.84k +r9 net-_q13-pad3_ net-_r13-pad2_ 100 +r14 net-_q16-pad3_ net-_r13-pad2_ 1.9 +r13 net-_q12-pad1_ net-_r13-pad2_ 2.5k +r11 net-_q16-pad3_ net-_q13-pad2_ 100 +r15 net-_r13-pad2_ net-_r12-pad1_ 1.5k +r12 net-_r12-pad1_ net-_c1-pad2_ 15k +c1 net-_c1-pad1_ net-_c1-pad2_ 5u +r16 net-_r12-pad1_ net-_j1-pad2_ 2.23k +q13 net-_q11-pad3_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +a1 net-_j1-pad2_ net-_j1-pad3_ u1 +a2 net-_j1-pad2_ net-_q1-pad3_ u2 +a3 net-_r10-pad1_ net-_j1-pad1_ u3 +a4 net-_q13-pad2_ net-_r10-pad2_ u4 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM140L_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml new file mode 100644 index 00000000..c58cd7ba --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/LM140L_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u4></model><devicemodel><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM140L_sub/NJF.lib b/library/SubcircuitLibrary/LM140L_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM140L_sub/NPN.lib b/library/SubcircuitLibrary/LM140L_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM140L_sub/PNP.lib b/library/SubcircuitLibrary/LM140L_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM140L_sub/analysis b/library/SubcircuitLibrary/LM140L_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM140L_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/D.lib b/library/SubcircuitLibrary/LM143_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib b/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib new file mode 100644 index 00000000..5e755436 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC-cache.lib @@ -0,0 +1,183 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir new file mode 100644 index 00000000..a903cdea --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir @@ -0,0 +1,42 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM143_IC\LM143_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:26:26 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I2 Net-_I2-Pad1_ Net-_I2-Pad2_ 80u +I3 Net-_I2-Pad1_ Net-_I3-Pad2_ 80u +I4 Net-_I2-Pad1_ Net-_I4-Pad2_ 80u +Q1 Net-_I2-Pad2_ Net-_Q1-Pad2_ Net-_I1-Pad1_ eSim_NPN +Q2 Net-_I1-Pad2_ Net-_I1-Pad1_ Net-_I2-Pad2_ eSim_PNP +Q6 Net-_I1-Pad2_ Net-_I5-Pad1_ Net-_I4-Pad2_ eSim_PNP +Q8 Net-_I4-Pad2_ Net-_Q8-Pad2_ Net-_I5-Pad1_ eSim_NPN +R2 Net-_Q3-Pad3_ Net-_I3-Pad2_ 5.6k +R3 Net-_I3-Pad2_ Net-_Q7-Pad3_ 5.6k +Q3 Net-_Q3-Pad1_ Net-_I1-Pad1_ Net-_Q3-Pad3_ eSim_PNP +Q7 Net-_C1-Pad2_ Net-_I5-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_I1-Pad2_ eSim_NPN +Q5 Net-_C1-Pad2_ Net-_Q3-Pad1_ Net-_I1-Pad2_ eSim_NPN +I1 Net-_I1-Pad1_ Net-_I1-Pad2_ 20u +I5 Net-_I5-Pad1_ Net-_I1-Pad2_ 20u +I6 Net-_I2-Pad1_ Net-_D1-Pad1_ 400u +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_C1-Pad1_ eSim_Diode +Q11 Net-_C1-Pad1_ Net-_Q11-Pad2_ Net-_Q10-Pad1_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 27p +Q9 Net-_I2-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_I1-Pad2_ eSim_NPN +R5 Net-_Q10-Pad2_ Net-_I1-Pad2_ 39k +v1 Net-_Q11-Pad2_ Net-_I1-Pad2_ 2 +Q15 Net-_I2-Pad1_ Net-_I7-Pad2_ Net-_Q13-Pad1_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_D1-Pad1_ Net-_Q13-Pad3_ eSim_NPN +Q14 Net-_I1-Pad2_ Net-_Q12-Pad3_ Net-_Q13-Pad3_ eSim_PNP +Q12 Net-_I1-Pad2_ Net-_C1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +I7 Net-_I2-Pad1_ Net-_I7-Pad2_ 400u +v2 Net-_I7-Pad2_ Net-_Q13-Pad3_ 3.5 +U1 Net-_Q1-Pad2_ Net-_Q8-Pad2_ Net-_I1-Pad2_ Net-_Q13-Pad3_ Net-_I2-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out new file mode 100644 index 00000000..4cac6cfc --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.cir.out @@ -0,0 +1,46 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm143_ic\lm143_ic.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +i2 net-_i2-pad1_ net-_i2-pad2_ 80u +i3 net-_i2-pad1_ net-_i3-pad2_ 80u +i4 net-_i2-pad1_ net-_i4-pad2_ 80u +q1 net-_i2-pad2_ net-_q1-pad2_ net-_i1-pad1_ Q2N2222 +q2 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2907A +q6 net-_i1-pad2_ net-_i5-pad1_ net-_i4-pad2_ Q2N2907A +q8 net-_i4-pad2_ net-_q8-pad2_ net-_i5-pad1_ Q2N2222 +r2 net-_q3-pad3_ net-_i3-pad2_ 5.6k +r3 net-_i3-pad2_ net-_q7-pad3_ 5.6k +q3 net-_q3-pad1_ net-_i1-pad1_ net-_q3-pad3_ Q2N2907A +q7 net-_c1-pad2_ net-_i5-pad1_ net-_q7-pad3_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +q5 net-_c1-pad2_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +i1 net-_i1-pad1_ net-_i1-pad2_ 20u +i5 net-_i5-pad1_ net-_i1-pad2_ 20u +i6 net-_i2-pad1_ net-_d1-pad1_ 400u +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_c1-pad1_ 1N4148 +q11 net-_c1-pad1_ net-_q11-pad2_ net-_q10-pad1_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 27p +q9 net-_i2-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_i1-pad2_ Q2N2222 +r5 net-_q10-pad2_ net-_i1-pad2_ 39k +v1 net-_q11-pad2_ net-_i1-pad2_ 2 +q15 net-_i2-pad1_ net-_i7-pad2_ net-_q13-pad1_ Q2N2222 +q13 net-_q13-pad1_ net-_d1-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_i1-pad2_ net-_q12-pad3_ net-_q13-pad3_ Q2N2907A +q12 net-_i1-pad2_ net-_c1-pad1_ net-_q12-pad3_ Q2N2907A +i7 net-_i2-pad1_ net-_i7-pad2_ 400u +v2 net-_i7-pad2_ net-_q13-pad3_ 3.5 +* u1 net-_q1-pad2_ net-_q8-pad2_ net-_i1-pad2_ net-_q13-pad3_ net-_i2-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro b/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch new file mode 100644 index 00000000..a86aa174 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sch @@ -0,0 +1,664 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM143_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I2 +U 1 1 668A62E5 +P 8200 5700 +F 0 "I2" H 8000 5800 60 0000 C CNN +F 1 "80u" H 8000 5650 60 0000 C CNN +F 2 "R1" H 7900 5700 60 0000 C CNN +F 3 "" H 8200 5700 60 0000 C CNN + 1 8200 5700 + -1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 668A62E6 +P 9000 5750 +F 0 "I3" H 8800 5850 60 0000 C CNN +F 1 "80u" H 8800 5700 60 0000 C CNN +F 2 "R1" H 8700 5750 60 0000 C CNN +F 3 "" H 9000 5750 60 0000 C CNN + 1 9000 5750 + -1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 668A62E7 +P 9800 5700 +F 0 "I4" H 9600 5800 60 0000 C CNN +F 1 "80u" H 9600 5650 60 0000 C CNN +F 2 "R1" H 9500 5700 60 0000 C CNN +F 3 "" H 9800 5700 60 0000 C CNN + 1 9800 5700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 668A62E8 +P 7400 6600 +F 0 "Q1" H 7300 6650 50 0000 R CNN +F 1 "eSim_NPN" H 7350 6750 50 0000 R CNN +F 2 "" H 7600 6700 29 0000 C CNN +F 3 "" H 7400 6600 60 0000 C CNN + 1 7400 6600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 668A62E9 +P 8100 6850 +F 0 "Q2" H 8000 6900 50 0000 R CNN +F 1 "eSim_PNP" H 8050 7000 50 0000 R CNN +F 2 "" H 8300 6950 29 0000 C CNN +F 3 "" H 8100 6850 60 0000 C CNN + 1 8100 6850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 668A62EA +P 9900 6850 +F 0 "Q6" H 9800 6900 50 0000 R CNN +F 1 "eSim_PNP" H 9850 7000 50 0000 R CNN +F 2 "" H 10100 6950 29 0000 C CNN +F 3 "" H 9900 6850 60 0000 C CNN + 1 9900 6850 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 668A62EB +P 10900 6550 +F 0 "Q8" H 10800 6600 50 0000 R CNN +F 1 "eSim_NPN" H 10850 6700 50 0000 R CNN +F 2 "" H 11100 6650 29 0000 C CNN +F 3 "" H 10900 6550 60 0000 C CNN + 1 10900 6550 + -1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 668A62EC +P 8600 7500 +F 0 "R2" H 8650 7630 50 0000 C CNN +F 1 "5.6k" H 8650 7450 50 0000 C CNN +F 2 "" H 8650 7480 30 0000 C CNN +F 3 "" V 8650 7550 30 0000 C CNN + 1 8600 7500 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 668A62ED +P 9250 7500 +F 0 "R3" H 9300 7630 50 0000 C CNN +F 1 "5.6k" H 9300 7450 50 0000 C CNN +F 2 "" H 9300 7480 30 0000 C CNN +F 3 "" V 9300 7550 30 0000 C CNN + 1 9250 7500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 668A62EE +P 8200 7650 +F 0 "Q3" H 8100 7700 50 0000 R CNN +F 1 "eSim_PNP" H 8150 7800 50 0000 R CNN +F 2 "" H 8400 7750 29 0000 C CNN +F 3 "" H 8200 7650 60 0000 C CNN + 1 8200 7650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 668A62EF +P 9900 7650 +F 0 "Q7" H 9800 7700 50 0000 R CNN +F 1 "eSim_PNP" H 9850 7800 50 0000 R CNN +F 2 "" H 10100 7750 29 0000 C CNN +F 3 "" H 9900 7650 60 0000 C CNN + 1 9900 7650 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 668A62F0 +P 8400 8750 +F 0 "Q4" H 8300 8800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 8900 50 0000 R CNN +F 2 "" H 8600 8850 29 0000 C CNN +F 3 "" H 8400 8750 60 0000 C CNN + 1 8400 8750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 668A62F1 +P 9700 8750 +F 0 "Q5" H 9600 8800 50 0000 R CNN +F 1 "eSim_NPN" H 9650 8900 50 0000 R CNN +F 2 "" H 9900 8850 29 0000 C CNN +F 3 "" H 9700 8750 60 0000 C CNN + 1 9700 8750 + 1 0 0 -1 +$EndComp +$Comp +L dc I1 +U 1 1 668A62F2 +P 7650 8350 +F 0 "I1" H 7450 8450 60 0000 C CNN +F 1 "20u" H 7450 8300 60 0000 C CNN +F 2 "R1" H 7350 8350 60 0000 C CNN +F 3 "" H 7650 8350 60 0000 C CNN + 1 7650 8350 + -1 0 0 -1 +$EndComp +$Comp +L dc I5 +U 1 1 668A62F3 +P 10400 8500 +F 0 "I5" H 10200 8600 60 0000 C CNN +F 1 "20u" H 10200 8450 60 0000 C CNN +F 2 "R1" H 10100 8500 60 0000 C CNN +F 3 "" H 10400 8500 60 0000 C CNN + 1 10400 8500 + -1 0 0 -1 +$EndComp +$Comp +L dc I6 +U 1 1 668A62F4 +P 12600 5800 +F 0 "I6" H 12400 5900 60 0000 C CNN +F 1 "400u" H 12400 5750 60 0000 C CNN +F 2 "R1" H 12300 5800 60 0000 C CNN +F 3 "" H 12600 5800 60 0000 C CNN + 1 12600 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 668A62F5 +P 12600 6800 +F 0 "D1" H 12600 6900 50 0000 C CNN +F 1 "eSim_Diode" H 12600 6700 50 0000 C CNN +F 2 "" H 12600 6800 60 0000 C CNN +F 3 "" H 12600 6800 60 0000 C CNN + 1 12600 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 668A62F6 +P 12600 7300 +F 0 "D2" H 12600 7400 50 0000 C CNN +F 1 "eSim_Diode" H 12600 7200 50 0000 C CNN +F 2 "" H 12600 7300 60 0000 C CNN +F 3 "" H 12600 7300 60 0000 C CNN + 1 12600 7300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 668A62F7 +P 12600 7800 +F 0 "D3" H 12600 7900 50 0000 C CNN +F 1 "eSim_Diode" H 12600 7700 50 0000 C CNN +F 2 "" H 12600 7800 60 0000 C CNN +F 3 "" H 12600 7800 60 0000 C CNN + 1 12600 7800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 668A62F8 +P 12700 8550 +F 0 "Q11" H 12600 8600 50 0000 R CNN +F 1 "eSim_NPN" H 12650 8700 50 0000 R CNN +F 2 "" H 12900 8650 29 0000 C CNN +F 3 "" H 12700 8550 60 0000 C CNN + 1 12700 8550 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 668A62F9 +P 12050 8250 +F 0 "C1" H 12075 8350 50 0000 L CNN +F 1 "27p" H 12075 8150 50 0000 L CNN +F 2 "" H 12088 8100 30 0000 C CNN +F 3 "" H 12050 8250 60 0000 C CNN + 1 12050 8250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 668A62FA +P 11600 9000 +F 0 "Q9" H 11500 9050 50 0000 R CNN +F 1 "eSim_NPN" H 11550 9150 50 0000 R CNN +F 2 "" H 11800 9100 29 0000 C CNN +F 3 "" H 11600 9000 60 0000 C CNN + 1 11600 9000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 668A62FB +P 12500 9000 +F 0 "Q10" H 12400 9050 50 0000 R CNN +F 1 "eSim_NPN" H 12450 9150 50 0000 R CNN +F 2 "" H 12700 9100 29 0000 C CNN +F 3 "" H 12500 9000 60 0000 C CNN + 1 12500 9000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 668A62FC +P 11950 9500 +F 0 "R5" H 12000 9630 50 0000 C CNN +F 1 "39k" H 12000 9450 50 0000 C CNN +F 2 "" H 12000 9480 30 0000 C CNN +F 3 "" V 12000 9550 30 0000 C CNN + 1 11950 9500 + 0 1 1 0 +$EndComp +$Comp +L DC v1 +U 1 1 668A62FD +P 13150 9150 +F 0 "v1" H 12950 9250 60 0000 C CNN +F 1 "2" H 12950 9100 60 0000 C CNN +F 2 "R1" H 12850 9150 60 0000 C CNN +F 3 "" H 13150 9150 60 0000 C CNN + 1 13150 9150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 668A62FE +P 14100 5550 +F 0 "Q15" H 14000 5600 50 0000 R CNN +F 1 "eSim_NPN" H 14050 5700 50 0000 R CNN +F 2 "" H 14300 5650 29 0000 C CNN +F 3 "" H 14100 5550 60 0000 C CNN + 1 14100 5550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 668A62FF +P 13900 6200 +F 0 "Q13" H 13800 6250 50 0000 R CNN +F 1 "eSim_NPN" H 13850 6350 50 0000 R CNN +F 2 "" H 14100 6300 29 0000 C CNN +F 3 "" H 13900 6200 60 0000 C CNN + 1 13900 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 668A6300 +P 13900 6700 +F 0 "Q14" H 13800 6750 50 0000 R CNN +F 1 "eSim_PNP" H 13850 6850 50 0000 R CNN +F 2 "" H 14100 6800 29 0000 C CNN +F 3 "" H 13900 6700 60 0000 C CNN + 1 13900 6700 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 668A6301 +P 13450 6950 +F 0 "Q12" H 13350 7000 50 0000 R CNN +F 1 "eSim_PNP" H 13400 7100 50 0000 R CNN +F 2 "" H 13650 7050 29 0000 C CNN +F 3 "" H 13450 6950 60 0000 C CNN + 1 13450 6950 + 1 0 0 1 +$EndComp +$Comp +L dc I7 +U 1 1 668A6302 +P 14750 5700 +F 0 "I7" H 14550 5800 60 0000 C CNN +F 1 "400u" H 14550 5650 60 0000 C CNN +F 2 "R1" H 14450 5700 60 0000 C CNN +F 3 "" H 14750 5700 60 0000 C CNN + 1 14750 5700 + -1 0 0 -1 +$EndComp +$Comp +L DC v2 +U 1 1 668A6303 +P 14750 6950 +F 0 "v2" H 14550 7050 60 0000 C CNN +F 1 "3.5" H 14550 6900 60 0000 C CNN +F 2 "R1" H 14450 6950 60 0000 C CNN +F 3 "" H 14750 6950 60 0000 C CNN + 1 14750 6950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8200 6150 8200 6650 +Wire Wire Line + 7500 6800 7500 6850 +Wire Wire Line + 7500 6850 7900 6850 +Wire Wire Line + 7500 6400 7500 6350 +Wire Wire Line + 7500 6350 8200 6350 +Connection ~ 8200 6350 +Wire Wire Line + 9800 6150 9800 6650 +Connection ~ 9800 6250 +Wire Wire Line + 10800 6850 10800 6750 +Wire Wire Line + 10100 6850 10800 6850 +Wire Wire Line + 10800 6350 9850 6350 +Wire Wire Line + 9850 6350 9850 6250 +Wire Wire Line + 9850 6250 9800 6250 +Wire Wire Line + 8200 5250 14750 5250 +Wire Wire Line + 9000 5300 9000 5250 +Connection ~ 9000 5250 +Wire Wire Line + 8800 7450 9150 7450 +Wire Wire Line + 8300 7450 8500 7450 +Wire Wire Line + 9800 7450 9450 7450 +Wire Wire Line + 8000 7650 7650 7650 +Connection ~ 7650 6850 +Wire Wire Line + 8300 7850 8300 8550 +Wire Wire Line + 8600 8750 9500 8750 +Wire Wire Line + 9800 8550 9800 7850 +Wire Wire Line + 7650 6850 7650 7900 +Connection ~ 7650 7650 +Wire Wire Line + 7650 8800 7650 9950 +Wire Wire Line + 9800 9950 9800 8950 +Wire Wire Line + 8300 8950 8300 9950 +Wire Wire Line + 8300 8400 8900 8400 +Wire Wire Line + 8900 8400 8900 8750 +Connection ~ 8900 8750 +Connection ~ 8300 8400 +Wire Wire Line + 9000 6200 9000 7450 +Connection ~ 9000 7450 +Wire Wire Line + 10400 6850 10400 8050 +Connection ~ 10400 6850 +Wire Wire Line + 10100 7650 10400 7650 +Connection ~ 10400 7650 +Wire Wire Line + 10400 9950 10400 8950 +Wire Wire Line + 12600 5250 12600 5350 +Connection ~ 9800 5250 +Wire Wire Line + 12600 6250 12600 6650 +Wire Wire Line + 12600 7150 12600 6950 +Wire Wire Line + 12600 7650 12600 7450 +Wire Wire Line + 12600 7950 12600 8350 +Wire Wire Line + 12200 8250 12600 8250 +Connection ~ 12600 8250 +Wire Wire Line + 11900 8250 11150 8250 +Wire Wire Line + 11150 8250 11150 9000 +Wire Wire Line + 9950 9000 11400 9000 +Wire Wire Line + 12600 8800 12600 8750 +Wire Wire Line + 12300 9300 12300 9000 +Wire Wire Line + 11700 9300 12300 9300 +Wire Wire Line + 11700 9300 11700 9200 +Wire Wire Line + 12000 9400 12000 9300 +Connection ~ 12000 9300 +Wire Wire Line + 13150 8700 13150 8550 +Wire Wire Line + 13150 8550 12900 8550 +Wire Wire Line + 7650 9950 14000 9950 +Wire Wire Line + 13150 9950 13150 9600 +Wire Wire Line + 12000 9700 12000 9950 +Connection ~ 12000 9950 +Connection ~ 10400 9950 +Connection ~ 9800 9950 +Connection ~ 8300 9950 +Wire Wire Line + 14000 5250 14000 5350 +Connection ~ 12600 5250 +Wire Wire Line + 14000 6000 14000 5750 +Wire Wire Line + 13700 6200 12800 6200 +Wire Wire Line + 12800 6200 12800 6400 +Wire Wire Line + 12800 6400 12600 6400 +Connection ~ 12600 6400 +Wire Wire Line + 14000 6400 14000 6500 +Wire Wire Line + 13550 6750 13550 6700 +Wire Wire Line + 13550 6700 13700 6700 +Wire Wire Line + 13250 6950 12900 6950 +Wire Wire Line + 12900 6950 12900 8100 +Wire Wire Line + 12900 8100 12600 8100 +Connection ~ 12600 8100 +Wire Wire Line + 14000 9950 14000 6900 +Connection ~ 13150 9950 +Wire Wire Line + 13550 7150 13550 7200 +Wire Wire Line + 13550 7200 14000 7200 +Connection ~ 14000 7200 +Connection ~ 14000 5250 +Wire Wire Line + 14300 5550 14300 6300 +Wire Wire Line + 14300 6300 14750 6300 +Wire Wire Line + 14750 6150 14750 6500 +Connection ~ 14750 6300 +Wire Wire Line + 14000 6450 14350 6450 +Wire Wire Line + 14350 6450 14350 7450 +Connection ~ 14000 6450 +Wire Wire Line + 11600 4850 11600 5250 +Connection ~ 11600 5250 +Wire Wire Line + 11200 9950 11200 10600 +Connection ~ 11200 9950 +Wire Wire Line + 8200 7050 8200 7250 +Wire Wire Line + 8200 7250 7950 7250 +Wire Wire Line + 7950 7250 7950 10450 +Wire Wire Line + 7950 10450 11200 10450 +Connection ~ 11200 10450 +Wire Wire Line + 9800 7050 10050 7050 +Wire Wire Line + 10050 7050 10050 10350 +Wire Wire Line + 10050 10350 11200 10350 +Connection ~ 11200 10350 +Wire Wire Line + 11700 8800 11700 7900 +Wire Wire Line + 11700 7900 11850 7900 +Wire Wire Line + 12600 9200 12600 9950 +Connection ~ 12600 9950 +Wire Wire Line + 14750 7700 15150 7700 +Wire Wire Line + 9950 9000 9950 8400 +Wire Wire Line + 9950 8400 9800 8400 +Connection ~ 9800 8400 +Connection ~ 11150 9000 +Wire Wire Line + 14350 7450 14750 7450 +Connection ~ 14750 7450 +Wire Wire Line + 11850 7900 11850 5250 +Connection ~ 11850 5250 +Connection ~ 14750 7700 +Wire Wire Line + 14750 7700 14750 7400 +Wire Wire Line + 6450 6600 7200 6600 +$Comp +L PORT U1 +U 1 1 668A67B8 +P 6200 6600 +F 0 "U1" H 6250 6700 30 0000 C CNN +F 1 "PORT" H 6200 6600 30 0000 C CNN +F 2 "" H 6200 6600 60 0000 C CNN +F 3 "" H 6200 6600 60 0000 C CNN + 1 6200 6600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 668A6ADF +P 11550 6550 +F 0 "U1" H 11600 6650 30 0000 C CNN +F 1 "PORT" H 11550 6550 30 0000 C CNN +F 2 "" H 11550 6550 60 0000 C CNN +F 3 "" H 11550 6550 60 0000 C CNN + 2 11550 6550 + -1 0 0 1 +$EndComp +Wire Wire Line + 11100 6550 11300 6550 +$Comp +L PORT U1 +U 3 1 668A7018 +P 11200 10850 +F 0 "U1" H 11250 10950 30 0000 C CNN +F 1 "PORT" H 11200 10850 30 0000 C CNN +F 2 "" H 11200 10850 60 0000 C CNN +F 3 "" H 11200 10850 60 0000 C CNN + 3 11200 10850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 668A744A +P 11850 4850 +F 0 "U1" H 11900 4950 30 0000 C CNN +F 1 "PORT" H 11850 4850 30 0000 C CNN +F 2 "" H 11850 4850 60 0000 C CNN +F 3 "" H 11850 4850 60 0000 C CNN + 5 11850 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 668A7705 +P 15400 7700 +F 0 "U1" H 15450 7800 30 0000 C CNN +F 1 "PORT" H 15400 7700 30 0000 C CNN +F 2 "" H 15400 7700 60 0000 C CNN +F 3 "" H 15400 7700 60 0000 C CNN + 4 15400 7700 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub new file mode 100644 index 00000000..41b29af7 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC.sub @@ -0,0 +1,40 @@ +* Subcircuit LM143_IC +.subckt LM143_IC net-_q1-pad2_ net-_q8-pad2_ net-_i1-pad2_ net-_q13-pad3_ net-_i2-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\lm143_ic\lm143_ic.cir +.include NPN.lib +.include PNP.lib +.include D.lib +i2 net-_i2-pad1_ net-_i2-pad2_ 80u +i3 net-_i2-pad1_ net-_i3-pad2_ 80u +i4 net-_i2-pad1_ net-_i4-pad2_ 80u +q1 net-_i2-pad2_ net-_q1-pad2_ net-_i1-pad1_ Q2N2222 +q2 net-_i1-pad2_ net-_i1-pad1_ net-_i2-pad2_ Q2N2907A +q6 net-_i1-pad2_ net-_i5-pad1_ net-_i4-pad2_ Q2N2907A +q8 net-_i4-pad2_ net-_q8-pad2_ net-_i5-pad1_ Q2N2222 +r2 net-_q3-pad3_ net-_i3-pad2_ 5.6k +r3 net-_i3-pad2_ net-_q7-pad3_ 5.6k +q3 net-_q3-pad1_ net-_i1-pad1_ net-_q3-pad3_ Q2N2907A +q7 net-_c1-pad2_ net-_i5-pad1_ net-_q7-pad3_ Q2N2907A +q4 net-_q3-pad1_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +q5 net-_c1-pad2_ net-_q3-pad1_ net-_i1-pad2_ Q2N2222 +i1 net-_i1-pad1_ net-_i1-pad2_ 20u +i5 net-_i5-pad1_ net-_i1-pad2_ 20u +i6 net-_i2-pad1_ net-_d1-pad1_ 400u +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_c1-pad1_ 1N4148 +q11 net-_c1-pad1_ net-_q11-pad2_ net-_q10-pad1_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 27p +q9 net-_i2-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_i1-pad2_ Q2N2222 +r5 net-_q10-pad2_ net-_i1-pad2_ 39k +v1 net-_q11-pad2_ net-_i1-pad2_ 2 +q15 net-_i2-pad1_ net-_i7-pad2_ net-_q13-pad1_ Q2N2222 +q13 net-_q13-pad1_ net-_d1-pad1_ net-_q13-pad3_ Q2N2222 +q14 net-_i1-pad2_ net-_q12-pad3_ net-_q13-pad3_ Q2N2907A +q12 net-_i1-pad2_ net-_c1-pad1_ net-_q12-pad3_ Q2N2907A +i7 net-_i2-pad1_ net-_i7-pad2_ 400u +v2 net-_i7-pad2_ net-_q13-pad3_ 3.5 +* Control Statements + +.ends LM143_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml new file mode 100644 index 00000000..241d7b93 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/LM143_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i2 name="Source type">80u</i2><i3 name="Source type">80u</i3><i4 name="Source type">80u</i4><i1 name="Source type">20u</i1><i5 name="Source type">20u</i5><i6 name="Source type">400u</i6><v1 name="Source type">2</v1><i7 name="Source type">400u</i7><v2 name="Source type">3.5</v2></source><model /><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM143_sub/NPN.lib b/library/SubcircuitLibrary/LM143_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM143_sub/PNP.lib b/library/SubcircuitLibrary/LM143_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM143_sub/analysis b/library/SubcircuitLibrary/LM143_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM143_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib new file mode 100644 index 00000000..27408fec --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC-cache.lib @@ -0,0 +1,138 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir new file mode 100644 index 00000000..4b52a3c4 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir @@ -0,0 +1,56 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\LM78M05_IC\LM78M05_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/02/24 21:24:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 80k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +U1 Net-_Q16-Pad3_ Net-_Q1-Pad2_ zener +R2 Net-_Q1-Pad3_ Net-_Q13-Pad2_ 7k +R3 Net-_Q13-Pad2_ Net-_Q3-Pad2_ 4.97k +R4 Net-_Q3-Pad2_ Net-_Q16-Pad3_ 830 +Q4 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q8 Net-_Q12-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q5 Net-_Q2-Pad1_ Net-_Q1-Pad3_ Net-_Q5-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q13-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q5-Pad3_ Net-_Q13-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R5 Net-_Q2-Pad3_ Net-_Q6-Pad3_ 500 +Q7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ Net-_C1-Pad2_ eSim_NPN +R6 Net-_C1-Pad2_ Net-_Q16-Pad3_ 1.2k +R7 Net-_Q6-Pad3_ Net-_Q7-Pad2_ 1.9k +R8 Net-_Q7-Pad2_ Net-_C1-Pad1_ 26 +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 0.4p +Q9 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q16-Pad3_ eSim_NPN +U2 Net-_R12-Pad1_ Net-_Q1-Pad1_ zener +R12 Net-_R12-Pad1_ Net-_R12-Pad2_ 5k +U3 Net-_Q12-Pad2_ Net-_R12-Pad2_ zener +Q18 Net-_Q1-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad1_ eSim_NPN +Q19 Net-_Q1-Pad1_ Net-_Q13-Pad1_ Net-_Q19-Pad3_ eSim_NPN +R18 Net-_Q13-Pad1_ Net-_Q12-Pad2_ 1.14k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_NPN +R16 Net-_Q19-Pad3_ Net-_Q12-Pad2_ 100 +R17 Net-_R17-Pad1_ Net-_Q12-Pad3_ 100 +R19 Net-_R17-Pad1_ Net-_Q19-Pad3_ 0.5 +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q10-Pad1_ eSim_NPN +R20 Net-_Q13-Pad2_ Net-_R17-Pad1_ 1.6k +R14 Net-_Q17-Pad3_ Net-_Q12-Pad1_ 850 +R10 Net-_C2-Pad2_ Net-_Q10-Pad1_ 16.5k +Q10 Net-_Q10-Pad1_ Net-_C1-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R9 Net-_Q16-Pad3_ Net-_Q10-Pad3_ 12.1k +R15 Net-_C2-Pad1_ Net-_Q17-Pad3_ 4k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 20p +Q14 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q14-Pad3_ eSim_NPN +Q3 Net-_Q12-Pad1_ Net-_Q3-Pad2_ Net-_Q16-Pad3_ eSim_NPN +Q11 Net-_C2-Pad2_ Net-_Q10-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R11 Net-_Q16-Pad3_ Net-_Q11-Pad3_ 1k +Q15 Net-_Q14-Pad3_ Net-_Q14-Pad3_ Net-_Q15-Pad3_ eSim_NPN +R13 Net-_Q16-Pad3_ Net-_Q15-Pad3_ 4k +Q16 Net-_C2-Pad1_ Net-_Q14-Pad3_ Net-_Q16-Pad3_ eSim_NPN +R21 Net-_Q16-Pad3_ Net-_Q13-Pad2_ 4k +Q17 Net-_Q16-Pad3_ Net-_C2-Pad1_ Net-_Q17-Pad3_ eSim_PNP +U4 Net-_Q1-Pad1_ Net-_R17-Pad1_ Net-_Q16-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out new file mode 100644 index 00000000..1cc0d232 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.cir.out @@ -0,0 +1,68 @@ +* d:\fossee\esim\library\subcircuitlibrary\lm78m05_ic\lm78m05_ic.cir + +.include PNP.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 80k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q16-pad3_ net-_q1-pad2_ zener +r2 net-_q1-pad3_ net-_q13-pad2_ 7k +r3 net-_q13-pad2_ net-_q3-pad2_ 4.97k +r4 net-_q3-pad2_ net-_q16-pad3_ 830 +q4 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q8 net-_q12-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q5 net-_q2-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q13-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222 +r5 net-_q2-pad3_ net-_q6-pad3_ 500 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad2_ Q2N2222 +r6 net-_c1-pad2_ net-_q16-pad3_ 1.2k +r7 net-_q6-pad3_ net-_q7-pad2_ 1.9k +r8 net-_q7-pad2_ net-_c1-pad1_ 26 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.4p +q9 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +* u2 net-_r12-pad1_ net-_q1-pad1_ zener +r12 net-_r12-pad1_ net-_r12-pad2_ 5k +* u3 net-_q12-pad2_ net-_r12-pad2_ zener +q18 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222 +q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222 +r18 net-_q13-pad1_ net-_q12-pad2_ 1.14k +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r16 net-_q19-pad3_ net-_q12-pad2_ 100 +r17 net-_r17-pad1_ net-_q12-pad3_ 100 +r19 net-_r17-pad1_ net-_q19-pad3_ 0.5 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +r20 net-_q13-pad2_ net-_r17-pad1_ 1.6k +r14 net-_q17-pad3_ net-_q12-pad1_ 850 +r10 net-_c2-pad2_ net-_q10-pad1_ 16.5k +q10 net-_q10-pad1_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k +r15 net-_c2-pad1_ net-_q17-pad3_ 4k +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +q14 net-_c2-pad1_ net-_c2-pad2_ net-_q14-pad3_ Q2N2222 +q3 net-_q12-pad1_ net-_q3-pad2_ net-_q16-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r11 net-_q16-pad3_ net-_q11-pad3_ 1k +q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222 +r13 net-_q16-pad3_ net-_q15-pad3_ 4k +q16 net-_c2-pad1_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222 +r21 net-_q16-pad3_ net-_q13-pad2_ 4k +q17 net-_q16-pad3_ net-_c2-pad1_ net-_q17-pad3_ Q2N2907A +* u4 net-_q1-pad1_ net-_r17-pad1_ net-_q16-pad3_ port +a1 net-_q16-pad3_ net-_q1-pad2_ u1 +a2 net-_r12-pad1_ net-_q1-pad1_ u2 +a3 net-_q12-pad2_ net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0.01e-03 0.1e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch new file mode 100644 index 00000000..3693b791 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sch @@ -0,0 +1,828 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:LM78M05-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 66842368 +P 2150 1500 +F 0 "R1" H 2200 1630 50 0000 C CNN +F 1 "80k" H 2200 1450 50 0000 C CNN +F 2 "" H 2200 1480 30 0000 C CNN +F 3 "" V 2200 1550 30 0000 C CNN + 1 2150 1500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 66842369 +P 2600 1900 +F 0 "Q1" H 2500 1950 50 0000 R CNN +F 1 "eSim_NPN" H 2550 2050 50 0000 R CNN +F 2 "" H 2800 2000 29 0000 C CNN +F 3 "" H 2600 1900 60 0000 C CNN + 1 2600 1900 + 1 0 0 -1 +$EndComp +$Comp +L zener U1 +U 1 1 6684236A +P 2200 3350 +F 0 "U1" H 2150 3250 60 0000 C CNN +F 1 "zener" H 2200 3450 60 0000 C CNN +F 2 "" H 2250 3350 60 0000 C CNN +F 3 "" H 2250 3350 60 0000 C CNN + 1 2200 3350 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2200 1700 2200 3050 +$Comp +L resistor R2 +U 1 1 6684236B +P 2650 2800 +F 0 "R2" H 2700 2930 50 0000 C CNN +F 1 "7k" H 2700 2750 50 0000 C CNN +F 2 "" H 2700 2780 30 0000 C CNN +F 3 "" V 2700 2850 30 0000 C CNN + 1 2650 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6684236C +P 2650 3550 +F 0 "R3" H 2700 3680 50 0000 C CNN +F 1 "4.97k" H 2700 3500 50 0000 C CNN +F 2 "" H 2700 3530 30 0000 C CNN +F 3 "" V 2700 3600 30 0000 C CNN + 1 2650 3550 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6684236D +P 2650 6200 +F 0 "R4" H 2700 6330 50 0000 C CNN +F 1 "830" H 2700 6150 50 0000 C CNN +F 2 "" H 2700 6180 30 0000 C CNN +F 3 "" V 2700 6250 30 0000 C CNN + 1 2650 6200 + 0 1 1 0 +$EndComp +Wire Wire Line + 2200 3550 2200 6700 +Wire Wire Line + 2700 3750 2700 6100 +Wire Wire Line + 2700 2100 2700 2700 +Wire Wire Line + 2400 1900 2200 1900 +Connection ~ 2200 1900 +Wire Wire Line + 2700 1700 2700 1300 +Wire Wire Line + 2200 1300 7600 1300 +Wire Wire Line + 2200 1300 2200 1400 +$Comp +L eSim_PNP Q4 +U 1 1 6684236E +P 3350 1650 +F 0 "Q4" H 3250 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3300 1800 50 0000 R CNN +F 2 "" H 3550 1750 29 0000 C CNN +F 3 "" H 3350 1650 60 0000 C CNN + 1 3350 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6684236F +P 3800 1650 +F 0 "Q8" H 3700 1700 50 0000 R CNN +F 1 "eSim_PNP" H 3750 1800 50 0000 R CNN +F 2 "" H 4000 1750 29 0000 C CNN +F 3 "" H 3800 1650 60 0000 C CNN + 1 3800 1650 + 1 0 0 1 +$EndComp +Wire Wire Line + 3600 1650 3150 1650 +Wire Wire Line + 3450 1850 3450 2350 +Wire Wire Line + 3900 1850 3900 1950 +Wire Wire Line + 3450 1450 3900 1450 +Wire Wire Line + 3700 1300 3700 1450 +Connection ~ 2700 1300 +Connection ~ 3700 1450 +$Comp +L eSim_NPN Q5 +U 1 1 66842370 +P 3350 2550 +F 0 "Q5" H 3250 2600 50 0000 R CNN +F 1 "eSim_NPN" H 3300 2700 50 0000 R CNN +F 2 "" H 3550 2650 29 0000 C CNN +F 3 "" H 3350 2550 60 0000 C CNN + 1 3350 2550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3150 2550 2700 2550 +Connection ~ 2700 2550 +Wire Wire Line + 3150 1650 3150 1950 +Wire Wire Line + 3150 1950 3450 1950 +Connection ~ 3450 1950 +Wire Wire Line + 2700 3000 2700 3450 +$Comp +L eSim_NPN Q2 +U 1 1 66842371 +P 2950 3250 +F 0 "Q2" H 2850 3300 50 0000 R CNN +F 1 "eSim_NPN" H 2900 3400 50 0000 R CNN +F 2 "" H 3150 3350 29 0000 C CNN +F 3 "" H 2950 3250 60 0000 C CNN + 1 2950 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 66842372 +P 3550 3250 +F 0 "Q6" H 3450 3300 50 0000 R CNN +F 1 "eSim_NPN" H 3500 3400 50 0000 R CNN +F 2 "" H 3750 3350 29 0000 C CNN +F 3 "" H 3550 3250 60 0000 C CNN + 1 3550 3250 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3450 2750 3450 3050 +Wire Wire Line + 3050 3050 3050 2300 +Wire Wire Line + 3050 2300 3450 2300 +Connection ~ 3450 2300 +$Comp +L resistor R5 +U 1 1 66842373 +P 3000 3700 +F 0 "R5" H 3050 3830 50 0000 C CNN +F 1 "500" H 3050 3650 50 0000 C CNN +F 2 "" H 3050 3680 30 0000 C CNN +F 3 "" V 3050 3750 30 0000 C CNN + 1 3000 3700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3050 3600 3050 3450 +$Comp +L eSim_NPN Q7 +U 1 1 66842374 +P 3550 4150 +F 0 "Q7" H 3450 4200 50 0000 R CNN +F 1 "eSim_NPN" H 3500 4300 50 0000 R CNN +F 2 "" H 3750 4250 29 0000 C CNN +F 3 "" H 3550 4150 60 0000 C CNN + 1 3550 4150 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3450 3450 3450 3950 +$Comp +L resistor R6 +U 1 1 66842375 +P 3400 6100 +F 0 "R6" H 3450 6230 50 0000 C CNN +F 1 "1.2k" H 3450 6050 50 0000 C CNN +F 2 "" H 3450 6080 30 0000 C CNN +F 3 "" V 3450 6150 30 0000 C CNN + 1 3400 6100 + 0 1 1 0 +$EndComp +Wire Wire Line + 3450 4350 3450 6000 +$Comp +L resistor R7 +U 1 1 66842376 +P 4000 3850 +F 0 "R7" H 4050 3980 50 0000 C CNN +F 1 "1.9k" H 4050 3800 50 0000 C CNN +F 2 "" H 4050 3830 30 0000 C CNN +F 3 "" V 4050 3900 30 0000 C CNN + 1 4000 3850 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 66842377 +P 4000 4350 +F 0 "R8" H 4050 4480 50 0000 C CNN +F 1 "26" H 4050 4300 50 0000 C CNN +F 2 "" H 4050 4330 30 0000 C CNN +F 3 "" V 4050 4400 30 0000 C CNN + 1 4000 4350 + 0 1 1 0 +$EndComp +Wire Wire Line + 4050 4050 4050 4250 +Wire Wire Line + 3750 4150 4050 4150 +Connection ~ 4050 4150 +Wire Wire Line + 3050 3900 3750 3900 +Wire Wire Line + 3750 3900 3750 3700 +Wire Wire Line + 3750 3700 4050 3700 +Wire Wire Line + 4050 3700 4050 3750 +Connection ~ 3450 3900 +$Comp +L capacitor C1 +U 1 1 66842378 +P 3750 4700 +F 0 "C1" H 3775 4800 50 0000 L CNN +F 1 "0.4p" H 3775 4600 50 0000 L CNN +F 2 "" H 3788 4550 30 0000 C CNN +F 3 "" H 3750 4700 60 0000 C CNN + 1 3750 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 3600 4700 3450 4700 +Connection ~ 3450 4700 +Wire Wire Line + 4050 4550 4050 5400 +Wire Wire Line + 3900 4700 4200 4700 +$Comp +L eSim_NPN Q9 +U 1 1 66842379 +P 3950 5600 +F 0 "Q9" H 3850 5650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 5750 50 0000 R CNN +F 2 "" H 4150 5700 29 0000 C CNN +F 3 "" H 3950 5600 60 0000 C CNN + 1 3950 5600 + 1 0 0 -1 +$EndComp +Connection ~ 4050 4700 +$Comp +L zener U2 +U 1 1 6684237A +P 5400 1700 +F 0 "U2" H 5350 1600 60 0000 C CNN +F 1 "zener" H 5400 1800 60 0000 C CNN +F 2 "" H 5450 1700 60 0000 C CNN +F 3 "" H 5450 1700 60 0000 C CNN + 1 5400 1700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5400 1300 5400 1400 +Connection ~ 3700 1300 +$Comp +L resistor R12 +U 1 1 6684237B +P 5350 2300 +F 0 "R12" H 5400 2430 50 0000 C CNN +F 1 "5k" H 5400 2250 50 0000 C CNN +F 2 "" H 5400 2280 30 0000 C CNN +F 3 "" V 5400 2350 30 0000 C CNN + 1 5350 2300 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 6684237C +P 5400 2900 +F 0 "U3" H 5350 2800 60 0000 C CNN +F 1 "zener" H 5400 3000 60 0000 C CNN +F 2 "" H 5450 2900 60 0000 C CNN +F 3 "" H 5450 2900 60 0000 C CNN + 1 5400 2900 + 0 1 -1 0 +$EndComp +Wire Wire Line + 5400 1900 5400 2200 +Wire Wire Line + 5400 2500 5400 2600 +$Comp +L eSim_NPN Q18 +U 1 1 6684237D +P 6000 1950 +F 0 "Q18" H 5900 2000 50 0000 R CNN +F 1 "eSim_NPN" H 5950 2100 50 0000 R CNN +F 2 "" H 6200 2050 29 0000 C CNN +F 3 "" H 6000 1950 60 0000 C CNN + 1 6000 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6100 1300 6100 1750 +Connection ~ 5400 1300 +Wire Wire Line + 3900 1950 5800 1950 +$Comp +L eSim_NPN Q19 +U 1 1 6684237E +P 6800 2200 +F 0 "Q19" H 6700 2250 50 0000 R CNN +F 1 "eSim_NPN" H 6750 2350 50 0000 R CNN +F 2 "" H 7000 2300 29 0000 C CNN +F 3 "" H 6800 2200 60 0000 C CNN + 1 6800 2200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6900 1300 6900 2000 +Connection ~ 6100 1300 +Wire Wire Line + 6100 2200 6600 2200 +Wire Wire Line + 6100 2200 6100 2150 +$Comp +L resistor R18 +U 1 1 6684237F +P 6200 2400 +F 0 "R18" H 6250 2530 50 0000 C CNN +F 1 "1.14k" H 6250 2350 50 0000 C CNN +F 2 "" H 6250 2380 30 0000 C CNN +F 3 "" V 6250 2450 30 0000 C CNN + 1 6200 2400 + 0 1 1 0 +$EndComp +Wire Wire Line + 6250 3150 6250 2600 +Wire Wire Line + 5400 3100 5400 3350 +Wire Wire Line + 6250 2300 6250 2200 +Connection ~ 6250 2200 +$Comp +L eSim_NPN Q12 +U 1 1 66842380 +P 4950 3350 +F 0 "Q12" H 4850 3400 50 0000 R CNN +F 1 "eSim_NPN" H 4900 3500 50 0000 R CNN +F 2 "" H 5150 3450 29 0000 C CNN +F 3 "" H 4950 3350 60 0000 C CNN + 1 4950 3350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4850 1950 4850 3150 +Connection ~ 4850 1950 +Wire Wire Line + 5400 3150 6250 3150 +$Comp +L resistor R16 +U 1 1 66842381 +P 5850 3300 +F 0 "R16" H 5900 3430 50 0000 C CNN +F 1 "100" H 5900 3250 50 0000 C CNN +F 2 "" H 5900 3280 30 0000 C CNN +F 3 "" V 5900 3350 30 0000 C CNN + 1 5850 3300 + -1 0 0 1 +$EndComp +Wire Wire Line + 5150 3350 5650 3350 +Connection ~ 5400 3350 +Connection ~ 5400 3150 +Wire Wire Line + 5950 3350 6900 3350 +Wire Wire Line + 6900 2400 6900 3400 +$Comp +L resistor R17 +U 1 1 66842382 +P 5850 3750 +F 0 "R17" H 5900 3880 50 0000 C CNN +F 1 "100" H 5900 3700 50 0000 C CNN +F 2 "" H 5900 3730 30 0000 C CNN +F 3 "" V 5900 3800 30 0000 C CNN + 1 5850 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 4850 3550 4850 3800 +$Comp +L resistor R19 +U 1 1 66842383 +P 6950 3600 +F 0 "R19" H 7000 3730 50 0000 C CNN +F 1 "0.5" H 7000 3550 50 0000 C CNN +F 2 "" H 7000 3580 30 0000 C CNN +F 3 "" V 7000 3650 30 0000 C CNN + 1 6950 3600 + 0 -1 -1 0 +$EndComp +Connection ~ 6900 3350 +$Comp +L eSim_NPN Q13 +U 1 1 66842384 +P 4950 4250 +F 0 "Q13" H 4850 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4900 4400 50 0000 R CNN +F 2 "" H 5150 4350 29 0000 C CNN +F 3 "" H 4950 4250 60 0000 C CNN + 1 4950 4250 + -1 0 0 -1 +$EndComp +Connection ~ 6450 2200 +Wire Wire Line + 4850 4050 4850 4000 +Wire Wire Line + 4850 4000 6450 4000 +Wire Wire Line + 6450 4000 6450 2200 +Wire Wire Line + 2700 3250 4600 3250 +Wire Wire Line + 4600 3250 4600 4250 +Wire Wire Line + 4600 4250 6900 4250 +Connection ~ 2700 3250 +$Comp +L resistor R20 +U 1 1 66842385 +P 6950 4100 +F 0 "R20" H 7000 4230 50 0000 C CNN +F 1 "1.6k" H 7000 4050 50 0000 C CNN +F 2 "" H 7000 4080 30 0000 C CNN +F 3 "" V 7000 4150 30 0000 C CNN + 1 6950 4100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 6900 4200 6900 5600 +Wire Wire Line + 6900 3700 6900 3900 +Wire Wire Line + 4850 3800 5650 3800 +Wire Wire Line + 5950 3800 7500 3800 +Connection ~ 6900 3800 +Connection ~ 5150 4250 +Connection ~ 3750 3250 +Connection ~ 2750 3250 +$Comp +L resistor R14 +U 1 1 66842386 +P 5550 4600 +F 0 "R14" H 5600 4730 50 0000 C CNN +F 1 "850" H 5600 4550 50 0000 C CNN +F 2 "" H 5600 4580 30 0000 C CNN +F 3 "" V 5600 4650 30 0000 C CNN + 1 5550 4600 + 0 -1 -1 0 +$EndComp +Connection ~ 5500 1950 +Wire Wire Line + 5500 4400 5500 1950 +$Comp +L resistor R10 +U 1 1 66842387 +P 4900 4900 +F 0 "R10" H 4950 5030 50 0000 C CNN +F 1 "16.5k" H 4950 4850 50 0000 C CNN +F 2 "" H 4950 4880 30 0000 C CNN +F 3 "" V 4950 4950 30 0000 C CNN + 1 4900 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4850 4450 4850 4700 +$Comp +L eSim_NPN Q10 +U 1 1 66842388 +P 4400 4700 +F 0 "Q10" H 4300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 4350 4850 50 0000 R CNN +F 2 "" H 4600 4800 29 0000 C CNN +F 3 "" H 4400 4700 60 0000 C CNN + 1 4400 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 4500 4850 4500 +Connection ~ 4850 4500 +$Comp +L resistor R9 +U 1 1 66842389 +P 4550 6300 +F 0 "R9" H 4600 6430 50 0000 C CNN +F 1 "12.1k" H 4600 6250 50 0000 C CNN +F 2 "" H 4600 6280 30 0000 C CNN +F 3 "" V 4600 6350 30 0000 C CNN + 1 4550 6300 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4900 4500 6100 +$Comp +L resistor R15 +U 1 1 6684238A +P 5550 5100 +F 0 "R15" H 5600 5230 50 0000 C CNN +F 1 "4k" H 5600 5050 50 0000 C CNN +F 2 "" H 5600 5080 30 0000 C CNN +F 3 "" V 5600 5150 30 0000 C CNN + 1 5550 5100 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5500 4700 5500 4900 +$Comp +L capacitor C2 +U 1 1 6684238B +P 5050 5300 +F 0 "C2" H 5075 5400 50 0000 L CNN +F 1 "20p" H 5075 5200 50 0000 L CNN +F 2 "" H 5088 5150 30 0000 C CNN +F 3 "" H 5050 5300 60 0000 C CNN + 1 5050 5300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5500 5200 5500 5750 +Wire Wire Line + 4850 5000 4850 5850 +Wire Wire Line + 4850 5300 4900 5300 +$Comp +L eSim_NPN Q14 +U 1 1 6684238C +P 5200 5700 +F 0 "Q14" H 5100 5750 50 0000 R CNN +F 1 "eSim_NPN" H 5150 5850 50 0000 R CNN +F 2 "" H 5400 5800 29 0000 C CNN +F 3 "" H 5200 5700 60 0000 C CNN + 1 5200 5700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5500 5300 5300 +Connection ~ 5300 5300 +Wire Wire Line + 4850 5700 5000 5700 +Connection ~ 4850 5300 +Wire Wire Line + 2200 6700 4850 6700 +Wire Wire Line + 2700 6700 2700 6400 +Connection ~ 2700 6700 +$Comp +L eSim_NPN Q3 +U 1 1 6684238D +P 3000 5900 +F 0 "Q3" H 2900 5950 50 0000 R CNN +F 1 "eSim_NPN" H 2950 6050 50 0000 R CNN +F 2 "" H 3200 6000 29 0000 C CNN +F 3 "" H 3000 5900 60 0000 C CNN + 1 3000 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 5900 2700 5900 +Connection ~ 2700 5900 +Wire Wire Line + 3100 5700 3100 3100 +Wire Wire Line + 3100 3100 4850 3100 +Connection ~ 4850 3100 +Wire Wire Line + 3100 6100 3100 6700 +Connection ~ 3100 6700 +Connection ~ 3450 6700 +Wire Wire Line + 4500 6700 4500 6400 +Connection ~ 4050 6700 +Wire Wire Line + 3450 6300 3450 6700 +$Comp +L eSim_NPN Q11 +U 1 1 6684238E +P 4750 6050 +F 0 "Q11" H 4650 6100 50 0000 R CNN +F 1 "eSim_NPN" H 4700 6200 50 0000 R CNN +F 2 "" H 4950 6150 29 0000 C CNN +F 3 "" H 4750 6050 60 0000 C CNN + 1 4750 6050 + 1 0 0 -1 +$EndComp +Connection ~ 4850 5700 +Wire Wire Line + 4550 6050 4500 6050 +Connection ~ 4500 6050 +$Comp +L resistor R11 +U 1 1 6684238F +P 4900 6550 +F 0 "R11" H 4950 6680 50 0000 C CNN +F 1 "1k" H 4950 6500 50 0000 C CNN +F 2 "" H 4950 6530 30 0000 C CNN +F 3 "" V 4950 6600 30 0000 C CNN + 1 4900 6550 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4850 6650 4850 6900 +Connection ~ 4500 6700 +Wire Wire Line + 4850 6350 4850 6250 +$Comp +L eSim_NPN Q15 +U 1 1 66842390 +P 5400 6300 +F 0 "Q15" H 5300 6350 50 0000 R CNN +F 1 "eSim_NPN" H 5350 6450 50 0000 R CNN +F 2 "" H 5600 6400 29 0000 C CNN +F 3 "" H 5400 6300 60 0000 C CNN + 1 5400 6300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66842391 +P 5350 6800 +F 0 "R13" H 5400 6930 50 0000 C CNN +F 1 "4k" H 5400 6750 50 0000 C CNN +F 2 "" H 5400 6780 30 0000 C CNN +F 3 "" V 5400 6850 30 0000 C CNN + 1 5350 6800 + 0 -1 -1 0 +$EndComp +Connection ~ 4850 6700 +Wire Wire Line + 5300 6600 5300 6500 +Wire Wire Line + 5300 5900 5300 6100 +$Comp +L eSim_NPN Q16 +U 1 1 66842392 +P 5650 5950 +F 0 "Q16" H 5550 6000 50 0000 R CNN +F 1 "eSim_NPN" H 5600 6100 50 0000 R CNN +F 2 "" H 5850 6050 29 0000 C CNN +F 3 "" H 5650 5950 60 0000 C CNN + 1 5650 5950 + 1 0 0 -1 +$EndComp +Connection ~ 5500 5300 +Wire Wire Line + 5600 6050 5600 6300 +Wire Wire Line + 5600 6050 5300 6050 +Connection ~ 5300 6050 +Connection ~ 5300 6900 +$Comp +L resistor R21 +U 1 1 66842393 +P 6950 5800 +F 0 "R21" H 7000 5930 50 0000 C CNN +F 1 "4k" H 7000 5750 50 0000 C CNN +F 2 "" H 7000 5780 30 0000 C CNN +F 3 "" V 7000 5850 30 0000 C CNN + 1 6950 5800 + 0 -1 -1 0 +$EndComp +Connection ~ 6900 4250 +Wire Wire Line + 3750 5600 3450 5600 +Connection ~ 3450 5600 +Wire Wire Line + 4050 5800 4050 6700 +Wire Wire Line + 5500 5750 5750 5750 +Wire Wire Line + 5450 5950 5300 5950 +Connection ~ 5300 5950 +Wire Wire Line + 5750 6900 5750 6150 +Connection ~ 5750 6900 +$Comp +L eSim_PNP Q17 +U 1 1 66842394 +P 5800 5300 +F 0 "Q17" H 5700 5350 50 0000 R CNN +F 1 "eSim_PNP" H 5750 5450 50 0000 R CNN +F 2 "" H 6000 5400 29 0000 C CNN +F 3 "" H 5800 5300 60 0000 C CNN + 1 5800 5300 + 1 0 0 1 +$EndComp +Wire Wire Line + 5200 5300 5600 5300 +Wire Wire Line + 5900 5100 5900 4800 +Wire Wire Line + 5900 4800 5500 4800 +Connection ~ 5500 4800 +Wire Wire Line + 5900 6900 5900 5500 +Connection ~ 5900 6900 +Connection ~ 6900 1300 +Wire Wire Line + 6950 6900 6950 7050 +Wire Wire Line + 6900 5900 6900 7000 +Wire Wire Line + 6900 7000 6950 7000 +Connection ~ 6950 7000 +Wire Wire Line + 4850 6900 6950 6900 +$Comp +L PORT U4 +U 1 1 66842F0A +P 7850 1300 +F 0 "U4" H 7900 1400 30 0000 C CNN +F 1 "PORT" H 7850 1300 30 0000 C CNN +F 2 "" H 7850 1300 60 0000 C CNN +F 3 "" H 7850 1300 60 0000 C CNN + 1 7850 1300 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 668432FF +P 7750 3800 +F 0 "U4" H 7800 3900 30 0000 C CNN +F 1 "PORT" H 7750 3800 30 0000 C CNN +F 2 "" H 7750 3800 60 0000 C CNN +F 3 "" H 7750 3800 60 0000 C CNN + 2 7750 3800 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 3 1 66843537 +P 6950 7300 +F 0 "U4" H 7000 7400 30 0000 C CNN +F 1 "PORT" H 6950 7300 30 0000 C CNN +F 2 "" H 6950 7300 60 0000 C CNN +F 3 "" H 6950 7300 60 0000 C CNN + 3 6950 7300 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub new file mode 100644 index 00000000..17df98f3 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC.sub @@ -0,0 +1,62 @@ +* Subcircuit LM78M05_IC +.subckt LM78M05_IC net-_q1-pad1_ net-_r17-pad1_ net-_q16-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\lm78m05_ic\lm78m05_ic.cir +.include PNP.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 80k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +* u1 net-_q16-pad3_ net-_q1-pad2_ zener +r2 net-_q1-pad3_ net-_q13-pad2_ 7k +r3 net-_q13-pad2_ net-_q3-pad2_ 4.97k +r4 net-_q3-pad2_ net-_q16-pad3_ 830 +q4 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q8 net-_q12-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2907A +q5 net-_q2-pad1_ net-_q1-pad3_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q13-pad2_ net-_q2-pad3_ Q2N2222 +q6 net-_q5-pad3_ net-_q13-pad2_ net-_q6-pad3_ Q2N2222 +r5 net-_q2-pad3_ net-_q6-pad3_ 500 +q7 net-_q6-pad3_ net-_q7-pad2_ net-_c1-pad2_ Q2N2222 +r6 net-_c1-pad2_ net-_q16-pad3_ 1.2k +r7 net-_q6-pad3_ net-_q7-pad2_ 1.9k +r8 net-_q7-pad2_ net-_c1-pad1_ 26 +c1 net-_c1-pad1_ net-_c1-pad2_ 0.4p +q9 net-_c1-pad1_ net-_c1-pad2_ net-_q16-pad3_ Q2N2222 +* u2 net-_r12-pad1_ net-_q1-pad1_ zener +r12 net-_r12-pad1_ net-_r12-pad2_ 5k +* u3 net-_q12-pad2_ net-_r12-pad2_ zener +q18 net-_q1-pad1_ net-_q12-pad1_ net-_q13-pad1_ Q2N2222 +q19 net-_q1-pad1_ net-_q13-pad1_ net-_q19-pad3_ Q2N2222 +r18 net-_q13-pad1_ net-_q12-pad2_ 1.14k +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2222 +r16 net-_q19-pad3_ net-_q12-pad2_ 100 +r17 net-_r17-pad1_ net-_q12-pad3_ 100 +r19 net-_r17-pad1_ net-_q19-pad3_ 0.5 +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q10-pad1_ Q2N2222 +r20 net-_q13-pad2_ net-_r17-pad1_ 1.6k +r14 net-_q17-pad3_ net-_q12-pad1_ 850 +r10 net-_c2-pad2_ net-_q10-pad1_ 16.5k +q10 net-_q10-pad1_ net-_c1-pad1_ net-_q10-pad3_ Q2N2222 +r9 net-_q16-pad3_ net-_q10-pad3_ 12.1k +r15 net-_c2-pad1_ net-_q17-pad3_ 4k +c2 net-_c2-pad1_ net-_c2-pad2_ 20p +q14 net-_c2-pad1_ net-_c2-pad2_ net-_q14-pad3_ Q2N2222 +q3 net-_q12-pad1_ net-_q3-pad2_ net-_q16-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_q10-pad3_ net-_q11-pad3_ Q2N2222 +r11 net-_q16-pad3_ net-_q11-pad3_ 1k +q15 net-_q14-pad3_ net-_q14-pad3_ net-_q15-pad3_ Q2N2222 +r13 net-_q16-pad3_ net-_q15-pad3_ 4k +q16 net-_c2-pad1_ net-_q14-pad3_ net-_q16-pad3_ Q2N2222 +r21 net-_q16-pad3_ net-_q13-pad2_ 4k +q17 net-_q16-pad3_ net-_c2-pad1_ net-_q17-pad3_ Q2N2907A +a1 net-_q16-pad3_ net-_q1-pad2_ u1 +a2 net-_r12-pad1_ net-_q1-pad1_ u2 +a3 net-_q12-pad2_ net-_r12-pad2_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM78M05_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml new file mode 100644 index 00000000..1be6e874 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/LM78M05_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1><u2 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">0.1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/LM78M05_sub/NPN.lib b/library/SubcircuitLibrary/LM78M05_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM78M05_sub/PNP.lib b/library/SubcircuitLibrary/LM78M05_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM78M05_sub/analysis b/library/SubcircuitLibrary/LM78M05_sub/analysis new file mode 100644 index 00000000..e69f4e9b --- /dev/null +++ b/library/SubcircuitLibrary/LM78M05_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 0.1e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/D.lib b/library/SubcircuitLibrary/MC1489_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/NPN.lib b/library/SubcircuitLibrary/MC1489_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC1489_0/analysis b/library/SubcircuitLibrary/MC1489_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib new file mode 100644 index 00000000..7eda2392 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir new file mode 100644 index 00000000..170c7d7f --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir @@ -0,0 +1,179 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\MC3403_IC\MC3403_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:49:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q19 Net-_Q19-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q22 Net-_Q22-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q42 Net-_Q1-Pad2_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q43 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q47 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q47-Pad3_ eSim_NPN +Q49 Net-_J1-Pad1_ Net-_Q47-Pad3_ Net-_Q49-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q12-Pad3_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q2 Net-_J1-Pad2_ Net-_Q12-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q7 Net-_Q12-Pad2_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q18 Net-_C1-Pad2_ Net-_Q18-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q21 Net-_Q18-Pad2_ Net-_Q18-Pad2_ Net-_Q12-Pad3_ eSim_PNP +Q3 Net-_J1-Pad2_ Net-_Q3-Pad2_ Net-_Q12-Pad2_ eSim_PNP +Q8 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q16 Net-_C1-Pad2_ Net-_Q12-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q25 Net-_J1-Pad2_ Net-_Q25-Pad2_ Net-_Q18-Pad2_ eSim_PNP +Q29 Net-_J1-Pad2_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q30 Net-_Q19-Pad1_ Net-_Q10-Pad1_ Net-_Q30-Pad3_ eSim_NPN +Q32 Net-_Q30-Pad3_ Net-_Q22-Pad1_ Net-_Q32-Pad3_ eSim_NPN +R3 Net-_Q32-Pad3_ Net-_J1-Pad2_ 12k +Q35 Net-_J1-Pad2_ Net-_Q22-Pad1_ Net-_Q19-Pad1_ eSim_PNP +Q37 Net-_Q22-Pad1_ Net-_Q22-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q39 Net-_Q1-Pad2_ Net-_Q39-Pad2_ Net-_Q39-Pad3_ eSim_NPN +R5 Net-_Q39-Pad3_ Net-_J1-Pad2_ 0.7k +Q41 Net-_C1-Pad1_ Net-_Q30-Pad3_ Net-_J1-Pad2_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 8p +Q50 Net-_Q49-Pad3_ Net-_Q50-Pad2_ Net-_Q50-Pad3_ eSim_NPN +Q51 Net-_Q50-Pad3_ Net-_Q22-Pad1_ Net-_J1-Pad2_ eSim_NPN +R9 Net-_Q49-Pad3_ Net-_Q50-Pad2_ 31k +R10 Net-_Q50-Pad2_ Net-_Q50-Pad3_ 37k +Q57 Net-_J1-Pad1_ Net-_Q47-Pad3_ Net-_Q57-Pad3_ eSim_NPN +R13 Net-_Q57-Pad3_ Net-_Q58-Pad3_ 25 +Q58 Net-_J1-Pad2_ Net-_Q55-Pad3_ Net-_Q58-Pad3_ eSim_PNP +Q55 Net-_J1-Pad2_ Net-_Q50-Pad3_ Net-_Q55-Pad3_ eSim_PNP +Q61 Net-_C1-Pad1_ Net-_Q57-Pad3_ Net-_Q58-Pad3_ eSim_NPN +Q63 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q39-Pad2_ eSim_NPN +Q67 Net-_J1-Pad1_ Net-_J1-Pad3_ Net-_Q64-Pad2_ eSim_NPN +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +Q64 Net-_Q39-Pad2_ Net-_Q64-Pad2_ Net-_J1-Pad2_ eSim_NPN +R15 Net-_Q64-Pad2_ Net-_J1-Pad2_ 8.2k +Q89 Net-_Q103-Pad3_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q93 Net-_Q101-Pad2_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q111 Net-_Q107-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q113 Net-_C3-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q115 Net-_J1-Pad1_ Net-_C3-Pad1_ Net-_Q115-Pad3_ eSim_NPN +Q117 Net-_J1-Pad1_ Net-_Q115-Pad3_ Net-_Q117-Pad3_ eSim_NPN +Q81 Net-_Q81-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q75 Net-_Q75-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q69 Net-_Q69-Pad1_ Net-_Q107-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q71 Net-_J1-Pad2_ Net-_Q71-Pad2_ Net-_Q69-Pad1_ eSim_PNP +Q77 Net-_Q73-Pad3_ Net-_Q73-Pad3_ Net-_Q75-Pad1_ eSim_PNP +Q83 Net-_Q71-Pad2_ Net-_Q73-Pad3_ Net-_Q75-Pad1_ eSim_PNP +Q87 Net-_C3-Pad2_ Net-_Q87-Pad2_ Net-_Q75-Pad1_ eSim_PNP +Q91 Net-_Q87-Pad2_ Net-_Q87-Pad2_ Net-_Q75-Pad1_ eSim_PNP +Q73 Net-_J1-Pad2_ Net-_Q73-Pad2_ Net-_Q73-Pad3_ eSim_PNP +Q79 Net-_Q71-Pad2_ Net-_Q71-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q85 Net-_C3-Pad2_ Net-_Q71-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q95 Net-_J1-Pad2_ Net-_Q95-Pad2_ Net-_Q87-Pad2_ eSim_PNP +Q97 Net-_J1-Pad2_ Net-_C3-Pad2_ Net-_Q81-Pad1_ eSim_PNP +Q99 Net-_Q103-Pad3_ Net-_Q81-Pad1_ Net-_Q101-Pad1_ eSim_NPN +Q101 Net-_Q101-Pad1_ Net-_Q101-Pad2_ Net-_Q101-Pad3_ eSim_NPN +R19 Net-_Q101-Pad3_ Net-_J1-Pad2_ 12k +Q103 Net-_J1-Pad2_ Net-_Q101-Pad2_ Net-_Q103-Pad3_ eSim_PNP +Q105 Net-_Q101-Pad2_ Net-_Q101-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q107 Net-_Q107-Pad1_ Net-_Q107-Pad2_ Net-_Q107-Pad3_ eSim_NPN +R21 Net-_Q107-Pad3_ Net-_J1-Pad2_ 0.7k +Q109 Net-_C3-Pad1_ Net-_Q101-Pad1_ Net-_J1-Pad2_ eSim_NPN +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 8p +Q118 Net-_Q117-Pad3_ Net-_Q118-Pad2_ Net-_Q118-Pad3_ eSim_NPN +Q119 Net-_Q118-Pad3_ Net-_Q101-Pad2_ Net-_J1-Pad2_ eSim_NPN +R25 Net-_Q117-Pad3_ Net-_Q118-Pad2_ 31k +R26 Net-_Q118-Pad2_ Net-_Q118-Pad3_ 37k +Q125 Net-_J1-Pad1_ Net-_Q115-Pad3_ Net-_Q125-Pad3_ eSim_NPN +R29 Net-_Q125-Pad3_ Net-_Q126-Pad3_ 25 +Q126 Net-_J1-Pad2_ Net-_Q123-Pad3_ Net-_Q126-Pad3_ eSim_PNP +Q123 Net-_J1-Pad2_ Net-_Q118-Pad3_ Net-_Q123-Pad3_ eSim_PNP +Q129 Net-_C3-Pad1_ Net-_Q125-Pad3_ Net-_Q126-Pad3_ eSim_NPN +Q131 Net-_J3-Pad3_ Net-_J3-Pad3_ Net-_Q107-Pad2_ eSim_NPN +Q135 Net-_J1-Pad1_ Net-_J3-Pad3_ Net-_Q132-Pad2_ eSim_NPN +J3 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J3-Pad3_ jfet_n +Q132 Net-_Q107-Pad2_ Net-_Q132-Pad2_ Net-_J1-Pad2_ eSim_NPN +R31 Net-_Q132-Pad2_ Net-_J1-Pad2_ 8.2k +Q24 Net-_Q24-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q27 Net-_Q27-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q45 Net-_Q11-Pad2_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q46 Net-_C2-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q48 Net-_J1-Pad1_ Net-_C2-Pad1_ Net-_Q48-Pad3_ eSim_NPN +Q52 Net-_J1-Pad1_ Net-_Q48-Pad3_ Net-_Q52-Pad3_ eSim_NPN +Q15 Net-_Q15-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q5 Net-_Q5-Pad1_ Net-_Q11-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q6 Net-_J1-Pad2_ Net-_Q14-Pad1_ Net-_Q5-Pad1_ eSim_PNP +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_Q11-Pad1_ eSim_PNP +Q17 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_Q11-Pad1_ eSim_PNP +Q23 Net-_C2-Pad2_ Net-_Q23-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q26 Net-_Q23-Pad2_ Net-_Q23-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q9 Net-_J1-Pad2_ Net-_Q9-Pad2_ Net-_Q13-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q20 Net-_C2-Pad2_ Net-_Q14-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q28 Net-_J1-Pad2_ Net-_Q28-Pad2_ Net-_Q23-Pad2_ eSim_PNP +Q31 Net-_J1-Pad2_ Net-_C2-Pad2_ Net-_Q15-Pad1_ eSim_PNP +Q33 Net-_Q24-Pad1_ Net-_Q15-Pad1_ Net-_Q33-Pad3_ eSim_NPN +Q34 Net-_Q33-Pad3_ Net-_Q27-Pad1_ Net-_Q34-Pad3_ eSim_NPN +R4 Net-_Q34-Pad3_ Net-_J1-Pad2_ 12k +Q36 Net-_J1-Pad2_ Net-_Q27-Pad1_ Net-_Q24-Pad1_ eSim_PNP +Q38 Net-_Q27-Pad1_ Net-_Q27-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q40 Net-_Q11-Pad2_ Net-_Q40-Pad2_ Net-_Q40-Pad3_ eSim_NPN +R6 Net-_Q40-Pad3_ Net-_J1-Pad2_ 0.7k +Q44 Net-_C2-Pad1_ Net-_Q33-Pad3_ Net-_J1-Pad2_ eSim_NPN +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 8p +Q53 Net-_Q52-Pad3_ Net-_Q53-Pad2_ Net-_Q53-Pad3_ eSim_NPN +Q54 Net-_Q53-Pad3_ Net-_Q27-Pad1_ Net-_J1-Pad2_ eSim_NPN +R11 Net-_Q52-Pad3_ Net-_Q53-Pad2_ 31k +R12 Net-_Q53-Pad2_ Net-_Q53-Pad3_ 37k +Q59 Net-_J1-Pad1_ Net-_Q48-Pad3_ Net-_Q59-Pad3_ eSim_NPN +R14 Net-_Q59-Pad3_ Net-_Q60-Pad3_ 25 +Q60 Net-_J1-Pad2_ Net-_Q56-Pad3_ Net-_Q60-Pad3_ eSim_PNP +Q56 Net-_J1-Pad2_ Net-_Q53-Pad3_ Net-_Q56-Pad3_ eSim_PNP +Q62 Net-_C2-Pad1_ Net-_Q59-Pad3_ Net-_Q60-Pad3_ eSim_NPN +Q65 Net-_J2-Pad3_ Net-_J2-Pad3_ Net-_Q40-Pad2_ eSim_NPN +Q68 Net-_J1-Pad1_ Net-_J2-Pad3_ Net-_Q66-Pad2_ eSim_NPN +J2 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J2-Pad3_ jfet_n +Q66 Net-_Q40-Pad2_ Net-_Q66-Pad2_ Net-_J1-Pad2_ eSim_NPN +R16 Net-_Q66-Pad2_ Net-_J1-Pad2_ 8.2k +Q90 Net-_Q100-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q94 Net-_Q102-Pad2_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q112 Net-_Q108-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q114 Net-_C4-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q116 Net-_J1-Pad1_ Net-_C4-Pad1_ Net-_Q116-Pad3_ eSim_NPN +Q120 Net-_J1-Pad1_ Net-_Q116-Pad3_ Net-_Q120-Pad3_ eSim_NPN +Q82 Net-_Q100-Pad2_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q76 Net-_Q76-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q70 Net-_Q70-Pad1_ Net-_Q108-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q72 Net-_J1-Pad2_ Net-_Q72-Pad2_ Net-_Q70-Pad1_ eSim_PNP +Q78 Net-_Q74-Pad3_ Net-_Q74-Pad3_ Net-_Q76-Pad1_ eSim_PNP +Q84 Net-_Q72-Pad2_ Net-_Q74-Pad3_ Net-_Q76-Pad1_ eSim_PNP +Q88 Net-_C4-Pad2_ Net-_Q88-Pad2_ Net-_Q76-Pad1_ eSim_PNP +Q92 Net-_Q88-Pad2_ Net-_Q88-Pad2_ Net-_Q76-Pad1_ eSim_PNP +Q74 Net-_J1-Pad2_ Net-_Q74-Pad2_ Net-_Q74-Pad3_ eSim_PNP +Q80 Net-_Q72-Pad2_ Net-_Q72-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q86 Net-_C4-Pad2_ Net-_Q72-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q96 Net-_J1-Pad2_ Net-_Q96-Pad2_ Net-_Q88-Pad2_ eSim_PNP +Q98 Net-_J1-Pad2_ Net-_C4-Pad2_ Net-_Q100-Pad2_ eSim_PNP +Q100 Net-_Q100-Pad1_ Net-_Q100-Pad2_ Net-_Q100-Pad3_ eSim_NPN +Q102 Net-_Q100-Pad3_ Net-_Q102-Pad2_ Net-_Q102-Pad3_ eSim_NPN +R20 Net-_Q102-Pad3_ Net-_J1-Pad2_ 12k +Q104 Net-_J1-Pad2_ Net-_Q102-Pad2_ Net-_Q100-Pad1_ eSim_PNP +Q106 Net-_Q102-Pad2_ Net-_Q102-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q108 Net-_Q108-Pad1_ Net-_Q108-Pad2_ Net-_Q108-Pad3_ eSim_NPN +R22 Net-_Q108-Pad3_ Net-_J1-Pad2_ 0.7k +Q110 Net-_C4-Pad1_ Net-_Q100-Pad3_ Net-_J1-Pad2_ eSim_NPN +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 8p +Q121 Net-_Q120-Pad3_ Net-_Q121-Pad2_ Net-_Q121-Pad3_ eSim_NPN +Q122 Net-_Q121-Pad3_ Net-_Q102-Pad2_ Net-_J1-Pad2_ eSim_NPN +R27 Net-_Q120-Pad3_ Net-_Q121-Pad2_ 31k +R28 Net-_Q121-Pad2_ Net-_Q121-Pad3_ 37k +Q127 Net-_J1-Pad1_ Net-_Q116-Pad3_ Net-_Q127-Pad3_ eSim_NPN +R30 Net-_Q127-Pad3_ Net-_Q128-Pad3_ 25 +Q128 Net-_J1-Pad2_ Net-_Q124-Pad3_ Net-_Q128-Pad3_ eSim_PNP +Q124 Net-_J1-Pad2_ Net-_Q121-Pad3_ Net-_Q124-Pad3_ eSim_PNP +Q130 Net-_C4-Pad1_ Net-_Q127-Pad3_ Net-_Q128-Pad3_ eSim_NPN +Q133 Net-_J4-Pad3_ Net-_J4-Pad3_ Net-_Q108-Pad2_ eSim_NPN +Q136 Net-_J1-Pad1_ Net-_J4-Pad3_ Net-_Q134-Pad2_ eSim_NPN +J4 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J4-Pad3_ jfet_n +Q134 Net-_Q108-Pad2_ Net-_Q134-Pad2_ Net-_J1-Pad2_ eSim_NPN +R32 Net-_Q134-Pad2_ Net-_J1-Pad2_ 8.2k +U1 Net-_Q58-Pad3_ Net-_Q3-Pad2_ Net-_Q25-Pad2_ Net-_J1-Pad1_ Net-_Q28-Pad2_ Net-_Q9-Pad2_ Net-_Q60-Pad3_ Net-_Q126-Pad3_ Net-_Q73-Pad2_ Net-_Q95-Pad2_ Net-_J1-Pad2_ Net-_Q96-Pad2_ Net-_Q74-Pad2_ Net-_Q128-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out new file mode 100644 index 00000000..36e3635e --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.cir.out @@ -0,0 +1,183 @@ +* d:\fossee\esim\library\subcircuitlibrary\mc3403_ic\mc3403_ic.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +q19 net-_q19-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q22 net-_q22-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q42 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q43 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q47 net-_j1-pad1_ net-_c1-pad1_ net-_q47-pad3_ Q2N2222 +q49 net-_j1-pad1_ net-_q47-pad3_ net-_q49-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q12-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q12-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q18 net-_c1-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q21 net-_q18-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q12-pad2_ Q2N2907A +q8 net-_q12-pad1_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q16 net-_c1-pad2_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q25 net-_j1-pad2_ net-_q25-pad2_ net-_q18-pad2_ Q2N2907A +q29 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q30 net-_q19-pad1_ net-_q10-pad1_ net-_q30-pad3_ Q2N2222 +q32 net-_q30-pad3_ net-_q22-pad1_ net-_q32-pad3_ Q2N2222 +r3 net-_q32-pad3_ net-_j1-pad2_ 12k +q35 net-_j1-pad2_ net-_q22-pad1_ net-_q19-pad1_ Q2N2907A +q37 net-_q22-pad1_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +q39 net-_q1-pad2_ net-_q39-pad2_ net-_q39-pad3_ Q2N2222 +r5 net-_q39-pad3_ net-_j1-pad2_ 0.7k +q41 net-_c1-pad1_ net-_q30-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 8p +q50 net-_q49-pad3_ net-_q50-pad2_ net-_q50-pad3_ Q2N2222 +q51 net-_q50-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r9 net-_q49-pad3_ net-_q50-pad2_ 31k +r10 net-_q50-pad2_ net-_q50-pad3_ 37k +q57 net-_j1-pad1_ net-_q47-pad3_ net-_q57-pad3_ Q2N2222 +r13 net-_q57-pad3_ net-_q58-pad3_ 25 +q58 net-_j1-pad2_ net-_q55-pad3_ net-_q58-pad3_ Q2N2907A +q55 net-_j1-pad2_ net-_q50-pad3_ net-_q55-pad3_ Q2N2907A +q61 net-_c1-pad1_ net-_q57-pad3_ net-_q58-pad3_ Q2N2222 +q63 net-_j1-pad3_ net-_j1-pad3_ net-_q39-pad2_ Q2N2222 +q67 net-_j1-pad1_ net-_j1-pad3_ net-_q64-pad2_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q64 net-_q39-pad2_ net-_q64-pad2_ net-_j1-pad2_ Q2N2222 +r15 net-_q64-pad2_ net-_j1-pad2_ 8.2k +q89 net-_q103-pad3_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q93 net-_q101-pad2_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q111 net-_q107-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q113 net-_c3-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q115 net-_j1-pad1_ net-_c3-pad1_ net-_q115-pad3_ Q2N2222 +q117 net-_j1-pad1_ net-_q115-pad3_ net-_q117-pad3_ Q2N2222 +q81 net-_q81-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q75 net-_q75-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q69 net-_q69-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q71 net-_j1-pad2_ net-_q71-pad2_ net-_q69-pad1_ Q2N2907A +q77 net-_q73-pad3_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q83 net-_q71-pad2_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q87 net-_c3-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q91 net-_q87-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q73 net-_j1-pad2_ net-_q73-pad2_ net-_q73-pad3_ Q2N2907A +q79 net-_q71-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q85 net-_c3-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q95 net-_j1-pad2_ net-_q95-pad2_ net-_q87-pad2_ Q2N2907A +q97 net-_j1-pad2_ net-_c3-pad2_ net-_q81-pad1_ Q2N2907A +q99 net-_q103-pad3_ net-_q81-pad1_ net-_q101-pad1_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad2_ net-_q101-pad3_ Q2N2222 +r19 net-_q101-pad3_ net-_j1-pad2_ 12k +q103 net-_j1-pad2_ net-_q101-pad2_ net-_q103-pad3_ Q2N2907A +q105 net-_q101-pad2_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +q107 net-_q107-pad1_ net-_q107-pad2_ net-_q107-pad3_ Q2N2222 +r21 net-_q107-pad3_ net-_j1-pad2_ 0.7k +q109 net-_c3-pad1_ net-_q101-pad1_ net-_j1-pad2_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 8p +q118 net-_q117-pad3_ net-_q118-pad2_ net-_q118-pad3_ Q2N2222 +q119 net-_q118-pad3_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +r25 net-_q117-pad3_ net-_q118-pad2_ 31k +r26 net-_q118-pad2_ net-_q118-pad3_ 37k +q125 net-_j1-pad1_ net-_q115-pad3_ net-_q125-pad3_ Q2N2222 +r29 net-_q125-pad3_ net-_q126-pad3_ 25 +q126 net-_j1-pad2_ net-_q123-pad3_ net-_q126-pad3_ Q2N2907A +q123 net-_j1-pad2_ net-_q118-pad3_ net-_q123-pad3_ Q2N2907A +q129 net-_c3-pad1_ net-_q125-pad3_ net-_q126-pad3_ Q2N2222 +q131 net-_j3-pad3_ net-_j3-pad3_ net-_q107-pad2_ Q2N2222 +q135 net-_j1-pad1_ net-_j3-pad3_ net-_q132-pad2_ Q2N2222 +j3 net-_j1-pad1_ net-_j1-pad2_ net-_j3-pad3_ J2N3819 +q132 net-_q107-pad2_ net-_q132-pad2_ net-_j1-pad2_ Q2N2222 +r31 net-_q132-pad2_ net-_j1-pad2_ 8.2k +q24 net-_q24-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q27 net-_q27-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q45 net-_q11-pad2_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q46 net-_c2-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q48 net-_j1-pad1_ net-_c2-pad1_ net-_q48-pad3_ Q2N2222 +q52 net-_j1-pad1_ net-_q48-pad3_ net-_q52-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_j1-pad2_ net-_q14-pad1_ net-_q5-pad1_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q17 net-_q14-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q23 net-_c2-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q26 net-_q23-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q9 net-_j1-pad2_ net-_q9-pad2_ net-_q13-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q20 net-_c2-pad2_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_j1-pad2_ net-_q28-pad2_ net-_q23-pad2_ Q2N2907A +q31 net-_j1-pad2_ net-_c2-pad2_ net-_q15-pad1_ Q2N2907A +q33 net-_q24-pad1_ net-_q15-pad1_ net-_q33-pad3_ Q2N2222 +q34 net-_q33-pad3_ net-_q27-pad1_ net-_q34-pad3_ Q2N2222 +r4 net-_q34-pad3_ net-_j1-pad2_ 12k +q36 net-_j1-pad2_ net-_q27-pad1_ net-_q24-pad1_ Q2N2907A +q38 net-_q27-pad1_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +q40 net-_q11-pad2_ net-_q40-pad2_ net-_q40-pad3_ Q2N2222 +r6 net-_q40-pad3_ net-_j1-pad2_ 0.7k +q44 net-_c2-pad1_ net-_q33-pad3_ net-_j1-pad2_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 8p +q53 net-_q52-pad3_ net-_q53-pad2_ net-_q53-pad3_ Q2N2222 +q54 net-_q53-pad3_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +r11 net-_q52-pad3_ net-_q53-pad2_ 31k +r12 net-_q53-pad2_ net-_q53-pad3_ 37k +q59 net-_j1-pad1_ net-_q48-pad3_ net-_q59-pad3_ Q2N2222 +r14 net-_q59-pad3_ net-_q60-pad3_ 25 +q60 net-_j1-pad2_ net-_q56-pad3_ net-_q60-pad3_ Q2N2907A +q56 net-_j1-pad2_ net-_q53-pad3_ net-_q56-pad3_ Q2N2907A +q62 net-_c2-pad1_ net-_q59-pad3_ net-_q60-pad3_ Q2N2222 +q65 net-_j2-pad3_ net-_j2-pad3_ net-_q40-pad2_ Q2N2222 +q68 net-_j1-pad1_ net-_j2-pad3_ net-_q66-pad2_ Q2N2222 +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j2-pad3_ J2N3819 +q66 net-_q40-pad2_ net-_q66-pad2_ net-_j1-pad2_ Q2N2222 +r16 net-_q66-pad2_ net-_j1-pad2_ 8.2k +q90 net-_q100-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q94 net-_q102-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q112 net-_q108-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q114 net-_c4-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q116 net-_j1-pad1_ net-_c4-pad1_ net-_q116-pad3_ Q2N2222 +q120 net-_j1-pad1_ net-_q116-pad3_ net-_q120-pad3_ Q2N2222 +q82 net-_q100-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q76 net-_q76-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q70 net-_q70-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q72 net-_j1-pad2_ net-_q72-pad2_ net-_q70-pad1_ Q2N2907A +q78 net-_q74-pad3_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q84 net-_q72-pad2_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q88 net-_c4-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q92 net-_q88-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q74 net-_j1-pad2_ net-_q74-pad2_ net-_q74-pad3_ Q2N2907A +q80 net-_q72-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q86 net-_c4-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q96 net-_j1-pad2_ net-_q96-pad2_ net-_q88-pad2_ Q2N2907A +q98 net-_j1-pad2_ net-_c4-pad2_ net-_q100-pad2_ Q2N2907A +q100 net-_q100-pad1_ net-_q100-pad2_ net-_q100-pad3_ Q2N2222 +q102 net-_q100-pad3_ net-_q102-pad2_ net-_q102-pad3_ Q2N2222 +r20 net-_q102-pad3_ net-_j1-pad2_ 12k +q104 net-_j1-pad2_ net-_q102-pad2_ net-_q100-pad1_ Q2N2907A +q106 net-_q102-pad2_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +q108 net-_q108-pad1_ net-_q108-pad2_ net-_q108-pad3_ Q2N2222 +r22 net-_q108-pad3_ net-_j1-pad2_ 0.7k +q110 net-_c4-pad1_ net-_q100-pad3_ net-_j1-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 8p +q121 net-_q120-pad3_ net-_q121-pad2_ net-_q121-pad3_ Q2N2222 +q122 net-_q121-pad3_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +r27 net-_q120-pad3_ net-_q121-pad2_ 31k +r28 net-_q121-pad2_ net-_q121-pad3_ 37k +q127 net-_j1-pad1_ net-_q116-pad3_ net-_q127-pad3_ Q2N2222 +r30 net-_q127-pad3_ net-_q128-pad3_ 25 +q128 net-_j1-pad2_ net-_q124-pad3_ net-_q128-pad3_ Q2N2907A +q124 net-_j1-pad2_ net-_q121-pad3_ net-_q124-pad3_ Q2N2907A +q130 net-_c4-pad1_ net-_q127-pad3_ net-_q128-pad3_ Q2N2222 +q133 net-_j4-pad3_ net-_j4-pad3_ net-_q108-pad2_ Q2N2222 +q136 net-_j1-pad1_ net-_j4-pad3_ net-_q134-pad2_ Q2N2222 +j4 net-_j1-pad1_ net-_j1-pad2_ net-_j4-pad3_ J2N3819 +q134 net-_q108-pad2_ net-_q134-pad2_ net-_j1-pad2_ Q2N2222 +r32 net-_q134-pad2_ net-_j1-pad2_ 8.2k +* u1 net-_q58-pad3_ net-_q3-pad2_ net-_q25-pad2_ net-_j1-pad1_ net-_q28-pad2_ net-_q9-pad2_ net-_q60-pad3_ net-_q126-pad3_ net-_q73-pad2_ net-_q95-pad2_ net-_j1-pad2_ net-_q96-pad2_ net-_q74-pad2_ net-_q128-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch new file mode 100644 index 00000000..f2268e6b --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sch @@ -0,0 +1,3447 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC3403_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 47244 39370 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q19 +U 1 1 66882D3A +P 4750 5450 +F 0 "Q19" H 4650 5500 50 0000 R CNN +F 1 "eSim_PNP" H 4700 5600 50 0000 R CNN +F 2 "" H 4950 5550 29 0000 C CNN +F 3 "" H 4750 5450 60 0000 C CNN + 1 4750 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q22 +U 1 1 66882D3B +P 5200 5450 +F 0 "Q22" H 5100 5500 50 0000 R CNN +F 1 "eSim_PNP" H 5150 5600 50 0000 R CNN +F 2 "" H 5400 5550 29 0000 C CNN +F 3 "" H 5200 5450 60 0000 C CNN + 1 5200 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q42 +U 1 1 66882D3C +P 11850 5450 +F 0 "Q42" H 11750 5500 50 0000 R CNN +F 1 "eSim_PNP" H 11800 5600 50 0000 R CNN +F 2 "" H 12050 5550 29 0000 C CNN +F 3 "" H 11850 5450 60 0000 C CNN + 1 11850 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q43 +U 1 1 66882D3D +P 12250 5450 +F 0 "Q43" H 12150 5500 50 0000 R CNN +F 1 "eSim_PNP" H 12200 5600 50 0000 R CNN +F 2 "" H 12450 5550 29 0000 C CNN +F 3 "" H 12250 5450 60 0000 C CNN + 1 12250 5450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q47 +U 1 1 66882D3E +P 13600 6150 +F 0 "Q47" H 13500 6200 50 0000 R CNN +F 1 "eSim_NPN" H 13550 6300 50 0000 R CNN +F 2 "" H 13800 6250 29 0000 C CNN +F 3 "" H 13600 6150 60 0000 C CNN + 1 13600 6150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q49 +U 1 1 66882D3F +P 14150 6450 +F 0 "Q49" H 14050 6500 50 0000 R CNN +F 1 "eSim_NPN" H 14100 6600 50 0000 R CNN +F 2 "" H 14350 6550 29 0000 C CNN +F 3 "" H 14150 6450 60 0000 C CNN + 1 14150 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 66882D40 +P 3850 7000 +F 0 "Q10" H 3750 7050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 7150 50 0000 R CNN +F 2 "" H 4050 7100 29 0000 C CNN +F 3 "" H 3850 7000 60 0000 C CNN + 1 3850 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 66882D41 +P 3400 7000 +F 0 "Q4" H 3300 7050 50 0000 R CNN +F 1 "eSim_PNP" H 3350 7150 50 0000 R CNN +F 2 "" H 3600 7100 29 0000 C CNN +F 3 "" H 3400 7000 60 0000 C CNN + 1 3400 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66882D42 +P 2900 7000 +F 0 "Q1" H 2800 7050 50 0000 R CNN +F 1 "eSim_PNP" H 2850 7150 50 0000 R CNN +F 2 "" H 3100 7100 29 0000 C CNN +F 3 "" H 2900 7000 60 0000 C CNN + 1 2900 7000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 66882D43 +P 3050 11750 +F 0 "Q2" H 2950 11800 50 0000 R CNN +F 1 "eSim_PNP" H 3000 11900 50 0000 R CNN +F 2 "" H 3250 11850 29 0000 C CNN +F 3 "" H 3050 11750 60 0000 C CNN + 1 3050 11750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 66882D44 +P 3650 9050 +F 0 "Q7" H 3550 9100 50 0000 R CNN +F 1 "eSim_PNP" H 3600 9200 50 0000 R CNN +F 2 "" H 3850 9150 29 0000 C CNN +F 3 "" H 3650 9050 60 0000 C CNN + 1 3650 9050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 66882D45 +P 4050 9050 +F 0 "Q12" H 3950 9100 50 0000 R CNN +F 1 "eSim_PNP" H 4000 9200 50 0000 R CNN +F 2 "" H 4250 9150 29 0000 C CNN +F 3 "" H 4050 9050 60 0000 C CNN + 1 4050 9050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q18 +U 1 1 66882D46 +P 4700 9050 +F 0 "Q18" H 4600 9100 50 0000 R CNN +F 1 "eSim_PNP" H 4650 9200 50 0000 R CNN +F 2 "" H 4900 9150 29 0000 C CNN +F 3 "" H 4700 9050 60 0000 C CNN + 1 4700 9050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 66882D47 +P 5150 9050 +F 0 "Q21" H 5050 9100 50 0000 R CNN +F 1 "eSim_PNP" H 5100 9200 50 0000 R CNN +F 2 "" H 5350 9150 29 0000 C CNN +F 3 "" H 5150 9050 60 0000 C CNN + 1 5150 9050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 66882D48 +P 3250 10350 +F 0 "Q3" H 3150 10400 50 0000 R CNN +F 1 "eSim_PNP" H 3200 10500 50 0000 R CNN +F 2 "" H 3450 10450 29 0000 C CNN +F 3 "" H 3250 10350 60 0000 C CNN + 1 3250 10350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66882D49 +P 3700 12100 +F 0 "Q8" H 3600 12150 50 0000 R CNN +F 1 "eSim_NPN" H 3650 12250 50 0000 R CNN +F 2 "" H 3900 12200 29 0000 C CNN +F 3 "" H 3700 12100 60 0000 C CNN + 1 3700 12100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66882D4A +P 4400 12100 +F 0 "Q16" H 4300 12150 50 0000 R CNN +F 1 "eSim_NPN" H 4350 12250 50 0000 R CNN +F 2 "" H 4600 12200 29 0000 C CNN +F 3 "" H 4400 12100 60 0000 C CNN + 1 4400 12100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q25 +U 1 1 66882D4B +P 5600 10400 +F 0 "Q25" H 5500 10450 50 0000 R CNN +F 1 "eSim_PNP" H 5550 10550 50 0000 R CNN +F 2 "" H 5800 10500 29 0000 C CNN +F 3 "" H 5600 10400 60 0000 C CNN + 1 5600 10400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 66882D4C +P 6550 11900 +F 0 "Q29" H 6450 11950 50 0000 R CNN +F 1 "eSim_PNP" H 6500 12050 50 0000 R CNN +F 2 "" H 6750 12000 29 0000 C CNN +F 3 "" H 6550 11900 60 0000 C CNN + 1 6550 11900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q30 +U 1 1 66882D4D +P 7050 10400 +F 0 "Q30" H 6950 10450 50 0000 R CNN +F 1 "eSim_NPN" H 7000 10550 50 0000 R CNN +F 2 "" H 7250 10500 29 0000 C CNN +F 3 "" H 7050 10400 60 0000 C CNN + 1 7050 10400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q32 +U 1 1 66882D4E +P 7250 11200 +F 0 "Q32" H 7150 11250 50 0000 R CNN +F 1 "eSim_NPN" H 7200 11350 50 0000 R CNN +F 2 "" H 7450 11300 29 0000 C CNN +F 3 "" H 7250 11200 60 0000 C CNN + 1 7250 11200 + -1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 66882D4F +P 7100 11850 +F 0 "R3" H 7150 11980 50 0000 C CNN +F 1 "12k" H 7150 11800 50 0000 C CNN +F 2 "" H 7150 11830 30 0000 C CNN +F 3 "" V 7150 11900 30 0000 C CNN + 1 7100 11850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q35 +U 1 1 66882D50 +P 8150 10400 +F 0 "Q35" H 8050 10450 50 0000 R CNN +F 1 "eSim_PNP" H 8100 10550 50 0000 R CNN +F 2 "" H 8350 10500 29 0000 C CNN +F 3 "" H 8150 10400 60 0000 C CNN + 1 8150 10400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q37 +U 1 1 66882D51 +P 9250 11200 +F 0 "Q37" H 9150 11250 50 0000 R CNN +F 1 "eSim_NPN" H 9200 11350 50 0000 R CNN +F 2 "" H 9450 11300 29 0000 C CNN +F 3 "" H 9250 11200 60 0000 C CNN + 1 9250 11200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q39 +U 1 1 66882D52 +P 10350 7700 +F 0 "Q39" H 10250 7750 50 0000 R CNN +F 1 "eSim_NPN" H 10300 7850 50 0000 R CNN +F 2 "" H 10550 7800 29 0000 C CNN +F 3 "" H 10350 7700 60 0000 C CNN + 1 10350 7700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 66882D53 +P 10200 8200 +F 0 "R5" H 10250 8330 50 0000 C CNN +F 1 "0.7k" H 10250 8150 50 0000 C CNN +F 2 "" H 10250 8180 30 0000 C CNN +F 3 "" V 10250 8250 30 0000 C CNN + 1 10200 8200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q41 +U 1 1 66882D54 +P 11800 9500 +F 0 "Q41" H 11700 9550 50 0000 R CNN +F 1 "eSim_NPN" H 11750 9650 50 0000 R CNN +F 2 "" H 12000 9600 29 0000 C CNN +F 3 "" H 11800 9500 60 0000 C CNN + 1 11800 9500 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 66882D55 +P 6250 7900 +F 0 "C1" H 6275 8000 50 0000 L CNN +F 1 "8p" H 6275 7800 50 0000 L CNN +F 2 "" H 6288 7750 30 0000 C CNN +F 3 "" H 6250 7900 60 0000 C CNN + 1 6250 7900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q50 +U 1 1 66882D56 +P 14150 9100 +F 0 "Q50" H 14050 9150 50 0000 R CNN +F 1 "eSim_NPN" H 14100 9250 50 0000 R CNN +F 2 "" H 14350 9200 29 0000 C CNN +F 3 "" H 14150 9100 60 0000 C CNN + 1 14150 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q51 +U 1 1 66882D57 +P 14150 11400 +F 0 "Q51" H 14050 11450 50 0000 R CNN +F 1 "eSim_NPN" H 14100 11550 50 0000 R CNN +F 2 "" H 14350 11500 29 0000 C CNN +F 3 "" H 14150 11400 60 0000 C CNN + 1 14150 11400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 66882D58 +P 13450 7100 +F 0 "R9" H 13500 7230 50 0000 C CNN +F 1 "31k" H 13500 7050 50 0000 C CNN +F 2 "" H 13500 7080 30 0000 C CNN +F 3 "" V 13500 7150 30 0000 C CNN + 1 13450 7100 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 66882D59 +P 13450 9650 +F 0 "R10" H 13500 9780 50 0000 C CNN +F 1 "37k" H 13500 9600 50 0000 C CNN +F 2 "" H 13500 9630 30 0000 C CNN +F 3 "" V 13500 9700 30 0000 C CNN + 1 13450 9650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q57 +U 1 1 66882D5A +P 15850 6450 +F 0 "Q57" H 15750 6500 50 0000 R CNN +F 1 "eSim_NPN" H 15800 6600 50 0000 R CNN +F 2 "" H 16050 6550 29 0000 C CNN +F 3 "" H 15850 6450 60 0000 C CNN + 1 15850 6450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66882D5B +P 15900 8200 +F 0 "R13" H 15950 8330 50 0000 C CNN +F 1 "25" H 15950 8150 50 0000 C CNN +F 2 "" H 15950 8180 30 0000 C CNN +F 3 "" V 15950 8250 30 0000 C CNN + 1 15900 8200 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q58 +U 1 1 66882D5C +P 15850 9200 +F 0 "Q58" H 15750 9250 50 0000 R CNN +F 1 "eSim_PNP" H 15800 9350 50 0000 R CNN +F 2 "" H 16050 9300 29 0000 C CNN +F 3 "" H 15850 9200 60 0000 C CNN + 1 15850 9200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q55 +U 1 1 66882D5D +P 15300 10150 +F 0 "Q55" H 15200 10200 50 0000 R CNN +F 1 "eSim_PNP" H 15250 10300 50 0000 R CNN +F 2 "" H 15500 10250 29 0000 C CNN +F 3 "" H 15300 10150 60 0000 C CNN + 1 15300 10150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q61 +U 1 1 66882D5E +P 16650 7800 +F 0 "Q61" H 16550 7850 50 0000 R CNN +F 1 "eSim_NPN" H 16600 7950 50 0000 R CNN +F 2 "" H 16850 7900 29 0000 C CNN +F 3 "" H 16650 7800 60 0000 C CNN + 1 16650 7800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q63 +U 1 1 66882D60 +P 18300 6400 +F 0 "Q63" H 18200 6450 50 0000 R CNN +F 1 "eSim_NPN" H 18250 6550 50 0000 R CNN +F 2 "" H 18500 6500 29 0000 C CNN +F 3 "" H 18300 6400 60 0000 C CNN + 1 18300 6400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q67 +U 1 1 66882D61 +P 19400 6400 +F 0 "Q67" H 19300 6450 50 0000 R CNN +F 1 "eSim_NPN" H 19350 6550 50 0000 R CNN +F 2 "" H 19600 6500 29 0000 C CNN +F 3 "" H 19400 6400 60 0000 C CNN + 1 19400 6400 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J1 +U 1 1 66882D62 +P 18300 5400 +F 0 "J1" H 18200 5450 50 0000 R CNN +F 1 "jfet_n" H 18250 5550 50 0000 R CNN +F 2 "" H 18500 5500 29 0000 C CNN +F 3 "" H 18300 5400 60 0000 C CNN + 1 18300 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q64 +U 1 1 66882D63 +P 18300 10300 +F 0 "Q64" H 18200 10350 50 0000 R CNN +F 1 "eSim_NPN" H 18250 10450 50 0000 R CNN +F 2 "" H 18500 10400 29 0000 C CNN +F 3 "" H 18300 10300 60 0000 C CNN + 1 18300 10300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 66882D64 +P 19450 10900 +F 0 "R15" H 19500 11030 50 0000 C CNN +F 1 "8.2k" H 19500 10850 50 0000 C CNN +F 2 "" H 19500 10880 30 0000 C CNN +F 3 "" V 19500 10950 30 0000 C CNN + 1 19450 10900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q89 +U 1 1 66883B02 +P 26900 5850 +F 0 "Q89" H 26800 5900 50 0000 R CNN +F 1 "eSim_PNP" H 26850 6000 50 0000 R CNN +F 2 "" H 27100 5950 29 0000 C CNN +F 3 "" H 26900 5850 60 0000 C CNN + 1 26900 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q93 +U 1 1 66883B08 +P 27350 5850 +F 0 "Q93" H 27250 5900 50 0000 R CNN +F 1 "eSim_PNP" H 27300 6000 50 0000 R CNN +F 2 "" H 27550 5950 29 0000 C CNN +F 3 "" H 27350 5850 60 0000 C CNN + 1 27350 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q111 +U 1 1 66883B0E +P 34000 5850 +F 0 "Q111" H 33900 5900 50 0000 R CNN +F 1 "eSim_PNP" H 33950 6000 50 0000 R CNN +F 2 "" H 34200 5950 29 0000 C CNN +F 3 "" H 34000 5850 60 0000 C CNN + 1 34000 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q113 +U 1 1 66883B14 +P 34400 5850 +F 0 "Q113" H 34300 5900 50 0000 R CNN +F 1 "eSim_PNP" H 34350 6000 50 0000 R CNN +F 2 "" H 34600 5950 29 0000 C CNN +F 3 "" H 34400 5850 60 0000 C CNN + 1 34400 5850 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q115 +U 1 1 66883B1A +P 35750 6550 +F 0 "Q115" H 35650 6600 50 0000 R CNN +F 1 "eSim_NPN" H 35700 6700 50 0000 R CNN +F 2 "" H 35950 6650 29 0000 C CNN +F 3 "" H 35750 6550 60 0000 C CNN + 1 35750 6550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q117 +U 1 1 66883B20 +P 36300 6850 +F 0 "Q117" H 36200 6900 50 0000 R CNN +F 1 "eSim_NPN" H 36250 7000 50 0000 R CNN +F 2 "" H 36500 6950 29 0000 C CNN +F 3 "" H 36300 6850 60 0000 C CNN + 1 36300 6850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q81 +U 1 1 66883B26 +P 26000 7400 +F 0 "Q81" H 25900 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25950 7550 50 0000 R CNN +F 2 "" H 26200 7500 29 0000 C CNN +F 3 "" H 26000 7400 60 0000 C CNN + 1 26000 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q75 +U 1 1 66883B2C +P 25550 7400 +F 0 "Q75" H 25450 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25500 7550 50 0000 R CNN +F 2 "" H 25750 7500 29 0000 C CNN +F 3 "" H 25550 7400 60 0000 C CNN + 1 25550 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q69 +U 1 1 66883B32 +P 25050 7400 +F 0 "Q69" H 24950 7450 50 0000 R CNN +F 1 "eSim_PNP" H 25000 7550 50 0000 R CNN +F 2 "" H 25250 7500 29 0000 C CNN +F 3 "" H 25050 7400 60 0000 C CNN + 1 25050 7400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q71 +U 1 1 66883B38 +P 25200 12150 +F 0 "Q71" H 25100 12200 50 0000 R CNN +F 1 "eSim_PNP" H 25150 12300 50 0000 R CNN +F 2 "" H 25400 12250 29 0000 C CNN +F 3 "" H 25200 12150 60 0000 C CNN + 1 25200 12150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q77 +U 1 1 66883B3E +P 25800 9450 +F 0 "Q77" H 25700 9500 50 0000 R CNN +F 1 "eSim_PNP" H 25750 9600 50 0000 R CNN +F 2 "" H 26000 9550 29 0000 C CNN +F 3 "" H 25800 9450 60 0000 C CNN + 1 25800 9450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q83 +U 1 1 66883B44 +P 26200 9450 +F 0 "Q83" H 26100 9500 50 0000 R CNN +F 1 "eSim_PNP" H 26150 9600 50 0000 R CNN +F 2 "" H 26400 9550 29 0000 C CNN +F 3 "" H 26200 9450 60 0000 C CNN + 1 26200 9450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q87 +U 1 1 66883B4A +P 26850 9450 +F 0 "Q87" H 26750 9500 50 0000 R CNN +F 1 "eSim_PNP" H 26800 9600 50 0000 R CNN +F 2 "" H 27050 9550 29 0000 C CNN +F 3 "" H 26850 9450 60 0000 C CNN + 1 26850 9450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q91 +U 1 1 66883B50 +P 27300 9450 +F 0 "Q91" H 27200 9500 50 0000 R CNN +F 1 "eSim_PNP" H 27250 9600 50 0000 R CNN +F 2 "" H 27500 9550 29 0000 C CNN +F 3 "" H 27300 9450 60 0000 C CNN + 1 27300 9450 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q73 +U 1 1 66883B56 +P 25400 10750 +F 0 "Q73" H 25300 10800 50 0000 R CNN +F 1 "eSim_PNP" H 25350 10900 50 0000 R CNN +F 2 "" H 25600 10850 29 0000 C CNN +F 3 "" H 25400 10750 60 0000 C CNN + 1 25400 10750 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q79 +U 1 1 66883B5C +P 25850 12500 +F 0 "Q79" H 25750 12550 50 0000 R CNN +F 1 "eSim_NPN" H 25800 12650 50 0000 R CNN +F 2 "" H 26050 12600 29 0000 C CNN +F 3 "" H 25850 12500 60 0000 C CNN + 1 25850 12500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q85 +U 1 1 66883B62 +P 26550 12500 +F 0 "Q85" H 26450 12550 50 0000 R CNN +F 1 "eSim_NPN" H 26500 12650 50 0000 R CNN +F 2 "" H 26750 12600 29 0000 C CNN +F 3 "" H 26550 12500 60 0000 C CNN + 1 26550 12500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q95 +U 1 1 66883B68 +P 27750 10800 +F 0 "Q95" H 27650 10850 50 0000 R CNN +F 1 "eSim_PNP" H 27700 10950 50 0000 R CNN +F 2 "" H 27950 10900 29 0000 C CNN +F 3 "" H 27750 10800 60 0000 C CNN + 1 27750 10800 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q97 +U 1 1 66883B6E +P 28700 12300 +F 0 "Q97" H 28600 12350 50 0000 R CNN +F 1 "eSim_PNP" H 28650 12450 50 0000 R CNN +F 2 "" H 28900 12400 29 0000 C CNN +F 3 "" H 28700 12300 60 0000 C CNN + 1 28700 12300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q99 +U 1 1 66883B74 +P 29200 10800 +F 0 "Q99" H 29100 10850 50 0000 R CNN +F 1 "eSim_NPN" H 29150 10950 50 0000 R CNN +F 2 "" H 29400 10900 29 0000 C CNN +F 3 "" H 29200 10800 60 0000 C CNN + 1 29200 10800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q101 +U 1 1 66883B7A +P 29400 11600 +F 0 "Q101" H 29300 11650 50 0000 R CNN +F 1 "eSim_NPN" H 29350 11750 50 0000 R CNN +F 2 "" H 29600 11700 29 0000 C CNN +F 3 "" H 29400 11600 60 0000 C CNN + 1 29400 11600 + -1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 66883B80 +P 29250 12250 +F 0 "R19" H 29300 12380 50 0000 C CNN +F 1 "12k" H 29300 12200 50 0000 C CNN +F 2 "" H 29300 12230 30 0000 C CNN +F 3 "" V 29300 12300 30 0000 C CNN + 1 29250 12250 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q103 +U 1 1 66883B86 +P 30300 10800 +F 0 "Q103" H 30200 10850 50 0000 R CNN +F 1 "eSim_PNP" H 30250 10950 50 0000 R CNN +F 2 "" H 30500 10900 29 0000 C CNN +F 3 "" H 30300 10800 60 0000 C CNN + 1 30300 10800 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q105 +U 1 1 66883B8C +P 31400 11600 +F 0 "Q105" H 31300 11650 50 0000 R CNN +F 1 "eSim_NPN" H 31350 11750 50 0000 R CNN +F 2 "" H 31600 11700 29 0000 C CNN +F 3 "" H 31400 11600 60 0000 C CNN + 1 31400 11600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q107 +U 1 1 66883B92 +P 32500 8100 +F 0 "Q107" H 32400 8150 50 0000 R CNN +F 1 "eSim_NPN" H 32450 8250 50 0000 R CNN +F 2 "" H 32700 8200 29 0000 C CNN +F 3 "" H 32500 8100 60 0000 C CNN + 1 32500 8100 + -1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 66883B98 +P 32350 8600 +F 0 "R21" H 32400 8730 50 0000 C CNN +F 1 "0.7k" H 32400 8550 50 0000 C CNN +F 2 "" H 32400 8580 30 0000 C CNN +F 3 "" V 32400 8650 30 0000 C CNN + 1 32350 8600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q109 +U 1 1 66883B9E +P 33950 9900 +F 0 "Q109" H 33850 9950 50 0000 R CNN +F 1 "eSim_NPN" H 33900 10050 50 0000 R CNN +F 2 "" H 34150 10000 29 0000 C CNN +F 3 "" H 33950 9900 60 0000 C CNN + 1 33950 9900 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C3 +U 1 1 66883BA4 +P 28400 8300 +F 0 "C3" H 28425 8400 50 0000 L CNN +F 1 "8p" H 28425 8200 50 0000 L CNN +F 2 "" H 28438 8150 30 0000 C CNN +F 3 "" H 28400 8300 60 0000 C CNN + 1 28400 8300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q118 +U 1 1 66883BAA +P 36300 9500 +F 0 "Q118" H 36200 9550 50 0000 R CNN +F 1 "eSim_NPN" H 36250 9650 50 0000 R CNN +F 2 "" H 36500 9600 29 0000 C CNN +F 3 "" H 36300 9500 60 0000 C CNN + 1 36300 9500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q119 +U 1 1 66883BB0 +P 36300 11800 +F 0 "Q119" H 36200 11850 50 0000 R CNN +F 1 "eSim_NPN" H 36250 11950 50 0000 R CNN +F 2 "" H 36500 11900 29 0000 C CNN +F 3 "" H 36300 11800 60 0000 C CNN + 1 36300 11800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R25 +U 1 1 66883BB6 +P 35600 7500 +F 0 "R25" H 35650 7630 50 0000 C CNN +F 1 "31k" H 35650 7450 50 0000 C CNN +F 2 "" H 35650 7480 30 0000 C CNN +F 3 "" V 35650 7550 30 0000 C CNN + 1 35600 7500 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 66883BBC +P 35600 10050 +F 0 "R26" H 35650 10180 50 0000 C CNN +F 1 "37k" H 35650 10000 50 0000 C CNN +F 2 "" H 35650 10030 30 0000 C CNN +F 3 "" V 35650 10100 30 0000 C CNN + 1 35600 10050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q125 +U 1 1 66883BC2 +P 38000 6850 +F 0 "Q125" H 37900 6900 50 0000 R CNN +F 1 "eSim_NPN" H 37950 7000 50 0000 R CNN +F 2 "" H 38200 6950 29 0000 C CNN +F 3 "" H 38000 6850 60 0000 C CNN + 1 38000 6850 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 66883BC8 +P 38050 8600 +F 0 "R29" H 38100 8730 50 0000 C CNN +F 1 "25" H 38100 8550 50 0000 C CNN +F 2 "" H 38100 8580 30 0000 C CNN +F 3 "" V 38100 8650 30 0000 C CNN + 1 38050 8600 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q126 +U 1 1 66883BCE +P 38000 9600 +F 0 "Q126" H 37900 9650 50 0000 R CNN +F 1 "eSim_PNP" H 37950 9750 50 0000 R CNN +F 2 "" H 38200 9700 29 0000 C CNN +F 3 "" H 38000 9600 60 0000 C CNN + 1 38000 9600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q123 +U 1 1 66883BD4 +P 37450 10550 +F 0 "Q123" H 37350 10600 50 0000 R CNN +F 1 "eSim_PNP" H 37400 10700 50 0000 R CNN +F 2 "" H 37650 10650 29 0000 C CNN +F 3 "" H 37450 10550 60 0000 C CNN + 1 37450 10550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q129 +U 1 1 66883BDA +P 38800 8200 +F 0 "Q129" H 38700 8250 50 0000 R CNN +F 1 "eSim_NPN" H 38750 8350 50 0000 R CNN +F 2 "" H 39000 8300 29 0000 C CNN +F 3 "" H 38800 8200 60 0000 C CNN + 1 38800 8200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q131 +U 1 1 66883BE6 +P 40450 6800 +F 0 "Q131" H 40350 6850 50 0000 R CNN +F 1 "eSim_NPN" H 40400 6950 50 0000 R CNN +F 2 "" H 40650 6900 29 0000 C CNN +F 3 "" H 40450 6800 60 0000 C CNN + 1 40450 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q135 +U 1 1 66883BEC +P 41550 6800 +F 0 "Q135" H 41450 6850 50 0000 R CNN +F 1 "eSim_NPN" H 41500 6950 50 0000 R CNN +F 2 "" H 41750 6900 29 0000 C CNN +F 3 "" H 41550 6800 60 0000 C CNN + 1 41550 6800 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J3 +U 1 1 66883BF2 +P 40450 5800 +F 0 "J3" H 40350 5850 50 0000 R CNN +F 1 "jfet_n" H 40400 5950 50 0000 R CNN +F 2 "" H 40650 5900 29 0000 C CNN +F 3 "" H 40450 5800 60 0000 C CNN + 1 40450 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q132 +U 1 1 66883BF8 +P 40450 10700 +F 0 "Q132" H 40350 10750 50 0000 R CNN +F 1 "eSim_NPN" H 40400 10850 50 0000 R CNN +F 2 "" H 40650 10800 29 0000 C CNN +F 3 "" H 40450 10700 60 0000 C CNN + 1 40450 10700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R31 +U 1 1 66883BFE +P 41600 11300 +F 0 "R31" H 41650 11430 50 0000 C CNN +F 1 "8.2k" H 41650 11250 50 0000 C CNN +F 2 "" H 41650 11280 30 0000 C CNN +F 3 "" V 41650 11350 30 0000 C CNN + 1 41600 11300 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q24 +U 1 1 66886F38 +P 5250 22400 +F 0 "Q24" H 5150 22450 50 0000 R CNN +F 1 "eSim_PNP" H 5200 22550 50 0000 R CNN +F 2 "" H 5450 22500 29 0000 C CNN +F 3 "" H 5250 22400 60 0000 C CNN + 1 5250 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q27 +U 1 1 66886F3E +P 5700 22400 +F 0 "Q27" H 5600 22450 50 0000 R CNN +F 1 "eSim_PNP" H 5650 22550 50 0000 R CNN +F 2 "" H 5900 22500 29 0000 C CNN +F 3 "" H 5700 22400 60 0000 C CNN + 1 5700 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 66886F44 +P 12350 22400 +F 0 "Q45" H 12250 22450 50 0000 R CNN +F 1 "eSim_PNP" H 12300 22550 50 0000 R CNN +F 2 "" H 12550 22500 29 0000 C CNN +F 3 "" H 12350 22400 60 0000 C CNN + 1 12350 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q46 +U 1 1 66886F4A +P 12750 22400 +F 0 "Q46" H 12650 22450 50 0000 R CNN +F 1 "eSim_PNP" H 12700 22550 50 0000 R CNN +F 2 "" H 12950 22500 29 0000 C CNN +F 3 "" H 12750 22400 60 0000 C CNN + 1 12750 22400 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q48 +U 1 1 66886F50 +P 14100 23100 +F 0 "Q48" H 14000 23150 50 0000 R CNN +F 1 "eSim_NPN" H 14050 23250 50 0000 R CNN +F 2 "" H 14300 23200 29 0000 C CNN +F 3 "" H 14100 23100 60 0000 C CNN + 1 14100 23100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q52 +U 1 1 66886F56 +P 14650 23400 +F 0 "Q52" H 14550 23450 50 0000 R CNN +F 1 "eSim_NPN" H 14600 23550 50 0000 R CNN +F 2 "" H 14850 23500 29 0000 C CNN +F 3 "" H 14650 23400 60 0000 C CNN + 1 14650 23400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 66886F5C +P 4350 23950 +F 0 "Q15" H 4250 24000 50 0000 R CNN +F 1 "eSim_PNP" H 4300 24100 50 0000 R CNN +F 2 "" H 4550 24050 29 0000 C CNN +F 3 "" H 4350 23950 60 0000 C CNN + 1 4350 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 66886F62 +P 3900 23950 +F 0 "Q11" H 3800 24000 50 0000 R CNN +F 1 "eSim_PNP" H 3850 24100 50 0000 R CNN +F 2 "" H 4100 24050 29 0000 C CNN +F 3 "" H 3900 23950 60 0000 C CNN + 1 3900 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 66886F68 +P 3400 23950 +F 0 "Q5" H 3300 24000 50 0000 R CNN +F 1 "eSim_PNP" H 3350 24100 50 0000 R CNN +F 2 "" H 3600 24050 29 0000 C CNN +F 3 "" H 3400 23950 60 0000 C CNN + 1 3400 23950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 66886F6E +P 3550 28700 +F 0 "Q6" H 3450 28750 50 0000 R CNN +F 1 "eSim_PNP" H 3500 28850 50 0000 R CNN +F 2 "" H 3750 28800 29 0000 C CNN +F 3 "" H 3550 28700 60 0000 C CNN + 1 3550 28700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 66886F74 +P 4150 26000 +F 0 "Q13" H 4050 26050 50 0000 R CNN +F 1 "eSim_PNP" H 4100 26150 50 0000 R CNN +F 2 "" H 4350 26100 29 0000 C CNN +F 3 "" H 4150 26000 60 0000 C CNN + 1 4150 26000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 66886F7A +P 4550 26000 +F 0 "Q17" H 4450 26050 50 0000 R CNN +F 1 "eSim_PNP" H 4500 26150 50 0000 R CNN +F 2 "" H 4750 26100 29 0000 C CNN +F 3 "" H 4550 26000 60 0000 C CNN + 1 4550 26000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 66886F80 +P 5200 26000 +F 0 "Q23" H 5100 26050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 26150 50 0000 R CNN +F 2 "" H 5400 26100 29 0000 C CNN +F 3 "" H 5200 26000 60 0000 C CNN + 1 5200 26000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 66886F86 +P 5650 26000 +F 0 "Q26" H 5550 26050 50 0000 R CNN +F 1 "eSim_PNP" H 5600 26150 50 0000 R CNN +F 2 "" H 5850 26100 29 0000 C CNN +F 3 "" H 5650 26000 60 0000 C CNN + 1 5650 26000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 66886F8C +P 3750 27300 +F 0 "Q9" H 3650 27350 50 0000 R CNN +F 1 "eSim_PNP" H 3700 27450 50 0000 R CNN +F 2 "" H 3950 27400 29 0000 C CNN +F 3 "" H 3750 27300 60 0000 C CNN + 1 3750 27300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 66886F92 +P 4200 29050 +F 0 "Q14" H 4100 29100 50 0000 R CNN +F 1 "eSim_NPN" H 4150 29200 50 0000 R CNN +F 2 "" H 4400 29150 29 0000 C CNN +F 3 "" H 4200 29050 60 0000 C CNN + 1 4200 29050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 66886F98 +P 4900 29050 +F 0 "Q20" H 4800 29100 50 0000 R CNN +F 1 "eSim_NPN" H 4850 29200 50 0000 R CNN +F 2 "" H 5100 29150 29 0000 C CNN +F 3 "" H 4900 29050 60 0000 C CNN + 1 4900 29050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 66886F9E +P 6100 27350 +F 0 "Q28" H 6000 27400 50 0000 R CNN +F 1 "eSim_PNP" H 6050 27500 50 0000 R CNN +F 2 "" H 6300 27450 29 0000 C CNN +F 3 "" H 6100 27350 60 0000 C CNN + 1 6100 27350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q31 +U 1 1 66886FA4 +P 7050 28850 +F 0 "Q31" H 6950 28900 50 0000 R CNN +F 1 "eSim_PNP" H 7000 29000 50 0000 R CNN +F 2 "" H 7250 28950 29 0000 C CNN +F 3 "" H 7050 28850 60 0000 C CNN + 1 7050 28850 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q33 +U 1 1 66886FAA +P 7550 27350 +F 0 "Q33" H 7450 27400 50 0000 R CNN +F 1 "eSim_NPN" H 7500 27500 50 0000 R CNN +F 2 "" H 7750 27450 29 0000 C CNN +F 3 "" H 7550 27350 60 0000 C CNN + 1 7550 27350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q34 +U 1 1 66886FB0 +P 7750 28150 +F 0 "Q34" H 7650 28200 50 0000 R CNN +F 1 "eSim_NPN" H 7700 28300 50 0000 R CNN +F 2 "" H 7950 28250 29 0000 C CNN +F 3 "" H 7750 28150 60 0000 C CNN + 1 7750 28150 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 66886FB6 +P 7600 28800 +F 0 "R4" H 7650 28930 50 0000 C CNN +F 1 "12k" H 7650 28750 50 0000 C CNN +F 2 "" H 7650 28780 30 0000 C CNN +F 3 "" V 7650 28850 30 0000 C CNN + 1 7600 28800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q36 +U 1 1 66886FBC +P 8650 27350 +F 0 "Q36" H 8550 27400 50 0000 R CNN +F 1 "eSim_PNP" H 8600 27500 50 0000 R CNN +F 2 "" H 8850 27450 29 0000 C CNN +F 3 "" H 8650 27350 60 0000 C CNN + 1 8650 27350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q38 +U 1 1 66886FC2 +P 9750 28150 +F 0 "Q38" H 9650 28200 50 0000 R CNN +F 1 "eSim_NPN" H 9700 28300 50 0000 R CNN +F 2 "" H 9950 28250 29 0000 C CNN +F 3 "" H 9750 28150 60 0000 C CNN + 1 9750 28150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q40 +U 1 1 66886FC8 +P 10850 24650 +F 0 "Q40" H 10750 24700 50 0000 R CNN +F 1 "eSim_NPN" H 10800 24800 50 0000 R CNN +F 2 "" H 11050 24750 29 0000 C CNN +F 3 "" H 10850 24650 60 0000 C CNN + 1 10850 24650 + -1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 66886FCE +P 10700 25150 +F 0 "R6" H 10750 25280 50 0000 C CNN +F 1 "0.7k" H 10750 25100 50 0000 C CNN +F 2 "" H 10750 25130 30 0000 C CNN +F 3 "" V 10750 25200 30 0000 C CNN + 1 10700 25150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q44 +U 1 1 66886FD4 +P 12300 26450 +F 0 "Q44" H 12200 26500 50 0000 R CNN +F 1 "eSim_NPN" H 12250 26600 50 0000 R CNN +F 2 "" H 12500 26550 29 0000 C CNN +F 3 "" H 12300 26450 60 0000 C CNN + 1 12300 26450 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 66886FDA +P 6750 24850 +F 0 "C2" H 6775 24950 50 0000 L CNN +F 1 "8p" H 6775 24750 50 0000 L CNN +F 2 "" H 6788 24700 30 0000 C CNN +F 3 "" H 6750 24850 60 0000 C CNN + 1 6750 24850 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q53 +U 1 1 66886FE0 +P 14650 26050 +F 0 "Q53" H 14550 26100 50 0000 R CNN +F 1 "eSim_NPN" H 14600 26200 50 0000 R CNN +F 2 "" H 14850 26150 29 0000 C CNN +F 3 "" H 14650 26050 60 0000 C CNN + 1 14650 26050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q54 +U 1 1 66886FE6 +P 14650 28350 +F 0 "Q54" H 14550 28400 50 0000 R CNN +F 1 "eSim_NPN" H 14600 28500 50 0000 R CNN +F 2 "" H 14850 28450 29 0000 C CNN +F 3 "" H 14650 28350 60 0000 C CNN + 1 14650 28350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 66886FEC +P 13950 24050 +F 0 "R11" H 14000 24180 50 0000 C CNN +F 1 "31k" H 14000 24000 50 0000 C CNN +F 2 "" H 14000 24030 30 0000 C CNN +F 3 "" V 14000 24100 30 0000 C CNN + 1 13950 24050 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 66886FF2 +P 13950 26600 +F 0 "R12" H 14000 26730 50 0000 C CNN +F 1 "37k" H 14000 26550 50 0000 C CNN +F 2 "" H 14000 26580 30 0000 C CNN +F 3 "" V 14000 26650 30 0000 C CNN + 1 13950 26600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q59 +U 1 1 66886FF8 +P 16350 23400 +F 0 "Q59" H 16250 23450 50 0000 R CNN +F 1 "eSim_NPN" H 16300 23550 50 0000 R CNN +F 2 "" H 16550 23500 29 0000 C CNN +F 3 "" H 16350 23400 60 0000 C CNN + 1 16350 23400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R14 +U 1 1 66886FFE +P 16400 25150 +F 0 "R14" H 16450 25280 50 0000 C CNN +F 1 "25" H 16450 25100 50 0000 C CNN +F 2 "" H 16450 25130 30 0000 C CNN +F 3 "" V 16450 25200 30 0000 C CNN + 1 16400 25150 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q60 +U 1 1 66887004 +P 16350 26150 +F 0 "Q60" H 16250 26200 50 0000 R CNN +F 1 "eSim_PNP" H 16300 26300 50 0000 R CNN +F 2 "" H 16550 26250 29 0000 C CNN +F 3 "" H 16350 26150 60 0000 C CNN + 1 16350 26150 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q56 +U 1 1 6688700A +P 15800 27100 +F 0 "Q56" H 15700 27150 50 0000 R CNN +F 1 "eSim_PNP" H 15750 27250 50 0000 R CNN +F 2 "" H 16000 27200 29 0000 C CNN +F 3 "" H 15800 27100 60 0000 C CNN + 1 15800 27100 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q62 +U 1 1 66887010 +P 17150 24750 +F 0 "Q62" H 17050 24800 50 0000 R CNN +F 1 "eSim_NPN" H 17100 24900 50 0000 R CNN +F 2 "" H 17350 24850 29 0000 C CNN +F 3 "" H 17150 24750 60 0000 C CNN + 1 17150 24750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q65 +U 1 1 6688701C +P 18800 23350 +F 0 "Q65" H 18700 23400 50 0000 R CNN +F 1 "eSim_NPN" H 18750 23500 50 0000 R CNN +F 2 "" H 19000 23450 29 0000 C CNN +F 3 "" H 18800 23350 60 0000 C CNN + 1 18800 23350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q68 +U 1 1 66887022 +P 19900 23350 +F 0 "Q68" H 19800 23400 50 0000 R CNN +F 1 "eSim_NPN" H 19850 23500 50 0000 R CNN +F 2 "" H 20100 23450 29 0000 C CNN +F 3 "" H 19900 23350 60 0000 C CNN + 1 19900 23350 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J2 +U 1 1 66887028 +P 18800 22350 +F 0 "J2" H 18700 22400 50 0000 R CNN +F 1 "jfet_n" H 18750 22500 50 0000 R CNN +F 2 "" H 19000 22450 29 0000 C CNN +F 3 "" H 18800 22350 60 0000 C CNN + 1 18800 22350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q66 +U 1 1 6688702E +P 18800 27250 +F 0 "Q66" H 18700 27300 50 0000 R CNN +F 1 "eSim_NPN" H 18750 27400 50 0000 R CNN +F 2 "" H 19000 27350 29 0000 C CNN +F 3 "" H 18800 27250 60 0000 C CNN + 1 18800 27250 + -1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 66887034 +P 19950 27850 +F 0 "R16" H 20000 27980 50 0000 C CNN +F 1 "8.2k" H 20000 27800 50 0000 C CNN +F 2 "" H 20000 27830 30 0000 C CNN +F 3 "" V 20000 27900 30 0000 C CNN + 1 19950 27850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q90 +U 1 1 66887932 +P 26900 23450 +F 0 "Q90" H 26800 23500 50 0000 R CNN +F 1 "eSim_PNP" H 26850 23600 50 0000 R CNN +F 2 "" H 27100 23550 29 0000 C CNN +F 3 "" H 26900 23450 60 0000 C CNN + 1 26900 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q94 +U 1 1 66887938 +P 27350 23450 +F 0 "Q94" H 27250 23500 50 0000 R CNN +F 1 "eSim_PNP" H 27300 23600 50 0000 R CNN +F 2 "" H 27550 23550 29 0000 C CNN +F 3 "" H 27350 23450 60 0000 C CNN + 1 27350 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q112 +U 1 1 6688793E +P 34000 23450 +F 0 "Q112" H 33900 23500 50 0000 R CNN +F 1 "eSim_PNP" H 33950 23600 50 0000 R CNN +F 2 "" H 34200 23550 29 0000 C CNN +F 3 "" H 34000 23450 60 0000 C CNN + 1 34000 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q114 +U 1 1 66887944 +P 34400 23450 +F 0 "Q114" H 34300 23500 50 0000 R CNN +F 1 "eSim_PNP" H 34350 23600 50 0000 R CNN +F 2 "" H 34600 23550 29 0000 C CNN +F 3 "" H 34400 23450 60 0000 C CNN + 1 34400 23450 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q116 +U 1 1 6688794A +P 35750 24150 +F 0 "Q116" H 35650 24200 50 0000 R CNN +F 1 "eSim_NPN" H 35700 24300 50 0000 R CNN +F 2 "" H 35950 24250 29 0000 C CNN +F 3 "" H 35750 24150 60 0000 C CNN + 1 35750 24150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q120 +U 1 1 66887950 +P 36300 24450 +F 0 "Q120" H 36200 24500 50 0000 R CNN +F 1 "eSim_NPN" H 36250 24600 50 0000 R CNN +F 2 "" H 36500 24550 29 0000 C CNN +F 3 "" H 36300 24450 60 0000 C CNN + 1 36300 24450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q82 +U 1 1 66887956 +P 26000 25000 +F 0 "Q82" H 25900 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25950 25150 50 0000 R CNN +F 2 "" H 26200 25100 29 0000 C CNN +F 3 "" H 26000 25000 60 0000 C CNN + 1 26000 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q76 +U 1 1 6688795C +P 25550 25000 +F 0 "Q76" H 25450 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25500 25150 50 0000 R CNN +F 2 "" H 25750 25100 29 0000 C CNN +F 3 "" H 25550 25000 60 0000 C CNN + 1 25550 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q70 +U 1 1 66887962 +P 25050 25000 +F 0 "Q70" H 24950 25050 50 0000 R CNN +F 1 "eSim_PNP" H 25000 25150 50 0000 R CNN +F 2 "" H 25250 25100 29 0000 C CNN +F 3 "" H 25050 25000 60 0000 C CNN + 1 25050 25000 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q72 +U 1 1 66887968 +P 25200 29750 +F 0 "Q72" H 25100 29800 50 0000 R CNN +F 1 "eSim_PNP" H 25150 29900 50 0000 R CNN +F 2 "" H 25400 29850 29 0000 C CNN +F 3 "" H 25200 29750 60 0000 C CNN + 1 25200 29750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q78 +U 1 1 6688796E +P 25800 27050 +F 0 "Q78" H 25700 27100 50 0000 R CNN +F 1 "eSim_PNP" H 25750 27200 50 0000 R CNN +F 2 "" H 26000 27150 29 0000 C CNN +F 3 "" H 25800 27050 60 0000 C CNN + 1 25800 27050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q84 +U 1 1 66887974 +P 26200 27050 +F 0 "Q84" H 26100 27100 50 0000 R CNN +F 1 "eSim_PNP" H 26150 27200 50 0000 R CNN +F 2 "" H 26400 27150 29 0000 C CNN +F 3 "" H 26200 27050 60 0000 C CNN + 1 26200 27050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q88 +U 1 1 6688797A +P 26850 27050 +F 0 "Q88" H 26750 27100 50 0000 R CNN +F 1 "eSim_PNP" H 26800 27200 50 0000 R CNN +F 2 "" H 27050 27150 29 0000 C CNN +F 3 "" H 26850 27050 60 0000 C CNN + 1 26850 27050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q92 +U 1 1 66887980 +P 27300 27050 +F 0 "Q92" H 27200 27100 50 0000 R CNN +F 1 "eSim_PNP" H 27250 27200 50 0000 R CNN +F 2 "" H 27500 27150 29 0000 C CNN +F 3 "" H 27300 27050 60 0000 C CNN + 1 27300 27050 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q74 +U 1 1 66887986 +P 25400 28350 +F 0 "Q74" H 25300 28400 50 0000 R CNN +F 1 "eSim_PNP" H 25350 28500 50 0000 R CNN +F 2 "" H 25600 28450 29 0000 C CNN +F 3 "" H 25400 28350 60 0000 C CNN + 1 25400 28350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q80 +U 1 1 6688798C +P 25850 30100 +F 0 "Q80" H 25750 30150 50 0000 R CNN +F 1 "eSim_NPN" H 25800 30250 50 0000 R CNN +F 2 "" H 26050 30200 29 0000 C CNN +F 3 "" H 25850 30100 60 0000 C CNN + 1 25850 30100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q86 +U 1 1 66887992 +P 26550 30100 +F 0 "Q86" H 26450 30150 50 0000 R CNN +F 1 "eSim_NPN" H 26500 30250 50 0000 R CNN +F 2 "" H 26750 30200 29 0000 C CNN +F 3 "" H 26550 30100 60 0000 C CNN + 1 26550 30100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q96 +U 1 1 66887998 +P 27750 28400 +F 0 "Q96" H 27650 28450 50 0000 R CNN +F 1 "eSim_PNP" H 27700 28550 50 0000 R CNN +F 2 "" H 27950 28500 29 0000 C CNN +F 3 "" H 27750 28400 60 0000 C CNN + 1 27750 28400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q98 +U 1 1 6688799E +P 28700 29900 +F 0 "Q98" H 28600 29950 50 0000 R CNN +F 1 "eSim_PNP" H 28650 30050 50 0000 R CNN +F 2 "" H 28900 30000 29 0000 C CNN +F 3 "" H 28700 29900 60 0000 C CNN + 1 28700 29900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q100 +U 1 1 668879A4 +P 29200 28400 +F 0 "Q100" H 29100 28450 50 0000 R CNN +F 1 "eSim_NPN" H 29150 28550 50 0000 R CNN +F 2 "" H 29400 28500 29 0000 C CNN +F 3 "" H 29200 28400 60 0000 C CNN + 1 29200 28400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q102 +U 1 1 668879AA +P 29400 29200 +F 0 "Q102" H 29300 29250 50 0000 R CNN +F 1 "eSim_NPN" H 29350 29350 50 0000 R CNN +F 2 "" H 29600 29300 29 0000 C CNN +F 3 "" H 29400 29200 60 0000 C CNN + 1 29400 29200 + -1 0 0 -1 +$EndComp +$Comp +L resistor R20 +U 1 1 668879B0 +P 29250 29850 +F 0 "R20" H 29300 29980 50 0000 C CNN +F 1 "12k" H 29300 29800 50 0000 C CNN +F 2 "" H 29300 29830 30 0000 C CNN +F 3 "" V 29300 29900 30 0000 C CNN + 1 29250 29850 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q104 +U 1 1 668879B6 +P 30300 28400 +F 0 "Q104" H 30200 28450 50 0000 R CNN +F 1 "eSim_PNP" H 30250 28550 50 0000 R CNN +F 2 "" H 30500 28500 29 0000 C CNN +F 3 "" H 30300 28400 60 0000 C CNN + 1 30300 28400 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q106 +U 1 1 668879BC +P 31400 29200 +F 0 "Q106" H 31300 29250 50 0000 R CNN +F 1 "eSim_NPN" H 31350 29350 50 0000 R CNN +F 2 "" H 31600 29300 29 0000 C CNN +F 3 "" H 31400 29200 60 0000 C CNN + 1 31400 29200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q108 +U 1 1 668879C2 +P 32500 25700 +F 0 "Q108" H 32400 25750 50 0000 R CNN +F 1 "eSim_NPN" H 32450 25850 50 0000 R CNN +F 2 "" H 32700 25800 29 0000 C CNN +F 3 "" H 32500 25700 60 0000 C CNN + 1 32500 25700 + -1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 668879C8 +P 32350 26200 +F 0 "R22" H 32400 26330 50 0000 C CNN +F 1 "0.7k" H 32400 26150 50 0000 C CNN +F 2 "" H 32400 26180 30 0000 C CNN +F 3 "" V 32400 26250 30 0000 C CNN + 1 32350 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q110 +U 1 1 668879CE +P 33950 27500 +F 0 "Q110" H 33850 27550 50 0000 R CNN +F 1 "eSim_NPN" H 33900 27650 50 0000 R CNN +F 2 "" H 34150 27600 29 0000 C CNN +F 3 "" H 33950 27500 60 0000 C CNN + 1 33950 27500 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 668879D4 +P 28400 25900 +F 0 "C4" H 28425 26000 50 0000 L CNN +F 1 "8p" H 28425 25800 50 0000 L CNN +F 2 "" H 28438 25750 30 0000 C CNN +F 3 "" H 28400 25900 60 0000 C CNN + 1 28400 25900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q121 +U 1 1 668879DA +P 36300 27100 +F 0 "Q121" H 36200 27150 50 0000 R CNN +F 1 "eSim_NPN" H 36250 27250 50 0000 R CNN +F 2 "" H 36500 27200 29 0000 C CNN +F 3 "" H 36300 27100 60 0000 C CNN + 1 36300 27100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q122 +U 1 1 668879E0 +P 36300 29400 +F 0 "Q122" H 36200 29450 50 0000 R CNN +F 1 "eSim_NPN" H 36250 29550 50 0000 R CNN +F 2 "" H 36500 29500 29 0000 C CNN +F 3 "" H 36300 29400 60 0000 C CNN + 1 36300 29400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R27 +U 1 1 668879E6 +P 35600 25100 +F 0 "R27" H 35650 25230 50 0000 C CNN +F 1 "31k" H 35650 25050 50 0000 C CNN +F 2 "" H 35650 25080 30 0000 C CNN +F 3 "" V 35650 25150 30 0000 C CNN + 1 35600 25100 + 0 1 1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 668879EC +P 35600 27650 +F 0 "R28" H 35650 27780 50 0000 C CNN +F 1 "37k" H 35650 27600 50 0000 C CNN +F 2 "" H 35650 27630 30 0000 C CNN +F 3 "" V 35650 27700 30 0000 C CNN + 1 35600 27650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q127 +U 1 1 668879F2 +P 38000 24450 +F 0 "Q127" H 37900 24500 50 0000 R CNN +F 1 "eSim_NPN" H 37950 24600 50 0000 R CNN +F 2 "" H 38200 24550 29 0000 C CNN +F 3 "" H 38000 24450 60 0000 C CNN + 1 38000 24450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R30 +U 1 1 668879F8 +P 38050 26200 +F 0 "R30" H 38100 26330 50 0000 C CNN +F 1 "25" H 38100 26150 50 0000 C CNN +F 2 "" H 38100 26180 30 0000 C CNN +F 3 "" V 38100 26250 30 0000 C CNN + 1 38050 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q128 +U 1 1 668879FE +P 38000 27200 +F 0 "Q128" H 37900 27250 50 0000 R CNN +F 1 "eSim_PNP" H 37950 27350 50 0000 R CNN +F 2 "" H 38200 27300 29 0000 C CNN +F 3 "" H 38000 27200 60 0000 C CNN + 1 38000 27200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q124 +U 1 1 66887A04 +P 37450 28150 +F 0 "Q124" H 37350 28200 50 0000 R CNN +F 1 "eSim_PNP" H 37400 28300 50 0000 R CNN +F 2 "" H 37650 28250 29 0000 C CNN +F 3 "" H 37450 28150 60 0000 C CNN + 1 37450 28150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q130 +U 1 1 66887A0A +P 38800 25800 +F 0 "Q130" H 38700 25850 50 0000 R CNN +F 1 "eSim_NPN" H 38750 25950 50 0000 R CNN +F 2 "" H 39000 25900 29 0000 C CNN +F 3 "" H 38800 25800 60 0000 C CNN + 1 38800 25800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q133 +U 1 1 66887A16 +P 40450 24400 +F 0 "Q133" H 40350 24450 50 0000 R CNN +F 1 "eSim_NPN" H 40400 24550 50 0000 R CNN +F 2 "" H 40650 24500 29 0000 C CNN +F 3 "" H 40450 24400 60 0000 C CNN + 1 40450 24400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q136 +U 1 1 66887A1C +P 41550 24400 +F 0 "Q136" H 41450 24450 50 0000 R CNN +F 1 "eSim_NPN" H 41500 24550 50 0000 R CNN +F 2 "" H 41750 24500 29 0000 C CNN +F 3 "" H 41550 24400 60 0000 C CNN + 1 41550 24400 + 1 0 0 -1 +$EndComp +$Comp +L jfet_n J4 +U 1 1 66887A22 +P 40450 23400 +F 0 "J4" H 40350 23450 50 0000 R CNN +F 1 "jfet_n" H 40400 23550 50 0000 R CNN +F 2 "" H 40650 23500 29 0000 C CNN +F 3 "" H 40450 23400 60 0000 C CNN + 1 40450 23400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q134 +U 1 1 66887A28 +P 40450 28300 +F 0 "Q134" H 40350 28350 50 0000 R CNN +F 1 "eSim_NPN" H 40400 28450 50 0000 R CNN +F 2 "" H 40650 28400 29 0000 C CNN +F 3 "" H 40450 28300 60 0000 C CNN + 1 40450 28300 + -1 0 0 -1 +$EndComp +$Comp +L resistor R32 +U 1 1 66887A2E +P 41600 28900 +F 0 "R32" H 41650 29030 50 0000 C CNN +F 1 "8.2k" H 41650 28850 50 0000 C CNN +F 2 "" H 41650 28880 30 0000 C CNN +F 3 "" V 41650 28950 30 0000 C CNN + 1 41600 28900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 6688C2EA +P 21600 4700 +F 0 "U1" H 21650 4800 30 0000 C CNN +F 1 "PORT" H 21600 4700 30 0000 C CNN +F 2 "" H 21600 4700 60 0000 C CNN +F 3 "" H 21600 4700 60 0000 C CNN + 4 21600 4700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 6689C72D +P 20800 12600 +F 0 "U1" H 20850 12700 30 0000 C CNN +F 1 "PORT" H 20800 12600 30 0000 C CNN +F 2 "" H 20800 12600 60 0000 C CNN +F 3 "" H 20800 12600 60 0000 C CNN + 11 20800 12600 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 668A97B5 +P 17150 3500 +F 0 "U1" H 17200 3600 30 0000 C CNN +F 1 "PORT" H 17150 3500 30 0000 C CNN +F 2 "" H 17150 3500 60 0000 C CNN +F 3 "" H 17150 3500 60 0000 C CNN + 1 17150 3500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 668AB399 +P 1750 10350 +F 0 "U1" H 1800 10450 30 0000 C CNN +F 1 "PORT" H 1750 10350 30 0000 C CNN +F 2 "" H 1750 10350 60 0000 C CNN +F 3 "" H 1750 10350 60 0000 C CNN + 2 1750 10350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 668ABE39 +P 6250 10400 +F 0 "U1" H 6300 10500 30 0000 C CNN +F 1 "PORT" H 6250 10400 30 0000 C CNN +F 2 "" H 6250 10400 60 0000 C CNN +F 3 "" H 6250 10400 60 0000 C CNN + 3 6250 10400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 668AD6A7 +P 39300 3900 +F 0 "U1" H 39350 4000 30 0000 C CNN +F 1 "PORT" H 39300 3900 30 0000 C CNN +F 2 "" H 39300 3900 60 0000 C CNN +F 3 "" H 39300 3900 60 0000 C CNN + 8 39300 3900 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 668AEEA7 +P 23900 10750 +F 0 "U1" H 23950 10850 30 0000 C CNN +F 1 "PORT" H 23900 10750 30 0000 C CNN +F 2 "" H 23900 10750 60 0000 C CNN +F 3 "" H 23900 10750 60 0000 C CNN + 9 23900 10750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 668AFE62 +P 28400 10800 +F 0 "U1" H 28450 10900 30 0000 C CNN +F 1 "PORT" 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14250 12850 14250 11600 +Wire Wire Line + 14250 9300 14250 11200 +Connection ~ 13050 7150 +Wire Wire Line + 9800 7150 13050 7150 +Wire Wire Line + 9800 7900 9800 7150 +Wire Wire Line + 6400 7900 9800 7900 +Connection ~ 4500 11900 +Wire Wire Line + 4400 7900 4400 11900 +Wire Wire Line + 6100 7900 4400 7900 +Connection ~ 7150 10850 +Wire Wire Line + 7600 10850 7150 10850 +Wire Wire Line + 7600 9500 7600 10850 +Wire Wire Line + 11600 9500 7600 9500 +Connection ~ 11900 10400 +Wire Wire Line + 10250 10400 11900 10400 +Wire Wire Line + 10250 8400 10250 10400 +Connection ~ 9150 12850 +Wire Wire Line + 11900 12850 11900 9700 +Connection ~ 13050 6150 +Wire Wire Line + 13050 6150 13050 8600 +Wire Wire Line + 13050 8600 11900 8600 +Wire Wire Line + 11900 8600 11900 9300 +Connection ~ 11650 5450 +Connection ~ 10250 6300 +Wire Wire Line + 11950 6300 10250 6300 +Wire Wire Line + 11950 5650 11950 6300 +Connection ~ 10250 5450 +Wire Wire Line + 10250 5450 10250 7500 +Wire Wire Line + 10250 7900 10250 8100 +Wire Wire Line + 13700 6450 15650 6450 +Wire Wire Line + 13700 6350 13700 6450 +Connection ~ 13700 4700 +Wire Wire Line + 14250 4700 14250 6250 +Connection ~ 12150 4700 +Wire Wire Line + 13700 4700 13700 5950 +Wire Wire Line + 12350 6150 13400 6150 +Wire Wire Line + 12350 5650 12350 6150 +Connection ~ 12150 5200 +Wire Wire Line + 12150 4700 12150 5200 +Wire Wire Line + 12350 5200 12350 5250 +Wire Wire Line + 11950 5200 12350 5200 +Wire Wire Line + 11950 5250 11950 5200 +Connection ~ 4550 5450 +Connection ~ 9150 10400 +Connection ~ 9450 11200 +Wire Wire Line + 9700 10400 9700 11200 +Wire Wire Line + 7450 11200 13850 11200 +Connection ~ 8050 12850 +Wire Wire Line + 9150 12850 9150 11400 +Wire Wire Line + 9150 10400 9150 11000 +Wire Wire Line + 8350 10400 9700 10400 +Connection ~ 7150 12850 +Wire Wire Line + 8050 12850 8050 10600 +Connection ~ 7300 10200 +Connection ~ 6650 12850 +Wire Wire Line + 7150 12850 7150 12050 +Wire Wire Line + 7150 11400 7150 11750 +Wire Wire Line + 7150 10600 7150 11000 +Wire Wire Line + 7150 10200 8050 10200 +Wire Wire Line + 7300 6850 7300 10200 +Wire Wire Line + 6650 10400 6850 10400 +Wire Wire Line + 4400 11900 6350 11900 +Connection ~ 5500 12850 +Wire Wire Line + 6650 12850 6650 12100 +Wire Wire Line + 4850 6850 4850 5650 +Wire Wire Line + 7300 6850 4850 6850 +Wire Wire Line + 6650 10400 6650 11700 +Connection ~ 4800 8700 +Wire Wire Line + 4800 8500 4800 8700 +Wire Wire Line + 3500 8500 4800 8500 +Wire Wire Line + 3500 7200 3500 8500 +Connection ~ 4500 12850 +Wire Wire Line + 5500 12850 5500 10600 +Connection ~ 5500 9600 +Wire Wire Line + 5050 9600 5500 9600 +Wire Wire Line + 5050 9250 5050 9600 +Connection ~ 5350 9050 +Wire Wire Line + 5500 9050 5500 10200 +Connection ~ 3600 11750 +Wire Wire Line + 3600 11900 3600 11750 +Connection ~ 4150 11750 +Wire Wire Line + 3250 11750 4150 11750 +Connection ~ 4150 12100 +Wire Wire Line + 4150 9250 4150 12100 +Connection ~ 3350 12850 +Wire Wire Line + 3350 10550 3350 12850 +Connection ~ 3600 12850 +Wire Wire Line + 3600 12850 3600 12300 +Wire Wire Line + 4500 12850 4500 12300 +Wire Wire Line + 2950 12850 20800 12850 +Wire Wire Line + 2950 11950 2950 12850 +Wire Wire Line + 3900 12100 4200 12100 +Connection ~ 3350 9600 +Wire Wire Line + 3750 9600 3350 9600 +Wire Wire Line + 3750 9250 3750 9600 +Connection ~ 3450 9050 +Wire Wire Line + 3350 9050 3350 10150 +Connection ~ 3950 8800 +Connection ~ 4850 8800 +Wire Wire Line + 4850 8700 4850 8800 +Wire Wire Line + 3950 8700 4850 8700 +Wire Wire Line + 3950 8800 3950 8700 +Wire Wire Line + 4150 8800 4150 8850 +Wire Wire Line + 3750 8800 4150 8800 +Wire Wire Line + 3750 8850 3750 8800 +Wire Wire Line + 5050 8800 5050 8850 +Wire Wire Line + 4600 8800 5050 8800 +Wire Wire Line + 4600 8850 4600 8800 +Wire Wire Line + 4900 9050 5500 9050 +Wire Wire Line + 3350 9050 3850 9050 +Wire Wire Line + 2950 7200 3000 7200 +Wire Wire Line + 2950 7200 2950 11550 +Connection ~ 3200 7000 +Wire Wire Line + 2700 5450 12050 5450 +Wire Wire Line + 2700 7000 2700 5450 +Connection ~ 5050 4700 +Connection ~ 3500 6650 +Wire Wire Line + 3500 4700 3500 6800 +Wire Wire Line + 3000 6650 3000 6800 +Wire Wire Line + 3000 6650 3950 6650 +Wire Wire Line + 3950 6650 3950 6800 +Wire Wire Line + 2700 7000 3650 7000 +Connection ~ 5050 5200 +Wire Wire Line + 5050 4700 5050 5200 +Wire Wire Line + 3500 4700 21350 4700 +Wire Wire Line + 5300 5200 5300 5250 +Wire Wire Line + 4850 5200 5300 5200 +Wire Wire Line + 4850 5250 4850 5200 +Connection ~ 5000 5450 +Wire Wire Line + 17650 20700 17650 25600 +$Comp +L PORT U1 +U 7 1 668BD5A0 +P 17650 20450 +F 0 "U1" H 17700 20550 30 0000 C CNN +F 1 "PORT" H 17650 20450 30 0000 C CNN +F 2 "" H 17650 20450 60 0000 C CNN +F 3 "" H 17650 20450 60 0000 C CNN + 7 17650 20450 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 668BEA81 +P 2250 27300 +F 0 "U1" H 2300 27400 30 0000 C CNN +F 1 "PORT" H 2250 27300 30 0000 C CNN +F 2 "" H 2250 27300 60 0000 C CNN +F 3 "" H 2250 27300 60 0000 C CNN + 6 2250 27300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 668BF2D4 +P 6750 27350 +F 0 "U1" H 6800 27450 30 0000 C CNN +F 1 "PORT" H 6750 27350 30 0000 C CNN +F 2 "" H 6750 27350 60 0000 C CNN +F 3 "" H 6750 27350 60 0000 C CNN + 5 6750 27350 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 27350 6300 27350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub new file mode 100644 index 00000000..8c261c2f --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC.sub @@ -0,0 +1,177 @@ +* Subcircuit MC3403_IC +.subckt MC3403_IC net-_q58-pad3_ net-_q3-pad2_ net-_q25-pad2_ net-_j1-pad1_ net-_q28-pad2_ net-_q9-pad2_ net-_q60-pad3_ net-_q126-pad3_ net-_q73-pad2_ net-_q95-pad2_ net-_j1-pad2_ net-_q96-pad2_ net-_q74-pad2_ net-_q128-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\mc3403_ic\mc3403_ic.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +q19 net-_q19-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q22 net-_q22-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q42 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q43 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q47 net-_j1-pad1_ net-_c1-pad1_ net-_q47-pad3_ Q2N2222 +q49 net-_j1-pad1_ net-_q47-pad3_ net-_q49-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q12-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q12-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q12-pad2_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad2_ net-_q12-pad3_ Q2N2907A +q18 net-_c1-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q21 net-_q18-pad2_ net-_q18-pad2_ net-_q12-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q12-pad2_ Q2N2907A +q8 net-_q12-pad1_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q16 net-_c1-pad2_ net-_q12-pad1_ net-_j1-pad2_ Q2N2222 +q25 net-_j1-pad2_ net-_q25-pad2_ net-_q18-pad2_ Q2N2907A +q29 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q30 net-_q19-pad1_ net-_q10-pad1_ net-_q30-pad3_ Q2N2222 +q32 net-_q30-pad3_ net-_q22-pad1_ net-_q32-pad3_ Q2N2222 +r3 net-_q32-pad3_ net-_j1-pad2_ 12k +q35 net-_j1-pad2_ net-_q22-pad1_ net-_q19-pad1_ Q2N2907A +q37 net-_q22-pad1_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +q39 net-_q1-pad2_ net-_q39-pad2_ net-_q39-pad3_ Q2N2222 +r5 net-_q39-pad3_ net-_j1-pad2_ 0.7k +q41 net-_c1-pad1_ net-_q30-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 8p +q50 net-_q49-pad3_ net-_q50-pad2_ net-_q50-pad3_ Q2N2222 +q51 net-_q50-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r9 net-_q49-pad3_ net-_q50-pad2_ 31k +r10 net-_q50-pad2_ net-_q50-pad3_ 37k +q57 net-_j1-pad1_ net-_q47-pad3_ net-_q57-pad3_ Q2N2222 +r13 net-_q57-pad3_ net-_q58-pad3_ 25 +q58 net-_j1-pad2_ net-_q55-pad3_ net-_q58-pad3_ Q2N2907A +q55 net-_j1-pad2_ net-_q50-pad3_ net-_q55-pad3_ Q2N2907A +q61 net-_c1-pad1_ net-_q57-pad3_ net-_q58-pad3_ Q2N2222 +q63 net-_j1-pad3_ net-_j1-pad3_ net-_q39-pad2_ Q2N2222 +q67 net-_j1-pad1_ net-_j1-pad3_ net-_q64-pad2_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q64 net-_q39-pad2_ net-_q64-pad2_ net-_j1-pad2_ Q2N2222 +r15 net-_q64-pad2_ net-_j1-pad2_ 8.2k +q89 net-_q103-pad3_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q93 net-_q101-pad2_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q111 net-_q107-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q113 net-_c3-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q115 net-_j1-pad1_ net-_c3-pad1_ net-_q115-pad3_ Q2N2222 +q117 net-_j1-pad1_ net-_q115-pad3_ net-_q117-pad3_ Q2N2222 +q81 net-_q81-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q75 net-_q75-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q69 net-_q69-pad1_ net-_q107-pad1_ net-_j1-pad1_ Q2N2907A +q71 net-_j1-pad2_ net-_q71-pad2_ net-_q69-pad1_ Q2N2907A +q77 net-_q73-pad3_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q83 net-_q71-pad2_ net-_q73-pad3_ net-_q75-pad1_ Q2N2907A +q87 net-_c3-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q91 net-_q87-pad2_ net-_q87-pad2_ net-_q75-pad1_ Q2N2907A +q73 net-_j1-pad2_ net-_q73-pad2_ net-_q73-pad3_ Q2N2907A +q79 net-_q71-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q85 net-_c3-pad2_ net-_q71-pad2_ net-_j1-pad2_ Q2N2222 +q95 net-_j1-pad2_ net-_q95-pad2_ net-_q87-pad2_ Q2N2907A +q97 net-_j1-pad2_ net-_c3-pad2_ net-_q81-pad1_ Q2N2907A +q99 net-_q103-pad3_ net-_q81-pad1_ net-_q101-pad1_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad2_ net-_q101-pad3_ Q2N2222 +r19 net-_q101-pad3_ net-_j1-pad2_ 12k +q103 net-_j1-pad2_ net-_q101-pad2_ net-_q103-pad3_ Q2N2907A +q105 net-_q101-pad2_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +q107 net-_q107-pad1_ net-_q107-pad2_ net-_q107-pad3_ Q2N2222 +r21 net-_q107-pad3_ net-_j1-pad2_ 0.7k +q109 net-_c3-pad1_ net-_q101-pad1_ net-_j1-pad2_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 8p +q118 net-_q117-pad3_ net-_q118-pad2_ net-_q118-pad3_ Q2N2222 +q119 net-_q118-pad3_ net-_q101-pad2_ net-_j1-pad2_ Q2N2222 +r25 net-_q117-pad3_ net-_q118-pad2_ 31k +r26 net-_q118-pad2_ net-_q118-pad3_ 37k +q125 net-_j1-pad1_ net-_q115-pad3_ net-_q125-pad3_ Q2N2222 +r29 net-_q125-pad3_ net-_q126-pad3_ 25 +q126 net-_j1-pad2_ net-_q123-pad3_ net-_q126-pad3_ Q2N2907A +q123 net-_j1-pad2_ net-_q118-pad3_ net-_q123-pad3_ Q2N2907A +q129 net-_c3-pad1_ net-_q125-pad3_ net-_q126-pad3_ Q2N2222 +q131 net-_j3-pad3_ net-_j3-pad3_ net-_q107-pad2_ Q2N2222 +q135 net-_j1-pad1_ net-_j3-pad3_ net-_q132-pad2_ Q2N2222 +j3 net-_j1-pad1_ net-_j1-pad2_ net-_j3-pad3_ J2N3819 +q132 net-_q107-pad2_ net-_q132-pad2_ net-_j1-pad2_ Q2N2222 +r31 net-_q132-pad2_ net-_j1-pad2_ 8.2k +q24 net-_q24-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q27 net-_q27-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q45 net-_q11-pad2_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q46 net-_c2-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q48 net-_j1-pad1_ net-_c2-pad1_ net-_q48-pad3_ Q2N2222 +q52 net-_j1-pad1_ net-_q48-pad3_ net-_q52-pad3_ Q2N2222 +q15 net-_q15-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q5 net-_q5-pad1_ net-_q11-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_j1-pad2_ net-_q14-pad1_ net-_q5-pad1_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q17 net-_q14-pad1_ net-_q13-pad1_ net-_q11-pad1_ Q2N2907A +q23 net-_c2-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q26 net-_q23-pad2_ net-_q23-pad2_ net-_q11-pad1_ Q2N2907A +q9 net-_j1-pad2_ net-_q9-pad2_ net-_q13-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q20 net-_c2-pad2_ net-_q14-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_j1-pad2_ net-_q28-pad2_ net-_q23-pad2_ Q2N2907A +q31 net-_j1-pad2_ net-_c2-pad2_ net-_q15-pad1_ Q2N2907A +q33 net-_q24-pad1_ net-_q15-pad1_ net-_q33-pad3_ Q2N2222 +q34 net-_q33-pad3_ net-_q27-pad1_ net-_q34-pad3_ Q2N2222 +r4 net-_q34-pad3_ net-_j1-pad2_ 12k +q36 net-_j1-pad2_ net-_q27-pad1_ net-_q24-pad1_ Q2N2907A +q38 net-_q27-pad1_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +q40 net-_q11-pad2_ net-_q40-pad2_ net-_q40-pad3_ Q2N2222 +r6 net-_q40-pad3_ net-_j1-pad2_ 0.7k +q44 net-_c2-pad1_ net-_q33-pad3_ net-_j1-pad2_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 8p +q53 net-_q52-pad3_ net-_q53-pad2_ net-_q53-pad3_ Q2N2222 +q54 net-_q53-pad3_ net-_q27-pad1_ net-_j1-pad2_ Q2N2222 +r11 net-_q52-pad3_ net-_q53-pad2_ 31k +r12 net-_q53-pad2_ net-_q53-pad3_ 37k +q59 net-_j1-pad1_ net-_q48-pad3_ net-_q59-pad3_ Q2N2222 +r14 net-_q59-pad3_ net-_q60-pad3_ 25 +q60 net-_j1-pad2_ net-_q56-pad3_ net-_q60-pad3_ Q2N2907A +q56 net-_j1-pad2_ net-_q53-pad3_ net-_q56-pad3_ Q2N2907A +q62 net-_c2-pad1_ net-_q59-pad3_ net-_q60-pad3_ Q2N2222 +q65 net-_j2-pad3_ net-_j2-pad3_ net-_q40-pad2_ Q2N2222 +q68 net-_j1-pad1_ net-_j2-pad3_ net-_q66-pad2_ Q2N2222 +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j2-pad3_ J2N3819 +q66 net-_q40-pad2_ net-_q66-pad2_ net-_j1-pad2_ Q2N2222 +r16 net-_q66-pad2_ net-_j1-pad2_ 8.2k +q90 net-_q100-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q94 net-_q102-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q112 net-_q108-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q114 net-_c4-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q116 net-_j1-pad1_ net-_c4-pad1_ net-_q116-pad3_ Q2N2222 +q120 net-_j1-pad1_ net-_q116-pad3_ net-_q120-pad3_ Q2N2222 +q82 net-_q100-pad2_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q76 net-_q76-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q70 net-_q70-pad1_ net-_q108-pad1_ net-_j1-pad1_ Q2N2907A +q72 net-_j1-pad2_ net-_q72-pad2_ net-_q70-pad1_ Q2N2907A +q78 net-_q74-pad3_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q84 net-_q72-pad2_ net-_q74-pad3_ net-_q76-pad1_ Q2N2907A +q88 net-_c4-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q92 net-_q88-pad2_ net-_q88-pad2_ net-_q76-pad1_ Q2N2907A +q74 net-_j1-pad2_ net-_q74-pad2_ net-_q74-pad3_ Q2N2907A +q80 net-_q72-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q86 net-_c4-pad2_ net-_q72-pad2_ net-_j1-pad2_ Q2N2222 +q96 net-_j1-pad2_ net-_q96-pad2_ net-_q88-pad2_ Q2N2907A +q98 net-_j1-pad2_ net-_c4-pad2_ net-_q100-pad2_ Q2N2907A +q100 net-_q100-pad1_ net-_q100-pad2_ net-_q100-pad3_ Q2N2222 +q102 net-_q100-pad3_ net-_q102-pad2_ net-_q102-pad3_ Q2N2222 +r20 net-_q102-pad3_ net-_j1-pad2_ 12k +q104 net-_j1-pad2_ net-_q102-pad2_ net-_q100-pad1_ Q2N2907A +q106 net-_q102-pad2_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +q108 net-_q108-pad1_ net-_q108-pad2_ net-_q108-pad3_ Q2N2222 +r22 net-_q108-pad3_ net-_j1-pad2_ 0.7k +q110 net-_c4-pad1_ net-_q100-pad3_ net-_j1-pad2_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 8p +q121 net-_q120-pad3_ net-_q121-pad2_ net-_q121-pad3_ Q2N2222 +q122 net-_q121-pad3_ net-_q102-pad2_ net-_j1-pad2_ Q2N2222 +r27 net-_q120-pad3_ net-_q121-pad2_ 31k +r28 net-_q121-pad2_ net-_q121-pad3_ 37k +q127 net-_j1-pad1_ net-_q116-pad3_ net-_q127-pad3_ Q2N2222 +r30 net-_q127-pad3_ net-_q128-pad3_ 25 +q128 net-_j1-pad2_ net-_q124-pad3_ net-_q128-pad3_ Q2N2907A +q124 net-_j1-pad2_ net-_q121-pad3_ net-_q124-pad3_ Q2N2907A +q130 net-_c4-pad1_ net-_q127-pad3_ net-_q128-pad3_ Q2N2222 +q133 net-_j4-pad3_ net-_j4-pad3_ net-_q108-pad2_ Q2N2222 +q136 net-_j1-pad1_ net-_j4-pad3_ net-_q134-pad2_ Q2N2222 +j4 net-_j1-pad1_ net-_j1-pad2_ net-_j4-pad3_ J2N3819 +q134 net-_q108-pad2_ net-_q134-pad2_ net-_j1-pad2_ Q2N2222 +r32 net-_q134-pad2_ net-_j1-pad2_ 8.2k +* Control Statements + +.ends MC3403_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml new file mode 100644 index 00000000..edbbc0a6 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/MC3403_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q22><q42><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q42><q43><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q43><q47><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q47><q49><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q25><q29><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q29><q30><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q32><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><q35><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q35><q37><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q37><q39><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q39><q41><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q41><q50><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q50><q51><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q57><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q57><q58><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q58><q55><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q55><q61><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q61><q63><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q63><q67><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q67><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q64><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q64><q89><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q89><q93><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q93><q111><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q111><q113><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q113><q115><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q115><q117><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q117><q81><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q81><q75><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q75><q69><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q69><q71><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q71><q77><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q77><q83><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q83><q87><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q87><q91><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q91><q73><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q73><q79><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q79><q85><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q85><q95><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q95><q97><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q97><q99><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q99><q101><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q101><q103><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q103><q105><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q105><q107><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q107><q109><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q109><q118><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q118><q119><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q119><q125><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q125><q126><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q126><q123><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q123><q129><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q129><q131><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q131><q135><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q135><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j3><q132><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q132><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q24><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q45><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q46><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q46><q48><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q52><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q52><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q31><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q31><q33><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q34><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q34><q36><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q36><q38><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q38><q40><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q44><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q44><q53><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q53><q54><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q54><q59><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q59><q60><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q60><q56><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q56><q62><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q62><q65><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q65><q68><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q68><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j2><q66><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q66><q90><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q90><q94><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q94><q112><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q112><q114><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q114><q116><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q116><q120><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q120><q82><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q82><q76><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q76><q70><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q70><q72><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q72><q78><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q78><q84><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q84><q88><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q88><q92><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q92><q74><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q74><q80><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q80><q86><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q86><q96><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q96><q98><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q98><q100><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q100><q102><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q102><q104><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q104><q106><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q106><q108><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q108><q110><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q110><q121><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q121><q122><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q122><q127><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q127><q128><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q128><q124><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q124><q130><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q130><q133><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q133><q136><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q136><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j4><q134><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q134></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC3403_sub/NJF.lib b/library/SubcircuitLibrary/MC3403_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/MC3403_sub/NPN.lib b/library/SubcircuitLibrary/MC3403_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC3403_sub/PNP.lib b/library/SubcircuitLibrary/MC3403_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC3403_sub/analysis b/library/SubcircuitLibrary/MC3403_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC3403_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/D.lib b/library/SubcircuitLibrary/MC78L05_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib new file mode 100644 index 00000000..c353ac98 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC-cache.lib @@ -0,0 +1,164 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_CP1 +# +DEF eSim_CP1 C 0 10 N N 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_CP1" 25 -100 50 H V L CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +ALIAS capacitor_polarised +$FPLIST + CP_* +$ENDFPLIST +DRAW +A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50 +P 2 0 1 20 -80 30 80 30 N +P 2 0 1 0 -70 90 -30 90 N +P 2 0 1 0 -50 70 -50 110 N +X ~ 1 0 150 110 D 50 50 1 1 P +X ~ 2 0 -150 130 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir new file mode 100644 index 00000000..768e3dcd --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir @@ -0,0 +1,38 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\MC78L05_IC\MC78L05_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/03/24 11:39:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ 15k +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R2 Net-_Q1-Pad3_ Net-_Q3-Pad2_ 3.8k +R3 Net-_Q3-Pad2_ Net-_Q2-Pad2_ 1.2k +R4 Net-_Q2-Pad2_ Net-_D1-Pad2_ 420 +U1 Net-_D1-Pad2_ Net-_Q1-Pad2_ zener +Q4 Net-_Q3-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q7 Net-_Q10-Pad1_ Net-_Q3-Pad1_ Net-_Q1-Pad1_ eSim_PNP +Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad1_ Net-_Q6-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R5 Net-_Q3-Pad3_ Net-_D1-Pad1_ 0.18k +R6 Net-_Q3-Pad3_ Net-_C1-Pad2_ 20k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_C1-Pad2_ Net-_D1-Pad1_ Net-_Q5-Pad3_ eSim_NPN +R7 Net-_Q5-Pad3_ Net-_D1-Pad2_ 1.0k +R8 Net-_Q10-Pad1_ Net-_C1-Pad1_ 2.2k +Q8 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q9 Net-_D1-Pad2_ Net-_C1-Pad1_ Net-_Q10-Pad1_ eSim_PNP +Q11 Net-_Q1-Pad1_ Net-_Q10-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q2 Net-_Q10-Pad1_ Net-_Q2-Pad2_ Net-_D1-Pad2_ eSim_NPN +R9 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 5.0k +Q12 Net-_Q1-Pad1_ Net-_Q11-Pad3_ Net-_Q10-Pad2_ eSim_NPN +R10 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 3.0 +R11 Net-_Q10-Pad3_ Net-_Q6-Pad2_ 2.0k +R12 Net-_Q6-Pad2_ Net-_D1-Pad2_ 2.85k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5p +U2 Net-_Q10-Pad3_ Net-_D1-Pad2_ Net-_Q1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out new file mode 100644 index 00000000..8486c6ca --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.cir.out @@ -0,0 +1,45 @@ +* d:\fossee\esim\library\subcircuitlibrary\mc78l05_ic\mc78l05_ic.cir + +.include PNP.lib +.include D.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q3-pad2_ 3.8k +r3 net-_q3-pad2_ net-_q2-pad2_ 1.2k +r4 net-_q2-pad2_ net-_d1-pad2_ 420 +* u1 net-_d1-pad2_ net-_q1-pad2_ zener +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q10-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q6-pad2_ net-_q3-pad3_ Q2N2222 +r5 net-_q3-pad3_ net-_d1-pad1_ 0.18k +r6 net-_q3-pad3_ net-_c1-pad2_ 20k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_c1-pad2_ net-_d1-pad1_ net-_q5-pad3_ Q2N2222 +r7 net-_q5-pad3_ net-_d1-pad2_ 1.0k +r8 net-_q10-pad1_ net-_c1-pad1_ 2.2k +q8 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad2_ Q2N2222 +q9 net-_d1-pad2_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q11 net-_q1-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q10-pad1_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r9 net-_q11-pad3_ net-_q10-pad3_ 5.0k +q12 net-_q1-pad1_ net-_q11-pad3_ net-_q10-pad2_ Q2N2222 +r10 net-_q10-pad2_ net-_q10-pad3_ 3.0 +r11 net-_q10-pad3_ net-_q6-pad2_ 2.0k +r12 net-_q6-pad2_ net-_d1-pad2_ 2.85k +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +* u2 net-_q10-pad3_ net-_d1-pad2_ net-_q1-pad1_ port +a1 net-_d1-pad2_ net-_q1-pad2_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch new file mode 100644 index 00000000..b86442f0 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sch @@ -0,0 +1,549 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:MC78L05-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R1 +U 1 1 6684EB64 +P 2750 1700 +F 0 "R1" H 2800 1830 50 0000 C CNN +F 1 "15k" H 2800 1650 50 0000 C CNN +F 2 "" H 2800 1680 30 0000 C CNN +F 3 "" V 2800 1750 30 0000 C CNN + 1 2750 1700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6684EB65 +P 3200 2300 +F 0 "Q1" H 3100 2350 50 0000 R CNN +F 1 "eSim_NPN" H 3150 2450 50 0000 R CNN +F 2 "" H 3400 2400 29 0000 C CNN +F 3 "" H 3200 2300 60 0000 C CNN + 1 3200 2300 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 6684EB66 +P 3250 2700 +F 0 "R2" H 3300 2830 50 0000 C CNN +F 1 "3.8k" H 3300 2650 50 0000 C CNN +F 2 "" H 3300 2680 30 0000 C CNN +F 3 "" V 3300 2750 30 0000 C CNN + 1 3250 2700 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 6684EB67 +P 3250 3400 +F 0 "R3" H 3300 3530 50 0000 C CNN +F 1 "1.2k" H 3300 3350 50 0000 C CNN +F 2 "" H 3300 3380 30 0000 C CNN +F 3 "" V 3300 3450 30 0000 C CNN + 1 3250 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6684EB68 +P 3250 4600 +F 0 "R4" H 3300 4730 50 0000 C CNN +F 1 "420" H 3300 4550 50 0000 C CNN +F 2 "" H 3300 4580 30 0000 C CNN +F 3 "" V 3300 4650 30 0000 C CNN + 1 3250 4600 + 0 1 1 0 +$EndComp +Wire Wire Line + 3300 2500 3300 2600 +Wire Wire Line + 3300 2900 3300 3300 +Wire Wire Line + 3300 3600 3300 4500 +$Comp +L zener U1 +U 1 1 6684EB69 +P 2800 3900 +F 0 "U1" H 2750 3800 60 0000 C CNN +F 1 "zener" H 2800 4000 60 0000 C CNN +F 2 "" H 2850 3900 60 0000 C CNN +F 3 "" H 2850 3900 60 0000 C CNN + 1 2800 3900 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2800 1900 2800 3600 +Wire Wire Line + 2800 4100 2800 5100 +Wire Wire Line + 2800 5100 8350 5100 +Wire Wire Line + 3300 5100 3300 4800 +$Comp +L eSim_PNP Q4 +U 1 1 6684EB6A +P 4700 1900 +F 0 "Q4" H 4600 1950 50 0000 R CNN +F 1 "eSim_PNP" H 4650 2050 50 0000 R CNN +F 2 "" H 4900 2000 29 0000 C CNN +F 3 "" H 4700 1900 60 0000 C CNN + 1 4700 1900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6684EB6B +P 5900 1900 +F 0 "Q7" H 5800 1950 50 0000 R CNN +F 1 "eSim_PNP" H 5850 2050 50 0000 R CNN +F 2 "" H 6100 2000 29 0000 C CNN +F 3 "" H 5900 1900 60 0000 C CNN + 1 5900 1900 + 1 0 0 1 +$EndComp +Wire Wire Line + 4900 1900 5700 1900 +$Comp +L eSim_NPN Q3 +U 1 1 6684EB6C +P 4200 3100 +F 0 "Q3" H 4100 3150 50 0000 R CNN +F 1 "eSim_NPN" H 4150 3250 50 0000 R CNN +F 2 "" H 4400 3200 29 0000 C CNN +F 3 "" H 4200 3100 60 0000 C CNN + 1 4200 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 3100 4000 3100 +Connection ~ 3300 3100 +$Comp +L eSim_NPN Q6 +U 1 1 6684EB6D +P 5300 3100 +F 0 "Q6" H 5200 3150 50 0000 R CNN +F 1 "eSim_NPN" H 5250 3250 50 0000 R CNN +F 2 "" H 5500 3200 29 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 1 5300 3100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4300 2900 5200 2900 +Wire Wire Line + 4600 2100 4600 2900 +Connection ~ 4600 2900 +Wire Wire Line + 5100 1900 5100 2400 +Wire Wire Line + 5100 2400 4600 2400 +Connection ~ 4600 2400 +Connection ~ 5100 1900 +$Comp +L resistor R5 +U 1 1 6684EB6E +P 4250 3500 +F 0 "R5" H 4300 3630 50 0000 C CNN +F 1 "0.18k" H 4300 3450 50 0000 C CNN +F 2 "" H 4300 3480 30 0000 C CNN +F 3 "" V 4300 3550 30 0000 C CNN + 1 4250 3500 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 6684EB6F +P 5150 3500 +F 0 "R6" H 5200 3630 50 0000 C CNN +F 1 "20k" H 5200 3450 50 0000 C CNN +F 2 "" H 5200 3480 30 0000 C CNN +F 3 "" V 5200 3550 30 0000 C CNN + 1 5150 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 4300 3300 4300 3400 +Wire Wire Line + 5200 3300 5200 3400 +Wire Wire Line + 4300 3350 5200 3350 +Connection ~ 5200 3350 +Connection ~ 4300 3350 +$Comp +L eSim_Diode D1 +U 1 1 6684EB70 +P 4300 4650 +F 0 "D1" H 4300 4750 50 0000 C CNN +F 1 "eSim_Diode" H 4300 4550 50 0000 C CNN +F 2 "" H 4300 4650 60 0000 C CNN +F 3 "" H 4300 4650 60 0000 C CNN + 1 4300 4650 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6684EB71 +P 5100 4300 +F 0 "Q5" H 5000 4350 50 0000 R CNN +F 1 "eSim_NPN" H 5050 4450 50 0000 R CNN +F 2 "" H 5300 4400 29 0000 C CNN +F 3 "" H 5100 4300 60 0000 C CNN + 1 5100 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4300 3700 4300 4500 +Wire Wire Line + 5200 3700 5200 4100 +Wire Wire Line + 4900 4300 4300 4300 +Connection ~ 4300 4300 +$Comp +L resistor R7 +U 1 1 6684EB72 +P 5150 4700 +F 0 "R7" H 5200 4830 50 0000 C CNN +F 1 "1.0k" H 5200 4650 50 0000 C CNN +F 2 "" H 5200 4680 30 0000 C CNN +F 3 "" V 5200 4750 30 0000 C CNN + 1 5150 4700 + 0 1 1 0 +$EndComp +Wire Wire Line + 5200 4600 5200 4500 +Wire Wire Line + 5200 5100 5200 4900 +Connection ~ 3300 5100 +Wire Wire Line + 4300 4800 4300 5100 +Connection ~ 4300 5100 +$Comp +L resistor R8 +U 1 1 6684EB73 +P 5950 3500 +F 0 "R8" H 6000 3630 50 0000 C CNN +F 1 "2.2k" H 6000 3450 50 0000 C CNN +F 2 "" H 6000 3480 30 0000 C CNN +F 3 "" V 6000 3550 30 0000 C CNN + 1 5950 3500 + 0 1 1 0 +$EndComp +Wire Wire Line + 6000 2100 6000 3400 +$Comp +L eSim_NPN Q8 +U 1 1 6684EB74 +P 5900 4100 +F 0 "Q8" H 5800 4150 50 0000 R CNN +F 1 "eSim_NPN" H 5850 4250 50 0000 R CNN +F 2 "" H 6100 4200 29 0000 C CNN +F 3 "" H 5900 4100 60 0000 C CNN + 1 5900 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5700 4100 +Wire Wire Line + 5250 4100 5250 4050 +Wire Wire Line + 5250 4050 5200 4050 +Connection ~ 5200 4050 +Wire Wire Line + 5500 3900 5500 4100 +Connection ~ 5500 4100 +Wire Wire Line + 6000 3700 6000 3900 +$Comp +L eSim_PNP Q9 +U 1 1 6684EB75 +P 6700 3800 +F 0 "Q9" H 6600 3850 50 0000 R CNN +F 1 "eSim_PNP" H 6650 3950 50 0000 R CNN +F 2 "" H 6900 3900 29 0000 C CNN +F 3 "" H 6700 3800 60 0000 C CNN + 1 6700 3800 + 1 0 0 1 +$EndComp +Wire Wire Line + 5800 3800 6500 3800 +Connection ~ 6000 3800 +Wire Wire Line + 5500 3600 5800 3600 +Wire Wire Line + 5800 3600 5800 3800 +Wire Wire Line + 6800 3600 6800 3200 +Wire Wire Line + 6800 3200 6000 3200 +Connection ~ 6000 3200 +Wire Wire Line + 6000 5100 6000 4300 +Connection ~ 5200 5100 +Connection ~ 6000 5100 +$Comp +L eSim_NPN Q11 +U 1 1 6684EB76 +P 7600 1900 +F 0 "Q11" H 7500 1950 50 0000 R CNN +F 1 "eSim_NPN" H 7550 2050 50 0000 R CNN +F 2 "" H 7800 2000 29 0000 C CNN +F 3 "" H 7600 1900 60 0000 C CNN + 1 7600 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6684EB77 +P 7200 2600 +F 0 "Q10" H 7100 2650 50 0000 R CNN +F 1 "eSim_NPN" H 7150 2750 50 0000 R CNN +F 2 "" H 7400 2700 29 0000 C CNN +F 3 "" H 7200 2600 60 0000 C CNN + 1 7200 2600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 6684EB78 +P 3700 4100 +F 0 "Q2" H 3600 4150 50 0000 R CNN +F 1 "eSim_NPN" H 3650 4250 50 0000 R CNN +F 2 "" H 3900 4200 29 0000 C CNN +F 3 "" H 3700 4100 60 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3300 4100 3500 4100 +Connection ~ 3300 4100 +Wire Wire Line + 3800 3900 3800 2650 +Wire Wire Line + 3800 2650 6400 2650 +Connection ~ 6000 2650 +Wire Wire Line + 6400 1900 7400 1900 +Wire Wire Line + 6400 2650 6400 1900 +$Comp +L resistor R9 +U 1 1 6684EB79 +P 7650 2900 +F 0 "R9" H 7700 3030 50 0000 C CNN +F 1 "5.0k" H 7700 2850 50 0000 C CNN +F 2 "" H 7700 2880 30 0000 C CNN +F 3 "" V 7700 2950 30 0000 C CNN + 1 7650 2900 + 0 1 1 0 +$EndComp +Wire Wire Line + 7700 2100 7700 2800 +$Comp +L eSim_NPN Q12 +U 1 1 6684EB7A +P 8200 2300 +F 0 "Q12" H 8100 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8150 2450 50 0000 R CNN +F 2 "" H 8400 2400 29 0000 C CNN +F 3 "" H 8200 2300 60 0000 C CNN + 1 8200 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8000 2300 7700 2300 +Connection ~ 7700 2300 +$Comp +L resistor R10 +U 1 1 6684EB7B +P 8250 2800 +F 0 "R10" H 8300 2930 50 0000 C CNN +F 1 "3.0" H 8300 2750 50 0000 C CNN +F 2 "" H 8300 2780 30 0000 C CNN +F 3 "" V 8300 2850 30 0000 C CNN + 1 8250 2800 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 6684EB7C +P 8250 3400 +F 0 "R11" H 8300 3530 50 0000 C CNN +F 1 "2.0k" H 8300 3350 50 0000 C CNN +F 2 "" H 8300 3380 30 0000 C CNN +F 3 "" V 8300 3450 30 0000 C CNN + 1 8250 3400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8300 2500 8300 2700 +Wire Wire Line + 8300 3000 8300 3300 +Wire Wire Line + 7400 2600 8300 2600 +Connection ~ 8300 2600 +Wire Wire Line + 7100 2800 7100 3200 +Wire Wire Line + 7100 3200 9000 3200 +Connection ~ 8300 3200 +Wire Wire Line + 7700 3100 7700 3200 +Connection ~ 7700 3200 +$Comp +L resistor R12 +U 1 1 6684EB7D +P 8250 4400 +F 0 "R12" H 8300 4530 50 0000 C CNN +F 1 "2.85k" H 8300 4350 50 0000 C CNN +F 2 "" H 8300 4380 30 0000 C CNN +F 3 "" V 8300 4450 30 0000 C CNN + 1 8250 4400 + 0 1 1 0 +$EndComp +Wire Wire Line + 8300 3600 8300 4300 +Wire Wire Line + 8300 5100 8300 4600 +Connection ~ 6800 5100 +Wire Wire Line + 8300 1300 8300 2100 +Wire Wire Line + 2800 1400 8300 1400 +Wire Wire Line + 2800 1400 2800 1600 +Wire Wire Line + 7700 1700 7700 1400 +Connection ~ 7700 1400 +Wire Wire Line + 6000 1700 6000 1400 +Connection ~ 6000 1400 +Wire Wire Line + 4600 1700 4600 1400 +Connection ~ 4600 1400 +Wire Wire Line + 3300 2100 3300 1400 +Connection ~ 3300 1400 +Wire Wire Line + 3000 2300 2800 2300 +Connection ~ 2800 2300 +Wire Wire Line + 5500 3100 7000 3100 +Wire Wire Line + 7000 3100 7000 3700 +Wire Wire Line + 7000 3700 8300 3700 +Connection ~ 8300 3700 +Wire Wire Line + 3800 4300 3800 5100 +Connection ~ 3800 5100 +Wire Wire Line + 7100 1900 7100 2400 +Connection ~ 7100 1900 +Wire Wire Line + 8300 1300 9100 1300 +Connection ~ 8300 1400 +$Comp +L capacitor_polarised C1 +U 1 1 6684EB83 +P 5500 3750 +F 0 "C1" H 5525 3850 50 0000 L CNN +F 1 "5p" H 5525 3650 50 0000 L CNN +F 2 "" H 5500 3750 50 0001 C CNN +F 3 "" H 5500 3750 50 0001 C CNN + 1 5500 3750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6800 4000 6800 5100 +Wire Wire Line + 8350 5100 8350 5250 +Connection ~ 8300 5100 +$Comp +L PORT U2 +U 1 1 6684ECD2 +P 9250 3200 +F 0 "U2" H 9300 3300 30 0000 C CNN +F 1 "PORT" H 9250 3200 30 0000 C CNN +F 2 "" H 9250 3200 60 0000 C CNN +F 3 "" H 9250 3200 60 0000 C CNN + 1 9250 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U2 +U 2 1 6684F14A +P 8350 5500 +F 0 "U2" H 8400 5600 30 0000 C CNN +F 1 "PORT" H 8350 5500 30 0000 C CNN +F 2 "" H 8350 5500 60 0000 C CNN +F 3 "" H 8350 5500 60 0000 C CNN + 2 8350 5500 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U2 +U 3 1 6684F492 +P 9350 1300 +F 0 "U2" H 9400 1400 30 0000 C CNN +F 1 "PORT" H 9350 1300 30 0000 C CNN +F 2 "" H 9350 1300 60 0000 C CNN +F 3 "" H 9350 1300 60 0000 C CNN + 3 9350 1300 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub new file mode 100644 index 00000000..4c0d6df5 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC.sub @@ -0,0 +1,39 @@ +* Subcircuit MC78L05_IC +.subckt MC78L05_IC net-_q10-pad3_ net-_d1-pad2_ net-_q1-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\mc78l05_ic\mc78l05_ic.cir +.include PNP.lib +.include D.lib +.include NPN.lib +r1 net-_q1-pad1_ net-_q1-pad2_ 15k +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r2 net-_q1-pad3_ net-_q3-pad2_ 3.8k +r3 net-_q3-pad2_ net-_q2-pad2_ 1.2k +r4 net-_q2-pad2_ net-_d1-pad2_ 420 +* u1 net-_d1-pad2_ net-_q1-pad2_ zener +q4 net-_q3-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q7 net-_q10-pad1_ net-_q3-pad1_ net-_q1-pad1_ Q2N2907A +q3 net-_q3-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q3-pad1_ net-_q6-pad2_ net-_q3-pad3_ Q2N2222 +r5 net-_q3-pad3_ net-_d1-pad1_ 0.18k +r6 net-_q3-pad3_ net-_c1-pad2_ 20k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_c1-pad2_ net-_d1-pad1_ net-_q5-pad3_ Q2N2222 +r7 net-_q5-pad3_ net-_d1-pad2_ 1.0k +r8 net-_q10-pad1_ net-_c1-pad1_ 2.2k +q8 net-_c1-pad1_ net-_c1-pad2_ net-_d1-pad2_ Q2N2222 +q9 net-_d1-pad2_ net-_c1-pad1_ net-_q10-pad1_ Q2N2907A +q11 net-_q1-pad1_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q10-pad1_ net-_q2-pad2_ net-_d1-pad2_ Q2N2222 +r9 net-_q11-pad3_ net-_q10-pad3_ 5.0k +q12 net-_q1-pad1_ net-_q11-pad3_ net-_q10-pad2_ Q2N2222 +r10 net-_q10-pad2_ net-_q10-pad3_ 3.0 +r11 net-_q10-pad3_ net-_q6-pad2_ 2.0k +r12 net-_q6-pad2_ net-_d1-pad2_ 2.85k +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +a1 net-_d1-pad2_ net-_q1-pad2_ u1 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends MC78L05_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml new file mode 100644 index 00000000..4f54bdf7 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/MC78L05_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u1 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u1></model><devicemodel><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC78L05_sub/NPN.lib b/library/SubcircuitLibrary/MC78L05_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC78L05_sub/PNP.lib b/library/SubcircuitLibrary/MC78L05_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/MC78L05_sub/analysis b/library/SubcircuitLibrary/MC78L05_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC78L05_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..895e7634 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:44:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 500 +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 60k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 10k +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 10k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..2c658aae --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..99c63cf9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "500" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "60k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "10k" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "10k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..544c5e10 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/OP497/D.lib b/library/SubcircuitLibrary/OP497/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/OP497/NPN.lib b/library/SubcircuitLibrary/OP497/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib b/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib new file mode 100644 index 00000000..76ef5bfc --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir new file mode 100644 index 00000000..3e749818 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir @@ -0,0 +1,46 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\OP497_Subcircuit\OP497_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/04/25 21:20:34
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q12-Pad1_ 2.5k
+Q1 Net-_Q1-Pad1_ ? Net-_Q1-Pad3_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q1-Pad3_ Net-_Q12-Pad1_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q12-Pad1_ Net-_C3-Pad2_ eSim_NPN
+R2 Net-_R2-Pad1_ Net-_Q1-Pad3_ 2.5k
+R3 Net-_Q1-Pad1_ Net-_Q7-Pad3_ 10k
+Q6 Net-_Q5-Pad3_ Net-_Q1-Pad3_ Net-_C3-Pad2_ eSim_NPN
+Q4 Net-_C1-Pad2_ Net-_C1-Pad1_ Net-_Q3-Pad1_ eSim_NPN
+Q5 Net-_C2-Pad1_ Net-_C1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+R4 Net-_C1-Pad1_ Net-_C1-Pad2_ 10k
+R5 Net-_C1-Pad1_ Net-_C2-Pad1_ 10k
+Q8 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q7-Pad3_ eSim_NPN
+Q7 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_Q7-Pad3_ eSim_PNP
+Q9 Net-_Q10-Pad3_ Net-_Q14-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q10 Net-_Q1-Pad3_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q12 Net-_Q12-Pad1_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q14 Net-_Q14-Pad1_ Net-_C3-Pad2_ Net-_Q10-Pad3_ eSim_PNP
+Q11 Net-_Q10-Pad3_ Net-_C3-Pad2_ Net-_C1-Pad1_ eSim_PNP
+Q13 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_C1-Pad1_ eSim_PNP
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10nF
+Q15 Net-_Q15-Pad1_ Net-_C1-Pad2_ Net-_C1-Pad1_ eSim_PNP
+Q18 Net-_C3-Pad1_ Net-_C2-Pad1_ Net-_C1-Pad1_ eSim_PNP
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+R6 Net-_C2-Pad2_ Net-_C3-Pad1_ 10k
+D1 Net-_C1-Pad1_ Net-_D1-Pad2_ eSim_Diode
+D2 Net-_D1-Pad2_ Net-_C3-Pad2_ eSim_Diode
+Q16 Net-_Q15-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q17 Net-_C3-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad2_ eSim_NPN
+C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10nF
+Q19 Net-_Q19-Pad1_ Net-_C3-Pad1_ Net-_C3-Pad2_ eSim_NPN
+Q21 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_D3-Pad2_ eSim_PNP
+Q23 Net-_C3-Pad2_ Net-_C3-Pad2_ Net-_Q22-Pad3_ eSim_PNP
+D3 Net-_C1-Pad1_ Net-_D3-Pad2_ eSim_Diode
+Q20 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q19-Pad1_ eSim_NPN
+Q22 Net-_C1-Pad1_ Net-_C1-Pad1_ Net-_Q22-Pad3_ eSim_NPN
+U1 Net-_R1-Pad1_ Net-_R2-Pad1_ Net-_Q22-Pad3_ Net-_C1-Pad1_ Net-_C3-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out new file mode 100644 index 00000000..869eda86 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.cir.out @@ -0,0 +1,50 @@ +* c:\fossee\esim\library\subcircuitlibrary\op497_subcircuit\op497_subcircuit.cir
+
+.include NPN.lib
+.include PNP.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q12-pad1_ 2.5k
+q1 net-_q1-pad1_ ? net-_q1-pad3_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad3_ net-_q12-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q12-pad1_ net-_c3-pad2_ Q2N2222
+r2 net-_r2-pad1_ net-_q1-pad3_ 2.5k
+r3 net-_q1-pad1_ net-_q7-pad3_ 10k
+q6 net-_q5-pad3_ net-_q1-pad3_ net-_c3-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_q3-pad1_ Q2N2222
+q5 net-_c2-pad1_ net-_c1-pad1_ net-_q5-pad3_ Q2N2222
+r4 net-_c1-pad1_ net-_c1-pad2_ 10k
+r5 net-_c1-pad1_ net-_c2-pad1_ 10k
+q8 net-_c1-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222
+q7 net-_c3-pad2_ net-_c3-pad2_ net-_q7-pad3_ Q2N2907A
+q9 net-_q10-pad3_ net-_q14-pad1_ net-_c3-pad2_ Q2N2222
+q10 net-_q1-pad3_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q12 net-_q12-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q14 net-_q14-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad3_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+q13 net-_c3-pad2_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q15 net-_q15-pad1_ net-_c1-pad2_ net-_c1-pad1_ Q2N2907A
+q18 net-_c3-pad1_ net-_c2-pad1_ net-_c1-pad1_ Q2N2907A
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r6 net-_c2-pad2_ net-_c3-pad1_ 10k
+d1 net-_c1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c3-pad2_ 1N4148
+q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+q17 net-_c3-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+c3 net-_c3-pad1_ net-_c3-pad2_ 10uf
+q19 net-_q19-pad1_ net-_c3-pad1_ net-_c3-pad2_ Q2N2222
+q21 net-_c3-pad2_ net-_c3-pad2_ net-_d3-pad2_ Q2N2907A
+q23 net-_c3-pad2_ net-_c3-pad2_ net-_q22-pad3_ Q2N2907A
+d3 net-_c1-pad1_ net-_d3-pad2_ 1N4148
+q20 net-_c1-pad1_ net-_c1-pad1_ net-_q19-pad1_ Q2N2222
+q22 net-_c1-pad1_ net-_c1-pad1_ net-_q22-pad3_ Q2N2222
+* u1 net-_r1-pad1_ net-_r2-pad1_ net-_c1-pad1_ net-_c3-pad2_ net-_q22-pad3_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch new file mode 100644 index 00000000..4f39bc9c --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sch @@ -0,0 +1,801 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:OP497_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 679F6A14
+P 1680 3080
+F 0 "R1" H 1730 3210 50 0000 C CNN
+F 1 "2.5k" H 1730 3030 50 0000 C CNN
+F 2 "" H 1730 3060 30 0000 C CNN
+F 3 "" V 1730 3130 30 0000 C CNN
+ 1 1680 3080
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 679F6B29
+P 2200 3240
+F 0 "Q1" H 2100 3290 50 0000 R CNN
+F 1 "eSim_NPN" H 2150 3390 50 0000 R CNN
+F 2 "" H 2400 3340 29 0000 C CNN
+F 3 "" H 2200 3240 60 0000 C CNN
+ 1 2200 3240
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 679F6B86
+P 2460 3680
+F 0 "Q2" H 2360 3730 50 0000 R CNN
+F 1 "eSim_NPN" H 2410 3830 50 0000 R CNN
+F 2 "" H 2660 3780 29 0000 C CNN
+F 3 "" H 2460 3680 60 0000 C CNN
+ 1 2460 3680
+ 0 1 -1 0
+$EndComp
+$Comp
+L eSim_NPN Q3
+U 1 1 679F6C10
+P 2970 3030
+F 0 "Q3" H 2870 3080 50 0000 R CNN
+F 1 "eSim_NPN" H 2920 3180 50 0000 R CNN
+F 2 "" H 3170 3130 29 0000 C CNN
+F 3 "" H 2970 3030 60 0000 C CNN
+ 1 2970 3030
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 679F6C82
+P 1700 3630
+F 0 "R2" H 1750 3760 50 0000 C CNN
+F 1 "2.5k" H 1750 3580 50 0000 C CNN
+F 2 "" H 1750 3610 30 0000 C CNN
+F 3 "" V 1750 3680 30 0000 C CNN
+ 1 1700 3630
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R3
+U 1 1 67A21583
+P 2850 3470
+F 0 "R3" H 2900 3600 50 0000 C CNN
+F 1 "10k" H 2900 3420 50 0000 C CNN
+F 2 "" H 2900 3450 30 0000 C CNN
+F 3 "" V 2900 3520 30 0000 C CNN
+ 1 2850 3470
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 67A215FD
+P 3850 3030
+F 0 "Q6" H 3750 3080 50 0000 R CNN
+F 1 "eSim_NPN" H 3800 3180 50 0000 R CNN
+F 2 "" H 4050 3130 29 0000 C CNN
+F 3 "" H 3850 3030 60 0000 C CNN
+ 1 3850 3030
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 67A216BC
+P 3170 2530
+F 0 "Q4" H 3070 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 3120 2680 50 0000 R CNN
+F 2 "" H 3370 2630 29 0000 C CNN
+F 3 "" H 3170 2530 60 0000 C CNN
+ 1 3170 2530
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 67A21748
+P 3650 2530
+F 0 "Q5" H 3550 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 3600 2680 50 0000 R CNN
+F 2 "" H 3850 2630 29 0000 C CNN
+F 3 "" H 3650 2530 60 0000 C CNN
+ 1 3650 2530
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67A21A6B
+P 3020 1770
+F 0 "R4" H 3070 1900 50 0000 C CNN
+F 1 "10k" H 3070 1720 50 0000 C CNN
+F 2 "" H 3070 1750 30 0000 C CNN
+F 3 "" V 3070 1820 30 0000 C CNN
+ 1 3020 1770
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67A21AD4
+P 3700 1770
+F 0 "R5" H 3750 1900 50 0000 C CNN
+F 1 "10k" H 3750 1720 50 0000 C CNN
+F 2 "" H 3750 1750 30 0000 C CNN
+F 3 "" V 3750 1820 30 0000 C CNN
+ 1 3700 1770
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 67A21C5A
+P 4260 2530
+F 0 "Q8" H 4160 2580 50 0000 R CNN
+F 1 "eSim_NPN" H 4210 2680 50 0000 R CNN
+F 2 "" H 4460 2630 29 0000 C CNN
+F 3 "" H 4260 2530 60 0000 C CNN
+ 1 4260 2530
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q7
+U 1 1 67A21DA2
+P 3970 4290
+F 0 "Q7" H 3870 4340 50 0000 R CNN
+F 1 "eSim_PNP" H 3920 4440 50 0000 R CNN
+F 2 "" H 4170 4390 29 0000 C CNN
+F 3 "" H 3970 4290 60 0000 C CNN
+ 1 3970 4290
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 67A21DFE
+P 4490 4100
+F 0 "Q9" H 4390 4150 50 0000 R CNN
+F 1 "eSim_NPN" H 4440 4250 50 0000 R CNN
+F 2 "" H 4690 4200 29 0000 C CNN
+F 3 "" H 4490 4100 60 0000 C CNN
+ 1 4490 4100
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q10
+U 1 1 67A220BA
+P 4950 3400
+F 0 "Q10" H 4850 3450 50 0000 R CNN
+F 1 "eSim_PNP" H 4900 3550 50 0000 R CNN
+F 2 "" H 5150 3500 29 0000 C CNN
+F 3 "" H 4950 3400 60 0000 C CNN
+ 1 4950 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q12
+U 1 1 67A221C2
+P 5380 3390
+F 0 "Q12" H 5280 3440 50 0000 R CNN
+F 1 "eSim_PNP" H 5330 3540 50 0000 R CNN
+F 2 "" H 5580 3490 29 0000 C CNN
+F 3 "" H 5380 3390 60 0000 C CNN
+ 1 5380 3390
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q14
+U 1 1 67A22250
+P 5810 3380
+F 0 "Q14" H 5710 3430 50 0000 R CNN
+F 1 "eSim_PNP" H 5760 3530 50 0000 R CNN
+F 2 "" H 6010 3480 29 0000 C CNN
+F 3 "" H 5810 3380 60 0000 C CNN
+ 1 5810 3380
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q11
+U 1 1 67A2261A
+P 5370 2750
+F 0 "Q11" H 5270 2800 50 0000 R CNN
+F 1 "eSim_PNP" H 5320 2900 50 0000 R CNN
+F 2 "" H 5570 2850 29 0000 C CNN
+F 3 "" H 5370 2750 60 0000 C CNN
+ 1 5370 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q13
+U 1 1 67A22620
+P 5800 2740
+F 0 "Q13" H 5700 2790 50 0000 R CNN
+F 1 "eSim_PNP" H 5750 2890 50 0000 R CNN
+F 2 "" H 6000 2840 29 0000 C CNN
+F 3 "" H 5800 2740 60 0000 C CNN
+ 1 5800 2740
+ -1 0 0 1
+$EndComp
+$Comp
+L capacitor C1
+U 1 1 67A2272A
+P 5430 1840
+F 0 "C1" H 5455 1940 50 0000 L CNN
+F 1 "10nF" H 5455 1740 50 0000 L CNN
+F 2 "" H 5468 1690 30 0000 C CNN
+F 3 "" H 5430 1840 60 0000 C CNN
+ 1 5430 1840
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_PNP Q15
+U 1 1 67A22875
+P 6960 2230
+F 0 "Q15" H 6860 2280 50 0000 R CNN
+F 1 "eSim_PNP" H 6910 2380 50 0000 R CNN
+F 2 "" H 7160 2330 29 0000 C CNN
+F 3 "" H 6960 2230 60 0000 C CNN
+ 1 6960 2230
+ 1 0 0 1
+$EndComp
+$Comp
+L eSim_PNP Q18
+U 1 1 67A22B87
+P 7930 2230
+F 0 "Q18" H 7830 2280 50 0000 R CNN
+F 1 "eSim_PNP" H 7880 2380 50 0000 R CNN
+F 2 "" H 8130 2330 29 0000 C CNN
+F 3 "" H 7930 2230 60 0000 C CNN
+ 1 7930 2230
+ -1 0 0 1
+$EndComp
+$Comp
+L capacitor C2
+U 1 1 67A22C9D
+P 7460 2650
+F 0 "C2" H 7485 2750 50 0000 L CNN
+F 1 "10pF" H 7485 2550 50 0000 L CNN
+F 2 "" H 7498 2500 30 0000 C CNN
+F 3 "" H 7460 2650 60 0000 C CNN
+ 1 7460 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 67A22D3A
+P 7410 3080
+F 0 "R6" H 7460 3210 50 0000 C CNN
+F 1 "10k" H 7460 3030 50 0000 C CNN
+F 2 "" H 7460 3060 30 0000 C CNN
+F 3 "" V 7460 3130 30 0000 C CNN
+ 1 7410 3080
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 67A23102
+P 6490 2720
+F 0 "D1" H 6490 2820 50 0000 C CNN
+F 1 "eSim_Diode" H 6490 2620 50 0000 C CNN
+F 2 "" H 6490 2720 60 0000 C CNN
+F 3 "" H 6490 2720 60 0000 C CNN
+ 1 6490 2720
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 67A232E0
+P 6490 3080
+F 0 "D2" H 6490 3180 50 0000 C CNN
+F 1 "eSim_Diode" H 6490 2980 50 0000 C CNN
+F 2 "" H 6490 3080 60 0000 C CNN
+F 3 "" H 6490 3080 60 0000 C CNN
+ 1 6490 3080
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q16
+U 1 1 67A23B3C
+P 7160 3870
+F 0 "Q16" H 7060 3920 50 0000 R CNN
+F 1 "eSim_NPN" H 7110 4020 50 0000 R CNN
+F 2 "" H 7360 3970 29 0000 C CNN
+F 3 "" H 7160 3870 60 0000 C CNN
+ 1 7160 3870
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 67A23DFE
+P 7660 3870
+F 0 "Q17" H 7560 3920 50 0000 R CNN
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+F 2 "" H 7860 3970 29 0000 C CNN
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+$EndComp
+$Comp
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+$Comp
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+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+ 1 9370 3310
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+$Comp
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+$Comp
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+$Comp
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+F 2 "" H 10720 3140 60 0000 C CNN
+F 3 "" H 10720 3140 60 0000 C CNN
+ 3 10720 3140
+ -1 0 0 1
+$EndComp
+$Comp
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+F 1 "PORT" H 10220 1590 30 0000 C CNN
+F 2 "" H 10220 1590 60 0000 C CNN
+F 3 "" H 10220 1590 60 0000 C CNN
+ 4 10220 1590
+ -1 0 0 1
+$EndComp
+$Comp
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+U 5 1 67A3DE72
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+F 0 "U1" H 10380 5080 30 0000 C CNN
+F 1 "PORT" H 10330 4980 30 0000 C CNN
+F 2 "" H 10330 4980 60 0000 C CNN
+F 3 "" H 10330 4980 60 0000 C CNN
+ 5 10330 4980
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+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub new file mode 100644 index 00000000..9b3289d6 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit.sub @@ -0,0 +1,44 @@ +* Subcircuit OP497_Subcircuit
+.subckt OP497_Subcircuit net-_r1-pad1_ net-_r2-pad1_ net-_c1-pad1_ net-_c3-pad2_ net-_q22-pad3_
+* c:\fossee\esim\library\subcircuitlibrary\op497_subcircuit\op497_subcircuit.cir
+.include NPN.lib
+.include PNP.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q12-pad1_ 2.5k
+q1 net-_q1-pad1_ ? net-_q1-pad3_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad3_ net-_q12-pad1_ Q2N2222
+q3 net-_q3-pad1_ net-_q12-pad1_ net-_c3-pad2_ Q2N2222
+r2 net-_r2-pad1_ net-_q1-pad3_ 2.5k
+r3 net-_q1-pad1_ net-_q7-pad3_ 10k
+q6 net-_q5-pad3_ net-_q1-pad3_ net-_c3-pad2_ Q2N2222
+q4 net-_c1-pad2_ net-_c1-pad1_ net-_q3-pad1_ Q2N2222
+q5 net-_c2-pad1_ net-_c1-pad1_ net-_q5-pad3_ Q2N2222
+r4 net-_c1-pad1_ net-_c1-pad2_ 10k
+r5 net-_c1-pad1_ net-_c2-pad1_ 10k
+q8 net-_c1-pad1_ net-_c1-pad1_ net-_q7-pad3_ Q2N2222
+q7 net-_c3-pad2_ net-_c3-pad2_ net-_q7-pad3_ Q2N2907A
+q9 net-_q10-pad3_ net-_q14-pad1_ net-_c3-pad2_ Q2N2222
+q10 net-_q1-pad3_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q12 net-_q12-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q14 net-_q14-pad1_ net-_c3-pad2_ net-_q10-pad3_ Q2N2907A
+q11 net-_q10-pad3_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+q13 net-_c3-pad2_ net-_c3-pad2_ net-_c1-pad1_ Q2N2907A
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+q15 net-_q15-pad1_ net-_c1-pad2_ net-_c1-pad1_ Q2N2907A
+q18 net-_c3-pad1_ net-_c2-pad1_ net-_c1-pad1_ Q2N2907A
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r6 net-_c2-pad2_ net-_c3-pad1_ 10k
+d1 net-_c1-pad1_ net-_d1-pad2_ 1N4148
+d2 net-_d1-pad2_ net-_c3-pad2_ 1N4148
+q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+q17 net-_c3-pad1_ net-_q15-pad1_ net-_c3-pad2_ Q2N2222
+c3 net-_c3-pad1_ net-_c3-pad2_ 10uf
+q19 net-_q19-pad1_ net-_c3-pad1_ net-_c3-pad2_ Q2N2222
+q21 net-_c3-pad2_ net-_c3-pad2_ net-_d3-pad2_ Q2N2907A
+q23 net-_c3-pad2_ net-_c3-pad2_ net-_q22-pad3_ Q2N2907A
+d3 net-_c1-pad1_ net-_d3-pad2_ 1N4148
+q20 net-_c1-pad1_ net-_c1-pad1_ net-_q19-pad1_ Q2N2222
+q22 net-_c1-pad1_ net-_c1-pad1_ net-_q22-pad3_ Q2N2222
+* Control Statements
+
+.ends OP497_Subcircuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml new file mode 100644 index 00000000..bb0cc8b7 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/OP497_Subcircuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q14><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q11><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q18><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/OP497/PNP.lib b/library/SubcircuitLibrary/OP497/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/OP497/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/OP497/analysis b/library/SubcircuitLibrary/OP497/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/OP497/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/D.lib b/library/SubcircuitLibrary/RC4559N_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/RC4559N_sub/NJF.lib b/library/SubcircuitLibrary/RC4559N_sub/NJF.lib new file mode 100644 index 00000000..dbb2cbae --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/RC4559N_sub/NPN.lib b/library/SubcircuitLibrary/RC4559N_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/RC4559N_sub/PNP.lib b/library/SubcircuitLibrary/RC4559N_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib new file mode 100644 index 00000000..3dddd3f6 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC-cache.lib @@ -0,0 +1,182 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir new file mode 100644 index 00000000..4209920b --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir @@ -0,0 +1,67 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\RC4559N_IC\RC4559N_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 18:31:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 Net-_J1-Pad3_ Net-_Q3-Pad3_ 8.7k +Q3 Net-_Q1-Pad3_ Net-_Q13-Pad1_ Net-_Q3-Pad3_ eSim_PNP +Q5 Net-_C2-Pad2_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad1_ eSim_NPN +Q4 Net-_C2-Pad2_ Net-_Q1-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R2 Net-_C1-Pad1_ Net-_C1-Pad2_ 5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 15p +R4 Net-_Q4-Pad3_ Net-_C1-Pad2_ 5k +Q9 Net-_Q10-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad3_ eSim_PNP +Q11 Net-_J1-Pad3_ Net-_Q10-Pad1_ Net-_Q11-Pad3_ eSim_NPN +Q7 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad2_ eSim_NPN +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_C2-Pad1_ eSim_NPN +R7 Net-_Q10-Pad2_ Net-_C2-Pad1_ 50k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 15p +D1 Net-_C2-Pad2_ Net-_C2-Pad1_ eSim_Diode +Q6 Net-_J1-Pad3_ Net-_C2-Pad2_ Net-_Q6-Pad3_ eSim_NPN +R6 Net-_Q6-Pad3_ Net-_C1-Pad2_ 50k +R8 Net-_Q11-Pad3_ Net-_R10-Pad2_ 27 +R9 Net-_R10-Pad2_ Net-_Q12-Pad3_ 27 +Q12 Net-_C1-Pad2_ Net-_C2-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q8 Net-_C2-Pad1_ Net-_Q6-Pad3_ Net-_C1-Pad2_ eSim_NPN +Q14 Net-_Q13-Pad1_ Net-_J1-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R11 Net-_Q14-Pad3_ Net-_C1-Pad2_ 5.8k +J1 Net-_J1-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad3_ jfet_n +U2 Net-_C1-Pad2_ Net-_J1-Pad1_ zener +R10 Net-_R10-Pad1_ Net-_R10-Pad2_ 120 +R14 Net-_J1-Pad3_ Net-_Q17-Pad3_ 8.7k +Q17 Net-_Q15-Pad3_ Net-_Q17-Pad2_ Net-_Q17-Pad3_ eSim_PNP +Q19 Net-_C4-Pad2_ Net-_Q19-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q16 Net-_Q15-Pad1_ Net-_Q15-Pad1_ Net-_C3-Pad1_ eSim_NPN +Q18 Net-_C4-Pad2_ Net-_Q15-Pad1_ Net-_Q18-Pad3_ eSim_NPN +R13 Net-_C3-Pad1_ Net-_C1-Pad2_ 5k +C3 Net-_C3-Pad1_ Net-_C1-Pad2_ 15p +R15 Net-_Q18-Pad3_ Net-_C1-Pad2_ 5k +Q23 Net-_Q21-Pad1_ Net-_Q17-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q27 Net-_Q17-Pad2_ Net-_Q17-Pad2_ Net-_J1-Pad3_ eSim_PNP +Q25 Net-_J1-Pad3_ Net-_Q21-Pad1_ Net-_Q25-Pad3_ eSim_NPN +Q21 Net-_Q21-Pad1_ Net-_Q21-Pad1_ Net-_Q21-Pad3_ eSim_NPN +Q24 Net-_Q21-Pad1_ Net-_Q21-Pad3_ Net-_C4-Pad1_ eSim_NPN +R18 Net-_Q21-Pad3_ Net-_C4-Pad1_ 50k +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 15p +D2 Net-_C4-Pad2_ Net-_C4-Pad1_ eSim_Diode +Q20 Net-_J1-Pad3_ Net-_C4-Pad2_ Net-_Q20-Pad3_ eSim_NPN +R16 Net-_Q20-Pad3_ Net-_C1-Pad2_ 50k +R19 Net-_Q25-Pad3_ Net-_R19-Pad2_ 27 +R20 Net-_R19-Pad2_ Net-_Q26-Pad3_ 27 +Q26 Net-_C1-Pad2_ Net-_C4-Pad1_ Net-_Q26-Pad3_ eSim_PNP +Q22 Net-_C4-Pad1_ Net-_Q20-Pad3_ Net-_C1-Pad2_ eSim_NPN +Q28 Net-_Q17-Pad2_ Net-_J2-Pad1_ Net-_Q28-Pad3_ eSim_NPN +R22 Net-_Q28-Pad3_ Net-_C1-Pad2_ 5.8k +J2 Net-_J2-Pad1_ Net-_C1-Pad2_ Net-_J1-Pad3_ jfet_n +U3 Net-_C1-Pad2_ Net-_J2-Pad1_ zener +R21 Net-_R21-Pad1_ Net-_R19-Pad2_ 120 +U1 Net-_R10-Pad1_ Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_C1-Pad2_ Net-_Q19-Pad2_ Net-_Q15-Pad2_ Net-_R21-Pad1_ Net-_J1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out new file mode 100644 index 00000000..417a2f72 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.cir.out @@ -0,0 +1,78 @@ +* d:\fossee\esim\library\subcircuitlibrary\rc4559n_ic\rc4559n_ic.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +.include D.lib +r3 net-_j1-pad3_ net-_q3-pad3_ 8.7k +q3 net-_q1-pad3_ net-_q13-pad1_ net-_q3-pad3_ Q2N2907A +q5 net-_c2-pad2_ net-_q5-pad2_ net-_q1-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222 +q4 net-_c2-pad2_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +r2 net-_c1-pad1_ net-_c1-pad2_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 15p +r4 net-_q4-pad3_ net-_c1-pad2_ 5k +q9 net-_q10-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q11 net-_j1-pad3_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q7 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_c2-pad1_ Q2N2222 +r7 net-_q10-pad2_ net-_c2-pad1_ 50k +c2 net-_c2-pad1_ net-_c2-pad2_ 15p +d1 net-_c2-pad2_ net-_c2-pad1_ 1N4148 +q6 net-_j1-pad3_ net-_c2-pad2_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_c1-pad2_ 50k +r8 net-_q11-pad3_ net-_r10-pad2_ 27 +r9 net-_r10-pad2_ net-_q12-pad3_ 27 +q12 net-_c1-pad2_ net-_c2-pad1_ net-_q12-pad3_ Q2N2907A +q8 net-_c2-pad1_ net-_q6-pad3_ net-_c1-pad2_ Q2N2222 +q14 net-_q13-pad1_ net-_j1-pad1_ net-_q14-pad3_ Q2N2222 +r11 net-_q14-pad3_ net-_c1-pad2_ 5.8k +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u2 net-_c1-pad2_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 120 +r14 net-_j1-pad3_ net-_q17-pad3_ 8.7k +q17 net-_q15-pad3_ net-_q17-pad2_ net-_q17-pad3_ Q2N2907A +q19 net-_c4-pad2_ net-_q19-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q15-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad1_ Q2N2222 +q18 net-_c4-pad2_ net-_q15-pad1_ net-_q18-pad3_ Q2N2222 +r13 net-_c3-pad1_ net-_c1-pad2_ 5k +c3 net-_c3-pad1_ net-_c1-pad2_ 15p +r15 net-_q18-pad3_ net-_c1-pad2_ 5k +q23 net-_q21-pad1_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q27 net-_q17-pad2_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q25 net-_j1-pad3_ net-_q21-pad1_ net-_q25-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad1_ net-_q21-pad3_ Q2N2222 +q24 net-_q21-pad1_ net-_q21-pad3_ net-_c4-pad1_ Q2N2222 +r18 net-_q21-pad3_ net-_c4-pad1_ 50k +c4 net-_c4-pad1_ net-_c4-pad2_ 15p +d2 net-_c4-pad2_ net-_c4-pad1_ 1N4148 +q20 net-_j1-pad3_ net-_c4-pad2_ net-_q20-pad3_ Q2N2222 +r16 net-_q20-pad3_ net-_c1-pad2_ 50k +r19 net-_q25-pad3_ net-_r19-pad2_ 27 +r20 net-_r19-pad2_ net-_q26-pad3_ 27 +q26 net-_c1-pad2_ net-_c4-pad1_ net-_q26-pad3_ Q2N2907A +q22 net-_c4-pad1_ net-_q20-pad3_ net-_c1-pad2_ Q2N2222 +q28 net-_q17-pad2_ net-_j2-pad1_ net-_q28-pad3_ Q2N2222 +r22 net-_q28-pad3_ net-_c1-pad2_ 5.8k +j2 net-_j2-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u3 net-_c1-pad2_ net-_j2-pad1_ zener +r21 net-_r21-pad1_ net-_r19-pad2_ 120 +* u1 net-_r10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_c1-pad2_ net-_q19-pad2_ net-_q15-pad2_ net-_r21-pad1_ net-_j1-pad3_ port +a1 net-_c1-pad2_ net-_j1-pad1_ u2 +a2 net-_c1-pad2_ net-_j2-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch new file mode 100644 index 00000000..9133b092 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sch @@ -0,0 +1,1107 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:RC4559N_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R3 +U 1 1 66744C0E +P 8000 6800 +F 0 "R3" H 8050 6930 50 0000 C CNN +F 1 "8.7k" H 8050 6750 50 0000 C CNN +F 2 "" H 8050 6780 30 0000 C CNN +F 3 "" V 8050 6850 30 0000 C CNN + 1 8000 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 66744C0F +P 8150 7350 +F 0 "Q3" H 8050 7400 50 0000 R CNN +F 1 "eSim_PNP" H 8100 7500 50 0000 R CNN +F 2 "" H 8350 7450 29 0000 C CNN +F 3 "" H 8150 7350 60 0000 C CNN + 1 8150 7350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 66744C10 +P 8850 7950 +F 0 "Q5" H 8750 8000 50 0000 R CNN +F 1 "eSim_PNP" H 8800 8100 50 0000 R CNN +F 2 "" H 9050 8050 29 0000 C CNN +F 3 "" H 8850 7950 60 0000 C CNN + 1 8850 7950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 66744C11 +P 7650 7950 +F 0 "Q1" H 7550 8000 50 0000 R CNN +F 1 "eSim_PNP" H 7600 8100 50 0000 R CNN +F 2 "" H 7850 8050 29 0000 C CNN +F 3 "" H 7650 7950 60 0000 C CNN + 1 7650 7950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 66744C12 +P 7850 9600 +F 0 "Q2" H 7750 9650 50 0000 R CNN +F 1 "eSim_NPN" H 7800 9750 50 0000 R CNN +F 2 "" H 8050 9700 29 0000 C CNN +F 3 "" H 7850 9600 60 0000 C CNN + 1 7850 9600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 66744C13 +P 8650 9600 +F 0 "Q4" H 8550 9650 50 0000 R CNN +F 1 "eSim_NPN" H 8600 9750 50 0000 R CNN +F 2 "" H 8850 9700 29 0000 C CNN +F 3 "" H 8650 9600 60 0000 C CNN + 1 8650 9600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 66744C14 +P 7700 10150 +F 0 "R2" H 7750 10280 50 0000 C CNN +F 1 "5k" H 7750 10100 50 0000 C CNN +F 2 "" H 7750 10130 30 0000 C CNN +F 3 "" V 7750 10200 30 0000 C CNN + 1 7700 10150 + 0 1 1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 66744C15 +P 8250 10200 +F 0 "C1" H 8275 10300 50 0000 L CNN +F 1 "15p" H 8275 10100 50 0000 L CNN +F 2 "" H 8288 10050 30 0000 C CNN +F 3 "" H 8250 10200 60 0000 C CNN + 1 8250 10200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 66744C16 +P 8700 10100 +F 0 "R4" H 8750 10230 50 0000 C CNN +F 1 "5k" H 8750 10050 50 0000 C CNN +F 2 "" H 8750 10080 30 0000 C CNN +F 3 "" V 8750 10150 30 0000 C CNN + 1 8700 10100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 66744C17 +P 10850 7350 +F 0 "Q9" H 10750 7400 50 0000 R CNN +F 1 "eSim_PNP" H 10800 7500 50 0000 R CNN +F 2 "" H 11050 7450 29 0000 C CNN +F 3 "" H 10850 7350 60 0000 C CNN + 1 10850 7350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q13 +U 1 1 66744C18 +P 12500 7350 +F 0 "Q13" H 12400 7400 50 0000 R CNN +F 1 "eSim_PNP" H 12450 7500 50 0000 R CNN +F 2 "" H 12700 7450 29 0000 C CNN +F 3 "" H 12500 7350 60 0000 C CNN + 1 12500 7350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 66744C19 +P 11700 7900 +F 0 "Q11" H 11600 7950 50 0000 R CNN +F 1 "eSim_NPN" H 11650 8050 50 0000 R CNN +F 2 "" H 11900 8000 29 0000 C CNN +F 3 "" H 11700 7900 60 0000 C CNN + 1 11700 7900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 66744C1A +P 10400 8200 +F 0 "Q7" H 10300 8250 50 0000 R CNN +F 1 "eSim_NPN" H 10350 8350 50 0000 R CNN +F 2 "" H 10600 8300 29 0000 C CNN +F 3 "" H 10400 8200 60 0000 C CNN + 1 10400 8200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 66744C1B +P 10950 8600 +F 0 "Q10" H 10850 8650 50 0000 R CNN +F 1 "eSim_NPN" H 10900 8750 50 0000 R CNN +F 2 "" H 11150 8700 29 0000 C CNN +F 3 "" H 10950 8600 60 0000 C CNN + 1 10950 8600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 66744C1C +P 10250 9000 +F 0 "R7" H 10300 9130 50 0000 C CNN +F 1 "50k" H 10300 8950 50 0000 C CNN +F 2 "" H 10300 8980 30 0000 C CNN +F 3 "" V 10300 9050 30 0000 C CNN + 1 10250 9000 + 0 1 1 0 +$EndComp +$Comp +L capacitor C2 +U 1 1 66744C1D +P 9100 9100 +F 0 "C2" H 9125 9200 50 0000 L CNN +F 1 "15p" H 9125 9000 50 0000 L CNN +F 2 "" H 9138 8950 30 0000 C CNN +F 3 "" H 9100 9100 60 0000 C CNN + 1 9100 9100 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 66744C1E +P 9100 8850 +F 0 "D1" H 9100 8950 50 0000 C CNN +F 1 "eSim_Diode" H 9100 8750 50 0000 C CNN +F 2 "" H 9100 8850 60 0000 C CNN +F 3 "" H 9100 8850 60 0000 C CNN + 1 9100 8850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 66744C1F +P 9500 9350 +F 0 "Q6" H 9400 9400 50 0000 R CNN +F 1 "eSim_NPN" H 9450 9500 50 0000 R CNN +F 2 "" H 9700 9450 29 0000 C CNN +F 3 "" H 9500 9350 60 0000 C CNN + 1 9500 9350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 66744C20 +P 9550 10050 +F 0 "R6" H 9600 10180 50 0000 C CNN +F 1 "50k" H 9600 10000 50 0000 C CNN +F 2 "" H 9600 10030 30 0000 C CNN +F 3 "" V 9600 10100 30 0000 C CNN + 1 9550 10050 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 66744C21 +P 11750 8400 +F 0 "R8" H 11800 8530 50 0000 C CNN +F 1 "27" H 11800 8350 50 0000 C CNN +F 2 "" H 11800 8380 30 0000 C CNN +F 3 "" V 11800 8450 30 0000 C CNN + 1 11750 8400 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 66744C22 +P 11750 8900 +F 0 "R9" H 11800 9030 50 0000 C CNN +F 1 "27" H 11800 8850 50 0000 C CNN +F 2 "" H 11800 8880 30 0000 C CNN +F 3 "" V 11800 8950 30 0000 C CNN + 1 11750 8900 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 66744C23 +P 11700 9400 +F 0 "Q12" H 11600 9450 50 0000 R CNN +F 1 "eSim_PNP" H 11650 9550 50 0000 R CNN +F 2 "" H 11900 9500 29 0000 C CNN +F 3 "" H 11700 9400 60 0000 C CNN + 1 11700 9400 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 66744C24 +P 10800 9800 +F 0 "Q8" H 10700 9850 50 0000 R CNN +F 1 "eSim_NPN" H 10750 9950 50 0000 R CNN +F 2 "" H 11000 9900 29 0000 C CNN +F 3 "" H 10800 9800 60 0000 C CNN + 1 10800 9800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 66744C25 +P 12700 8850 +F 0 "Q14" H 12600 8900 50 0000 R CNN +F 1 "eSim_NPN" H 12650 9000 50 0000 R CNN +F 2 "" H 12900 8950 29 0000 C CNN +F 3 "" H 12700 8850 60 0000 C CNN + 1 12700 8850 + -1 0 0 -1 +$EndComp +$Comp +L resistor R11 +U 1 1 66744C26 +P 12550 9550 +F 0 "R11" H 12600 9680 50 0000 C CNN +F 1 "5.8k" H 12600 9500 50 0000 C CNN +F 2 "" H 12600 9530 30 0000 C CNN +F 3 "" V 12600 9600 30 0000 C CNN + 1 12550 9550 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J1 +U 1 1 66744C27 +P 13400 8200 +F 0 "J1" H 13300 8250 50 0000 R CNN +F 1 "jfet_n" H 13350 8350 50 0000 R CNN +F 2 "" H 13600 8300 29 0000 C CNN +F 3 "" H 13400 8200 60 0000 C CNN + 1 13400 8200 + -1 0 0 1 +$EndComp +$Comp +L zener U2 +U 1 1 66744C28 +P 13300 9250 +F 0 "U2" H 13250 9150 60 0000 C CNN +F 1 "zener" H 13300 9350 60 0000 C CNN +F 2 "" H 13350 9250 60 0000 C CNN +F 3 "" H 13350 9250 60 0000 C CNN + 1 13300 9250 + 0 1 -1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 66744C29 +P 12200 8650 +F 0 "R10" H 12250 8780 50 0000 C CNN +F 1 "120" H 12250 8600 50 0000 C CNN +F 2 "" H 12250 8630 30 0000 C CNN +F 3 "" V 12250 8700 30 0000 C CNN + 1 12200 8650 + -1 0 0 1 +$EndComp +$Comp +L resistor R14 +U 1 1 66744C2A +P 16200 7000 +F 0 "R14" H 16250 7130 50 0000 C CNN +F 1 "8.7k" H 16250 6950 50 0000 C CNN +F 2 "" H 16250 6980 30 0000 C CNN +F 3 "" V 16250 7050 30 0000 C CNN + 1 16200 7000 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 66744C2B +P 16350 7550 +F 0 "Q17" H 16250 7600 50 0000 R CNN +F 1 "eSim_PNP" H 16300 7700 50 0000 R CNN +F 2 "" H 16550 7650 29 0000 C CNN +F 3 "" H 16350 7550 60 0000 C CNN + 1 16350 7550 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 66744C2C +P 17050 8150 +F 0 "Q19" H 16950 8200 50 0000 R CNN +F 1 "eSim_PNP" H 17000 8300 50 0000 R CNN +F 2 "" H 17250 8250 29 0000 C CNN +F 3 "" H 17050 8150 60 0000 C CNN + 1 17050 8150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 66744C2D +P 15850 8150 +F 0 "Q15" H 15750 8200 50 0000 R CNN +F 1 "eSim_PNP" H 15800 8300 50 0000 R CNN +F 2 "" H 16050 8250 29 0000 C CNN +F 3 "" H 15850 8150 60 0000 C CNN + 1 15850 8150 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 66744C2E +P 16050 9800 +F 0 "Q16" H 15950 9850 50 0000 R CNN +F 1 "eSim_NPN" H 16000 9950 50 0000 R CNN +F 2 "" H 16250 9900 29 0000 C CNN +F 3 "" H 16050 9800 60 0000 C CNN + 1 16050 9800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 66744C2F +P 16850 9800 +F 0 "Q18" H 16750 9850 50 0000 R CNN +F 1 "eSim_NPN" H 16800 9950 50 0000 R CNN +F 2 "" H 17050 9900 29 0000 C CNN +F 3 "" H 16850 9800 60 0000 C CNN + 1 16850 9800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 66744C30 +P 15900 10350 +F 0 "R13" H 15950 10480 50 0000 C CNN +F 1 "5k" H 15950 10300 50 0000 C CNN +F 2 "" H 15950 10330 30 0000 C CNN +F 3 "" V 15950 10400 30 0000 C CNN + 1 15900 10350 + 0 1 1 0 +$EndComp +$Comp +L capacitor C3 +U 1 1 66744C31 +P 16450 10400 +F 0 "C3" H 16475 10500 50 0000 L CNN +F 1 "15p" H 16475 10300 50 0000 L CNN +F 2 "" H 16488 10250 30 0000 C CNN +F 3 "" H 16450 10400 60 0000 C CNN + 1 16450 10400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 66744C32 +P 16900 10300 +F 0 "R15" H 16950 10430 50 0000 C CNN +F 1 "5k" H 16950 10250 50 0000 C CNN +F 2 "" H 16950 10280 30 0000 C CNN +F 3 "" V 16950 10350 30 0000 C CNN + 1 16900 10300 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 66744C33 +P 19050 7550 +F 0 "Q23" H 18950 7600 50 0000 R CNN +F 1 "eSim_PNP" H 19000 7700 50 0000 R CNN +F 2 "" H 19250 7650 29 0000 C CNN +F 3 "" H 19050 7550 60 0000 C CNN + 1 19050 7550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q27 +U 1 1 66744C34 +P 20700 7550 +F 0 "Q27" H 20600 7600 50 0000 R CNN +F 1 "eSim_PNP" H 20650 7700 50 0000 R CNN +F 2 "" H 20900 7650 29 0000 C CNN +F 3 "" H 20700 7550 60 0000 C CNN + 1 20700 7550 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 66744C35 +P 19900 8100 +F 0 "Q25" H 19800 8150 50 0000 R CNN +F 1 "eSim_NPN" H 19850 8250 50 0000 R CNN +F 2 "" H 20100 8200 29 0000 C CNN +F 3 "" H 19900 8100 60 0000 C CNN + 1 19900 8100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 66744C36 +P 18600 8400 +F 0 "Q21" H 18500 8450 50 0000 R CNN +F 1 "eSim_NPN" H 18550 8550 50 0000 R CNN +F 2 "" H 18800 8500 29 0000 C CNN +F 3 "" H 18600 8400 60 0000 C CNN + 1 18600 8400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 66744C37 +P 19150 8800 +F 0 "Q24" H 19050 8850 50 0000 R CNN +F 1 "eSim_NPN" H 19100 8950 50 0000 R CNN +F 2 "" H 19350 8900 29 0000 C CNN +F 3 "" H 19150 8800 60 0000 C CNN + 1 19150 8800 + 1 0 0 -1 +$EndComp +$Comp +L resistor R18 +U 1 1 66744C38 +P 18450 9200 +F 0 "R18" H 18500 9330 50 0000 C CNN +F 1 "50k" H 18500 9150 50 0000 C CNN +F 2 "" H 18500 9180 30 0000 C CNN +F 3 "" V 18500 9250 30 0000 C CNN + 1 18450 9200 + 0 1 1 0 +$EndComp +$Comp +L capacitor C4 +U 1 1 66744C39 +P 17300 9300 +F 0 "C4" H 17325 9400 50 0000 L CNN +F 1 "15p" H 17325 9200 50 0000 L CNN +F 2 "" H 17338 9150 30 0000 C CNN +F 3 "" H 17300 9300 60 0000 C CNN + 1 17300 9300 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 66744C3A +P 17300 9050 +F 0 "D2" H 17300 9150 50 0000 C CNN +F 1 "eSim_Diode" H 17300 8950 50 0000 C CNN +F 2 "" H 17300 9050 60 0000 C CNN +F 3 "" H 17300 9050 60 0000 C CNN + 1 17300 9050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 66744C3B +P 17700 9550 +F 0 "Q20" H 17600 9600 50 0000 R CNN +F 1 "eSim_NPN" H 17650 9700 50 0000 R CNN +F 2 "" H 17900 9650 29 0000 C CNN +F 3 "" H 17700 9550 60 0000 C CNN + 1 17700 9550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 66744C3C +P 17750 10250 +F 0 "R16" H 17800 10380 50 0000 C CNN +F 1 "50k" H 17800 10200 50 0000 C CNN +F 2 "" H 17800 10230 30 0000 C CNN +F 3 "" V 17800 10300 30 0000 C CNN + 1 17750 10250 + 0 1 1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 66744C3D +P 19950 8600 +F 0 "R19" H 20000 8730 50 0000 C CNN +F 1 "27" H 20000 8550 50 0000 C CNN +F 2 "" H 20000 8580 30 0000 C CNN +F 3 "" V 20000 8650 30 0000 C CNN + 1 19950 8600 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 66744C3E +P 19950 9100 +F 0 "R20" H 20000 9230 50 0000 C CNN +F 1 "27" H 20000 9050 50 0000 C CNN +F 2 "" H 20000 9080 30 0000 C CNN +F 3 "" V 20000 9150 30 0000 C CNN + 1 19950 9100 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 66744C3F +P 19900 9600 +F 0 "Q26" H 19800 9650 50 0000 R CNN +F 1 "eSim_PNP" H 19850 9750 50 0000 R CNN +F 2 "" H 20100 9700 29 0000 C CNN +F 3 "" H 19900 9600 60 0000 C CNN + 1 19900 9600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q22 +U 1 1 66744C40 +P 19000 10000 +F 0 "Q22" H 18900 10050 50 0000 R CNN +F 1 "eSim_NPN" H 18950 10150 50 0000 R CNN +F 2 "" H 19200 10100 29 0000 C CNN +F 3 "" H 19000 10000 60 0000 C CNN + 1 19000 10000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q28 +U 1 1 66744C41 +P 20900 9050 +F 0 "Q28" H 20800 9100 50 0000 R CNN +F 1 "eSim_NPN" H 20850 9200 50 0000 R CNN +F 2 "" H 21100 9150 29 0000 C CNN +F 3 "" H 20900 9050 60 0000 C CNN + 1 20900 9050 + -1 0 0 -1 +$EndComp +$Comp +L resistor R22 +U 1 1 66744C42 +P 20750 9750 +F 0 "R22" H 20800 9880 50 0000 C CNN +F 1 "5.8k" H 20800 9700 50 0000 C CNN +F 2 "" H 20800 9730 30 0000 C CNN +F 3 "" V 20800 9800 30 0000 C CNN + 1 20750 9750 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J2 +U 1 1 66744C43 +P 21600 8400 +F 0 "J2" H 21500 8450 50 0000 R CNN +F 1 "jfet_n" H 21550 8550 50 0000 R CNN +F 2 "" H 21800 8500 29 0000 C CNN +F 3 "" H 21600 8400 60 0000 C CNN + 1 21600 8400 + -1 0 0 1 +$EndComp +$Comp +L zener U3 +U 1 1 66744C44 +P 21500 9450 +F 0 "U3" H 21450 9350 60 0000 C CNN +F 1 "zener" H 21500 9550 60 0000 C CNN +F 2 "" H 21550 9450 60 0000 C CNN +F 3 "" H 21550 9450 60 0000 C CNN + 1 21500 9450 + 0 1 -1 0 +$EndComp +$Comp +L resistor R21 +U 1 1 66744C45 +P 20400 8850 +F 0 "R21" H 20450 8980 50 0000 C CNN +F 1 "120" H 20450 8800 50 0000 C CNN +F 2 "" H 20450 8830 30 0000 C CNN +F 3 "" V 20450 8900 30 0000 C CNN + 1 20400 8850 + -1 0 0 1 +$EndComp +Wire Wire Line + 8050 7150 8050 7000 +Wire Wire Line + 7750 7700 8750 7700 +Wire Wire Line + 7750 7700 7750 7750 +Wire Wire Line + 8050 7550 8050 7700 +Connection ~ 8050 7700 +Wire Wire Line + 8050 9600 8450 9600 +Wire Wire Line + 7750 8150 7750 9400 +Wire Wire Line + 8150 9600 8150 9300 +Wire Wire Line + 8150 9300 7750 9300 +Connection ~ 7750 9300 +Connection ~ 8150 9600 +Wire Wire Line + 7750 10050 7750 9800 +Wire Wire Line + 8250 10050 8250 9950 +Wire Wire Line + 8250 9950 7750 9950 +Connection ~ 7750 9950 +Wire Wire Line + 7750 10350 7750 10450 +Wire Wire Line + 7700 10450 13750 10450 +Wire Wire Line + 8250 10450 8250 10350 +Wire Wire Line + 8750 9800 8750 10000 +Wire Wire Line + 8750 10450 8750 10300 +Connection ~ 8250 10450 +Wire Wire Line + 8750 7700 8750 7750 +Wire Wire Line + 8750 8150 8750 9400 +Wire Wire Line + 6450 6700 13300 6700 +Wire Wire Line + 8350 7350 12300 7350 +Wire Wire Line + 10300 7900 11500 7900 +Wire Wire Line + 10300 7900 10300 8000 +Wire Wire Line + 10950 7550 10950 7900 +Connection ~ 10950 7900 +Connection ~ 11050 7900 +Wire Wire Line + 10300 8400 10300 8900 +Wire Wire Line + 10300 8600 10750 8600 +Wire Wire Line + 11050 8400 11050 7900 +Wire Wire Line + 10600 8200 11050 8200 +Connection ~ 11050 8200 +Connection ~ 10300 8600 +Wire Wire Line + 9300 9350 8750 9350 +Connection ~ 8750 9350 +Wire Wire Line + 8950 9100 8750 9100 +Connection ~ 8750 9100 +Wire Wire Line + 9600 9150 9600 6700 +Connection ~ 9600 6700 +Wire Wire Line + 8950 8850 8850 8850 +Wire Wire Line + 8850 8850 8850 9100 +Connection ~ 8850 9100 +Wire Wire Line + 9600 10450 9600 10250 +Connection ~ 8750 10450 +Connection ~ 10650 7350 +Wire Wire Line + 10950 7150 10950 6700 +Connection ~ 10950 6700 +Wire Wire Line + 11800 6700 11800 7700 +Wire Wire Line + 11500 9400 9850 9400 +Wire Wire Line + 9850 9400 9850 9100 +Wire Wire Line + 9850 9100 9250 9100 +Wire Wire Line + 9250 8850 9400 8850 +Wire Wire Line + 9400 8850 9400 9100 +Connection ~ 9400 9100 +Wire Wire Line + 10300 9200 10300 9400 +Connection ~ 10300 9400 +Wire Wire Line + 11050 8800 11050 9400 +Connection ~ 11050 9400 +Wire Wire Line + 9600 9950 9600 9550 +Wire Wire Line + 10600 9800 9600 9800 +Connection ~ 9600 9800 +Wire Wire Line + 10900 10450 10900 10000 +Connection ~ 9600 10450 +Wire Wire Line + 11800 10450 11800 9600 +Connection ~ 10900 10450 +Wire Wire Line + 11800 8100 11800 8300 +Wire Wire Line + 11800 8600 11800 8800 +Wire Wire Line + 11800 9200 11800 9100 +Wire Wire Line + 12600 6700 12600 7150 +Connection ~ 11800 6700 +Wire Wire Line + 12600 8650 12600 7550 +Wire Wire Line + 12600 9450 12600 9050 +Wire Wire Line + 12600 10450 12600 9750 +Connection ~ 11800 10450 +Wire Wire Line + 13300 8400 13300 8950 +Wire Wire Line + 12900 8850 13300 8850 +Connection ~ 13300 8850 +Wire Wire Line + 13300 10450 13300 9450 +Connection ~ 12600 10450 +Wire Wire Line + 13300 6700 13300 8000 +Connection ~ 12600 6700 +Wire Wire Line + 13600 8200 13750 8200 +Wire Wire Line + 13750 8200 13750 10450 +Connection ~ 13300 10450 +Wire Wire Line + 12200 7350 12200 7700 +Wire Wire Line + 12200 7700 12600 7700 +Connection ~ 12600 7700 +Connection ~ 12200 7350 +Wire Wire Line + 12000 8700 11800 8700 +Connection ~ 11800 8700 +Wire Wire Line + 12300 8700 14100 8700 +Wire Wire Line + 10900 9600 10900 9400 +Connection ~ 10900 9400 +Connection ~ 8050 6700 +Connection ~ 7750 10450 +Wire Wire Line + 9250 7950 9050 7950 +Wire Wire Line + 16250 7350 16250 7200 +Wire Wire Line + 15950 7900 16950 7900 +Wire Wire Line + 15950 7900 15950 7950 +Wire Wire Line + 16250 7750 16250 7900 +Connection ~ 16250 7900 +Wire Wire Line + 16250 9800 16650 9800 +Wire Wire Line + 15950 8350 15950 9600 +Wire Wire Line + 16350 9800 16350 9500 +Wire Wire Line + 16350 9500 15950 9500 +Connection ~ 15950 9500 +Connection ~ 16350 9800 +Wire Wire Line + 15950 10250 15950 10000 +Wire Wire Line + 16450 10250 16450 10150 +Wire Wire Line + 16450 10150 15950 10150 +Connection ~ 15950 10150 +Wire Wire Line + 15950 10550 15950 10650 +Wire Wire Line + 16450 10650 16450 10550 +Wire Wire Line + 16950 10000 16950 10200 +Wire Wire Line + 16950 10650 16950 10500 +Connection ~ 16450 10650 +Wire Wire Line + 16950 7900 16950 7950 +Wire Wire Line + 16950 8350 16950 9600 +Wire Wire Line + 16550 7550 20500 7550 +Wire Wire Line + 18500 8100 19700 8100 +Wire Wire Line + 18500 8100 18500 8200 +Wire Wire Line + 19150 7750 19150 8100 +Connection ~ 19150 8100 +Connection ~ 19250 8100 +Wire Wire Line + 18500 8600 18500 9100 +Wire Wire Line + 18500 8800 18950 8800 +Wire Wire Line + 19250 8600 19250 8100 +Wire Wire Line + 18800 8400 19250 8400 +Connection ~ 19250 8400 +Connection ~ 18500 8800 +Wire Wire Line + 17500 9550 16950 9550 +Connection ~ 16950 9550 +Wire Wire Line + 17150 9300 16950 9300 +Connection ~ 16950 9300 +Wire Wire Line + 17800 9350 17800 6900 +Connection ~ 17800 6900 +Wire Wire Line + 17150 9050 17050 9050 +Wire Wire Line + 17050 9050 17050 9300 +Connection ~ 17050 9300 +Wire Wire Line + 17800 10650 17800 10450 +Connection ~ 16950 10650 +Connection ~ 18850 7550 +Wire Wire Line + 19150 7350 19150 6900 +Connection ~ 19150 6900 +Wire Wire Line + 20000 6900 20000 7900 +Wire Wire Line + 19700 9600 18050 9600 +Wire Wire Line + 18050 9600 18050 9300 +Wire Wire Line + 18050 9300 17450 9300 +Wire Wire Line + 17450 9050 17600 9050 +Wire Wire Line + 17600 9050 17600 9300 +Connection ~ 17600 9300 +Wire Wire Line + 18500 9400 18500 9600 +Connection ~ 18500 9600 +Wire Wire Line + 19250 9000 19250 9600 +Connection ~ 19250 9600 +Wire Wire Line + 17800 10150 17800 9750 +Wire Wire Line + 18800 10000 17800 10000 +Connection ~ 17800 10000 +Wire Wire Line + 19100 10650 19100 10200 +Connection ~ 17800 10650 +Wire Wire Line + 20000 10650 20000 9800 +Connection ~ 19100 10650 +Wire Wire Line + 20000 8300 20000 8500 +Wire Wire Line + 20000 8800 20000 9000 +Wire Wire Line + 20000 9400 20000 9300 +Wire Wire Line + 20800 6900 20800 7350 +Connection ~ 20000 6900 +Wire Wire Line + 20800 8850 20800 7750 +Wire Wire Line + 20800 9650 20800 9250 +Wire Wire Line + 20800 10650 20800 9950 +Connection ~ 20000 10650 +Wire Wire Line + 21500 8600 21500 9150 +Wire Wire Line + 21100 9050 21500 9050 +Connection ~ 21500 9050 +Wire Wire Line + 21500 10650 21500 9650 +Connection ~ 20800 10650 +Wire Wire Line + 21500 6900 21500 8200 +Connection ~ 20800 6900 +Wire Wire Line + 21800 8400 21950 8400 +Wire Wire Line + 21950 8400 21950 10650 +Connection ~ 21500 10650 +Wire Wire Line + 20400 7550 20400 7900 +Wire Wire Line + 20400 7900 20800 7900 +Connection ~ 20800 7900 +Connection ~ 20400 7550 +Wire Wire Line + 20200 8900 20000 8900 +Connection ~ 20000 8900 +Wire Wire Line + 20500 8900 22300 8900 +Wire Wire Line + 19100 9800 19100 9600 +Connection ~ 19100 9600 +Connection ~ 16250 6900 +Connection ~ 15950 10650 +Wire Wire Line + 17450 8150 17250 8150 +Wire Wire Line + 15200 6900 21500 6900 +Wire Wire Line + 15200 5300 15200 6900 +Wire Wire Line + 6200 5300 15200 5300 +Wire Wire Line + 21950 10650 7700 10650 +Wire Wire Line + 6450 6700 6450 7000 +Wire Wire Line + 6200 5300 6200 6750 +Wire Wire Line + 6200 6750 6450 6750 +Connection ~ 6450 6750 +Connection ~ 7700 10650 +Wire Wire Line + 6800 7950 7450 7950 +Wire Wire Line + 15000 8150 15650 8150 +Wire Wire Line + 7700 10450 7700 10750 +$Comp +L PORT U1 +U 1 1 66746E63 +P 14350 8700 +F 0 "U1" H 14400 8800 30 0000 C CNN +F 1 "PORT" H 14350 8700 30 0000 C CNN +F 2 "" H 14350 8700 60 0000 C CNN +F 3 "" H 14350 8700 60 0000 C CNN + 1 14350 8700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 66747237 +P 6550 7950 +F 0 "U1" H 6600 8050 30 0000 C CNN +F 1 "PORT" H 6550 7950 30 0000 C CNN +F 2 "" H 6550 7950 60 0000 C CNN +F 3 "" H 6550 7950 60 0000 C CNN + 2 6550 7950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 667472F4 +P 7700 11000 +F 0 "U1" H 7750 11100 30 0000 C CNN +F 1 "PORT" H 7700 11000 30 0000 C CNN +F 2 "" H 7700 11000 60 0000 C CNN +F 3 "" H 7700 11000 60 0000 C CNN + 4 7700 11000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 66747403 +P 9500 7950 +F 0 "U1" H 9550 8050 30 0000 C CNN +F 1 "PORT" H 9500 7950 30 0000 C CNN +F 2 "" H 9500 7950 60 0000 C CNN +F 3 "" H 9500 7950 60 0000 C CNN + 3 9500 7950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 66747B3E +P 17700 8150 +F 0 "U1" H 17750 8250 30 0000 C CNN +F 1 "PORT" H 17700 8150 30 0000 C CNN +F 2 "" H 17700 8150 60 0000 C CNN +F 3 "" H 17700 8150 60 0000 C CNN + 5 17700 8150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 66747BED +P 14750 8150 +F 0 "U1" H 14800 8250 30 0000 C CNN +F 1 "PORT" H 14750 8150 30 0000 C CNN +F 2 "" H 14750 8150 60 0000 C CNN +F 3 "" H 14750 8150 60 0000 C CNN + 6 14750 8150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 66748118 +P 6450 7250 +F 0 "U1" H 6500 7350 30 0000 C CNN +F 1 "PORT" H 6450 7250 30 0000 C CNN +F 2 "" H 6450 7250 60 0000 C CNN +F 3 "" H 6450 7250 60 0000 C CNN + 8 6450 7250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 6674854A +P 22550 8900 +F 0 "U1" H 22600 9000 30 0000 C CNN +F 1 "PORT" H 22550 8900 30 0000 C CNN +F 2 "" H 22550 8900 60 0000 C CNN +F 3 "" H 22550 8900 60 0000 C CNN + 7 22550 8900 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub new file mode 100644 index 00000000..46e87586 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC.sub @@ -0,0 +1,72 @@ +* Subcircuit RC4559N_IC +.subckt RC4559N_IC net-_r10-pad1_ net-_q1-pad2_ net-_q5-pad2_ net-_c1-pad2_ net-_q19-pad2_ net-_q15-pad2_ net-_r21-pad1_ net-_j1-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\rc4559n_ic\rc4559n_ic.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +.include D.lib +r3 net-_j1-pad3_ net-_q3-pad3_ 8.7k +q3 net-_q1-pad3_ net-_q13-pad1_ net-_q3-pad3_ Q2N2907A +q5 net-_c2-pad2_ net-_q5-pad2_ net-_q1-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2907A +q2 net-_q1-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222 +q4 net-_c2-pad2_ net-_q1-pad1_ net-_q4-pad3_ Q2N2222 +r2 net-_c1-pad1_ net-_c1-pad2_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 15p +r4 net-_q4-pad3_ net-_c1-pad2_ 5k +q9 net-_q10-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q13 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad3_ Q2N2907A +q11 net-_j1-pad3_ net-_q10-pad1_ net-_q11-pad3_ Q2N2222 +q7 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad2_ Q2N2222 +q10 net-_q10-pad1_ net-_q10-pad2_ net-_c2-pad1_ Q2N2222 +r7 net-_q10-pad2_ net-_c2-pad1_ 50k +c2 net-_c2-pad1_ net-_c2-pad2_ 15p +d1 net-_c2-pad2_ net-_c2-pad1_ 1N4148 +q6 net-_j1-pad3_ net-_c2-pad2_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_c1-pad2_ 50k +r8 net-_q11-pad3_ net-_r10-pad2_ 27 +r9 net-_r10-pad2_ net-_q12-pad3_ 27 +q12 net-_c1-pad2_ net-_c2-pad1_ net-_q12-pad3_ Q2N2907A +q8 net-_c2-pad1_ net-_q6-pad3_ net-_c1-pad2_ Q2N2222 +q14 net-_q13-pad1_ net-_j1-pad1_ net-_q14-pad3_ Q2N2222 +r11 net-_q14-pad3_ net-_c1-pad2_ 5.8k +j1 net-_j1-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u2 net-_c1-pad2_ net-_j1-pad1_ zener +r10 net-_r10-pad1_ net-_r10-pad2_ 120 +r14 net-_j1-pad3_ net-_q17-pad3_ 8.7k +q17 net-_q15-pad3_ net-_q17-pad2_ net-_q17-pad3_ Q2N2907A +q19 net-_c4-pad2_ net-_q19-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q15-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q16 net-_q15-pad1_ net-_q15-pad1_ net-_c3-pad1_ Q2N2222 +q18 net-_c4-pad2_ net-_q15-pad1_ net-_q18-pad3_ Q2N2222 +r13 net-_c3-pad1_ net-_c1-pad2_ 5k +c3 net-_c3-pad1_ net-_c1-pad2_ 15p +r15 net-_q18-pad3_ net-_c1-pad2_ 5k +q23 net-_q21-pad1_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q27 net-_q17-pad2_ net-_q17-pad2_ net-_j1-pad3_ Q2N2907A +q25 net-_j1-pad3_ net-_q21-pad1_ net-_q25-pad3_ Q2N2222 +q21 net-_q21-pad1_ net-_q21-pad1_ net-_q21-pad3_ Q2N2222 +q24 net-_q21-pad1_ net-_q21-pad3_ net-_c4-pad1_ Q2N2222 +r18 net-_q21-pad3_ net-_c4-pad1_ 50k +c4 net-_c4-pad1_ net-_c4-pad2_ 15p +d2 net-_c4-pad2_ net-_c4-pad1_ 1N4148 +q20 net-_j1-pad3_ net-_c4-pad2_ net-_q20-pad3_ Q2N2222 +r16 net-_q20-pad3_ net-_c1-pad2_ 50k +r19 net-_q25-pad3_ net-_r19-pad2_ 27 +r20 net-_r19-pad2_ net-_q26-pad3_ 27 +q26 net-_c1-pad2_ net-_c4-pad1_ net-_q26-pad3_ Q2N2907A +q22 net-_c4-pad1_ net-_q20-pad3_ net-_c1-pad2_ Q2N2222 +q28 net-_q17-pad2_ net-_j2-pad1_ net-_q28-pad3_ Q2N2222 +r22 net-_q28-pad3_ net-_c1-pad2_ 5.8k +j2 net-_j2-pad1_ net-_c1-pad2_ net-_j1-pad3_ J2N3819 +* u3 net-_c1-pad2_ net-_j2-pad1_ zener +r21 net-_r21-pad1_ net-_r19-pad2_ 120 +a1 net-_c1-pad2_ net-_j1-pad1_ u2 +a2 net-_c1-pad2_ net-_j2-pad1_ u3 +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends RC4559N_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml new file mode 100644 index 00000000..e1685a88 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/RC4559N_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3></model><devicemodel><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q13><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q12><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j1><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q19><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q27><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q26><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.lib</field></j2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/RC4559N_sub/analysis b/library/SubcircuitLibrary/RC4559N_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/RC4559N_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir b/library/SubcircuitLibrary/SN54147_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.pro b/library/SubcircuitLibrary/SN54147_sub/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sch b/library/SubcircuitLibrary/SN54147_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and.sub b/library/SubcircuitLibrary/SN54147_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir b/library/SubcircuitLibrary/SN54147_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.pro b/library/SubcircuitLibrary/SN54147_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sch b/library/SubcircuitLibrary/SN54147_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and.sub b/library/SubcircuitLibrary/SN54147_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib new file mode 100644 index 00000000..45b9ccde --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC-cache.lib @@ -0,0 +1,189 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir new file mode 100644 index 00000000..772cd6bf --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir @@ -0,0 +1,64 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN54147_IC\SN54147_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/24 18:32:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter +U28 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U28-Pad3_ d_and +U29 Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U29-Pad3_ d_and +U35 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U35-Pad3_ d_and +U30 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U30-Pad3_ d_and +U36 Net-_U30-Pad3_ Net-_U17-Pad3_ Net-_U36-Pad3_ d_and +U31 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U31-Pad3_ d_and +U18 Net-_U10-Pad2_ Net-_U13-Pad2_ Net-_U18-Pad3_ d_and +U19 Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_and +U33 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U33-Pad3_ d_and +U20 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U14-Pad2_ Net-_U17-Pad3_ Net-_U21-Pad3_ d_and +U34 Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U34-Pad3_ d_and +U22 Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U22-Pad3_ d_and +U23 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U23-Pad3_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U7 Net-_U2-Pad11_ Net-_U13-Pad1_ d_inverter +U16 Net-_U10-Pad2_ Net-_U16-Pad2_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U24 Net-_U13-Pad1_ Net-_U17-Pad3_ Net-_U24-Pad3_ d_and +U25 Net-_U14-Pad1_ Net-_U17-Pad3_ Net-_U25-Pad3_ d_and +U26 Net-_U15-Pad1_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_and +U27 Net-_U23-Pad1_ Net-_U17-Pad3_ Net-_U27-Pad3_ d_and +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U8 Net-_U2-Pad12_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U9 Net-_U2-Pad13_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U6 Net-_U2-Pad14_ Net-_U23-Pad1_ d_inverter +U4 Net-_U2-Pad15_ Net-_U17-Pad1_ d_inverter +U5 Net-_U2-Pad16_ Net-_U17-Pad2_ d_inverter +U17 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U17-Pad3_ d_nor +X1 Net-_U11-Pad2_ Net-_U16-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U17-Pad3_ Net-_U42-Pad1_ 5_and +U32 Net-_U17-Pad2_ Net-_U17-Pad2_ Net-_U32-Pad3_ d_and +U37 Net-_U17-Pad1_ Net-_U17-Pad2_ Net-_U37-Pad3_ d_nor +U3 Net-_U1-Pad10_ Net-_U11-Pad1_ adc_bridge_1 +U2 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad9_ Net-_U10-Pad1_ Net-_U12-Pad1_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U2-Pad16_ adc_bridge_8 +U53 Net-_U52-Pad3_ Net-_U51-Pad3_ Net-_U46-Pad3_ Net-_U37-Pad3_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ Net-_U1-Pad13_ dac_bridge_4 +U42 Net-_U42-Pad1_ Net-_U35-Pad3_ Net-_U42-Pad3_ d_nor +U49 Net-_U42-Pad3_ Net-_U36-Pad3_ Net-_U49-Pad3_ d_nor +U43 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U43-Pad3_ d_nor +U52 Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U52-Pad3_ d_nor +U40 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor +U47 Net-_U40-Pad3_ Net-_U40-Pad3_ Net-_U47-Pad3_ d_nor +U41 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U41-Pad3_ d_nor +U48 Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nor +U51 Net-_U47-Pad3_ Net-_U48-Pad3_ Net-_U51-Pad3_ d_nor +U38 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U38-Pad3_ d_nor +U39 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U39-Pad3_ d_nor +U44 Net-_U38-Pad3_ Net-_U38-Pad3_ Net-_U44-Pad3_ d_nor +U45 Net-_U39-Pad3_ Net-_U39-Pad3_ Net-_U45-Pad3_ d_nor +U46 Net-_U44-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ d_nor +U50 Net-_U43-Pad3_ Net-_U43-Pad3_ Net-_U50-Pad3_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out new file mode 100644 index 00000000..eedd9eba --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.cir.out @@ -0,0 +1,222 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir + +.include 5_and.sub +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u28 net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u29 net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u30 net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and +* u36 net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and +* u31 net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and +* u18 net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and +* u19 net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and +* u33 net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and +* u20 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and +* u21 net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and +* u34 net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and +* u22 net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u7 net-_u2-pad11_ net-_u13-pad1_ d_inverter +* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u24 net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u25 net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u26 net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and +* u27 net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u2-pad12_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u2-pad13_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad14_ net-_u23-pad1_ d_inverter +* u4 net-_u2-pad15_ net-_u17-pad1_ d_inverter +* u5 net-_u2-pad16_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor +x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and +* u32 net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u37 net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor +* u3 net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1 +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u53 net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4 +* u42 net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor +* u49 net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor +* u52 net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor +* u40 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u47 net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u41 net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor +* u38 net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor +* u39 net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor +* u44 net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor +* u46 net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor +* u50 net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ port +a1 net-_u11-pad1_ net-_u11-pad2_ u11 +a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29 +a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30 +a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36 +a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18 +a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33 +a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20 +a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21 +a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34 +a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u2-pad11_ net-_u13-pad1_ u7 +a18 net-_u10-pad2_ net-_u16-pad2_ u16 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u2-pad12_ net-_u14-pad1_ u8 +a26 net-_u14-pad1_ net-_u14-pad2_ u14 +a27 net-_u2-pad13_ net-_u15-pad1_ u9 +a28 net-_u15-pad1_ net-_u15-pad2_ u15 +a29 net-_u2-pad14_ net-_u23-pad1_ u6 +a30 net-_u2-pad15_ net-_u17-pad1_ u4 +a31 net-_u2-pad16_ net-_u17-pad2_ u5 +a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3 +a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53 +a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49 +a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52 +a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41 +a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51 +a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38 +a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39 +a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44 +a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45 +a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46 +a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch new file mode 100644 index 00000000..d1d0e0ff --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sch @@ -0,0 +1,1363 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN54147-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 23622 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U11 +U 1 1 6676CB67 +P 9650 4750 +F 0 "U11" H 9650 4650 60 0000 C CNN +F 1 "d_inverter" H 9650 4900 60 0000 C CNN +F 2 "" H 9700 4700 60 0000 C CNN +F 3 "" H 9700 4700 60 0000 C CNN + 1 9650 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U28 +U 1 1 6676CB68 +P 14600 5900 +F 0 "U28" H 14600 5900 60 0000 C CNN +F 1 "d_and" H 14650 6000 60 0000 C CNN +F 2 "" H 14600 5900 60 0000 C CNN +F 3 "" H 14600 5900 60 0000 C CNN + 1 14600 5900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U29 +U 1 1 6676CB69 +P 14600 6200 +F 0 "U29" H 14600 6200 60 0000 C CNN +F 1 "d_and" H 14650 6300 60 0000 C CNN +F 2 "" H 14600 6200 60 0000 C CNN +F 3 "" H 14600 6200 60 0000 C CNN + 1 14600 6200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U35 +U 1 1 6676CB6A +P 15650 6050 +F 0 "U35" H 15650 6050 60 0000 C CNN +F 1 "d_and" H 15700 6150 60 0000 C CNN +F 2 "" H 15650 6050 60 0000 C CNN +F 3 "" H 15650 6050 60 0000 C CNN + 1 15650 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U30 +U 1 1 6676CB6B +P 14600 6600 +F 0 "U30" H 14600 6600 60 0000 C CNN +F 1 "d_and" H 14650 6700 60 0000 C CNN +F 2 "" H 14600 6600 60 0000 C CNN +F 3 "" H 14600 6600 60 0000 C CNN + 1 14600 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U36 +U 1 1 6676CB6C +P 15650 6750 +F 0 "U36" H 15650 6750 60 0000 C CNN +F 1 "d_and" H 15700 6850 60 0000 C CNN +F 2 "" H 15650 6750 60 0000 C CNN +F 3 "" H 15650 6750 60 0000 C CNN + 1 15650 6750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U31 +U 1 1 6676CB6D +P 14600 7300 +F 0 "U31" H 14600 7300 60 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1 "d_nor" H 17300 9150 60 0000 C CNN +F 2 "" H 17250 9050 60 0000 C CNN +F 3 "" H 17250 9050 60 0000 C CNN + 1 17250 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U47 +U 1 1 6676CB93 +P 18300 9050 +F 0 "U47" H 18300 9050 60 0000 C CNN +F 1 "d_nor" H 18350 9150 60 0000 C CNN +F 2 "" H 18300 9050 60 0000 C CNN +F 3 "" H 18300 9050 60 0000 C CNN + 1 18300 9050 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U41 +U 1 1 6676CB94 +P 17250 9850 +F 0 "U41" H 17250 9850 60 0000 C CNN +F 1 "d_nor" H 17300 9950 60 0000 C CNN +F 2 "" H 17250 9850 60 0000 C CNN +F 3 "" H 17250 9850 60 0000 C CNN + 1 17250 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U48 +U 1 1 6676CB95 +P 18300 9850 +F 0 "U48" H 18300 9850 60 0000 C CNN +F 1 "d_nor" H 18350 9950 60 0000 C CNN +F 2 "" H 18300 9850 60 0000 C CNN +F 3 "" H 18300 9850 60 0000 C CNN + 1 18300 9850 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U51 +U 1 1 6676CB96 +P 18850 9400 +F 0 "U51" H 18850 9400 60 0000 C CNN +F 1 "d_nor" H 18900 9500 60 0000 C CNN +F 2 "" H 18850 9400 60 0000 C CNN +F 3 "" H 18850 9400 60 0000 C CNN + 1 18850 9400 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U38 +U 1 1 6676CB97 +P 16200 12700 +F 0 "U38" H 16200 12700 60 0000 C CNN +F 1 "d_nor" H 16250 12800 60 0000 C CNN +F 2 "" H 16200 12700 60 0000 C CNN +F 3 "" H 16200 12700 60 0000 C CNN + 1 16200 12700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U39 +U 1 1 6676CB98 +P 16200 13500 +F 0 "U39" H 16200 13500 60 0000 C CNN +F 1 "d_nor" H 16250 13600 60 0000 C CNN +F 2 "" H 16200 13500 60 0000 C CNN +F 3 "" H 16200 13500 60 0000 C CNN + 1 16200 13500 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U44 +U 1 1 6676CB99 +P 17350 12700 +F 0 "U44" H 17350 12700 60 0000 C CNN +F 1 "d_nor" H 17400 12800 60 0000 C CNN +F 2 "" H 17350 12700 60 0000 C CNN +F 3 "" H 17350 12700 60 0000 C CNN + 1 17350 12700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U45 +U 1 1 6676CB9A +P 17350 13550 +F 0 "U45" H 17350 13550 60 0000 C CNN +F 1 "d_nor" H 17400 13650 60 0000 C CNN +F 2 "" H 17350 13550 60 0000 C CNN +F 3 "" H 17350 13550 60 0000 C CNN + 1 17350 13550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U46 +U 1 1 6676CB9B +P 18000 13100 +F 0 "U46" H 18000 13100 60 0000 C CNN +F 1 "d_nor" H 18050 13200 60 0000 C CNN +F 2 "" H 18000 13100 60 0000 C CNN +F 3 "" H 18000 13100 60 0000 C CNN + 1 18000 13100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U50 +U 1 1 6676CB9C +P 18350 6400 +F 0 "U50" H 18350 6400 60 0000 C CNN +F 1 "d_nor" H 18400 6500 60 0000 C CNN +F 2 "" H 18350 6400 60 0000 C CNN +F 3 "" H 18350 6400 60 0000 C CNN + 1 18350 6400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17900 6300 17850 6300 +Wire Wire Line + 17850 6300 17850 6400 +Wire Wire Line + 17850 6400 17900 6400 +Wire Wire Line + 17750 6350 17850 6350 +Connection ~ 17850 6350 +Wire Wire Line + 18800 6350 18850 6350 +$Comp +L PORT U1 +U 2 1 6676CB9D +P 5700 9900 +F 0 "U1" H 5750 10000 30 0000 C CNN +F 1 "PORT" H 5700 9900 30 0000 C CNN +F 2 "" H 5700 9900 60 0000 C CNN +F 3 "" H 5700 9900 60 0000 C CNN + 2 5700 9900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6676CB9E +P 5500 10050 +F 0 "U1" H 5550 10150 30 0000 C CNN +F 1 "PORT" H 5500 10050 30 0000 C CNN +F 2 "" H 5500 10050 60 0000 C CNN +F 3 "" H 5500 10050 60 0000 C CNN + 3 5500 10050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 6676CB9F +P 5700 10200 +F 0 "U1" H 5750 10300 30 0000 C CNN +F 1 "PORT" H 5700 10200 30 0000 C CNN +F 2 "" H 5700 10200 60 0000 C CNN +F 3 "" H 5700 10200 60 0000 C CNN + 4 5700 10200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6676CBA0 +P 5550 9750 +F 0 "U1" H 5600 9850 30 0000 C CNN +F 1 "PORT" H 5550 9750 30 0000 C CNN +F 2 "" H 5550 9750 60 0000 C CNN +F 3 "" H 5550 9750 60 0000 C CNN + 1 5550 9750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5800 9750 6500 9750 +Wire Wire Line + 5950 9900 6150 9900 +Wire Wire Line + 6150 9900 6150 9850 +Wire Wire Line + 6150 9850 6500 9850 +Wire Wire Line + 5750 10050 6150 10050 +Wire Wire Line + 6150 10050 6150 9950 +Wire Wire Line + 6150 9950 6500 9950 +Wire Wire Line + 5950 10200 6200 10200 +Wire Wire Line + 6200 10200 6200 10050 +Wire Wire Line + 6200 10050 6500 10050 +$Comp +L PORT U1 +U 5 1 6676CBA1 +P 5700 10400 +F 0 "U1" H 5750 10500 30 0000 C CNN +F 1 "PORT" H 5700 10400 30 0000 C CNN +F 2 "" H 5700 10400 60 0000 C CNN +F 3 "" H 5700 10400 60 0000 C CNN + 5 5700 10400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 10400 6300 10400 +Wire Wire Line + 6300 10400 6300 10150 +Wire Wire Line + 6300 10150 6500 10150 +$Comp +L PORT U1 +U 6 1 6676CBA2 +P 21250 10200 +F 0 "U1" H 21300 10300 30 0000 C CNN +F 1 "PORT" H 21250 10200 30 0000 C CNN +F 2 "" H 21250 10200 60 0000 C CNN +F 3 "" H 21250 10200 60 0000 C CNN + 6 21250 10200 + -1 0 0 1 +$EndComp +Wire Wire Line + 21000 10200 20700 10200 +$Comp +L PORT U1 +U 7 1 6676CBA3 +P 21250 10000 +F 0 "U1" H 21300 10100 30 0000 C CNN +F 1 "PORT" H 21250 10000 30 0000 C CNN +F 2 "" H 21250 10000 60 0000 C CNN +F 3 "" H 21250 10000 60 0000 C CNN + 7 21250 10000 + -1 0 0 1 +$EndComp +Wire Wire Line + 21000 10000 21000 10100 +Wire Wire Line + 21000 10100 20700 10100 +$Comp +L PORT U1 +U 8 1 6676CBA4 +P 21250 9800 +F 0 "U1" H 21300 9900 30 0000 C CNN +F 1 "PORT" H 21250 9800 30 0000 C CNN +F 2 "" H 21250 9800 60 0000 C CNN +F 3 "" H 21250 9800 60 0000 C CNN + 8 21250 9800 + -1 0 0 1 +$EndComp +Wire Wire Line + 21000 9800 20900 9800 +Wire Wire Line + 20900 9800 20900 10000 +Wire Wire Line + 20900 10000 20700 10000 +$Comp +L PORT U1 +U 9 1 6676CBA5 +P 5700 10600 +F 0 "U1" H 5750 10700 30 0000 C CNN +F 1 "PORT" H 5700 10600 30 0000 C CNN +F 2 "" H 5700 10600 60 0000 C CNN +F 3 "" H 5700 10600 60 0000 C CNN + 9 5700 10600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 10250 6400 10250 +Wire Wire Line + 6400 10250 6400 10600 +Wire Wire Line + 6400 10600 5950 10600 +$Comp +L PORT U1 +U 10 1 6676CBA6 +P 7350 4750 +F 0 "U1" H 7400 4850 30 0000 C CNN +F 1 "PORT" H 7350 4750 30 0000 C CNN +F 2 "" H 7350 4750 60 0000 C CNN +F 3 "" H 7350 4750 60 0000 C CNN + 10 7350 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7600 4750 7900 4750 +$Comp +L PORT U1 +U 11 1 6676CBA7 +P 5700 9350 +F 0 "U1" H 5750 9450 30 0000 C CNN +F 1 "PORT" H 5700 9350 30 0000 C CNN +F 2 "" H 5700 9350 60 0000 C CNN +F 3 "" H 5700 9350 60 0000 C CNN + 11 5700 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6676CBA8 +P 5700 9550 +F 0 "U1" H 5750 9650 30 0000 C CNN +F 1 "PORT" H 5700 9550 30 0000 C CNN +F 2 "" H 5700 9550 60 0000 C CNN +F 3 "" H 5700 9550 60 0000 C CNN + 12 5700 9550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 9350 6350 9350 +Wire Wire Line + 6350 9350 6350 9550 +Wire Wire Line + 6350 9550 6500 9550 +Wire Wire Line + 5950 9550 6300 9550 +Wire Wire Line + 6300 9550 6300 9650 +Wire Wire Line + 6300 9650 6500 9650 +$Comp +L PORT U1 +U 13 1 6676CBA9 +P 21250 10450 +F 0 "U1" H 21300 10550 30 0000 C CNN +F 1 "PORT" H 21250 10450 30 0000 C CNN +F 2 "" H 21250 10450 60 0000 C CNN +F 3 "" H 21250 10450 60 0000 C CNN + 13 21250 10450 + -1 0 0 1 +$EndComp +Wire Wire Line + 20700 10300 20900 10300 +Wire Wire Line + 20900 10300 20900 10450 +Wire Wire Line + 20900 10450 21000 10450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub new file mode 100644 index 00000000..f16660b7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC.sub @@ -0,0 +1,216 @@ +* Subcircuit SN54147_IC +.subckt SN54147_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ +* d:\fossee\esim\library\subcircuitlibrary\sn54147_ic\sn54147_ic.cir +.include 5_and.sub +* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter +* u28 net-_u12-pad2_ net-_u13-pad2_ net-_u28-pad3_ d_and +* u29 net-_u15-pad2_ net-_u17-pad3_ net-_u29-pad3_ d_and +* u35 net-_u28-pad3_ net-_u29-pad3_ net-_u35-pad3_ d_and +* u30 net-_u14-pad1_ net-_u15-pad2_ net-_u30-pad3_ d_and +* u36 net-_u30-pad3_ net-_u17-pad3_ net-_u36-pad3_ d_and +* u31 net-_u23-pad1_ net-_u17-pad3_ net-_u31-pad3_ d_and +* u18 net-_u10-pad2_ net-_u13-pad2_ net-_u18-pad3_ d_and +* u19 net-_u14-pad2_ net-_u17-pad3_ net-_u19-pad3_ d_and +* u33 net-_u18-pad3_ net-_u19-pad3_ net-_u33-pad3_ d_and +* u20 net-_u12-pad2_ net-_u13-pad2_ net-_u20-pad3_ d_and +* u21 net-_u14-pad2_ net-_u17-pad3_ net-_u21-pad3_ d_and +* u34 net-_u20-pad3_ net-_u21-pad3_ net-_u34-pad3_ d_and +* u22 net-_u15-pad1_ net-_u17-pad3_ net-_u22-pad3_ d_and +* u23 net-_u23-pad1_ net-_u17-pad3_ net-_u23-pad3_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u7 net-_u2-pad11_ net-_u13-pad1_ d_inverter +* u16 net-_u10-pad2_ net-_u16-pad2_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u24 net-_u13-pad1_ net-_u17-pad3_ net-_u24-pad3_ d_and +* u25 net-_u14-pad1_ net-_u17-pad3_ net-_u25-pad3_ d_and +* u26 net-_u15-pad1_ net-_u17-pad3_ net-_u26-pad3_ d_and +* u27 net-_u23-pad1_ net-_u17-pad3_ net-_u27-pad3_ d_and +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u8 net-_u2-pad12_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u9 net-_u2-pad13_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad14_ net-_u23-pad1_ d_inverter +* u4 net-_u2-pad15_ net-_u17-pad1_ d_inverter +* u5 net-_u2-pad16_ net-_u17-pad2_ d_inverter +* u17 net-_u17-pad1_ net-_u17-pad2_ net-_u17-pad3_ d_nor +x1 net-_u11-pad2_ net-_u16-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u17-pad3_ net-_u42-pad1_ 5_and +* u32 net-_u17-pad2_ net-_u17-pad2_ net-_u32-pad3_ d_and +* u37 net-_u17-pad1_ net-_u17-pad2_ net-_u37-pad3_ d_nor +* u3 net-_u1-pad10_ net-_u11-pad1_ adc_bridge_1 +* u2 net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ adc_bridge_8 +* u53 net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ dac_bridge_4 +* u42 net-_u42-pad1_ net-_u35-pad3_ net-_u42-pad3_ d_nor +* u49 net-_u42-pad3_ net-_u36-pad3_ net-_u49-pad3_ d_nor +* u43 net-_u31-pad3_ net-_u32-pad3_ net-_u43-pad3_ d_nor +* u52 net-_u49-pad3_ net-_u50-pad3_ net-_u52-pad3_ d_nor +* u40 net-_u33-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u47 net-_u40-pad3_ net-_u40-pad3_ net-_u47-pad3_ d_nor +* u41 net-_u22-pad3_ net-_u23-pad3_ net-_u41-pad3_ d_nor +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nor +* u51 net-_u47-pad3_ net-_u48-pad3_ net-_u51-pad3_ d_nor +* u38 net-_u24-pad3_ net-_u25-pad3_ net-_u38-pad3_ d_nor +* u39 net-_u26-pad3_ net-_u27-pad3_ net-_u39-pad3_ d_nor +* u44 net-_u38-pad3_ net-_u38-pad3_ net-_u44-pad3_ d_nor +* u45 net-_u39-pad3_ net-_u39-pad3_ net-_u45-pad3_ d_nor +* u46 net-_u44-pad3_ net-_u45-pad3_ net-_u46-pad3_ d_nor +* u50 net-_u43-pad3_ net-_u43-pad3_ net-_u50-pad3_ d_nor +a1 net-_u11-pad1_ net-_u11-pad2_ u11 +a2 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u28-pad3_ u28 +a3 [net-_u15-pad2_ net-_u17-pad3_ ] net-_u29-pad3_ u29 +a4 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u35-pad3_ u35 +a5 [net-_u14-pad1_ net-_u15-pad2_ ] net-_u30-pad3_ u30 +a6 [net-_u30-pad3_ net-_u17-pad3_ ] net-_u36-pad3_ u36 +a7 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u10-pad2_ net-_u13-pad2_ ] net-_u18-pad3_ u18 +a9 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u33-pad3_ u33 +a11 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u20-pad3_ u20 +a12 [net-_u14-pad2_ net-_u17-pad3_ ] net-_u21-pad3_ u21 +a13 [net-_u20-pad3_ net-_u21-pad3_ ] net-_u34-pad3_ u34 +a14 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u22-pad3_ u22 +a15 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u23-pad3_ u23 +a16 net-_u10-pad1_ net-_u10-pad2_ u10 +a17 net-_u2-pad11_ net-_u13-pad1_ u7 +a18 net-_u10-pad2_ net-_u16-pad2_ u16 +a19 net-_u13-pad1_ net-_u13-pad2_ u13 +a20 [net-_u13-pad1_ net-_u17-pad3_ ] net-_u24-pad3_ u24 +a21 [net-_u14-pad1_ net-_u17-pad3_ ] net-_u25-pad3_ u25 +a22 [net-_u15-pad1_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a23 [net-_u23-pad1_ net-_u17-pad3_ ] net-_u27-pad3_ u27 +a24 net-_u12-pad1_ net-_u12-pad2_ u12 +a25 net-_u2-pad12_ net-_u14-pad1_ u8 +a26 net-_u14-pad1_ net-_u14-pad2_ u14 +a27 net-_u2-pad13_ net-_u15-pad1_ u9 +a28 net-_u15-pad1_ net-_u15-pad2_ u15 +a29 net-_u2-pad14_ net-_u23-pad1_ u6 +a30 net-_u2-pad15_ net-_u17-pad1_ u4 +a31 net-_u2-pad16_ net-_u17-pad2_ u5 +a32 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u17-pad3_ u17 +a33 [net-_u17-pad2_ net-_u17-pad2_ ] net-_u32-pad3_ u32 +a34 [net-_u17-pad1_ net-_u17-pad2_ ] net-_u37-pad3_ u37 +a35 [net-_u1-pad10_ ] [net-_u11-pad1_ ] u3 +a36 [net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad9_ ] [net-_u10-pad1_ net-_u12-pad1_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u2-pad16_ ] u2 +a37 [net-_u52-pad3_ net-_u51-pad3_ net-_u46-pad3_ net-_u37-pad3_ ] [net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad13_ ] u53 +a38 [net-_u42-pad1_ net-_u35-pad3_ ] net-_u42-pad3_ u42 +a39 [net-_u42-pad3_ net-_u36-pad3_ ] net-_u49-pad3_ u49 +a40 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u43-pad3_ u43 +a41 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u52-pad3_ u52 +a42 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a43 [net-_u40-pad3_ net-_u40-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u41-pad3_ u41 +a45 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a46 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u51-pad3_ u51 +a47 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u38-pad3_ u38 +a48 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u39-pad3_ u39 +a49 [net-_u38-pad3_ net-_u38-pad3_ ] net-_u44-pad3_ u44 +a50 [net-_u39-pad3_ net-_u39-pad3_ ] net-_u45-pad3_ u45 +a51 [net-_u44-pad3_ net-_u45-pad3_ ] net-_u46-pad3_ u46 +a52 [net-_u43-pad3_ net-_u43-pad3_ ] net-_u50-pad3_ u50 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u25 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u26 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u27 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u53 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u42 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u49 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u52 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u41 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u48 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u51 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u50 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN54147_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml new file mode 100644 index 00000000..ecb2c383 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/SN54147_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u11 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u28 name="type">d_and<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_and<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u29><u35 name="type">d_and<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u35><u30 name="type">d_and<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u30><u36 name="type">d_and<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u36><u31 name="type">d_and<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u18 name="type">d_and<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u18><u19 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u19><u33 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u33><u20 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u21><u34 name="type">d_and<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u34><u22 name="type">d_and<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_and<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u23><u10 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u10><u7 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u16 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u16><u13 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u13><u24 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_and<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u27><u12 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u12><u8 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u8><u14 name="type">d_inverter<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u14><u9 name="type">d_inverter<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u9><u15 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u15><u6 name="type">d_inverter<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u6><u4 name="type">d_inverter<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u5><u17 name="type">d_nor<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u17><u32 name="type">d_and<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u32><u37 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u37><u3 name="type">adc_bridge<field103 name="Enter value for in_low (default=1.0)" /><field104 name="Enter value for in_high (default=2.0)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /><field106 name="Enter Fall Delay (default=1.0e-9)" /></u3><u2 name="type">adc_bridge<field107 name="Enter value for in_low (default=1.0)" /><field108 name="Enter value for in_high (default=2.0)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /></u2><u53 name="type">dac_bridge<field111 name="Enter value for out_low (default=0.0)" /><field112 name="Enter value for out_high (default=5.0)" /><field113 name="Enter value for out_undef (default=0.5)" /><field114 name="Enter value for input load (default=1.0e-12)" /><field115 name="Enter the Rise Time (default=1.0e-9)" /><field116 name="Enter the Fall Time (default=1.0e-9)" /></u53><u42 name="type">d_nor<field117 name="Enter Rise Delay (default=1.0e-9)" /><field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /></u42><u49 name="type">d_nor<field120 name="Enter Rise Delay (default=1.0e-9)" /><field121 name="Enter Fall Delay (default=1.0e-9)" /><field122 name="Enter Input Load (default=1.0e-12)" /></u49><u43 name="type">d_nor<field123 name="Enter Rise Delay (default=1.0e-9)" /><field124 name="Enter Fall Delay (default=1.0e-9)" /><field125 name="Enter Input Load (default=1.0e-12)" /></u43><u52 name="type">d_nor<field126 name="Enter Rise Delay (default=1.0e-9)" /><field127 name="Enter Fall Delay (default=1.0e-9)" /><field128 name="Enter Input Load (default=1.0e-12)" /></u52><u40 name="type">d_nor<field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /><field131 name="Enter Input Load (default=1.0e-12)" /></u40><u47 name="type">d_nor<field132 name="Enter Rise Delay (default=1.0e-9)" /><field133 name="Enter Fall Delay (default=1.0e-9)" /><field134 name="Enter Input Load (default=1.0e-12)" /></u47><u41 name="type">d_nor<field135 name="Enter Rise Delay (default=1.0e-9)" /><field136 name="Enter Fall Delay (default=1.0e-9)" /><field137 name="Enter Input Load (default=1.0e-12)" /></u41><u48 name="type">d_nor<field138 name="Enter Rise Delay (default=1.0e-9)" /><field139 name="Enter Fall Delay (default=1.0e-9)" /><field140 name="Enter Input Load (default=1.0e-12)" /></u48><u51 name="type">d_nor<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u51><u38 name="type">d_nor<field144 name="Enter Rise Delay (default=1.0e-9)" /><field145 name="Enter Fall Delay (default=1.0e-9)" /><field146 name="Enter Input Load (default=1.0e-12)" /></u38><u39 name="type">d_nor<field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /><field149 name="Enter Input Load (default=1.0e-12)" /></u39><u44 name="type">d_nor<field150 name="Enter Rise Delay (default=1.0e-9)" /><field151 name="Enter Fall Delay (default=1.0e-9)" /><field152 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_nor<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_nor<field156 name="Enter Rise Delay (default=1.0e-9)" /><field157 name="Enter Fall Delay (default=1.0e-9)" /><field158 name="Enter Input Load (default=1.0e-12)" /></u46><u50 name="type">d_nor<field159 name="Enter Rise Delay (default=1.0e-9)" /><field160 name="Enter Fall Delay (default=1.0e-9)" /><field161 name="Enter Input Load (default=1.0e-12)" /></u50></model><devicemodel /><subcircuit><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54147_sub/analysis b/library/SubcircuitLibrary/SN54147_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54147_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/SN54180-cache.lib b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib new file mode 100644 index 00000000..27b0f7f2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180-cache.lib @@ -0,0 +1,134 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_xnor +# +DEF d_xnor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xnor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 43 1 1 O I +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir b/library/SubcircuitLibrary/SN54180/SN54180.cir new file mode 100644 index 00000000..89146f7f --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir @@ -0,0 +1,25 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54180\SN54180.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/07/25 23:03:34 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U2-Pad3_ d_xnor +U3 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U3-Pad3_ d_xnor +U4 Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U4-Pad3_ d_xnor +U5 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U5-Pad3_ d_xnor +U8 Net-_U6-Pad3_ Net-_U7-Pad3_ Net-_U10-Pad1_ d_xnor +U6 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U6-Pad3_ d_xor +U7 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U7-Pad3_ d_xor +U9 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U1-Pad4_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U1-Pad3_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad3_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad4_ Net-_U13-Pad3_ d_and +U14 Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad5_ d_nor +U15 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U1-Pad6_ d_nor +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.cir.out b/library/SubcircuitLibrary/SN54180/SN54180.cir.out new file mode 100644 index 00000000..18993e8b --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.cir.out @@ -0,0 +1,68 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir + +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54180/SN54180.pro b/library/SubcircuitLibrary/SN54180/SN54180.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sch b/library/SubcircuitLibrary/SN54180/SN54180.sch new file mode 100644 index 00000000..1534f8b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sch @@ -0,0 +1,499 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54180-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xnor U2 +U 1 1 677290B0 +P 6050 7300 +F 0 "U2" H 6050 7300 60 0000 C CNN +F 1 "d_xnor" H 6100 7400 47 0000 C CNN +F 2 "" H 6050 7300 60 0000 C CNN +F 3 "" H 6050 7300 60 0000 C CNN + 1 6050 7300 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U3 +U 1 1 677290E7 +P 6050 7750 +F 0 "U3" H 6050 7750 60 0000 C CNN +F 1 "d_xnor" H 6100 7850 47 0000 C CNN +F 2 "" H 6050 7750 60 0000 C CNN +F 3 "" H 6050 7750 60 0000 C CNN + 1 6050 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U4 +U 1 1 67729137 +P 6050 8200 +F 0 "U4" H 6050 8200 60 0000 C CNN +F 1 "d_xnor" H 6100 8300 47 0000 C CNN +F 2 "" H 6050 8200 60 0000 C CNN +F 3 "" H 6050 8200 60 0000 C CNN + 1 6050 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U5 +U 1 1 6772913D +P 6050 8650 +F 0 "U5" H 6050 8650 60 0000 C CNN +F 1 "d_xnor" H 6100 8750 47 0000 C CNN +F 2 "" H 6050 8650 60 0000 C CNN +F 3 "" H 6050 8650 60 0000 C CNN + 1 6050 8650 + 1 0 0 -1 +$EndComp +$Comp +L d_xnor U8 +U 1 1 6772915D +P 8600 7950 +F 0 "U8" H 8600 7950 60 0000 C CNN +F 1 "d_xnor" H 8650 8050 47 0000 C CNN +F 2 "" H 8600 7950 60 0000 C CNN +F 3 "" H 8600 7950 60 0000 C CNN + 1 8600 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U6 +U 1 1 677291A8 +P 7350 7500 +F 0 "U6" H 7350 7500 60 0000 C CNN +F 1 "d_xor" H 7400 7600 47 0000 C CNN +F 2 "" H 7350 7500 60 0000 C CNN +F 3 "" H 7350 7500 60 0000 C CNN + 1 7350 7500 + 1 0 0 -1 +$EndComp +$Comp +L d_xor U7 +U 1 1 677291CD +P 7350 8400 +F 0 "U7" H 7350 8400 60 0000 C CNN +F 1 "d_xor" H 7400 8500 47 0000 C CNN +F 2 "" H 7350 8400 60 0000 C CNN +F 3 "" H 7350 8400 60 0000 C CNN + 1 7350 8400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U9 +U 1 1 67729482 +P 9800 7900 +F 0 "U9" H 9800 7800 60 0000 C CNN +F 1 "d_inverter" H 9800 8050 60 0000 C CNN +F 2 "" H 9850 7850 60 0000 C CNN +F 3 "" H 9850 7850 60 0000 C CNN + 1 9800 7900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U10 +U 1 1 67729715 +P 11450 7250 +F 0 "U10" H 11450 7250 60 0000 C CNN +F 1 "d_and" H 11500 7350 60 0000 C CNN +F 2 "" H 11450 7250 60 0000 C CNN +F 3 "" H 11450 7250 60 0000 C CNN + 1 11450 7250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U11 +U 1 1 6772978A +P 11450 7750 +F 0 "U11" H 11450 7750 60 0000 C CNN +F 1 "d_and" H 11500 7850 60 0000 C CNN +F 2 "" H 11450 7750 60 0000 C CNN +F 3 "" H 11450 7750 60 0000 C CNN + 1 11450 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_and U12 +U 1 1 677297EE +P 11450 8200 +F 0 "U12" H 11450 8200 60 0000 C CNN +F 1 "d_and" H 11500 8300 60 0000 C CNN +F 2 "" H 11450 8200 60 0000 C CNN +F 3 "" H 11450 8200 60 0000 C CNN + 1 11450 8200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 677297F4 +P 11450 8700 +F 0 "U13" H 11450 8700 60 0000 C CNN +F 1 "d_and" H 11500 8800 60 0000 C CNN +F 2 "" H 11450 8700 60 0000 C CNN +F 3 "" H 11450 8700 60 0000 C CNN + 1 11450 8700 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U14 +U 1 1 67729834 +P 13400 7550 +F 0 "U14" H 13400 7550 60 0000 C CNN +F 1 "d_nor" H 13450 7650 60 0000 C CNN +F 2 "" H 13400 7550 60 0000 C CNN +F 3 "" H 13400 7550 60 0000 C CNN + 1 13400 7550 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U15 +U 1 1 677299D9 +P 13400 8450 +F 0 "U15" H 13400 8450 60 0000 C CNN +F 1 "d_nor" H 13450 8550 60 0000 C CNN +F 2 "" H 13400 8450 60 0000 C CNN +F 3 "" H 13400 8450 60 0000 C CNN + 1 13400 8450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5600 7200 4850 7200 +Wire Wire Line + 5600 7300 4850 7300 +Wire Wire Line + 5600 7650 4850 7650 +Wire Wire Line + 5600 7750 4850 7750 +Wire Wire Line + 5600 8100 4850 8100 +Wire Wire Line + 5600 8200 4850 8200 +Wire Wire Line + 5600 8550 4850 8550 +Wire Wire Line + 5600 8650 4850 8650 +Wire Wire Line + 6500 7250 6750 7250 +Wire Wire Line + 6750 7250 6750 7400 +Wire Wire Line + 6750 7400 6900 7400 +Wire Wire Line + 6900 7500 6750 7500 +Wire Wire Line + 6750 7500 6750 7700 +Wire Wire Line + 6750 7700 6500 7700 +Wire Wire Line + 6500 8150 6700 8150 +Wire Wire Line + 6700 8150 6700 8300 +Wire Wire Line + 6700 8300 6900 8300 +Wire Wire Line + 6900 8400 6700 8400 +Wire Wire Line + 6700 8400 6700 8600 +Wire Wire Line + 6700 8600 6500 8600 +Wire Wire Line + 7800 7450 8000 7450 +Wire Wire Line + 8000 7450 8000 7850 +Wire Wire Line + 8000 7850 8150 7850 +Wire Wire Line + 8150 7950 8000 7950 +Wire Wire Line + 8000 7950 8000 8350 +Wire Wire Line + 8000 8350 7800 8350 +Wire Wire Line + 9050 7900 9500 7900 +Wire Wire Line + 11000 7150 9300 7150 +Wire Wire Line + 9300 7150 9300 8200 +Connection ~ 9300 7900 +Wire Wire Line + 9300 8200 11000 8200 +Wire Wire Line + 10350 7250 11000 7250 +Wire Wire Line + 10350 7250 10350 9350 +Wire Wire Line + 10350 8700 11000 8700 +Wire Wire Line + 11000 7650 10550 7650 +Wire Wire Line + 10550 7650 10550 8600 +Wire Wire Line + 10550 8600 11000 8600 +Wire Wire Line + 11000 7750 10800 7750 +Wire Wire Line + 10800 7750 10800 9550 +Wire Wire Line + 10800 8100 11000 8100 +Wire Wire Line + 10100 7900 10550 7900 +Connection ~ 10550 7900 +Wire Wire Line + 10350 9350 4850 9350 +Connection ~ 10350 8700 +Wire Wire Line + 10800 9550 4850 9550 +Connection ~ 10800 8100 +Wire Wire Line + 11900 7200 12500 7200 +Wire Wire Line + 12500 7200 12500 7450 +Wire Wire Line + 12500 7450 12950 7450 +Wire Wire Line + 12500 7550 12950 7550 +Wire Wire Line + 12500 7550 12500 7700 +Wire Wire Line + 12500 7700 11900 7700 +Wire Wire Line + 11900 8150 12500 8150 +Wire Wire Line + 12500 8150 12500 8350 +Wire Wire Line + 12500 8350 12950 8350 +Wire Wire Line + 12950 8450 12500 8450 +Wire Wire Line + 12500 8450 12500 8650 +Wire Wire Line + 12500 8650 11900 8650 +Wire Wire Line + 13850 7500 14550 7500 +Wire Wire Line + 13850 8400 14550 8400 +$Comp +L PORT U1 +U 1 1 677964E3 +P 4600 8550 +F 0 "U1" H 4650 8650 30 0000 C CNN +F 1 "PORT" H 4600 8550 30 0000 C CNN +F 2 "" H 4600 8550 60 0000 C CNN +F 3 "" H 4600 8550 60 0000 C CNN + 1 4600 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 677965B0 +P 4600 8750 +F 0 "U1" H 4650 8850 30 0000 C CNN +F 1 "PORT" H 4600 8750 30 0000 C CNN +F 2 "" H 4600 8750 60 0000 C CNN +F 3 "" H 4600 8750 60 0000 C CNN + 2 4600 8750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4850 8650 4850 8750 +$Comp +L PORT U1 +U 3 1 6779664F +P 4600 9550 +F 0 "U1" H 4650 9650 30 0000 C CNN +F 1 "PORT" H 4600 9550 30 0000 C CNN +F 2 "" H 4600 9550 60 0000 C CNN +F 3 "" H 4600 9550 60 0000 C CNN + 3 4600 9550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67796694 +P 4600 9350 +F 0 "U1" H 4650 9450 30 0000 C CNN +F 1 "PORT" H 4600 9350 30 0000 C CNN +F 2 "" H 4600 9350 60 0000 C CNN +F 3 "" H 4600 9350 60 0000 C CNN + 4 4600 9350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 677975B7 +P 14800 7500 +F 0 "U1" H 14850 7600 30 0000 C CNN +F 1 "PORT" H 14800 7500 30 0000 C CNN +F 2 "" H 14800 7500 60 0000 C CNN +F 3 "" H 14800 7500 60 0000 C CNN + 5 14800 7500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 6779764E +P 14800 8400 +F 0 "U1" H 14850 8500 30 0000 C CNN +F 1 "PORT" H 14800 8400 30 0000 C CNN +F 2 "" H 14800 8400 60 0000 C CNN +F 3 "" H 14800 8400 60 0000 C CNN + 6 14800 8400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 67798A6F +P 4600 7200 +F 0 "U1" H 4650 7300 30 0000 C CNN +F 1 "PORT" H 4600 7200 30 0000 C CNN +F 2 "" H 4600 7200 60 0000 C CNN +F 3 "" H 4600 7200 60 0000 C CNN + 8 4600 7200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67798ABE +P 4600 7400 +F 0 "U1" H 4650 7500 30 0000 C CNN +F 1 "PORT" H 4600 7400 30 0000 C CNN +F 2 "" H 4600 7400 60 0000 C CNN +F 3 "" H 4600 7400 60 0000 C CNN + 9 4600 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67798B09 +P 4200 7550 +F 0 "U1" H 4250 7650 30 0000 C CNN +F 1 "PORT" H 4200 7550 30 0000 C CNN +F 2 "" H 4200 7550 60 0000 C CNN +F 3 "" H 4200 7550 60 0000 C CNN + 10 4200 7550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67798B62 +P 4200 7800 +F 0 "U1" H 4250 7900 30 0000 C CNN +F 1 "PORT" H 4200 7800 30 0000 C CNN +F 2 "" H 4200 7800 60 0000 C CNN +F 3 "" H 4200 7800 60 0000 C CNN + 11 4200 7800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67798BAD +P 4450 8000 +F 0 "U1" H 4500 8100 30 0000 C CNN +F 1 "PORT" H 4450 8000 30 0000 C CNN +F 2 "" H 4450 8000 60 0000 C CNN +F 3 "" H 4450 8000 60 0000 C CNN + 12 4450 8000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67798BFE +P 4450 8250 +F 0 "U1" H 4500 8350 30 0000 C CNN +F 1 "PORT" H 4450 8250 30 0000 C CNN +F 2 "" H 4450 8250 60 0000 C CNN +F 3 "" H 4450 8250 60 0000 C CNN + 13 4450 8250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 7550 4850 7550 +Wire Wire Line + 4850 7550 4850 7650 +Wire Wire Line + 4450 7800 4850 7800 +Wire Wire Line + 4850 7800 4850 7750 +Wire Wire Line + 4850 7300 4850 7400 +Wire Wire Line + 4700 8000 4850 8000 +Wire Wire Line + 4850 8000 4850 8100 +Wire Wire Line + 4700 8250 4850 8250 +Wire Wire Line + 4850 8250 4850 8200 +$Comp +L PORT U1 +U 7 1 677A3419 +P 5650 10400 +F 0 "U1" H 5700 10500 30 0000 C CNN +F 1 "PORT" H 5650 10400 30 0000 C CNN +F 2 "" H 5650 10400 60 0000 C CNN +F 3 "" H 5650 10400 60 0000 C CNN + 7 5650 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 677A353F +P 5650 10650 +F 0 "U1" H 5700 10750 30 0000 C CNN +F 1 "PORT" H 5650 10650 30 0000 C CNN +F 2 "" H 5650 10650 60 0000 C CNN +F 3 "" H 5650 10650 60 0000 C CNN + 14 5650 10650 + 1 0 0 -1 +$EndComp +NoConn ~ 5900 10400 +NoConn ~ 5900 10650 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54180/SN54180.sub b/library/SubcircuitLibrary/SN54180/SN54180.sub new file mode 100644 index 00000000..34693793 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180.sub @@ -0,0 +1,62 @@ +* Subcircuit SN54180 +.subckt SN54180 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54180\sn54180.cir +* u2 net-_u1-pad8_ net-_u1-pad9_ net-_u2-pad3_ d_xnor +* u3 net-_u1-pad10_ net-_u1-pad11_ net-_u3-pad3_ d_xnor +* u4 net-_u1-pad12_ net-_u1-pad13_ net-_u4-pad3_ d_xnor +* u5 net-_u1-pad1_ net-_u1-pad2_ net-_u5-pad3_ d_xnor +* u8 net-_u6-pad3_ net-_u7-pad3_ net-_u10-pad1_ d_xnor +* u6 net-_u2-pad3_ net-_u3-pad3_ net-_u6-pad3_ d_xor +* u7 net-_u4-pad3_ net-_u5-pad3_ net-_u7-pad3_ d_xor +* u9 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u1-pad4_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u1-pad3_ net-_u11-pad3_ d_and +* u12 net-_u1-pad3_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad4_ net-_u13-pad3_ d_and +* u14 net-_u10-pad3_ net-_u11-pad3_ net-_u1-pad5_ d_nor +* u15 net-_u12-pad3_ net-_u13-pad3_ net-_u1-pad6_ d_nor +a1 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u2-pad3_ u2 +a2 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u3-pad3_ u3 +a3 [net-_u1-pad12_ net-_u1-pad13_ ] net-_u4-pad3_ u4 +a4 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u5-pad3_ u5 +a5 [net-_u6-pad3_ net-_u7-pad3_ ] net-_u10-pad1_ u8 +a6 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u6-pad3_ u6 +a7 [net-_u4-pad3_ net-_u5-pad3_ ] net-_u7-pad3_ u7 +a8 net-_u10-pad1_ net-_u11-pad1_ u9 +a9 [net-_u10-pad1_ net-_u1-pad4_ ] net-_u10-pad3_ u10 +a10 [net-_u11-pad1_ net-_u1-pad3_ ] net-_u11-pad3_ u11 +a11 [net-_u1-pad3_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a12 [net-_u11-pad1_ net-_u1-pad4_ ] net-_u13-pad3_ u13 +a13 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u1-pad5_ u14 +a14 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u1-pad6_ u15 +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u2 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u3 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u4 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u5 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xnor, NgSpice Name: d_xnor +.model u8 d_xnor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u6 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u7 d_xor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54180
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml new file mode 100644 index 00000000..a66526b3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/SN54180_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u5><u8 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Fall Delay (default=1.0e-9)" /></u8><u6 name="type">d_xor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Fall Delay (default=1.0e-9)" /></u6><u7 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Fall Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Fall Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Fall Delay (default=1.0e-9)" /></u12><u13 name="type">d_and<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Fall Delay (default=1.0e-9)" /></u13><u14 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Fall Delay (default=1.0e-9)" /></u14><u15 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /></u15></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54180/analysis b/library/SubcircuitLibrary/SN54180/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54180/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib new file mode 100644 index 00000000..aa224b4d --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC-cache.lib @@ -0,0 +1,139 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_4 +# +DEF adc_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_2 +# +DEF dac_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_2" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -250 200 350 -100 0 1 0 N +X IN1 1 -450 50 200 R 50 50 1 1 I +X IN2 2 -450 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT4 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_8 +# +DEF dac_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir new file mode 100644 index 00000000..1d25f385 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir @@ -0,0 +1,72 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN5442A_IC\SN5442A_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/30/24 18:49:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_nand +U12 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_nand +U31 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U31-Pad3_ d_nand +U32 Net-_U12-Pad3_ Net-_U12-Pad3_ Net-_U32-Pad3_ d_nand +U51 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U51-Pad3_ d_nand +U13 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U13-Pad3_ d_nand +U14 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U14-Pad3_ d_nand +U33 Net-_U13-Pad3_ Net-_U13-Pad3_ Net-_U33-Pad3_ d_nand +U34 Net-_U14-Pad3_ Net-_U14-Pad3_ Net-_U34-Pad3_ d_nand +U52 Net-_U33-Pad3_ Net-_U34-Pad3_ Net-_U52-Pad3_ d_nand +U15 Net-_U11-Pad1_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_nand +U16 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U16-Pad3_ d_nand +U35 Net-_U15-Pad3_ Net-_U15-Pad3_ Net-_U35-Pad3_ d_nand +U36 Net-_U16-Pad3_ Net-_U16-Pad3_ Net-_U36-Pad3_ d_nand +U53 Net-_U35-Pad3_ Net-_U36-Pad3_ Net-_U53-Pad3_ d_nand +U17 Net-_U13-Pad1_ Net-_U15-Pad2_ Net-_U17-Pad3_ d_nand +U18 Net-_U10-Pad1_ Net-_U12-Pad2_ Net-_U18-Pad3_ d_nand +U37 Net-_U17-Pad3_ Net-_U17-Pad3_ Net-_U37-Pad3_ d_nand +U38 Net-_U18-Pad3_ Net-_U18-Pad3_ Net-_U38-Pad3_ d_nand +U54 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U54-Pad3_ d_nand +U19 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U19-Pad3_ d_nand +U20 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U20-Pad3_ d_nand +U39 Net-_U19-Pad3_ Net-_U19-Pad3_ Net-_U39-Pad3_ d_nand +U40 Net-_U20-Pad3_ Net-_U20-Pad3_ Net-_U40-Pad3_ d_nand +U55 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U55-Pad3_ d_nand +U21 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U21-Pad3_ d_nand +U22 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U22-Pad3_ d_nand +U41 Net-_U21-Pad3_ Net-_U21-Pad3_ Net-_U41-Pad3_ d_nand +U42 Net-_U22-Pad3_ Net-_U22-Pad3_ Net-_U42-Pad3_ d_nand +U56 Net-_U41-Pad3_ Net-_U42-Pad3_ Net-_U56-Pad3_ d_nand +U23 Net-_U11-Pad1_ Net-_U15-Pad2_ Net-_U23-Pad3_ d_nand +U24 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U24-Pad3_ d_nand +U43 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U43-Pad3_ d_nand +U44 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U44-Pad3_ d_nand +U57 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U57-Pad3_ d_nand +U25 Net-_U13-Pad1_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_nand +U26 Net-_U10-Pad2_ Net-_U12-Pad2_ Net-_U26-Pad3_ d_nand +U45 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U45-Pad3_ d_nand +U46 Net-_U26-Pad3_ Net-_U26-Pad3_ Net-_U46-Pad3_ d_nand +U58 Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U58-Pad3_ d_nand +U27 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U27-Pad3_ d_nand +U28 Net-_U10-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_nand +U47 Net-_U27-Pad3_ Net-_U27-Pad3_ Net-_U47-Pad3_ d_nand +U48 Net-_U28-Pad3_ Net-_U28-Pad3_ Net-_U48-Pad3_ d_nand +U59 Net-_U47-Pad3_ Net-_U48-Pad3_ Net-_U59-Pad3_ d_nand +U29 Net-_U13-Pad1_ Net-_U11-Pad2_ Net-_U29-Pad3_ d_nand +U30 Net-_U10-Pad1_ Net-_U28-Pad2_ Net-_U30-Pad3_ d_nand +U49 Net-_U29-Pad3_ Net-_U29-Pad3_ Net-_U49-Pad3_ d_nand +U50 Net-_U30-Pad3_ Net-_U30-Pad3_ Net-_U50-Pad3_ d_nand +U60 Net-_U49-Pad3_ Net-_U50-Pad3_ Net-_U60-Pad3_ d_nand +U4 Net-_U2-Pad5_ Net-_U11-Pad1_ d_inverter +U9 Net-_U11-Pad1_ Net-_U13-Pad1_ d_inverter +U3 Net-_U2-Pad6_ Net-_U11-Pad2_ d_inverter +U7 Net-_U11-Pad2_ Net-_U15-Pad2_ d_inverter +U6 Net-_U2-Pad7_ Net-_U10-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U5 Net-_U2-Pad8_ Net-_U12-Pad2_ d_inverter +U8 Net-_U12-Pad2_ Net-_U28-Pad2_ d_inverter +U62 Net-_U51-Pad3_ Net-_U52-Pad3_ Net-_U53-Pad3_ Net-_U54-Pad3_ Net-_U55-Pad3_ Net-_U56-Pad3_ Net-_U57-Pad3_ Net-_U58-Pad3_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ dac_bridge_8 +U61 Net-_U59-Pad3_ Net-_U60-Pad3_ Net-_U1-Pad9_ Net-_U1-Pad10_ dac_bridge_2 +U2 Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U2-Pad7_ Net-_U2-Pad8_ adc_bridge_4 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out new file mode 100644 index 00000000..014d39a6 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.cir.out @@ -0,0 +1,256 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn5442a_ic\sn5442a_ic.cir + +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u31 net-_u11-pad3_ net-_u11-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u12-pad3_ net-_u12-pad3_ net-_u32-pad3_ d_nand +* u51 net-_u31-pad3_ net-_u32-pad3_ net-_u51-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u10-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_nand +* u33 net-_u13-pad3_ net-_u13-pad3_ net-_u33-pad3_ d_nand +* u34 net-_u14-pad3_ net-_u14-pad3_ net-_u34-pad3_ d_nand +* u52 net-_u33-pad3_ net-_u34-pad3_ net-_u52-pad3_ d_nand +* u15 net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_nand +* u35 net-_u15-pad3_ net-_u15-pad3_ net-_u35-pad3_ d_nand +* u36 net-_u16-pad3_ net-_u16-pad3_ net-_u36-pad3_ d_nand +* u53 net-_u35-pad3_ net-_u36-pad3_ net-_u53-pad3_ d_nand +* u17 net-_u13-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_nand +* u18 net-_u10-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_nand +* u37 net-_u17-pad3_ net-_u17-pad3_ net-_u37-pad3_ d_nand +* u38 net-_u18-pad3_ net-_u18-pad3_ net-_u38-pad3_ d_nand +* u54 net-_u37-pad3_ net-_u38-pad3_ net-_u54-pad3_ d_nand +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u10-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u39 net-_u19-pad3_ net-_u19-pad3_ net-_u39-pad3_ d_nand +* u40 net-_u20-pad3_ net-_u20-pad3_ net-_u40-pad3_ d_nand +* u55 net-_u39-pad3_ net-_u40-pad3_ net-_u55-pad3_ d_nand +* u21 net-_u13-pad1_ net-_u11-pad2_ net-_u21-pad3_ d_nand +* u22 net-_u10-pad2_ net-_u12-pad2_ net-_u22-pad3_ d_nand +* u41 net-_u21-pad3_ net-_u21-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u22-pad3_ net-_u22-pad3_ net-_u42-pad3_ d_nand +* u56 net-_u41-pad3_ net-_u42-pad3_ net-_u56-pad3_ d_nand +* u23 net-_u11-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_nand +* u24 net-_u10-pad2_ net-_u12-pad2_ net-_u24-pad3_ d_nand +* u43 net-_u23-pad3_ net-_u23-pad3_ net-_u43-pad3_ d_nand +* u44 net-_u24-pad3_ net-_u24-pad3_ net-_u44-pad3_ d_nand +* u57 net-_u43-pad3_ net-_u44-pad3_ net-_u57-pad3_ d_nand +* u25 net-_u13-pad1_ net-_u15-pad2_ net-_u25-pad3_ d_nand +* u26 net-_u10-pad2_ net-_u12-pad2_ net-_u26-pad3_ d_nand +* u45 net-_u25-pad3_ net-_u25-pad3_ net-_u45-pad3_ d_nand +* u46 net-_u26-pad3_ net-_u26-pad3_ net-_u46-pad3_ d_nand +* u58 net-_u45-pad3_ net-_u46-pad3_ net-_u58-pad3_ d_nand +* u27 net-_u11-pad1_ net-_u11-pad2_ net-_u27-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nand +* u47 net-_u27-pad3_ net-_u27-pad3_ net-_u47-pad3_ d_nand +* u48 net-_u28-pad3_ net-_u28-pad3_ net-_u48-pad3_ d_nand +* u59 net-_u47-pad3_ net-_u48-pad3_ net-_u59-pad3_ d_nand +* u29 net-_u13-pad1_ net-_u11-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u10-pad1_ net-_u28-pad2_ net-_u30-pad3_ d_nand +* u49 net-_u29-pad3_ net-_u29-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u30-pad3_ net-_u30-pad3_ net-_u50-pad3_ d_nand +* u60 net-_u49-pad3_ net-_u50-pad3_ net-_u60-pad3_ d_nand +* u4 net-_u2-pad5_ net-_u11-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u2-pad6_ net-_u11-pad2_ d_inverter +* u7 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad7_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u2-pad8_ net-_u12-pad2_ d_inverter +* u8 net-_u12-pad2_ net-_u28-pad2_ d_inverter +* u62 net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ dac_bridge_8 +* u61 net-_u59-pad3_ net-_u60-pad3_ net-_u1-pad9_ net-_u1-pad10_ dac_bridge_2 +* u2 net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a2 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a3 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u31-pad3_ u31 +a4 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u32-pad3_ u32 +a5 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u51-pad3_ u51 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u33-pad3_ u33 +a9 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u34-pad3_ u34 +a10 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u52-pad3_ u52 +a11 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a13 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u35-pad3_ u35 +a14 [net-_u16-pad3_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a15 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u53-pad3_ u53 +a16 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u17-pad3_ ] net-_u37-pad3_ u37 +a19 [net-_u18-pad3_ net-_u18-pad3_ ] net-_u38-pad3_ u38 +a20 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u54-pad3_ u54 +a21 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a22 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a23 [net-_u19-pad3_ net-_u19-pad3_ ] net-_u39-pad3_ u39 +a24 [net-_u20-pad3_ net-_u20-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u55-pad3_ u55 +a26 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a27 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u22-pad3_ u22 +a28 [net-_u21-pad3_ net-_u21-pad3_ ] net-_u41-pad3_ u41 +a29 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u42-pad3_ u42 +a30 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u56-pad3_ u56 +a31 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a32 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u24-pad3_ u24 +a33 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u43-pad3_ u43 +a34 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u44-pad3_ u44 +a35 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u57-pad3_ u57 +a36 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a37 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u26-pad3_ u26 +a38 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u45-pad3_ u45 +a39 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u46-pad3_ u46 +a40 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u58-pad3_ u58 +a41 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a42 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a43 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u48-pad3_ u48 +a45 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u59-pad3_ u59 +a46 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u29-pad3_ u29 +a47 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a48 [net-_u29-pad3_ net-_u29-pad3_ ] net-_u49-pad3_ u49 +a49 [net-_u30-pad3_ net-_u30-pad3_ ] net-_u50-pad3_ u50 +a50 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u60-pad3_ u60 +a51 net-_u2-pad5_ net-_u11-pad1_ u4 +a52 net-_u11-pad1_ net-_u13-pad1_ u9 +a53 net-_u2-pad6_ net-_u11-pad2_ u3 +a54 net-_u11-pad2_ net-_u15-pad2_ u7 +a55 net-_u2-pad7_ net-_u10-pad1_ u6 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u2-pad8_ net-_u12-pad2_ u5 +a58 net-_u12-pad2_ net-_u28-pad2_ u8 +a59 [net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ ] [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u62 +a60 [net-_u59-pad3_ net-_u60-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ ] u61 +a61 [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u62 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u61 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch new file mode 100644 index 00000000..d1cc4d39 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sch @@ -0,0 +1,1506 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN5442A-cache +EELAYER 25 0 +EELAYER END +$Descr User 23622 27559 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_nand U11 +U 1 1 66815193 +P 13050 4450 +F 0 "U11" H 13050 4450 60 0000 C CNN +F 1 "d_nand" H 13100 4550 60 0000 C CNN +F 2 "" H 13050 4450 60 0000 C CNN +F 3 "" H 13050 4450 60 0000 C CNN + 1 13050 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 66815194 +P 13050 5000 +F 0 "U12" H 13050 5000 60 0000 C CNN +F 1 "d_nand" H 13100 5100 60 0000 C CNN +F 2 "" H 13050 5000 60 0000 C CNN +F 3 "" H 13050 5000 60 0000 C CNN + 1 13050 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U31 +U 1 1 66815195 +P 14200 4450 +F 0 "U31" H 14200 4450 60 0000 C CNN +F 1 "d_nand" H 14250 4550 60 0000 C CNN +F 2 "" H 14200 4450 60 0000 C CNN +F 3 "" H 14200 4450 60 0000 C CNN + 1 14200 4450 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U32 +U 1 1 66815196 +P 14200 5000 +F 0 "U32" H 14200 5000 60 0000 C CNN +F 1 "d_nand" H 14250 5100 60 0000 C CNN +F 2 "" H 14200 5000 60 0000 C CNN +F 3 "" H 14200 5000 60 0000 C CNN + 1 14200 5000 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U51 +U 1 1 66815197 +P 15250 4650 +F 0 "U51" H 15250 4650 60 0000 C CNN +F 1 "d_nand" H 15300 4750 60 0000 C CNN +F 2 "" H 15250 4650 60 0000 C CNN +F 3 "" H 15250 4650 60 0000 C CNN + 1 15250 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 66815198 +P 13050 6050 +F 0 "U13" H 13050 6050 60 0000 C CNN +F 1 "d_nand" H 13100 6150 60 0000 C CNN +F 2 "" H 13050 6050 60 0000 C CNN +F 3 "" H 13050 6050 60 0000 C CNN + 1 13050 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 66815199 +P 13050 6600 +F 0 "U14" H 13050 6600 60 0000 C CNN +F 1 "d_nand" H 13100 6700 60 0000 C CNN +F 2 "" H 13050 6600 60 0000 C CNN +F 3 "" H 13050 6600 60 0000 C CNN + 1 13050 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U33 +U 1 1 6681519A +P 14200 6050 +F 0 "U33" H 14200 6050 60 0000 C CNN +F 1 "d_nand" H 14250 6150 60 0000 C CNN +F 2 "" H 14200 6050 60 0000 C CNN +F 3 "" H 14200 6050 60 0000 C CNN + 1 14200 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U34 +U 1 1 6681519B +P 14200 6600 +F 0 "U34" H 14200 6600 60 0000 C CNN +F 1 "d_nand" H 14250 6700 60 0000 C CNN +F 2 "" H 14200 6600 60 0000 C CNN +F 3 "" H 14200 6600 60 0000 C CNN + 1 14200 6600 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U52 +U 1 1 6681519C +P 15250 6250 +F 0 "U52" H 15250 6250 60 0000 C CNN +F 1 "d_nand" H 15300 6350 60 0000 C CNN +F 2 "" H 15250 6250 60 0000 C CNN +F 3 "" H 15250 6250 60 0000 C CNN + 1 15250 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 6681519D +P 13050 7750 +F 0 "U15" H 13050 7750 60 0000 C CNN +F 1 "d_nand" H 13100 7850 60 0000 C CNN +F 2 "" H 13050 7750 60 0000 C CNN +F 3 "" H 13050 7750 60 0000 C CNN + 1 13050 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 6681519E +P 13050 8300 +F 0 "U16" H 13050 8300 60 0000 C CNN +F 1 "d_nand" H 13100 8400 60 0000 C CNN +F 2 "" H 13050 8300 60 0000 C CNN +F 3 "" H 13050 8300 60 0000 C CNN + 1 13050 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 6681519F +P 14200 7750 +F 0 "U35" H 14200 7750 60 0000 C CNN +F 1 "d_nand" H 14250 7850 60 0000 C CNN +F 2 "" H 14200 7750 60 0000 C CNN +F 3 "" H 14200 7750 60 0000 C CNN + 1 14200 7750 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U36 +U 1 1 668151A0 +P 14200 8300 +F 0 "U36" H 14200 8300 60 0000 C CNN +F 1 "d_nand" H 14250 8400 60 0000 C CNN +F 2 "" H 14200 8300 60 0000 C CNN +F 3 "" H 14200 8300 60 0000 C CNN + 1 14200 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U53 +U 1 1 668151A1 +P 15250 7950 +F 0 "U53" H 15250 7950 60 0000 C CNN +F 1 "d_nand" H 15300 8050 60 0000 C CNN +F 2 "" H 15250 7950 60 0000 C CNN +F 3 "" H 15250 7950 60 0000 C CNN + 1 15250 7950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 668151A2 +P 13050 9250 +F 0 "U17" H 13050 9250 60 0000 C CNN +F 1 "d_nand" H 13100 9350 60 0000 C CNN +F 2 "" H 13050 9250 60 0000 C CNN +F 3 "" H 13050 9250 60 0000 C CNN + 1 13050 9250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 668151A3 +P 13050 9800 +F 0 "U18" H 13050 9800 60 0000 C CNN +F 1 "d_nand" H 13100 9900 60 0000 C CNN +F 2 "" H 13050 9800 60 0000 C CNN +F 3 "" H 13050 9800 60 0000 C CNN + 1 13050 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U37 +U 1 1 668151A4 +P 14200 9250 +F 0 "U37" H 14200 9250 60 0000 C CNN +F 1 "d_nand" H 14250 9350 60 0000 C CNN +F 2 "" H 14200 9250 60 0000 C CNN +F 3 "" H 14200 9250 60 0000 C CNN + 1 14200 9250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U38 +U 1 1 668151A5 +P 14200 9800 +F 0 "U38" H 14200 9800 60 0000 C CNN +F 1 "d_nand" H 14250 9900 60 0000 C CNN +F 2 "" H 14200 9800 60 0000 C CNN +F 3 "" H 14200 9800 60 0000 C CNN + 1 14200 9800 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U54 +U 1 1 668151A6 +P 15250 9450 +F 0 "U54" H 15250 9450 60 0000 C CNN +F 1 "d_nand" H 15300 9550 60 0000 C CNN +F 2 "" H 15250 9450 60 0000 C CNN +F 3 "" H 15250 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Wire Line + 15700 7900 16500 7900 +Wire Wire Line + 16500 7900 16500 9550 +Wire Wire Line + 16500 9550 17150 9550 +Wire Wire Line + 17150 9650 16350 9650 +Wire Wire Line + 16350 9650 16350 9400 +Wire Wire Line + 16350 9400 15700 9400 +Wire Wire Line + 17150 9750 16300 9750 +Wire Wire Line + 16300 9750 16300 11000 +Wire Wire Line + 16300 11000 15700 11000 +Wire Wire Line + 15700 12300 16650 12300 +Wire Wire Line + 16650 12300 16650 9850 +Wire Wire Line + 16650 9850 17150 9850 +Wire Wire Line + 17150 9950 16800 9950 +Wire Wire Line + 16800 9950 16800 13550 +Wire Wire Line + 16800 13550 15700 13550 +Wire Wire Line + 17150 10050 17000 10050 +Wire Wire Line + 17000 10050 17000 15000 +Wire Wire Line + 17000 15000 15700 15000 +Wire Wire Line + 15700 16400 16400 16400 +Wire Wire Line + 16400 16400 16400 17100 +Wire Wire Line + 16400 17100 16800 17100 +Wire Wire Line + 16800 17200 16350 17200 +Wire Wire Line + 16350 17200 16350 17950 +Wire Wire Line + 16350 17950 15700 17950 +Wire Wire Line + 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+ 2 19300 9250 + -1 0 0 1 +$EndComp +Wire Wire Line + 19050 9250 18850 9250 +Wire Wire Line + 18850 9250 18850 9450 +Wire Wire Line + 18850 9450 18300 9450 +$Comp +L PORT U1 +U 3 1 66816C29 +P 19400 9450 +F 0 "U1" H 19450 9550 30 0000 C CNN +F 1 "PORT" H 19400 9450 30 0000 C CNN +F 2 "" H 19400 9450 60 0000 C CNN +F 3 "" H 19400 9450 60 0000 C CNN + 3 19400 9450 + -1 0 0 1 +$EndComp +Wire Wire Line + 19150 9450 18950 9450 +Wire Wire Line + 18950 9450 18950 9550 +Wire Wire Line + 18950 9550 18300 9550 +$Comp +L PORT U1 +U 4 1 66816E91 +P 19450 9650 +F 0 "U1" H 19500 9750 30 0000 C CNN +F 1 "PORT" H 19450 9650 30 0000 C CNN +F 2 "" H 19450 9650 60 0000 C CNN +F 3 "" H 19450 9650 60 0000 C CNN + 4 19450 9650 + -1 0 0 1 +$EndComp +Wire Wire Line + 19200 9650 18300 9650 +$Comp +L PORT U1 +U 5 1 66817110 +P 19500 9850 +F 0 "U1" H 19550 9950 30 0000 C CNN +F 1 "PORT" H 19500 9850 30 0000 C CNN +F 2 "" H 19500 9850 60 0000 C CNN +F 3 "" H 19500 9850 60 0000 C CNN + 5 19500 9850 + -1 0 0 1 +$EndComp +Wire Wire Line + 19250 9850 19100 9850 +Wire Wire Line + 19100 9850 19100 9750 +Wire Wire Line + 19100 9750 18300 9750 +$Comp +L PORT U1 +U 6 1 66817388 +P 19600 10050 +F 0 "U1" H 19650 10150 30 0000 C CNN +F 1 "PORT" H 19600 10050 30 0000 C CNN +F 2 "" H 19600 10050 60 0000 C CNN +F 3 "" H 19600 10050 60 0000 C CNN + 6 19600 10050 + -1 0 0 1 +$EndComp +Wire Wire Line + 19350 10050 18950 10050 +Wire Wire Line + 18950 10050 18950 9850 +Wire Wire Line + 18950 9850 18300 9850 +$Comp +L PORT U1 +U 7 1 66817606 +P 19650 10250 +F 0 "U1" H 19700 10350 30 0000 C CNN +F 1 "PORT" H 19650 10250 30 0000 C CNN +F 2 "" H 19650 10250 60 0000 C CNN +F 3 "" H 19650 10250 60 0000 C CNN + 7 19650 10250 + -1 0 0 1 +$EndComp +Wire Wire Line + 19400 10250 18800 10250 +Wire Wire Line + 18800 10250 18800 9950 +Wire Wire Line + 18800 9950 18300 9950 +$Comp +L PORT U1 +U 8 1 66817F42 +P 19650 10500 +F 0 "U1" H 19700 10600 30 0000 C CNN +F 1 "PORT" H 19650 10500 30 0000 C CNN +F 2 "" H 19650 10500 60 0000 C CNN +F 3 "" H 19650 10500 60 0000 C CNN + 8 19650 10500 + -1 0 0 1 +$EndComp +Wire Wire Line + 19400 10500 18600 10500 +Wire Wire Line + 18600 10500 18600 10050 +Wire Wire Line + 18600 10050 18300 10050 +$Comp +L PORT U1 +U 9 1 668190C9 +P 18400 16950 +F 0 "U1" H 18450 17050 30 0000 C CNN +F 1 "PORT" H 18400 16950 30 0000 C CNN +F 2 "" H 18400 16950 60 0000 C CNN +F 3 "" H 18400 16950 60 0000 C CNN + 9 18400 16950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 10 1 6681932C +P 18400 17300 +F 0 "U1" H 18450 17400 30 0000 C CNN +F 1 "PORT" H 18400 17300 30 0000 C CNN +F 2 "" H 18400 17300 60 0000 C CNN +F 3 "" H 18400 17300 60 0000 C CNN + 10 18400 17300 + -1 0 0 1 +$EndComp +Wire Wire Line + 18150 16950 18000 16950 +Wire Wire Line + 18000 16950 18000 17100 +Wire Wire Line + 18000 17100 17800 17100 +Wire Wire Line + 17800 17200 18000 17200 +Wire Wire Line + 18000 17200 18000 17300 +Wire Wire Line + 18000 17300 18150 17300 +$Comp +L PORT U1 +U 11 1 6681AADD +P 5900 10550 +F 0 "U1" H 5950 10650 30 0000 C CNN +F 1 "PORT" H 5900 10550 30 0000 C CNN +F 2 "" H 5900 10550 60 0000 C CNN +F 3 "" H 5900 10550 60 0000 C CNN + 11 5900 10550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6681AC90 +P 5900 10350 +F 0 "U1" H 5950 10450 30 0000 C CNN +F 1 "PORT" H 5900 10350 30 0000 C CNN +F 2 "" H 5900 10350 60 0000 C CNN +F 3 "" H 5900 10350 60 0000 C CNN + 12 5900 10350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6681AD61 +P 5900 10150 +F 0 "U1" H 5950 10250 30 0000 C CNN +F 1 "PORT" H 5900 10150 30 0000 C CNN +F 2 "" H 5900 10150 60 0000 C CNN +F 3 "" H 5900 10150 60 0000 C CNN + 13 5900 10150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 6681AE2E +P 5900 9950 +F 0 "U1" H 5950 10050 30 0000 C CNN +F 1 "PORT" H 5900 9950 30 0000 C CNN +F 2 "" H 5900 9950 60 0000 C CNN +F 3 "" H 5900 9950 60 0000 C CNN + 14 5900 9950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6150 9950 6350 9950 +Wire Wire Line + 6350 9950 6350 10000 +Wire Wire Line + 6350 10000 6450 10000 +Wire Wire Line + 6150 10150 6350 10150 +Wire Wire Line + 6350 10150 6350 10100 +Wire Wire Line + 6350 10100 6450 10100 +Wire Wire Line + 6450 10200 6350 10200 +Wire Wire Line + 6350 10200 6350 10350 +Wire Wire Line + 6350 10350 6150 10350 +Wire Wire Line + 6150 10550 6400 10550 +Wire Wire Line + 6400 10550 6400 10300 +Wire Wire Line + 6400 10300 6450 10300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub new file mode 100644 index 00000000..98a5525d --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC.sub @@ -0,0 +1,250 @@ +* Subcircuit SN5442A_IC +.subckt SN5442A_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn5442a_ic\sn5442a_ic.cir +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nand +* u12 net-_u10-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nand +* u31 net-_u11-pad3_ net-_u11-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u12-pad3_ net-_u12-pad3_ net-_u32-pad3_ d_nand +* u51 net-_u31-pad3_ net-_u32-pad3_ net-_u51-pad3_ d_nand +* u13 net-_u13-pad1_ net-_u11-pad2_ net-_u13-pad3_ d_nand +* u14 net-_u10-pad1_ net-_u12-pad2_ net-_u14-pad3_ d_nand +* u33 net-_u13-pad3_ net-_u13-pad3_ net-_u33-pad3_ d_nand +* u34 net-_u14-pad3_ net-_u14-pad3_ net-_u34-pad3_ d_nand +* u52 net-_u33-pad3_ net-_u34-pad3_ net-_u52-pad3_ d_nand +* u15 net-_u11-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nand +* u16 net-_u10-pad1_ net-_u12-pad2_ net-_u16-pad3_ d_nand +* u35 net-_u15-pad3_ net-_u15-pad3_ net-_u35-pad3_ d_nand +* u36 net-_u16-pad3_ net-_u16-pad3_ net-_u36-pad3_ d_nand +* u53 net-_u35-pad3_ net-_u36-pad3_ net-_u53-pad3_ d_nand +* u17 net-_u13-pad1_ net-_u15-pad2_ net-_u17-pad3_ d_nand +* u18 net-_u10-pad1_ net-_u12-pad2_ net-_u18-pad3_ d_nand +* u37 net-_u17-pad3_ net-_u17-pad3_ net-_u37-pad3_ d_nand +* u38 net-_u18-pad3_ net-_u18-pad3_ net-_u38-pad3_ d_nand +* u54 net-_u37-pad3_ net-_u38-pad3_ net-_u54-pad3_ d_nand +* u19 net-_u11-pad1_ net-_u11-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u10-pad2_ net-_u12-pad2_ net-_u20-pad3_ d_nand +* u39 net-_u19-pad3_ net-_u19-pad3_ net-_u39-pad3_ d_nand +* u40 net-_u20-pad3_ net-_u20-pad3_ net-_u40-pad3_ d_nand +* u55 net-_u39-pad3_ net-_u40-pad3_ net-_u55-pad3_ d_nand +* u21 net-_u13-pad1_ net-_u11-pad2_ net-_u21-pad3_ d_nand +* u22 net-_u10-pad2_ net-_u12-pad2_ net-_u22-pad3_ d_nand +* u41 net-_u21-pad3_ net-_u21-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u22-pad3_ net-_u22-pad3_ net-_u42-pad3_ d_nand +* u56 net-_u41-pad3_ net-_u42-pad3_ net-_u56-pad3_ d_nand +* u23 net-_u11-pad1_ net-_u15-pad2_ net-_u23-pad3_ d_nand +* u24 net-_u10-pad2_ net-_u12-pad2_ net-_u24-pad3_ d_nand +* u43 net-_u23-pad3_ net-_u23-pad3_ net-_u43-pad3_ d_nand +* u44 net-_u24-pad3_ net-_u24-pad3_ net-_u44-pad3_ d_nand +* u57 net-_u43-pad3_ net-_u44-pad3_ net-_u57-pad3_ d_nand +* u25 net-_u13-pad1_ net-_u15-pad2_ net-_u25-pad3_ d_nand +* u26 net-_u10-pad2_ net-_u12-pad2_ net-_u26-pad3_ d_nand +* u45 net-_u25-pad3_ net-_u25-pad3_ net-_u45-pad3_ d_nand +* u46 net-_u26-pad3_ net-_u26-pad3_ net-_u46-pad3_ d_nand +* u58 net-_u45-pad3_ net-_u46-pad3_ net-_u58-pad3_ d_nand +* u27 net-_u11-pad1_ net-_u11-pad2_ net-_u27-pad3_ d_nand +* u28 net-_u10-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_nand +* u47 net-_u27-pad3_ net-_u27-pad3_ net-_u47-pad3_ d_nand +* u48 net-_u28-pad3_ net-_u28-pad3_ net-_u48-pad3_ d_nand +* u59 net-_u47-pad3_ net-_u48-pad3_ net-_u59-pad3_ d_nand +* u29 net-_u13-pad1_ net-_u11-pad2_ net-_u29-pad3_ d_nand +* u30 net-_u10-pad1_ net-_u28-pad2_ net-_u30-pad3_ d_nand +* u49 net-_u29-pad3_ net-_u29-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u30-pad3_ net-_u30-pad3_ net-_u50-pad3_ d_nand +* u60 net-_u49-pad3_ net-_u50-pad3_ net-_u60-pad3_ d_nand +* u4 net-_u2-pad5_ net-_u11-pad1_ d_inverter +* u9 net-_u11-pad1_ net-_u13-pad1_ d_inverter +* u3 net-_u2-pad6_ net-_u11-pad2_ d_inverter +* u7 net-_u11-pad2_ net-_u15-pad2_ d_inverter +* u6 net-_u2-pad7_ net-_u10-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u5 net-_u2-pad8_ net-_u12-pad2_ d_inverter +* u8 net-_u12-pad2_ net-_u28-pad2_ d_inverter +* u62 net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ dac_bridge_8 +* u61 net-_u59-pad3_ net-_u60-pad3_ net-_u1-pad9_ net-_u1-pad10_ dac_bridge_2 +* u2 net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ adc_bridge_4 +a1 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a2 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a3 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u31-pad3_ u31 +a4 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u32-pad3_ u32 +a5 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u51-pad3_ u51 +a6 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u13-pad3_ u13 +a7 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u14-pad3_ u14 +a8 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u33-pad3_ u33 +a9 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u34-pad3_ u34 +a10 [net-_u33-pad3_ net-_u34-pad3_ ] net-_u52-pad3_ u52 +a11 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a12 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u16-pad3_ u16 +a13 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u35-pad3_ u35 +a14 [net-_u16-pad3_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a15 [net-_u35-pad3_ net-_u36-pad3_ ] net-_u53-pad3_ u53 +a16 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u17-pad3_ u17 +a17 [net-_u10-pad1_ net-_u12-pad2_ ] net-_u18-pad3_ u18 +a18 [net-_u17-pad3_ net-_u17-pad3_ ] net-_u37-pad3_ u37 +a19 [net-_u18-pad3_ net-_u18-pad3_ ] net-_u38-pad3_ u38 +a20 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u54-pad3_ u54 +a21 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u19-pad3_ u19 +a22 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u20-pad3_ u20 +a23 [net-_u19-pad3_ net-_u19-pad3_ ] net-_u39-pad3_ u39 +a24 [net-_u20-pad3_ net-_u20-pad3_ ] net-_u40-pad3_ u40 +a25 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u55-pad3_ u55 +a26 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u21-pad3_ u21 +a27 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u22-pad3_ u22 +a28 [net-_u21-pad3_ net-_u21-pad3_ ] net-_u41-pad3_ u41 +a29 [net-_u22-pad3_ net-_u22-pad3_ ] net-_u42-pad3_ u42 +a30 [net-_u41-pad3_ net-_u42-pad3_ ] net-_u56-pad3_ u56 +a31 [net-_u11-pad1_ net-_u15-pad2_ ] net-_u23-pad3_ u23 +a32 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u24-pad3_ u24 +a33 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u43-pad3_ u43 +a34 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u44-pad3_ u44 +a35 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u57-pad3_ u57 +a36 [net-_u13-pad1_ net-_u15-pad2_ ] net-_u25-pad3_ u25 +a37 [net-_u10-pad2_ net-_u12-pad2_ ] net-_u26-pad3_ u26 +a38 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u45-pad3_ u45 +a39 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u46-pad3_ u46 +a40 [net-_u45-pad3_ net-_u46-pad3_ ] net-_u58-pad3_ u58 +a41 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u27-pad3_ u27 +a42 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a43 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u47-pad3_ u47 +a44 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u48-pad3_ u48 +a45 [net-_u47-pad3_ net-_u48-pad3_ ] net-_u59-pad3_ u59 +a46 [net-_u13-pad1_ net-_u11-pad2_ ] net-_u29-pad3_ u29 +a47 [net-_u10-pad1_ net-_u28-pad2_ ] net-_u30-pad3_ u30 +a48 [net-_u29-pad3_ net-_u29-pad3_ ] net-_u49-pad3_ u49 +a49 [net-_u30-pad3_ net-_u30-pad3_ ] net-_u50-pad3_ u50 +a50 [net-_u49-pad3_ net-_u50-pad3_ ] net-_u60-pad3_ u60 +a51 net-_u2-pad5_ net-_u11-pad1_ u4 +a52 net-_u11-pad1_ net-_u13-pad1_ u9 +a53 net-_u2-pad6_ net-_u11-pad2_ u3 +a54 net-_u11-pad2_ net-_u15-pad2_ u7 +a55 net-_u2-pad7_ net-_u10-pad1_ u6 +a56 net-_u10-pad1_ net-_u10-pad2_ u10 +a57 net-_u2-pad8_ net-_u12-pad2_ u5 +a58 net-_u12-pad2_ net-_u28-pad2_ u8 +a59 [net-_u51-pad3_ net-_u52-pad3_ net-_u53-pad3_ net-_u54-pad3_ net-_u55-pad3_ net-_u56-pad3_ net-_u57-pad3_ net-_u58-pad3_ ] [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u62 +a60 [net-_u59-pad3_ net-_u60-pad3_ ] [net-_u1-pad9_ net-_u1-pad10_ ] u61 +a61 [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ ] [net-_u2-pad5_ net-_u2-pad6_ net-_u2-pad7_ net-_u2-pad8_ ] u2 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u52 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u20 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u55 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u21 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u22 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u56 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u43 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u44 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u57 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u45 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u46 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u58 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u27 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u28 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u47 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u59 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u60 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge +.model u62 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge +.model u61 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN5442A_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml new file mode 100644 index 00000000..8c4697fb --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/SN5442A_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u11 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u11><u12 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u12><u31 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u32><u51 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u51><u13 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u13><u14 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u14><u33 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u34><u52 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u52><u15 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u15><u16 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u16><u35 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u36><u53 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u53><u17 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u18><u37 name="type">d_nand<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_nand<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u38><u54 name="type">d_nand<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u54><u19 name="type">d_nand<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_nand<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u20><u39 name="type">d_nand<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u39><u40 name="type">d_nand<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u40><u55 name="type">d_nand<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u55><u21 name="type">d_nand<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_nand<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u22><u41 name="type">d_nand<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u41><u42 name="type">d_nand<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u42><u56 name="type">d_nand<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u56><u23 name="type">d_nand<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u24><u43 name="type">d_nand<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_nand<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u44><u57 name="type">d_nand<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u57><u25 name="type">d_nand<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u26><u45 name="type">d_nand<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_nand<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u46><u58 name="type">d_nand<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u58><u27 name="type">d_nand<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nand<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u28><u47 name="type">d_nand<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u47><u48 name="type">d_nand<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u48><u59 name="type">d_nand<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u59><u29 name="type">d_nand<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u30><u49 name="type">d_nand<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u49><u50 name="type">d_nand<field145 name="Enter Rise Delay (default=1.0e-9)" /><field146 name="Enter Fall Delay (default=1.0e-9)" /><field147 name="Enter Input Load (default=1.0e-12)" /></u50><u60 name="type">d_nand<field148 name="Enter Rise Delay (default=1.0e-9)" /><field149 name="Enter Fall Delay (default=1.0e-9)" /><field150 name="Enter Input Load (default=1.0e-12)" /></u60><u4 name="type">d_inverter<field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /><field153 name="Enter Input Load (default=1.0e-12)" /></u4><u9 name="type">d_inverter<field154 name="Enter Rise Delay (default=1.0e-9)" /><field155 name="Enter Fall Delay (default=1.0e-9)" /><field156 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_inverter<field157 name="Enter Rise Delay (default=1.0e-9)" /><field158 name="Enter Fall Delay (default=1.0e-9)" /><field159 name="Enter Input Load (default=1.0e-12)" /></u3><u7 name="type">d_inverter<field160 name="Enter Rise Delay (default=1.0e-9)" /><field161 name="Enter Fall Delay (default=1.0e-9)" /><field162 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_inverter<field163 name="Enter Rise Delay (default=1.0e-9)" /><field164 name="Enter Fall Delay (default=1.0e-9)" /><field165 name="Enter Input Load (default=1.0e-12)" /></u6><u10 name="type">d_inverter<field166 name="Enter Rise Delay (default=1.0e-9)" /><field167 name="Enter Fall Delay (default=1.0e-9)" /><field168 name="Enter Input Load (default=1.0e-12)" /></u10><u5 name="type">d_inverter<field169 name="Enter Rise Delay (default=1.0e-9)" /><field170 name="Enter Fall Delay (default=1.0e-9)" /><field171 name="Enter Input Load (default=1.0e-12)" /></u5><u8 name="type">d_inverter<field172 name="Enter Rise Delay (default=1.0e-9)" /><field173 name="Enter Fall Delay (default=1.0e-9)" /><field174 name="Enter Input Load (default=1.0e-12)" /></u8><u62 name="type">dac_bridge<field175 name="Enter value for out_low (default=0.0)" /><field176 name="Enter value for out_high (default=5.0)" /><field177 name="Enter value for out_undef (default=0.5)" /><field178 name="Enter value for input load (default=1.0e-12)" /><field179 name="Enter the Rise Time (default=1.0e-9)" /><field180 name="Enter the Fall Time (default=1.0e-9)" /></u62><u61 name="type">dac_bridge<field181 name="Enter value for out_low (default=0.0)" /><field182 name="Enter value for out_high (default=5.0)" /><field183 name="Enter value for out_undef (default=0.5)" /><field184 name="Enter value for input load (default=1.0e-12)" /><field185 name="Enter the Rise Time (default=1.0e-9)" /><field186 name="Enter the Fall Time (default=1.0e-9)" /></u61><u2 name="type">adc_bridge<field187 name="Enter value for in_low (default=1.0)" /><field188 name="Enter value for in_high (default=2.0)" /><field189 name="Enter Rise Delay (default=1.0e-9)" /><field190 name="Enter Fall Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN5442A_sub/analysis b/library/SubcircuitLibrary/SN5442A_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN5442A_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro new file mode 100644 index 00000000..81bd9ad4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.pro @@ -0,0 +1,70 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Subckt +LibName23=transistors +LibName24=conn +LibName25=eSim_Plot +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User + diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib new file mode 100644 index 00000000..3e8d471c --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir new file mode 100644 index 00000000..f00d5bd3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir @@ -0,0 +1,51 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN54LS183\SN54LS183.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/25 22:53:19 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad2_ Net-_U18-Pad2_ Net-_U20-Pad2_ d_and +U4 Net-_U2-Pad1_ Net-_U18-Pad2_ Net-_U28-Pad2_ d_and +U5 Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U16-Pad1_ d_and +U16 Net-_U16-Pad1_ Net-_U1-Pad1_ Net-_U16-Pad3_ d_and +U6 Net-_U2-Pad1_ Net-_U1-Pad3_ Net-_U17-Pad1_ d_and +U17 Net-_U17-Pad1_ Net-_U1-Pad1_ Net-_U17-Pad3_ d_and +U7 Net-_U2-Pad1_ Net-_U2-Pad2_ Net-_U18-Pad1_ d_and +U18 Net-_U18-Pad1_ Net-_U18-Pad2_ Net-_U18-Pad3_ d_and +U8 Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U19-Pad1_ d_and +U19 Net-_U19-Pad1_ Net-_U18-Pad2_ Net-_U19-Pad3_ d_and +U9 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U25-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_and +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_and +U12 Net-_U1-Pad11_ Net-_U10-Pad1_ Net-_U12-Pad3_ d_and +U21 Net-_U12-Pad3_ Net-_U1-Pad13_ Net-_U21-Pad3_ d_and +U13 Net-_U11-Pad1_ Net-_U1-Pad12_ Net-_U13-Pad3_ d_and +U22 Net-_U13-Pad3_ Net-_U1-Pad13_ Net-_U22-Pad3_ d_and +U25 Net-_U25-Pad1_ Net-_U10-Pad3_ Net-_U25-Pad3_ d_nor +U31 Net-_U25-Pad3_ Net-_U11-Pad3_ Net-_U1-Pad10_ d_nor +U29 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U29-Pad3_ d_nor +U30 Net-_U23-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nor +U33 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U1-Pad8_ d_nor +U14 Net-_U11-Pad1_ Net-_U10-Pad1_ Net-_U14-Pad3_ d_and +U23 Net-_U14-Pad3_ Net-_U10-Pad2_ Net-_U23-Pad3_ d_and +U15 Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U15-Pad3_ d_and +U24 Net-_U15-Pad3_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_and +U1 Net-_U1-Pad1_ ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ ? Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ ? PORT +U35 Net-_U1-Pad4_ Net-_U2-Pad1_ d_inverter +U34 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U36 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter +U38 Net-_U1-Pad11_ Net-_U11-Pad1_ d_inverter +U37 Net-_U1-Pad12_ Net-_U10-Pad1_ d_inverter +U39 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter +U20 Net-_U2-Pad3_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_or +U28 Net-_U20-Pad3_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_or +U40 Net-_U28-Pad3_ Net-_U1-Pad5_ d_inverter +U41 Net-_U32-Pad3_ Net-_U1-Pad6_ d_inverter +U26 Net-_U16-Pad3_ Net-_U17-Pad3_ Net-_U26-Pad3_ d_or +U27 Net-_U18-Pad3_ Net-_U19-Pad3_ Net-_U27-Pad3_ d_or +U32 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U32-Pad3_ d_or + +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out new file mode 100644 index 00000000..198578d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.cir.out @@ -0,0 +1,172 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir + +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u1 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? port +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch new file mode 100644 index 00000000..b972d850 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sch @@ -0,0 +1,993 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN54LS183-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 67812973 +P 12300 3250 +F 0 "U2" H 12300 3250 60 0000 C CNN +F 1 "d_and" H 12350 3350 60 0000 C CNN +F 2 "" H 12300 3250 60 0000 C CNN +F 3 "" H 12300 3250 60 0000 C CNN + 1 12300 3250 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 67812A00 +P 12300 3650 +F 0 "U3" H 12300 3650 60 0000 C CNN +F 1 "d_and" H 12350 3750 60 0000 C CNN +F 2 "" H 12300 3650 60 0000 C CNN +F 3 "" H 12300 3650 60 0000 C CNN + 1 12300 3650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U4 +U 1 1 67812A24 +P 12300 4000 +F 0 "U4" H 12300 4000 60 0000 C CNN +F 1 "d_and" H 12350 4100 60 0000 C CNN +F 2 "" H 12300 4000 60 0000 C CNN +F 3 "" H 12300 4000 60 0000 C CNN + 1 12300 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_and U5 +U 1 1 67812AC5 +P 12300 4600 +F 0 "U5" H 12300 4600 60 0000 C CNN +F 1 "d_and" H 12350 4700 60 0000 C CNN +F 2 "" H 12300 4600 60 0000 C CNN +F 3 "" H 12300 4600 60 0000 C CNN + 1 12300 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U16 +U 1 1 67812ACB +P 13250 4850 +F 0 "U16" H 13250 4850 60 0000 C CNN +F 1 "d_and" H 13300 4950 60 0000 C CNN +F 2 "" H 13250 4850 60 0000 C CNN +F 3 "" H 13250 4850 60 0000 C CNN + 1 13250 4850 + 1 0 0 -1 +$EndComp +$Comp +L d_and U6 +U 1 1 67812AD1 +P 12300 5350 +F 0 "U6" H 12300 5350 60 0000 C CNN +F 1 "d_and" H 12350 5450 60 0000 C CNN +F 2 "" H 12300 5350 60 0000 C CNN +F 3 "" H 12300 5350 60 0000 C CNN + 1 12300 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U17 +U 1 1 67812AE3 +P 13250 5600 +F 0 "U17" H 13250 5600 60 0000 C CNN +F 1 "d_and" H 13300 5700 60 0000 C CNN +F 2 "" H 13250 5600 60 0000 C CNN +F 3 "" H 13250 5600 60 0000 C CNN + 1 13250 5600 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 67813298 +P 12300 6050 +F 0 "U7" H 12300 6050 60 0000 C CNN +F 1 "d_and" H 12350 6150 60 0000 C CNN +F 2 "" H 12300 6050 60 0000 C CNN +F 3 "" H 12300 6050 60 0000 C CNN + 1 12300 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U18 +U 1 1 6781329E +P 13250 6300 +F 0 "U18" H 13250 6300 60 0000 C CNN +F 1 "d_and" H 13300 6400 60 0000 C CNN +F 2 "" H 13250 6300 60 0000 C CNN +F 3 "" H 13250 6300 60 0000 C CNN + 1 13250 6300 + 1 0 0 -1 +$EndComp +$Comp +L d_and U8 +U 1 1 678132A4 +P 12300 6800 +F 0 "U8" H 12300 6800 60 0000 C CNN +F 1 "d_and" H 12350 6900 60 0000 C CNN +F 2 "" H 12300 6800 60 0000 C CNN +F 3 "" H 12300 6800 60 0000 C CNN + 1 12300 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_and U19 +U 1 1 678132AA +P 13250 7050 +F 0 "U19" H 13250 7050 60 0000 C CNN +F 1 "d_and" H 13300 7150 60 0000 C CNN +F 2 "" H 13250 7050 60 0000 C CNN +F 3 "" H 13250 7050 60 0000 C CNN + 1 13250 7050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U9 +U 1 1 678150DC +P 12750 8100 +F 0 "U9" H 12750 8100 60 0000 C CNN +F 1 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C CNN +F 3 "" H 13700 9700 60 0000 C CNN + 1 13700 9700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U13 +U 1 1 678150FA +P 12750 10200 +F 0 "U13" H 12750 10200 60 0000 C CNN +F 1 "d_and" H 12800 10300 60 0000 C CNN +F 2 "" H 12750 10200 60 0000 C CNN +F 3 "" H 12750 10200 60 0000 C CNN + 1 12750 10200 + 1 0 0 -1 +$EndComp +$Comp +L d_and U22 +U 1 1 67815100 +P 13700 10450 +F 0 "U22" H 13700 10450 60 0000 C CNN +F 1 "d_and" H 13750 10550 60 0000 C CNN +F 2 "" H 13700 10450 60 0000 C CNN +F 3 "" H 13700 10450 60 0000 C CNN + 1 13700 10450 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U25 +U 1 1 67815106 +P 14150 8300 +F 0 "U25" H 14150 8300 60 0000 C CNN +F 1 "d_nor" H 14200 8400 60 0000 C CNN +F 2 "" H 14150 8300 60 0000 C CNN +F 3 "" H 14150 8300 60 0000 C CNN + 1 14150 8300 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U31 +U 1 1 6781510C +P 15400 8600 +F 0 "U31" H 15400 8600 60 0000 C CNN +F 1 "d_nor" H 15450 8700 60 0000 C CNN +F 2 "" H 15400 8600 60 0000 C CNN +F 3 "" H 15400 8600 60 0000 C CNN + 1 15400 8600 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U29 +U 1 1 67815112 +P 15150 10350 +F 0 "U29" H 15150 10350 60 0000 C CNN +F 1 "d_nor" H 15200 10450 60 0000 C CNN +F 2 "" H 15150 10350 60 0000 C CNN +F 3 "" H 15150 10350 60 0000 C CNN + 1 15150 10350 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U30 +U 1 1 67815118 +P 15150 11100 +F 0 "U30" H 15150 11100 60 0000 C CNN +F 1 "d_nor" H 15200 11200 60 0000 C CNN +F 2 "" H 15150 11100 60 0000 C CNN +F 3 "" H 15150 11100 60 0000 C CNN + 1 15150 11100 + 1 0 0 -1 +$EndComp +$Comp +L d_nor U33 +U 1 1 6781511E +P 16350 10700 +F 0 "U33" H 16350 10700 60 0000 C CNN +F 1 "d_nor" H 16400 10800 60 0000 C CNN +F 2 "" H 16350 10700 60 0000 C CNN +F 3 "" H 16350 10700 60 0000 C CNN + 1 16350 10700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U14 +U 1 1 67815146 +P 12750 10900 +F 0 "U14" H 12750 10900 60 0000 C CNN +F 1 "d_and" H 12800 11000 60 0000 C CNN +F 2 "" H 12750 10900 60 0000 C CNN +F 3 "" H 12750 10900 60 0000 C CNN + 1 12750 10900 + 1 0 0 -1 +$EndComp +$Comp +L d_and U23 +U 1 1 6781514C +P 13700 11150 +F 0 "U23" H 13700 11150 60 0000 C CNN +F 1 "d_and" H 13750 11250 60 0000 C CNN +F 2 "" H 13700 11150 60 0000 C CNN +F 3 "" H 13700 11150 60 0000 C CNN + 1 13700 11150 + 1 0 0 -1 +$EndComp +$Comp +L d_and U15 +U 1 1 67815152 +P 12750 11650 +F 0 "U15" H 12750 11650 60 0000 C CNN +F 1 "d_and" H 12800 11750 60 0000 C CNN +F 2 "" H 12750 11650 60 0000 C CNN +F 3 "" H 12750 11650 60 0000 C CNN + 1 12750 11650 + 1 0 0 -1 +$EndComp +$Comp +L d_and U24 +U 1 1 67815158 +P 13700 11900 +F 0 "U24" H 13700 11900 60 0000 C CNN +F 1 "d_and" H 13750 12000 60 0000 C CNN +F 2 "" H 13700 11900 60 0000 C CNN +F 3 "" H 13700 11900 60 0000 C CNN + 1 13700 11900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 67815B00 +P 5250 5450 +F 0 "U1" H 5300 5550 30 0000 C CNN +F 1 "PORT" H 5250 5450 30 0000 C CNN +F 2 "" H 5250 5450 60 0000 C CNN +F 3 "" H 5250 5450 60 0000 C CNN + 1 5250 5450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67815B8E +P 5250 4800 +F 0 "U1" H 5300 4900 30 0000 C CNN +F 1 "PORT" H 5250 4800 30 0000 C CNN +F 2 "" H 5250 4800 60 0000 C CNN +F 3 "" H 5250 4800 60 0000 C CNN + 3 5250 4800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67815BF3 +P 5250 4100 +F 0 "U1" H 5300 4200 30 0000 C CNN +F 1 "PORT" H 5250 4100 30 0000 C CNN +F 2 "" H 5250 4100 60 0000 C CNN +F 3 "" H 5250 4100 60 0000 C CNN + 4 5250 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67815E4A +P 7900 13650 +F 0 "U1" H 7950 13750 30 0000 C CNN +F 1 "PORT" H 7900 13650 30 0000 C CNN +F 2 "" H 7900 13650 60 0000 C CNN +F 3 "" H 7900 13650 60 0000 C CNN + 2 7900 13650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 678161D1 +P 18000 3700 +F 0 "U1" H 18050 3800 30 0000 C CNN +F 1 "PORT" H 18000 3700 30 0000 C CNN +F 2 "" H 18000 3700 60 0000 C CNN +F 3 "" H 18000 3700 60 0000 C CNN + 5 18000 3700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 678163CB +P 18000 5800 +F 0 "U1" H 18050 5900 30 0000 C CNN +F 1 "PORT" H 18000 5800 30 0000 C CNN +F 2 "" H 18000 5800 60 0000 C CNN +F 3 "" H 18000 5800 60 0000 C CNN + 6 18000 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 678167B0 +P 7900 13900 +F 0 "U1" H 7950 14000 30 0000 C CNN +F 1 "PORT" H 7900 13900 30 0000 C CNN +F 2 "" H 7900 13900 60 0000 C CNN +F 3 "" H 7900 13900 60 0000 C CNN + 7 7900 13900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67816B24 +P 18400 10650 +F 0 "U1" H 18450 10750 30 0000 C CNN +F 1 "PORT" H 18400 10650 30 0000 C CNN +F 2 "" H 18400 10650 60 0000 C CNN +F 3 "" H 18400 10650 60 0000 C CNN + 8 18400 10650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 67816D6B +P 7900 14150 +F 0 "U1" H 7950 14250 30 0000 C CNN +F 1 "PORT" H 7900 14150 30 0000 C CNN +F 2 "" H 7900 14150 60 0000 C CNN +F 3 "" H 7900 14150 60 0000 C CNN + 9 7900 14150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 678170DA +P 18350 8550 +F 0 "U1" H 18400 8650 30 0000 C CNN +F 1 "PORT" H 18350 8550 30 0000 C CNN +F 2 "" H 18350 8550 60 0000 C CNN +F 3 "" H 18350 8550 60 0000 C CNN + 10 18350 8550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 67817605 +P 5350 8950 +F 0 "U1" H 5400 9050 30 0000 C CNN +F 1 "PORT" H 5350 8950 30 0000 C CNN +F 2 "" H 5350 8950 60 0000 C CNN +F 3 "" H 5350 8950 60 0000 C CNN + 11 5350 8950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6781767E +P 5500 9650 +F 0 "U1" H 5550 9750 30 0000 C CNN +F 1 "PORT" H 5500 9650 30 0000 C CNN +F 2 "" H 5500 9650 60 0000 C CNN +F 3 "" H 5500 9650 60 0000 C CNN + 12 5500 9650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 678176FB +P 5550 10300 +F 0 "U1" H 5600 10400 30 0000 C CNN +F 1 "PORT" H 5550 10300 30 0000 C CNN +F 2 "" H 5550 10300 60 0000 C CNN +F 3 "" H 5550 10300 60 0000 C CNN + 13 5550 10300 + 1 0 0 -1 +$EndComp +NoConn ~ 8150 13650 +NoConn ~ 8150 13900 +NoConn ~ 8150 14150 +$Comp +L PORT U1 +U 14 1 6781A929 +P 7900 14400 +F 0 "U1" H 7950 14500 30 0000 C CNN +F 1 "PORT" H 7900 14400 30 0000 C CNN +F 2 "" H 7900 14400 60 0000 C CNN +F 3 "" H 7900 14400 60 0000 C CNN + 14 7900 14400 + 1 0 0 -1 +$EndComp +NoConn ~ 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+Wire Wire Line + 6750 9950 11450 9950 +Wire Wire Line + 11450 9950 11450 11650 +Wire Wire Line + 11450 10200 12300 10200 +Wire Wire Line + 11450 11650 12300 11650 +Connection ~ 11450 10200 +Wire Wire Line + 5800 10300 7650 10300 +Wire Wire Line + 6750 10650 12500 10650 +Wire Wire Line + 12500 10650 12500 10450 +Wire Wire Line + 12500 10450 13250 10450 +Wire Wire Line + 13250 9700 12250 9700 +Wire Wire Line + 12250 9700 12250 9800 +Wire Wire Line + 12250 9800 10650 9800 +Wire Wire Line + 10650 9800 10650 10650 +Connection ~ 10650 10650 +Wire Wire Line + 13250 11150 12100 11150 +Connection ~ 12100 11150 +Wire Wire Line + 15850 8550 18100 8550 +Wire Wire Line + 16800 10650 18150 10650 +Wire Wire Line + 6750 10650 6750 10300 +Connection ~ 6750 10300 +Wire Wire Line + 6750 9950 6750 9650 +Connection ~ 6750 9650 +Wire Wire Line + 6750 9200 6750 8950 +Connection ~ 6750 8950 +$Comp +L d_inverter U35 +U 1 1 67815B9E +P 7500 4100 +F 0 "U35" H 7500 4000 60 0000 C CNN +F 1 "d_inverter" H 7500 4250 60 0000 C CNN +F 2 "" H 7550 4050 60 0000 C CNN +F 3 "" H 7550 4050 60 0000 C CNN + 1 7500 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U34 +U 1 1 67815C4E +P 7450 4800 +F 0 "U34" H 7450 4700 60 0000 C CNN +F 1 "d_inverter" H 7450 4950 60 0000 C CNN +F 2 "" H 7500 4750 60 0000 C CNN +F 3 "" H 7500 4750 60 0000 C CNN + 1 7450 4800 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U36 +U 1 1 67815CF8 +P 7500 5450 +F 0 "U36" H 7500 5350 60 0000 C CNN +F 1 "d_inverter" H 7500 5600 60 0000 C CNN +F 2 "" H 7550 5400 60 0000 C CNN +F 3 "" H 7550 5400 60 0000 C CNN + 1 7500 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U38 +U 1 1 6781606F +P 7950 8950 +F 0 "U38" H 7950 8850 60 0000 C CNN +F 1 "d_inverter" H 7950 9100 60 0000 C CNN +F 2 "" H 8000 8900 60 0000 C CNN +F 3 "" H 8000 8900 60 0000 C CNN + 1 7950 8950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U37 +U 1 1 6781613E +P 7900 9650 +F 0 "U37" H 7900 9550 60 0000 C CNN +F 1 "d_inverter" H 7900 9800 60 0000 C CNN +F 2 "" H 7950 9600 60 0000 C CNN +F 3 "" H 7950 9600 60 0000 C CNN + 1 7900 9650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U39 +U 1 1 678161F7 +P 7950 10300 +F 0 "U39" H 7950 10200 60 0000 C CNN +F 1 "d_inverter" H 7950 10450 60 0000 C CNN +F 2 "" H 8000 10250 60 0000 C CNN +F 3 "" H 8000 10250 60 0000 C CNN + 1 7950 10300 + 1 0 0 -1 +$EndComp +$Comp +L d_or U20 +U 1 1 67817C3D +P 13700 3450 +F 0 "U20" H 13700 3450 60 0000 C CNN +F 1 "d_or" H 13700 3550 60 0000 C CNN +F 2 "" H 13700 3450 60 0000 C CNN +F 3 "" H 13700 3450 60 0000 C CNN + 1 13700 3450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U28 +U 1 1 67817CC0 +P 14950 3750 +F 0 "U28" H 14950 3750 60 0000 C CNN +F 1 "d_or" H 14950 3850 60 0000 C CNN +F 2 "" H 14950 3750 60 0000 C CNN +F 3 "" H 14950 3750 60 0000 C CNN + 1 14950 3750 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U40 +U 1 1 67817DB5 +P 16000 3700 +F 0 "U40" H 16000 3600 60 0000 C CNN +F 1 "d_inverter" H 16000 3850 60 0000 C CNN +F 2 "" H 16050 3650 60 0000 C CNN +F 3 "" H 16050 3650 60 0000 C CNN + 1 16000 3700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U41 +U 1 1 67817F5D +P 16850 5800 +F 0 "U41" H 16850 5700 60 0000 C CNN +F 1 "d_inverter" H 16850 5950 60 0000 C CNN +F 2 "" H 16900 5750 60 0000 C CNN +F 3 "" H 16900 5750 60 0000 C CNN + 1 16850 5800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U26 +U 1 1 67818050 +P 14700 5500 +F 0 "U26" H 14700 5500 60 0000 C CNN +F 1 "d_or" H 14700 5600 60 0000 C CNN +F 2 "" H 14700 5500 60 0000 C CNN +F 3 "" H 14700 5500 60 0000 C CNN + 1 14700 5500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U27 +U 1 1 678180E7 +P 14700 6250 +F 0 "U27" H 14700 6250 60 0000 C CNN +F 1 "d_or" H 14700 6350 60 0000 C CNN +F 2 "" H 14700 6250 60 0000 C CNN +F 3 "" H 14700 6250 60 0000 C CNN + 1 14700 6250 + 1 0 0 -1 +$EndComp +$Comp +L d_or U32 +U 1 1 67818172 +P 15900 5850 +F 0 "U32" H 15900 5850 60 0000 C CNN +F 1 "d_or" H 15900 5950 60 0000 C CNN +F 2 "" H 15900 5850 60 0000 C CNN +F 3 "" H 15900 5850 60 0000 C CNN + 1 15900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16350 5800 16550 5800 +Wire Wire Line + 17150 5800 17750 5800 +Wire Wire Line + 15700 3700 15400 3700 +Wire Wire Line + 16300 3700 17750 3700 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub new file mode 100644 index 00000000..713804f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183.sub @@ -0,0 +1,166 @@ +* Subcircuit SN54LS183 +.subckt SN54LS183 net-_u1-pad1_ ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ ? net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn54ls183\sn54ls183.cir +* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad2_ net-_u18-pad2_ net-_u20-pad2_ d_and +* u4 net-_u2-pad1_ net-_u18-pad2_ net-_u28-pad2_ d_and +* u5 net-_u1-pad4_ net-_u2-pad2_ net-_u16-pad1_ d_and +* u16 net-_u16-pad1_ net-_u1-pad1_ net-_u16-pad3_ d_and +* u6 net-_u2-pad1_ net-_u1-pad3_ net-_u17-pad1_ d_and +* u17 net-_u17-pad1_ net-_u1-pad1_ net-_u17-pad3_ d_and +* u7 net-_u2-pad1_ net-_u2-pad2_ net-_u18-pad1_ d_and +* u18 net-_u18-pad1_ net-_u18-pad2_ net-_u18-pad3_ d_and +* u8 net-_u1-pad4_ net-_u1-pad3_ net-_u19-pad1_ d_and +* u19 net-_u19-pad1_ net-_u18-pad2_ net-_u19-pad3_ d_and +* u9 net-_u11-pad1_ net-_u10-pad1_ net-_u25-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_and +* u12 net-_u1-pad11_ net-_u10-pad1_ net-_u12-pad3_ d_and +* u21 net-_u12-pad3_ net-_u1-pad13_ net-_u21-pad3_ d_and +* u13 net-_u11-pad1_ net-_u1-pad12_ net-_u13-pad3_ d_and +* u22 net-_u13-pad3_ net-_u1-pad13_ net-_u22-pad3_ d_and +* u25 net-_u25-pad1_ net-_u10-pad3_ net-_u25-pad3_ d_nor +* u31 net-_u25-pad3_ net-_u11-pad3_ net-_u1-pad10_ d_nor +* u29 net-_u21-pad3_ net-_u22-pad3_ net-_u29-pad3_ d_nor +* u30 net-_u23-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nor +* u33 net-_u29-pad3_ net-_u30-pad3_ net-_u1-pad8_ d_nor +* u14 net-_u11-pad1_ net-_u10-pad1_ net-_u14-pad3_ d_and +* u23 net-_u14-pad3_ net-_u10-pad2_ net-_u23-pad3_ d_and +* u15 net-_u1-pad11_ net-_u1-pad12_ net-_u15-pad3_ d_and +* u24 net-_u15-pad3_ net-_u10-pad2_ net-_u24-pad3_ d_and +* u35 net-_u1-pad4_ net-_u2-pad1_ d_inverter +* u34 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u36 net-_u1-pad1_ net-_u18-pad2_ d_inverter +* u38 net-_u1-pad11_ net-_u11-pad1_ d_inverter +* u37 net-_u1-pad12_ net-_u10-pad1_ d_inverter +* u39 net-_u1-pad13_ net-_u10-pad2_ d_inverter +* u20 net-_u2-pad3_ net-_u20-pad2_ net-_u20-pad3_ d_or +* u28 net-_u20-pad3_ net-_u28-pad2_ net-_u28-pad3_ d_or +* u40 net-_u28-pad3_ net-_u1-pad5_ d_inverter +* u41 net-_u32-pad3_ net-_u1-pad6_ d_inverter +* u26 net-_u16-pad3_ net-_u17-pad3_ net-_u26-pad3_ d_or +* u27 net-_u18-pad3_ net-_u19-pad3_ net-_u27-pad3_ d_or +* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_or +a1 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad2_ net-_u18-pad2_ ] net-_u20-pad2_ u3 +a3 [net-_u2-pad1_ net-_u18-pad2_ ] net-_u28-pad2_ u4 +a4 [net-_u1-pad4_ net-_u2-pad2_ ] net-_u16-pad1_ u5 +a5 [net-_u16-pad1_ net-_u1-pad1_ ] net-_u16-pad3_ u16 +a6 [net-_u2-pad1_ net-_u1-pad3_ ] net-_u17-pad1_ u6 +a7 [net-_u17-pad1_ net-_u1-pad1_ ] net-_u17-pad3_ u17 +a8 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u18-pad1_ u7 +a9 [net-_u18-pad1_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a10 [net-_u1-pad4_ net-_u1-pad3_ ] net-_u19-pad1_ u8 +a11 [net-_u19-pad1_ net-_u18-pad2_ ] net-_u19-pad3_ u19 +a12 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u25-pad1_ u9 +a13 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a14 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a15 [net-_u1-pad11_ net-_u10-pad1_ ] net-_u12-pad3_ u12 +a16 [net-_u12-pad3_ net-_u1-pad13_ ] net-_u21-pad3_ u21 +a17 [net-_u11-pad1_ net-_u1-pad12_ ] net-_u13-pad3_ u13 +a18 [net-_u13-pad3_ net-_u1-pad13_ ] net-_u22-pad3_ u22 +a19 [net-_u25-pad1_ net-_u10-pad3_ ] net-_u25-pad3_ u25 +a20 [net-_u25-pad3_ net-_u11-pad3_ ] net-_u1-pad10_ u31 +a21 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u29-pad3_ u29 +a22 [net-_u23-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a23 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u1-pad8_ u33 +a24 [net-_u11-pad1_ net-_u10-pad1_ ] net-_u14-pad3_ u14 +a25 [net-_u14-pad3_ net-_u10-pad2_ ] net-_u23-pad3_ u23 +a26 [net-_u1-pad11_ net-_u1-pad12_ ] net-_u15-pad3_ u15 +a27 [net-_u15-pad3_ net-_u10-pad2_ ] net-_u24-pad3_ u24 +a28 net-_u1-pad4_ net-_u2-pad1_ u35 +a29 net-_u1-pad3_ net-_u2-pad2_ u34 +a30 net-_u1-pad1_ net-_u18-pad2_ u36 +a31 net-_u1-pad11_ net-_u11-pad1_ u38 +a32 net-_u1-pad12_ net-_u10-pad1_ u37 +a33 net-_u1-pad13_ net-_u10-pad2_ u39 +a34 [net-_u2-pad3_ net-_u20-pad2_ ] net-_u20-pad3_ u20 +a35 [net-_u20-pad3_ net-_u28-pad2_ ] net-_u28-pad3_ u28 +a36 net-_u28-pad3_ net-_u1-pad5_ u40 +a37 net-_u32-pad3_ net-_u1-pad6_ u41 +a38 [net-_u16-pad3_ net-_u17-pad3_ ] net-_u26-pad3_ u26 +a39 [net-_u18-pad3_ net-_u19-pad3_ ] net-_u27-pad3_ u27 +a40 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u31 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u29 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u30 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u14 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u23 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u24 d_and(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u39 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u20 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u28 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u40 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u41 d_inverter(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u26 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u27 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u32 d_or(input_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Control Statements + +.ends SN54LS183
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml new file mode 100644 index 00000000..ce7d687a --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/SN54LS183_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_and<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_and<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u5><u16 name="type">d_and<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u16><u6 name="type">d_and<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u6><u17 name="type">d_and<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u17><u20 name="type">d_nor<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_nor<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u28><u26 name="type">d_nor<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_nor<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_nor<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u32><u7 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u7><u18 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u18><u8 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u8><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u9 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u12><u21 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_and<field67 name="Enter Fall Delay (default=1.0e-9)" /><field68 name="Enter Input Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /></u22><u25 name="type">d_nor<field70 name="Enter Fall Delay (default=1.0e-9)" /><field71 name="Enter Input Load (default=1.0e-12)" /><field72 name="Enter Rise Delay (default=1.0e-9)" /></u25><u31 name="type">d_nor<field73 name="Enter Fall Delay (default=1.0e-9)" /><field74 name="Enter Input Load (default=1.0e-12)" /><field75 name="Enter Rise Delay (default=1.0e-9)" /></u31><u29 name="type">d_nor<field76 name="Enter Fall Delay (default=1.0e-9)" /><field77 name="Enter Input Load (default=1.0e-12)" /><field78 name="Enter Rise Delay (default=1.0e-9)" /></u29><u30 name="type">d_nor<field79 name="Enter Fall Delay (default=1.0e-9)" /><field80 name="Enter Input Load (default=1.0e-12)" /><field81 name="Enter Rise Delay (default=1.0e-9)" /></u30><u33 name="type">d_nor<field82 name="Enter Fall Delay (default=1.0e-9)" /><field83 name="Enter Input Load (default=1.0e-12)" /><field84 name="Enter Rise Delay (default=1.0e-9)" /></u33><u14 name="type">d_and<field85 name="Enter Fall Delay (default=1.0e-9)" /><field86 name="Enter Input Load (default=1.0e-12)" /><field87 name="Enter Rise Delay (default=1.0e-9)" /></u14><u23 name="type">d_and<field88 name="Enter Fall Delay (default=1.0e-9)" /><field89 name="Enter Input Load (default=1.0e-12)" /><field90 name="Enter Rise Delay (default=1.0e-9)" /></u23><u15 name="type">d_and<field91 name="Enter Fall Delay (default=1.0e-9)" /><field92 name="Enter Input Load (default=1.0e-12)" /><field93 name="Enter Rise Delay (default=1.0e-9)" /></u15><u24 name="type">d_and<field94 name="Enter Fall Delay (default=1.0e-9)" /><field95 name="Enter Input Load (default=1.0e-12)" /><field96 name="Enter Rise Delay (default=1.0e-9)" /></u24><u35 name="type">d_inverter<field97 name="Enter Fall Delay (default=1.0e-9)" /><field98 name="Enter Input Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /></u35><u34 name="type">d_inverter<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u34><u36 name="type">d_inverter<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u36><u38 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u38><u37 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u37><u39 name="type">d_inverter<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u39><u20 name="type">d_or<field100 name="Enter Fall Delay (default=1.0e-9)" /><field101 name="Enter Input Load (default=1.0e-12)" /><field102 name="Enter Rise Delay (default=1.0e-9)" /></u20><u28 name="type">d_or<field103 name="Enter Fall Delay (default=1.0e-9)" /><field104 name="Enter Input Load (default=1.0e-12)" /><field105 name="Enter Rise Delay (default=1.0e-9)" /></u28><u40 name="type">d_inverter<field106 name="Enter Fall Delay (default=1.0e-9)" /><field107 name="Enter Input Load (default=1.0e-12)" /><field108 name="Enter Rise Delay (default=1.0e-9)" /></u40><u41 name="type">d_inverter<field109 name="Enter Fall Delay (default=1.0e-9)" /><field110 name="Enter Input Load (default=1.0e-12)" /><field111 name="Enter Rise Delay (default=1.0e-9)" /></u41><u26 name="type">d_or<field112 name="Enter Fall Delay (default=1.0e-9)" /><field113 name="Enter Input Load (default=1.0e-12)" /><field114 name="Enter Rise Delay (default=1.0e-9)" /></u26><u27 name="type">d_or<field115 name="Enter Fall Delay (default=1.0e-9)" /><field116 name="Enter Input Load (default=1.0e-12)" /><field117 name="Enter Rise Delay (default=1.0e-9)" /></u27><u32 name="type">d_or<field118 name="Enter Fall Delay (default=1.0e-9)" /><field119 name="Enter Input Load (default=1.0e-12)" /><field120 name="Enter Rise Delay (default=1.0e-9)" /></u32></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54LS183/analysis b/library/SubcircuitLibrary/SN54LS183/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54LS183/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/D.lib b/library/SubcircuitLibrary/SN55188/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188/NPN.lib b/library/SubcircuitLibrary/SN55188/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/PNP.lib b/library/SubcircuitLibrary/SN55188/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/SN55188-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib new file mode 100644 index 00000000..e532722e --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SN55188_0 +# +DEF SN55188_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "SN55188_0" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 450 -300 0 1 0 N +X Vcc+ 1 -600 100 200 R 50 50 1 1 I +X A 2 -100 400 200 D 50 50 1 1 I +X B 3 200 400 200 D 50 50 1 1 I +X gnd 4 0 -500 200 U 50 50 1 1 I +X Vcc- 5 -600 -200 200 R 50 50 1 1 I +X OUTPUT 6 650 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir b/library/SubcircuitLibrary/SN55188/SN55188.cir new file mode 100644 index 00000000..d12a8992 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188\SN55188.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 00:32:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Vcc+ Net-_U1-Pad2_ Net-_U1-Pad2_ gnd Vcc- Net-_U1-Pad3_ SN55188_0 +X3 Vcc+ Net-_U1-Pad9_ Net-_U1-Pad10_ gnd Vcc- Net-_U1-Pad8_ SN55188_0 +X1 Vcc+ Net-_U1-Pad4_ Net-_U1-Pad5_ gnd Vcc- Net-_U1-Pad6_ SN55188_0 +X4 Vcc+ Net-_U1-Pad12_ Net-_U1-Pad13_ gnd Vcc- Net-_U1-Pad11_ SN55188_0 +U1 Vcc- Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Vcc+ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir.out b/library/SubcircuitLibrary/SN55188/SN55188.cir.out new file mode 100644 index 00000000..70d80115 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir + +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* u1 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.pro b/library/SubcircuitLibrary/SN55188/SN55188.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sch b/library/SubcircuitLibrary/SN55188/SN55188.sch new file mode 100644 index 00000000..55a59692 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sch @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SN55188_0 X2 +U 1 1 679A4CEC +P 5350 3700 +F 0 "X2" H 5350 3700 60 0000 C CNN +F 1 "SN55188_0" H 5350 3600 60 0000 C CNN +F 2 "" H 5350 3700 60 0001 C CNN +F 3 "" H 5350 3700 60 0001 C CNN + 1 5350 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X3 +U 1 1 679A4D5D +P 7150 3700 +F 0 "X3" H 7150 3700 60 0000 C CNN +F 1 "SN55188_0" H 7150 3600 60 0000 C CNN +F 2 "" H 7150 3700 60 0001 C CNN +F 3 "" H 7150 3700 60 0001 C CNN + 1 7150 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X1 +U 1 1 679A4D76 +P 5300 5100 +F 0 "X1" H 5300 5100 60 0000 C CNN +F 1 "SN55188_0" H 5300 5000 60 0000 C CNN +F 2 "" H 5300 5100 60 0001 C CNN +F 3 "" H 5300 5100 60 0001 C CNN + 1 5300 5100 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X4 +U 1 1 679A4D97 +P 7200 5150 +F 0 "X4" H 7200 5150 60 0000 C CNN +F 1 "SN55188_0" H 7200 5050 60 0000 C CNN +F 2 "" H 7200 5150 60 0001 C CNN +F 3 "" H 7200 5150 60 0001 C CNN + 1 7200 5150 + 1 0 0 -1 +$EndComp +Text GLabel 5500 4200 2 60 Input ~ 0 +gnd +Text GLabel 5450 5600 2 60 Input ~ 0 +gnd +Text GLabel 7350 5650 2 60 Input ~ 0 +gnd +Text GLabel 7300 4200 2 60 Input ~ 0 +gnd +Text GLabel 4600 3600 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 4800 0 60 Input ~ 0 +Vcc+ +Text GLabel 6550 3400 0 60 Input ~ 0 +Vcc+ +Text GLabel 6600 4850 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 6600 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 4600 3900 0 60 Input ~ 0 +Vcc- +Text GLabel 6550 4100 0 60 Input ~ 0 +Vcc- +$Comp +L PORT U1 +U 14 1 679A4FA0 +P 6150 3550 +F 0 "U1" H 6200 3650 30 0000 C CNN +F 1 "PORT" H 6150 3550 30 0000 C CNN +F 2 "" H 6150 3550 60 0000 C CNN +F 3 "" H 6150 3550 60 0000 C CNN + 14 6150 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A4FBF +P 7700 4600 +F 0 "U1" H 7750 4700 30 0000 C CNN +F 1 "PORT" H 7700 4600 30 0000 C CNN +F 2 "" H 7700 4600 60 0000 C CNN +F 3 "" H 7700 4600 60 0000 C CNN + 13 7700 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A4FF6 +P 6350 5150 +F 0 "U1" H 6400 5250 30 0000 C CNN +F 1 "PORT" H 6350 5150 30 0000 C CNN +F 2 "" H 6350 5150 60 0000 C CNN +F 3 "" H 6350 5150 60 0000 C CNN + 6 6350 5150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A5019 +P 6750 4200 +F 0 "U1" H 6800 4300 30 0000 C CNN +F 1 "PORT" H 6750 4200 30 0000 C CNN +F 2 "" H 6750 4200 60 0000 C CNN +F 3 "" H 6750 4200 60 0000 C CNN + 7 6750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A503E +P 7850 4000 +F 0 "U1" H 7900 4100 30 0000 C CNN +F 1 "PORT" H 7850 4000 30 0000 C CNN +F 2 "" H 7850 4000 60 0000 C CNN +F 3 "" H 7850 4000 60 0000 C CNN + 8 7850 4000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679A5065 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 9 6750 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A508E +P 7650 3150 +F 0 "U1" H 7700 3250 30 0000 C CNN +F 1 "PORT" H 7650 3150 30 0000 C CNN +F 2 "" H 7650 3150 60 0000 C CNN +F 3 "" H 7650 3150 60 0000 C CNN + 10 7650 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A50B9 +P 8250 5200 +F 0 "U1" H 8300 5300 30 0000 C CNN +F 1 "PORT" H 8250 5200 30 0000 C CNN +F 2 "" H 8250 5200 60 0000 C CNN +F 3 "" H 8250 5200 60 0000 C CNN + 11 8250 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A50E6 +P 4850 4450 +F 0 "U1" H 4900 4550 30 0000 C CNN +F 1 "PORT" H 4850 4450 30 0000 C CNN +F 2 "" H 4850 4450 60 0000 C CNN +F 3 "" H 4850 4450 60 0000 C CNN + 4 4850 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A5115 +P 5850 4450 +F 0 "U1" H 5900 4550 30 0000 C CNN +F 1 "PORT" H 5850 4450 30 0000 C CNN +F 2 "" H 5850 4450 60 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 5 5850 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A5146 +P 6800 4600 +F 0 "U1" H 6850 4700 30 0000 C CNN +F 1 "PORT" H 6800 4600 30 0000 C CNN +F 2 "" H 6800 4600 60 0000 C CNN +F 3 "" H 6800 4600 60 0000 C CNN + 12 6800 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A5179 +P 6300 3750 +F 0 "U1" H 6350 3850 30 0000 C CNN +F 1 "PORT" H 6300 3750 30 0000 C CNN +F 2 "" H 6300 3750 60 0000 C CNN +F 3 "" H 6300 3750 60 0000 C CNN + 3 6300 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A51C2 +P 5100 3000 +F 0 "U1" H 5150 3100 30 0000 C CNN +F 1 "PORT" H 5100 3000 30 0000 C CNN +F 2 "" H 5100 3000 60 0000 C CNN +F 3 "" H 5100 3000 60 0000 C CNN + 2 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A51F9 +P 6200 3950 +F 0 "U1" H 6250 4050 30 0000 C CNN +F 1 "PORT" H 6200 3950 30 0000 C CNN +F 2 "" H 6200 3950 60 0000 C CNN +F 3 "" H 6200 3950 60 0000 C CNN + 1 6200 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5600 5450 5600 +Wire Wire Line + 7200 5650 7350 5650 +Wire Wire Line + 7000 4200 7300 4200 +Wire Wire Line + 5350 4200 5500 4200 +Wire Wire Line + 4750 3600 4600 3600 +Wire Wire Line + 4750 3900 4600 3900 +Wire Wire Line + 6550 3600 6550 3400 +Wire Wire Line + 6550 3900 6550 4100 +Wire Wire Line + 6600 5050 6600 4850 +Wire Wire Line + 6600 5350 6600 5550 +Wire Wire Line + 4700 5300 4700 5550 +Wire Wire Line + 4700 5000 4700 4800 +Wire Wire Line + 5250 3300 5550 3300 +Wire Wire Line + 5350 3300 5350 3000 +Connection ~ 5350 3300 +Wire Wire Line + 6450 3950 6550 3950 +Connection ~ 6550 3950 +Wire Wire Line + 6400 3550 6550 3550 +Connection ~ 6550 3550 +Connection ~ 7150 4200 +Wire Wire Line + 7050 3300 7050 3150 +Wire Wire Line + 7050 3150 7000 3150 +Wire Wire Line + 7350 3300 7350 3150 +Wire Wire Line + 7350 3150 7400 3150 +Wire Wire Line + 7100 4750 7100 4600 +Wire Wire Line + 7100 4600 7050 4600 +Wire Wire Line + 7400 4750 7400 4600 +Wire Wire Line + 7400 4600 7450 4600 +Wire Wire Line + 5200 4700 5200 4450 +Wire Wire Line + 5200 4450 5100 4450 +Wire Wire Line + 5500 4700 5500 4450 +Wire Wire Line + 5500 4450 5600 4450 +Wire Wire Line + 7800 3750 7850 3750 +Wire Wire Line + 7850 5200 8000 5200 +Wire Wire Line + 5950 5150 6100 5150 +Wire Wire Line + 6000 3750 6050 3750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sub b/library/SubcircuitLibrary/SN55188/SN55188.sub new file mode 100644 index 00000000..eedf8204 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sub @@ -0,0 +1,11 @@ +* Subcircuit SN55188 +.subckt SN55188 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* Control Statements + +.ends SN55188
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir b/library/SubcircuitLibrary/SN55188/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.pro b/library/SubcircuitLibrary/SN55188/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sch b/library/SubcircuitLibrary/SN55188/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sub b/library/SubcircuitLibrary/SN55188/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml new file mode 100644 index 00000000..61a626af --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x1><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/analysis b/library/SubcircuitLibrary/SN55188/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/D.lib b/library/SubcircuitLibrary/SN55188_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188_0/NPN.lib b/library/SubcircuitLibrary/SN55188_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/PNP.lib b/library/SubcircuitLibrary/SN55188_0/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/analysis b/library/SubcircuitLibrary/SN55188_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7404/D.lib b/library/SubcircuitLibrary/SN7404/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN7404/NPN.lib b/library/SubcircuitLibrary/SN7404/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib new file mode 100644 index 00000000..0f688db8 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir new file mode 100644 index 00000000..51b43f71 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir @@ -0,0 +1,71 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7404_Subcircuit\SN7404_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 22:45:10
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 4k
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D9-Pad2_ eSim_NPN
+Q19 Net-_Q19-Pad1_ Net-_Q17-Pad1_ Net-_Q19-Pad3_ eSim_NPN
+Q21 Net-_Q21-Pad1_ Net-_Q19-Pad1_ Net-_D11-Pad1_ eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+Q22 Net-_D11-Pad2_ Net-_Q19-Pad3_ GNDPWR eSim_NPN
+R21 ? Net-_Q19-Pad1_ 1.6k
+R23 Net-_R1-Pad1_ Net-_Q21-Pad1_ 130
+R19 Net-_Q19-Pad3_ GNDPWR 1k
+D9 GNDPWR Net-_D9-Pad2_ eSim_Diode
+U1 Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_D3-Pad2_ Net-_D4-Pad2_ Net-_D5-Pad2_ Net-_D6-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D11-Pad2_ Net-_D12-Pad2_ PORT
+R18 Net-_R1-Pad1_ Net-_Q18-Pad2_ 4k
+Q18 Net-_Q18-Pad1_ Net-_Q18-Pad2_ Net-_D10-Pad2_ eSim_NPN
+Q20 Net-_Q20-Pad1_ Net-_Q18-Pad1_ Net-_Q20-Pad3_ eSim_NPN
+Q23 Net-_Q23-Pad1_ Net-_Q20-Pad1_ Net-_D12-Pad1_ eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+Q24 Net-_D12-Pad2_ Net-_Q20-Pad3_ GNDPWR eSim_NPN
+R22 Net-_R1-Pad1_ Net-_Q20-Pad1_ 1.6k
+R24 Net-_R1-Pad1_ Net-_Q23-Pad1_ 130
+R20 Net-_Q20-Pad3_ GNDPWR 1k
+D10 GNDPWR Net-_D10-Pad2_ eSim_Diode
+R9 Net-_R1-Pad1_ Net-_Q9-Pad2_ 4k
+Q9 Net-_Q11-Pad2_ Net-_Q9-Pad2_ Net-_D5-Pad2_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_D7-Pad1_ eSim_NPN
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+Q14 Net-_D7-Pad2_ Net-_Q11-Pad3_ GNDPWR eSim_NPN
+R13 ? Net-_Q11-Pad1_ 1.6k
+R15 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+R11 Net-_Q11-Pad3_ GNDPWR 1k
+D5 GNDPWR Net-_D5-Pad2_ eSim_Diode
+R10 Net-_R1-Pad1_ Net-_Q10-Pad2_ 4k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_D6-Pad2_ eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_Q10-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q12-Pad1_ Net-_D8-Pad1_ eSim_NPN
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+Q16 Net-_D8-Pad2_ Net-_Q12-Pad3_ GNDPWR eSim_NPN
+R14 ? Net-_Q12-Pad1_ 1.6k
+R16 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+R12 Net-_Q12-Pad3_ GNDPWR 1k
+D6 GNDPWR Net-_D6-Pad2_ eSim_Diode
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN
+Q5 Net-_Q5-Pad1_ Net-_Q3-Pad1_ Net-_D3-Pad1_ eSim_NPN
+D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode
+Q6 Net-_D3-Pad2_ Net-_Q3-Pad3_ GNDPWR eSim_NPN
+R5 ? Net-_Q3-Pad1_ 1.6k
+R7 Net-_R1-Pad1_ Net-_Q5-Pad1_ 130
+R3 Net-_Q3-Pad3_ GNDPWR 1k
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+R2 Net-_R1-Pad1_ Net-_Q2-Pad2_ 4k
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+Q7 Net-_Q7-Pad1_ Net-_Q4-Pad1_ Net-_D4-Pad1_ eSim_NPN
+D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode
+Q8 Net-_D4-Pad2_ Net-_Q4-Pad3_ GNDPWR eSim_NPN
+R6 ? Net-_Q4-Pad1_ 1.6k
+R8 Net-_R1-Pad1_ Net-_Q7-Pad1_ 130
+R4 Net-_Q4-Pad3_ GNDPWR 1k
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+
+.end
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out new file mode 100644 index 00000000..c180e7d8 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.cir.out @@ -0,0 +1,74 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn7404_subcircuit\sn7404_subcircuit.cir
+
+.include NPN.lib
+.include D.lib
+r17 net-_r1-pad1_ net-_q17-pad2_ 4k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q19-pad1_ net-_d11-pad1_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q22 net-_d11-pad2_ net-_q19-pad3_ gndpwr Q2N2222
+r21 ? net-_q19-pad1_ 1.6k
+r23 net-_r1-pad1_ net-_q21-pad1_ 130
+r19 net-_q19-pad3_ gndpwr 1k
+d9 gndpwr net-_d9-pad2_ 1N4148
+* u1 net-_d1-pad2_ net-_d2-pad2_ net-_d3-pad2_ net-_d4-pad2_ net-_d5-pad2_ net-_d6-pad2_ net-_r1-pad1_ gndpwr net-_d7-pad2_ net-_d8-pad2_ net-_d9-pad2_ net-_d10-pad2_ net-_d11-pad2_ net-_d12-pad2_ port
+r18 net-_r1-pad1_ net-_q18-pad2_ 4k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d10-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q23 net-_q23-pad1_ net-_q20-pad1_ net-_d12-pad1_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q24 net-_d12-pad2_ net-_q20-pad3_ gndpwr Q2N2222
+r22 net-_r1-pad1_ net-_q20-pad1_ 1.6k
+r24 net-_r1-pad1_ net-_q23-pad1_ 130
+r20 net-_q20-pad3_ gndpwr 1k
+d10 gndpwr net-_d10-pad2_ 1N4148
+r9 net-_r1-pad1_ net-_q9-pad2_ 4k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d5-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+r13 ? net-_q11-pad1_ 1.6k
+r15 net-_r1-pad1_ net-_q13-pad1_ 130
+r11 net-_q11-pad3_ gndpwr 1k
+d5 gndpwr net-_d5-pad2_ 1N4148
+r10 net-_r1-pad1_ net-_q10-pad2_ 4k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d6-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+r14 ? net-_q12-pad1_ 1.6k
+r16 net-_r1-pad1_ net-_q15-pad1_ 130
+r12 net-_q12-pad3_ gndpwr 1k
+d6 gndpwr net-_d6-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q3-pad1_ net-_d3-pad1_ Q2N2222
+d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148
+q6 net-_d3-pad2_ net-_q3-pad3_ gndpwr Q2N2222
+r5 ? net-_q3-pad1_ 1.6k
+r7 net-_r1-pad1_ net-_q5-pad1_ 130
+r3 net-_q3-pad3_ gndpwr 1k
+d1 gndpwr net-_d1-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q2-pad2_ 4k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q4-pad1_ net-_d4-pad1_ Q2N2222
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+q8 net-_d4-pad2_ net-_q4-pad3_ gndpwr Q2N2222
+r6 ? net-_q4-pad1_ 1.6k
+r8 net-_r1-pad1_ net-_q7-pad1_ 130
+r4 net-_q4-pad3_ gndpwr 1k
+d2 gndpwr net-_d2-pad2_ 1N4148
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch new file mode 100644 index 00000000..68a86895 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sch @@ -0,0 +1,1295 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R17
+U 1 1 67A8D41A
+P 8310 1340
+F 0 "R17" H 8360 1470 50 0000 C CNN
+F 1 "4k" H 8360 1290 50 0000 C CNN
+F 2 "" H 8360 1320 30 0000 C CNN
+F 3 "" V 8360 1390 30 0000 C CNN
+ 1 8310 1340
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 67A8D45F
+P 8360 2130
+F 0 "Q17" H 8260 2180 50 0000 R CNN
+F 1 "eSim_NPN" H 8310 2280 50 0000 R CNN
+F 2 "" H 8560 2230 29 0000 C CNN
+F 3 "" H 8360 2130 60 0000 C CNN
+ 1 8360 2130
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q19
+U 1 1 67A8D53A
+P 9060 2440
+F 0 "Q19" H 8960 2490 50 0000 R CNN
+F 1 "eSim_NPN" H 9010 2590 50 0000 R CNN
+F 2 "" H 9260 2540 29 0000 C CNN
+F 3 "" H 9060 2440 60 0000 C CNN
+ 1 9060 2440
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q21
+U 1 1 67A8D58D
+P 9670 2100
+F 0 "Q21" H 9570 2150 50 0000 R CNN
+F 1 "eSim_NPN" H 9620 2250 50 0000 R CNN
+F 2 "" H 9870 2200 29 0000 C CNN
+F 3 "" H 9670 2100 60 0000 C CNN
+ 1 9670 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D11
+U 1 1 67A8D5E0
+P 9770 2570
+F 0 "D11" H 9770 2670 50 0000 C CNN
+F 1 "eSim_Diode" H 9770 2470 50 0000 C CNN
+F 2 "" H 9770 2570 60 0000 C CNN
+F 3 "" H 9770 2570 60 0000 C CNN
+ 1 9770 2570
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q22
+U 1 1 67A8D651
+P 9670 3320
+F 0 "Q22" H 9570 3370 50 0000 R CNN
+F 1 "eSim_NPN" H 9620 3470 50 0000 R CNN
+F 2 "" H 9870 3420 29 0000 C CNN
+F 3 "" H 9670 3320 60 0000 C CNN
+ 1 9670 3320
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R21
+U 1 1 67A8D6B7
+P 9180 1340
+F 0 "R21" H 9230 1470 50 0000 C CNN
+F 1 "1.6k" H 9230 1290 50 0000 C CNN
+F 2 "" H 9230 1320 30 0000 C CNN
+F 3 "" V 9230 1390 30 0000 C CNN
+ 1 9180 1340
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R23
+U 1 1 67A8D748
+P 9720 1350
+F 0 "R23" H 9770 1480 50 0000 C CNN
+F 1 "130" H 9770 1300 50 0000 C CNN
+F 2 "" H 9770 1330 30 0000 C CNN
+F 3 "" V 9770 1400 30 0000 C CNN
+ 1 9720 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 67A8D7B4
+P 9150 3640
+F 0 "R19" H 9200 3770 50 0000 C CNN
+F 1 "1k" H 9200 3590 50 0000 C CNN
+F 2 "" H 9200 3620 30 0000 C CNN
+F 3 "" V 9200 3690 30 0000 C CNN
+ 1 9150 3640
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D9
+U 1 1 67A8DB8E
+P 8080 3160
+F 0 "D9" H 8080 3260 50 0000 C CNN
+F 1 "eSim_Diode" H 8080 3060 50 0000 C CNN
+F 2 "" H 8080 3160 60 0000 C CNN
+F 3 "" H 8080 3160 60 0000 C CNN
+ 1 8080 3160
+ 0 -1 -1 0
+$EndComp
+$Comp
+L GNDPWR #PWR01
+U 1 1 67A8DC1C
+P 8230 3870
+F 0 "#PWR01" H 8230 3670 50 0001 C CNN
+F 1 "GNDPWR" H 8230 3740 50 0000 C CNN
+F 2 "" H 8230 3820 50 0001 C CNN
+F 3 "" H 8230 3820 50 0001 C CNN
+ 1 8230 3870
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67A8E528
+P 7440 2230
+F 0 "U1" H 7490 2330 30 0000 C CNN
+F 1 "PORT" H 7440 2230 30 0000 C CNN
+F 2 "" H 7440 2230 60 0000 C CNN
+F 3 "" H 7440 2230 60 0000 C CNN
+ 11 7440 2230
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67A8E964
+P 10300 2930
+F 0 "U1" H 10350 3030 30 0000 C CNN
+F 1 "PORT" H 10300 2930 30 0000 C CNN
+F 2 "" H 10300 2930 60 0000 C CNN
+F 3 "" H 10300 2930 60 0000 C CNN
+ 13 10300 2930
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R18
+U 1 1 67A907F1
+P 8310 4420
+F 0 "R18" H 8360 4550 50 0000 C CNN
+F 1 "4k" H 8360 4370 50 0000 C CNN
+F 2 "" H 8360 4400 30 0000 C CNN
+F 3 "" V 8360 4470 30 0000 C CNN
+ 1 8310 4420
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q18
+U 1 1 67A907F7
+P 8360 5210
+F 0 "Q18" H 8260 5260 50 0000 R CNN
+F 1 "eSim_NPN" H 8310 5360 50 0000 R CNN
+F 2 "" H 8560 5310 29 0000 C CNN
+F 3 "" H 8360 5210 60 0000 C CNN
+ 1 8360 5210
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 67A907FD
+P 9060 5520
+F 0 "Q20" H 8960 5570 50 0000 R CNN
+F 1 "eSim_NPN" H 9010 5670 50 0000 R CNN
+F 2 "" H 9260 5620 29 0000 C CNN
+F 3 "" H 9060 5520 60 0000 C CNN
+ 1 9060 5520
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q23
+U 1 1 67A90803
+P 9670 5180
+F 0 "Q23" H 9570 5230 50 0000 R CNN
+F 1 "eSim_NPN" H 9620 5330 50 0000 R CNN
+F 2 "" H 9870 5280 29 0000 C CNN
+F 3 "" H 9670 5180 60 0000 C CNN
+ 1 9670 5180
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D12
+U 1 1 67A90809
+P 9770 5650
+F 0 "D12" H 9770 5750 50 0000 C CNN
+F 1 "eSim_Diode" H 9770 5550 50 0000 C CNN
+F 2 "" H 9770 5650 60 0000 C CNN
+F 3 "" H 9770 5650 60 0000 C CNN
+ 1 9770 5650
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q24
+U 1 1 67A9080F
+P 9670 6400
+F 0 "Q24" H 9570 6450 50 0000 R CNN
+F 1 "eSim_NPN" H 9620 6550 50 0000 R CNN
+F 2 "" H 9870 6500 29 0000 C CNN
+F 3 "" H 9670 6400 60 0000 C CNN
+ 1 9670 6400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R22
+U 1 1 67A90815
+P 9180 4420
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+F 1 "1.6k" H 9230 4370 50 0000 C CNN
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+Wire Wire Line
+ 5370 2230 5520 2230
+Wire Wire Line
+ 5520 2230 5520 2440
+Wire Wire Line
+ 5520 2440 5670 2440
+Wire Wire Line
+ 5970 2240 5970 2100
+Wire Wire Line
+ 5970 2100 6280 2100
+Wire Wire Line
+ 6580 2300 6580 2420
+Wire Wire Line
+ 6580 2720 6580 3120
+Wire Wire Line
+ 6580 3870 6580 3520
+Wire Wire Line
+ 4890 3870 6820 3870
+Wire Wire Line
+ 4890 3310 4890 3870
+Connection ~ 5040 3870
+Wire Wire Line
+ 6010 3840 6010 3870
+Connection ~ 6010 3870
+Wire Wire Line
+ 5970 3320 6280 3320
+Wire Wire Line
+ 6010 3320 6010 3540
+Wire Wire Line
+ 5970 2640 5970 3320
+Connection ~ 6010 3320
+Wire Wire Line
+ 6040 1540 6040 2100
+Connection ~ 6040 2100
+Wire Wire Line
+ 6580 1550 6580 1900
+Wire Wire Line
+ 6580 1200 5170 1200
+Wire Wire Line
+ 5170 1200 5170 1240
+Wire Wire Line
+ 4970 2230 4500 2230
+Wire Wire Line
+ 4890 3010 4890 2230
+Connection ~ 4890 2230
+Wire Wire Line
+ 6860 2930 6580 2930
+Connection ~ 6580 2930
+Wire Wire Line
+ 5170 4620 5170 5010
+Wire Wire Line
+ 5370 5310 5520 5310
+Wire Wire Line
+ 5520 5310 5520 5520
+Wire Wire Line
+ 5520 5520 5670 5520
+Wire Wire Line
+ 5970 5320 5970 5180
+Wire Wire Line
+ 5970 5180 6280 5180
+Wire Wire Line
+ 6580 5380 6580 5500
+Wire Wire Line
+ 6580 5800 6580 6200
+Wire Wire Line
+ 6580 6600 6580 7210
+Wire Wire Line
+ 4890 6950 6580 6950
+Wire Wire Line
+ 4890 6390 4890 6950
+Connection ~ 5040 6950
+Wire Wire Line
+ 6010 6920 6010 6950
+Connection ~ 6010 6950
+Wire Wire Line
+ 5970 6400 6280 6400
+Wire Wire Line
+ 6010 6400 6010 6620
+Wire Wire Line
+ 5970 5720 5970 6400
+Connection ~ 6010 6400
+Wire Wire Line
+ 6040 4620 6040 5180
+Connection ~ 6040 5180
+Wire Wire Line
+ 6580 4630 6580 4980
+Wire Wire Line
+ 6580 4330 6580 4280
+Wire Wire Line
+ 5170 4280 6760 4280
+Wire Wire Line
+ 5170 4280 5170 4320
+Wire Wire Line
+ 4970 5310 4500 5310
+Wire Wire Line
+ 4890 6090 4890 5310
+Connection ~ 4890 5310
+Wire Wire Line
+ 6860 6010 6580 6010
+Connection ~ 6580 6010
+Wire Wire Line
+ 2150 1540 2150 1930
+Wire Wire Line
+ 2350 2230 2500 2230
+Wire Wire Line
+ 2500 2230 2500 2440
+Wire Wire Line
+ 2500 2440 2650 2440
+Wire Wire Line
+ 2950 2240 2950 2100
+Wire Wire Line
+ 2950 2100 3260 2100
+Wire Wire Line
+ 3560 2300 3560 2420
+Wire Wire Line
+ 3560 2720 3560 3120
+Wire Wire Line
+ 3560 3870 3560 3520
+Wire Wire Line
+ 1870 3870 3680 3870
+Wire Wire Line
+ 1870 3310 1870 3870
+Connection ~ 2020 3870
+Wire Wire Line
+ 2990 3840 2990 3870
+Connection ~ 2990 3870
+Wire Wire Line
+ 2950 3320 3260 3320
+Wire Wire Line
+ 2990 3320 2990 3540
+Wire Wire Line
+ 2950 2640 2950 3320
+Connection ~ 2990 3320
+Wire Wire Line
+ 3020 1540 3020 2100
+Connection ~ 3020 2100
+Wire Wire Line
+ 3560 1550 3560 1900
+Wire Wire Line
+ 3560 1200 2150 1200
+Wire Wire Line
+ 2150 1200 2150 1240
+Wire Wire Line
+ 1950 2230 1480 2230
+Wire Wire Line
+ 1870 3010 1870 2230
+Connection ~ 1870 2230
+Wire Wire Line
+ 3840 2930 3560 2930
+Connection ~ 3560 2930
+Wire Wire Line
+ 2150 4620 2150 5010
+Wire Wire Line
+ 2350 5310 2500 5310
+Wire Wire Line
+ 2500 5310 2500 5520
+Wire Wire Line
+ 2500 5520 2650 5520
+Wire Wire Line
+ 2950 5320 2950 5180
+Wire Wire Line
+ 2950 5180 3260 5180
+Wire Wire Line
+ 3560 5380 3560 5500
+Wire Wire Line
+ 3560 5800 3560 6200
+Wire Wire Line
+ 3560 6600 3560 7210
+Wire Wire Line
+ 1870 6950 3560 6950
+Wire Wire Line
+ 1870 6390 1870 6950
+Connection ~ 2020 6950
+Wire Wire Line
+ 2990 6920 2990 6950
+Connection ~ 2990 6950
+Wire Wire Line
+ 2950 6400 3260 6400
+Wire Wire Line
+ 2990 6400 2990 6620
+Wire Wire Line
+ 2950 5720 2950 6400
+Connection ~ 2990 6400
+Wire Wire Line
+ 3020 4620 3020 5180
+Connection ~ 3020 5180
+Wire Wire Line
+ 3560 4630 3560 4980
+Wire Wire Line
+ 3560 4330 3560 4280
+Wire Wire Line
+ 2150 4280 3800 4280
+Wire Wire Line
+ 2150 4280 2150 4320
+Wire Wire Line
+ 1950 5310 1480 5310
+Wire Wire Line
+ 1870 6090 1870 5310
+Connection ~ 1870 5310
+Wire Wire Line
+ 3840 6010 3560 6010
+Connection ~ 3560 6010
+Connection ~ 3560 1200
+Connection ~ 6580 1200
+Wire Wire Line
+ 3560 1040 9920 1040
+Connection ~ 3560 1040
+Wire Wire Line
+ 3560 1040 3560 1250
+Wire Wire Line
+ 6580 1250 6580 1040
+Wire Wire Line
+ 5900 930 5900 1040
+Connection ~ 5900 1040
+Connection ~ 6580 1040
+Connection ~ 9770 1200
+Wire Wire Line
+ 3800 4280 3800 1040
+Connection ~ 3800 1040
+Connection ~ 3560 4280
+Wire Wire Line
+ 6760 4280 6760 1040
+Connection ~ 6760 1040
+Connection ~ 6580 4280
+Wire Wire Line
+ 9920 1040 9920 4280
+Connection ~ 9770 1040
+Connection ~ 9770 4280
+Wire Wire Line
+ 3560 7210 10010 7210
+Connection ~ 3560 6950
+Connection ~ 9770 6950
+Connection ~ 6580 7210
+Connection ~ 6580 6950
+Wire Wire Line
+ 6040 7340 6040 7210
+Connection ~ 6040 7210
+Wire Wire Line
+ 3680 3870 3680 7210
+Connection ~ 3680 7210
+Connection ~ 3560 3870
+Wire Wire Line
+ 6820 3870 6820 7210
+Connection ~ 6820 7210
+Connection ~ 6580 3870
+Connection ~ 9770 7210
+Connection ~ 9920 4280
+Wire Wire Line
+ 9920 4280 8360 4280
+Wire Wire Line
+ 9230 4320 9230 4280
+Connection ~ 9230 4280
+Wire Wire Line
+ 10010 7210 10010 3870
+Connection ~ 9770 3870
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub new file mode 100644 index 00000000..a86a8a62 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit.sub @@ -0,0 +1,68 @@ +* Subcircuit SN7404_Subcircuit
+.subckt SN7404_Subcircuit net-_d1-pad2_ net-_d2-pad2_ net-_d3-pad2_ net-_d4-pad2_ net-_d5-pad2_ net-_d6-pad2_ net-_r1-pad1_ gndpwr net-_d7-pad2_ net-_d8-pad2_ net-_d9-pad2_ net-_d10-pad2_ net-_d11-pad2_ net-_d12-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7404_subcircuit\sn7404_subcircuit.cir
+.include NPN.lib
+.include D.lib
+r17 net-_r1-pad1_ net-_q17-pad2_ 4k
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q17-pad1_ net-_q19-pad3_ Q2N2222
+q21 net-_q21-pad1_ net-_q19-pad1_ net-_d11-pad1_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q22 net-_d11-pad2_ net-_q19-pad3_ gndpwr Q2N2222
+r21 ? net-_q19-pad1_ 1.6k
+r23 net-_r1-pad1_ net-_q21-pad1_ 130
+r19 net-_q19-pad3_ gndpwr 1k
+d9 gndpwr net-_d9-pad2_ 1N4148
+r18 net-_r1-pad1_ net-_q18-pad2_ 4k
+q18 net-_q18-pad1_ net-_q18-pad2_ net-_d10-pad2_ Q2N2222
+q20 net-_q20-pad1_ net-_q18-pad1_ net-_q20-pad3_ Q2N2222
+q23 net-_q23-pad1_ net-_q20-pad1_ net-_d12-pad1_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q24 net-_d12-pad2_ net-_q20-pad3_ gndpwr Q2N2222
+r22 net-_r1-pad1_ net-_q20-pad1_ 1.6k
+r24 net-_r1-pad1_ net-_q23-pad1_ 130
+r20 net-_q20-pad3_ gndpwr 1k
+d10 gndpwr net-_d10-pad2_ 1N4148
+r9 net-_r1-pad1_ net-_q9-pad2_ 4k
+q9 net-_q11-pad2_ net-_q9-pad2_ net-_d5-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+r13 ? net-_q11-pad1_ 1.6k
+r15 net-_r1-pad1_ net-_q13-pad1_ 130
+r11 net-_q11-pad3_ gndpwr 1k
+d5 gndpwr net-_d5-pad2_ 1N4148
+r10 net-_r1-pad1_ net-_q10-pad2_ 4k
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_d6-pad2_ Q2N2222
+q12 net-_q12-pad1_ net-_q10-pad1_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+r14 ? net-_q12-pad1_ 1.6k
+r16 net-_r1-pad1_ net-_q15-pad1_ 130
+r12 net-_q12-pad3_ gndpwr 1k
+d6 gndpwr net-_d6-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222
+q5 net-_q5-pad1_ net-_q3-pad1_ net-_d3-pad1_ Q2N2222
+d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148
+q6 net-_d3-pad2_ net-_q3-pad3_ gndpwr Q2N2222
+r5 ? net-_q3-pad1_ 1.6k
+r7 net-_r1-pad1_ net-_q5-pad1_ 130
+r3 net-_q3-pad3_ gndpwr 1k
+d1 gndpwr net-_d1-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q2-pad2_ 4k
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+q7 net-_q7-pad1_ net-_q4-pad1_ net-_d4-pad1_ Q2N2222
+d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148
+q8 net-_d4-pad2_ net-_q4-pad3_ gndpwr Q2N2222
+r6 ? net-_q4-pad1_ 1.6k
+r8 net-_r1-pad1_ net-_q7-pad1_ 130
+r4 net-_q4-pad3_ gndpwr 1k
+d2 gndpwr net-_d2-pad2_ 1N4148
+* Control Statements
+
+.ends SN7404_Subcircuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml new file mode 100644 index 00000000..140b1ef3 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/SN7404_Subcircuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><d11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><d12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><d10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7404/analysis b/library/SubcircuitLibrary/SN7404/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7404/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7408/D.lib b/library/SubcircuitLibrary/SN7408/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN7408/NPN.lib b/library/SubcircuitLibrary/SN7408/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib new file mode 100644 index 00000000..0f688db8 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir new file mode 100644 index 00000000..79fe8ae1 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir @@ -0,0 +1,79 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7408_Subcircuit\SN7408_Subcircuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 22:43:20
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+R3 Net-_R1-Pad1_ Net-_D5-Pad1_ 2k
+R7 Net-_R1-Pad1_ Net-_Q11-Pad2_ 1.6k
+R11 Net-_R1-Pad1_ Net-_Q11-Pad1_ 130
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D3-Pad2_ eSim_NPN
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+D3 GNDPWR Net-_D3-Pad2_ eSim_Diode
+Q5 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+Q7 Net-_D5-Pad2_ Net-_Q5-Pad3_ GNDPWR eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+Q9 Net-_Q11-Pad2_ Net-_D5-Pad2_ Net-_Q12-Pad2_ eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_Q11-Pad2_ Net-_D7-Pad1_ eSim_NPN
+Q12 Net-_D7-Pad2_ Net-_Q12-Pad2_ GNDPWR eSim_NPN
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+R4 Net-_Q5-Pad3_ GNDPWR 800
+R8 Net-_Q12-Pad2_ GNDPWR 1k
+U1 Net-_D1-Pad2_ Net-_D3-Pad2_ Net-_D2-Pad2_ Net-_D4-Pad2_ Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D15-Pad2_ Net-_D13-Pad2_ Net-_D16-Pad2_ Net-_D14-Pad2_ PORT
+R2 Net-_R1-Pad1_ Net-_Q3-Pad2_ 4k
+R5 Net-_R1-Pad1_ Net-_D6-Pad1_ 2k
+R9 Net-_R1-Pad1_ Net-_Q10-Pad1_ 1.6k
+R12 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D4-Pad2_ eSim_NPN
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+D4 GNDPWR Net-_D4-Pad2_ eSim_Diode
+Q6 Net-_D6-Pad1_ Net-_Q3-Pad1_ Net-_Q6-Pad3_ eSim_NPN
+Q8 Net-_D6-Pad2_ Net-_Q6-Pad3_ GNDPWR eSim_NPN
+D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode
+Q10 Net-_Q10-Pad1_ Net-_D6-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q10-Pad1_ Net-_D8-Pad1_ eSim_NPN
+Q14 Net-_D8-Pad2_ Net-_Q10-Pad3_ GNDPWR eSim_NPN
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+R6 Net-_Q6-Pad3_ GNDPWR 800
+R10 Net-_Q10-Pad3_ GNDPWR 1k
+R23 Net-_R1-Pad1_ Net-_Q25-Pad2_ 4k
+R19 Net-_R1-Pad1_ Net-_D11-Pad1_ 2k
+R15 Net-_R1-Pad1_ Net-_Q15-Pad2_ 1.6k
+R13 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+Q25 Net-_Q23-Pad2_ Net-_Q25-Pad2_ Net-_D15-Pad2_ eSim_NPN
+Q26 Net-_Q23-Pad2_ Net-_Q25-Pad2_ Net-_D13-Pad2_ eSim_NPN
+D15 GNDPWR Net-_D15-Pad2_ eSim_Diode
+D13 GNDPWR Net-_D13-Pad2_ eSim_Diode
+Q23 Net-_D11-Pad1_ Net-_Q23-Pad2_ Net-_Q21-Pad2_ eSim_NPN
+Q21 Net-_D11-Pad2_ Net-_Q21-Pad2_ GNDPWR eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+Q19 Net-_Q15-Pad2_ Net-_D11-Pad2_ Net-_Q16-Pad2_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ Net-_D9-Pad1_ eSim_NPN
+Q16 Net-_D9-Pad2_ Net-_Q16-Pad2_ GNDPWR eSim_NPN
+D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode
+R20 Net-_Q21-Pad2_ GNDPWR 800
+R16 Net-_Q16-Pad2_ GNDPWR 1k
+R24 Net-_R1-Pad1_ Net-_Q27-Pad2_ 4k
+R21 Net-_R1-Pad1_ Net-_D12-Pad1_ 2k
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 1.6k
+R14 Net-_R1-Pad1_ Net-_Q17-Pad1_ 130
+Q27 Net-_Q24-Pad2_ Net-_Q27-Pad2_ Net-_D16-Pad2_ eSim_NPN
+Q28 Net-_Q24-Pad2_ Net-_Q27-Pad2_ Net-_D14-Pad2_ eSim_NPN
+D16 GNDPWR Net-_D16-Pad2_ eSim_Diode
+D14 GNDPWR Net-_D14-Pad2_ eSim_Diode
+Q24 Net-_D12-Pad1_ Net-_Q24-Pad2_ Net-_Q22-Pad2_ eSim_NPN
+Q22 Net-_D12-Pad2_ Net-_Q22-Pad2_ GNDPWR eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+Q20 Net-_Q17-Pad2_ Net-_D12-Pad2_ Net-_Q18-Pad2_ eSim_NPN
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D10-Pad1_ eSim_NPN
+Q18 Net-_D10-Pad2_ Net-_Q18-Pad2_ GNDPWR eSim_NPN
+D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode
+R22 Net-_Q22-Pad2_ GNDPWR 800
+R18 Net-_Q18-Pad2_ GNDPWR 1k
+
+.end
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out new file mode 100644 index 00000000..d25a0635 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.cir.out @@ -0,0 +1,82 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn7408_subcircuit\sn7408_subcircuit.cir
+
+.include NPN.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_d5-pad1_ 2k
+r7 net-_r1-pad1_ net-_q11-pad2_ 1.6k
+r11 net-_r1-pad1_ net-_q11-pad1_ 130
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_d3-pad2_ Q2N2222
+d1 gndpwr net-_d1-pad2_ 1N4148
+d3 gndpwr net-_d3-pad2_ 1N4148
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q7 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+q9 net-_q11-pad2_ net-_d5-pad2_ net-_q12-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d7-pad1_ Q2N2222
+q12 net-_d7-pad2_ net-_q12-pad2_ gndpwr Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+r4 net-_q5-pad3_ gndpwr 800
+r8 net-_q12-pad2_ gndpwr 1k
+* u1 net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_ port
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r5 net-_r1-pad1_ net-_d6-pad1_ 2k
+r9 net-_r1-pad1_ net-_q10-pad1_ 1.6k
+r12 net-_r1-pad1_ net-_q13-pad1_ 130
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad2_ net-_d4-pad2_ Q2N2222
+d2 gndpwr net-_d2-pad2_ 1N4148
+d4 gndpwr net-_d4-pad2_ 1N4148
+q6 net-_d6-pad1_ net-_q3-pad1_ net-_q6-pad3_ Q2N2222
+q8 net-_d6-pad2_ net-_q6-pad3_ gndpwr Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d6-pad2_ net-_q10-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_d8-pad1_ Q2N2222
+q14 net-_d8-pad2_ net-_q10-pad3_ gndpwr Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+r6 net-_q6-pad3_ gndpwr 800
+r10 net-_q10-pad3_ gndpwr 1k
+r23 net-_r1-pad1_ net-_q25-pad2_ 4k
+r19 net-_r1-pad1_ net-_d11-pad1_ 2k
+r15 net-_r1-pad1_ net-_q15-pad2_ 1.6k
+r13 net-_r1-pad1_ net-_q15-pad1_ 130
+q25 net-_q23-pad2_ net-_q25-pad2_ net-_d15-pad2_ Q2N2222
+q26 net-_q23-pad2_ net-_q25-pad2_ net-_d13-pad2_ Q2N2222
+d15 gndpwr net-_d15-pad2_ 1N4148
+d13 gndpwr net-_d13-pad2_ 1N4148
+q23 net-_d11-pad1_ net-_q23-pad2_ net-_q21-pad2_ Q2N2222
+q21 net-_d11-pad2_ net-_q21-pad2_ gndpwr Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q19 net-_q15-pad2_ net-_d11-pad2_ net-_q16-pad2_ Q2N2222
+q15 net-_q15-pad1_ net-_q15-pad2_ net-_d9-pad1_ Q2N2222
+q16 net-_d9-pad2_ net-_q16-pad2_ gndpwr Q2N2222
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+r20 net-_q21-pad2_ gndpwr 800
+r16 net-_q16-pad2_ gndpwr 1k
+r24 net-_r1-pad1_ net-_q27-pad2_ 4k
+r21 net-_r1-pad1_ net-_d12-pad1_ 2k
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r14 net-_r1-pad1_ net-_q17-pad1_ 130
+q27 net-_q24-pad2_ net-_q27-pad2_ net-_d16-pad2_ Q2N2222
+q28 net-_q24-pad2_ net-_q27-pad2_ net-_d14-pad2_ Q2N2222
+d16 gndpwr net-_d16-pad2_ 1N4148
+d14 gndpwr net-_d14-pad2_ 1N4148
+q24 net-_d12-pad1_ net-_q24-pad2_ net-_q22-pad2_ Q2N2222
+q22 net-_d12-pad2_ net-_q22-pad2_ gndpwr Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q20 net-_q17-pad2_ net-_d12-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d10-pad1_ Q2N2222
+q18 net-_d10-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+r22 net-_q22-pad2_ gndpwr 800
+r18 net-_q18-pad2_ gndpwr 1k
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch new file mode 100644 index 00000000..123da2b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sch @@ -0,0 +1,1367 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7408_Subcircuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L resistor R1
+U 1 1 678204C6
+P 2050 1270
+F 0 "R1" H 2100 1400 50 0000 C CNN
+F 1 "4k" H 2100 1220 50 0000 C CNN
+F 2 "" H 2100 1250 30 0000 C CNN
+F 3 "" V 2100 1320 30 0000 C CNN
+ 1 2050 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R3
+U 1 1 678205B9
+P 2680 1270
+F 0 "R3" H 2730 1400 50 0000 C CNN
+F 1 "2k" H 2730 1220 50 0000 C CNN
+F 2 "" H 2730 1250 30 0000 C CNN
+F 3 "" V 2730 1320 30 0000 C CNN
+ 1 2680 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R7
+U 1 1 67820653
+P 3550 1270
+F 0 "R7" H 3600 1400 50 0000 C CNN
+F 1 "1.6k" H 3600 1220 50 0000 C CNN
+F 2 "" H 3600 1250 30 0000 C CNN
+F 3 "" V 3600 1320 30 0000 C CNN
+ 1 3550 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R11
+U 1 1 678206FC
+P 3920 1270
+F 0 "R11" H 3970 1400 50 0000 C CNN
+F 1 "130" H 3970 1220 50 0000 C CNN
+F 2 "" H 3970 1250 30 0000 C CNN
+F 3 "" V 3970 1320 30 0000 C CNN
+ 1 3920 1270
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q1
+U 1 1 678207BE
+P 2100 2070
+F 0 "Q1" H 2000 2120 50 0000 R CNN
+F 1 "eSim_NPN" H 2050 2220 50 0000 R CNN
+F 2 "" H 2300 2170 29 0000 C CNN
+F 3 "" H 2100 2070 60 0000 C CNN
+ 1 2100 2070
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q2
+U 1 1 67820877
+P 2100 2480
+F 0 "Q2" H 2000 2530 50 0000 R CNN
+F 1 "eSim_NPN" H 2050 2630 50 0000 R CNN
+F 2 "" H 2300 2580 29 0000 C CNN
+F 3 "" H 2100 2480 60 0000 C CNN
+ 1 2100 2480
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_Diode D1
+U 1 1 67820907
+P 1700 2980
+F 0 "D1" H 1700 3080 50 0000 C CNN
+F 1 "eSim_Diode" H 1700 2880 50 0000 C CNN
+F 2 "" H 1700 2980 60 0000 C CNN
+F 3 "" H 1700 2980 60 0000 C CNN
+ 1 1700 2980
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D3
+U 1 1 67820AB9
+P 1900 3330
+F 0 "D3" H 1900 3430 50 0000 C CNN
+F 1 "eSim_Diode" H 1900 3230 50 0000 C CNN
+F 2 "" H 1900 3330 60 0000 C CNN
+F 3 "" H 1900 3330 60 0000 C CNN
+ 1 1900 3330
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 2100 2280 2370 2280
+Wire Wire Line
+ 2370 2280 2370 1870
+Wire Wire Line
+ 2370 1870 2100 1870
+Wire Wire Line
+ 2300 2170 2300 2580
+Wire Wire Line
+ 2300 2580 2430 2580
+$Comp
+L eSim_NPN Q5
+U 1 1 67826BC4
+P 2630 2580
+F 0 "Q5" H 2530 2630 50 0000 R CNN
+F 1 "eSim_NPN" H 2580 2730 50 0000 R CNN
+F 2 "" H 2830 2680 29 0000 C CNN
+F 3 "" H 2630 2580 60 0000 C CNN
+ 1 2630 2580
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 67826CF0
+P 3090 2780
+F 0 "Q7" H 2990 2830 50 0000 R CNN
+F 1 "eSim_NPN" H 3040 2930 50 0000 R CNN
+F 2 "" H 3290 2880 29 0000 C CNN
+F 3 "" H 3090 2780 60 0000 C CNN
+ 1 3090 2780
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D5
+U 1 1 67826D94
+P 2970 2380
+F 0 "D5" H 2970 2480 50 0000 C CNN
+F 1 "eSim_Diode" H 2970 2280 50 0000 C CNN
+F 2 "" H 2970 2380 60 0000 C CNN
+F 3 "" H 2970 2380 60 0000 C CNN
+ 1 2970 2380
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 67826E95
+P 3500 2380
+F 0 "Q9" H 3400 2430 50 0000 R CNN
+F 1 "eSim_NPN" H 3450 2530 50 0000 R CNN
+F 2 "" H 3700 2480 29 0000 C CNN
+F 3 "" H 3500 2380 60 0000 C CNN
+ 1 3500 2380
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 67826F1F
+P 3870 2120
+F 0 "Q11" H 3770 2170 50 0000 R CNN
+F 1 "eSim_NPN" H 3820 2270 50 0000 R CNN
+F 2 "" H 4070 2220 29 0000 C CNN
+F 3 "" H 3870 2120 60 0000 C CNN
+ 1 3870 2120
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 67827003
+P 3870 3050
+F 0 "Q12" H 3770 3100 50 0000 R CNN
+F 1 "eSim_NPN" H 3820 3200 50 0000 R CNN
+F 2 "" H 4070 3150 29 0000 C CNN
+F 3 "" H 3870 3050 60 0000 C CNN
+ 1 3870 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D7
+U 1 1 6782721B
+P 3970 2580
+F 0 "D7" H 3970 2680 50 0000 C CNN
+F 1 "eSim_Diode" H 3970 2480 50 0000 C CNN
+F 2 "" H 3970 2580 60 0000 C CNN
+F 3 "" H 3970 2580 60 0000 C CNN
+ 1 3970 2580
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 67827B70
+P 2680 3280
+F 0 "R4" H 2730 3410 50 0000 C CNN
+F 1 "800" H 2730 3230 50 0000 C CNN
+F 2 "" H 2730 3260 30 0000 C CNN
+F 3 "" V 2730 3330 30 0000 C CNN
+ 1 2680 3280
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R8
+U 1 1 67827E34
+P 3550 3280
+F 0 "R8" H 3600 3410 50 0000 C CNN
+F 1 "1k" H 3600 3230 50 0000 C CNN
+F 2 "" H 3600 3260 30 0000 C CNN
+F 3 "" V 3600 3330 30 0000 C CNN
+ 1 3550 3280
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 2820 2380 2730 2380
+Wire Wire Line
+ 2730 2380 2730 1470
+Wire Wire Line
+ 2100 1870 2100 1470
+Wire Wire Line
+ 3670 2120 3600 2120
+Wire Wire Line
+ 3600 1470 3600 2180
+Connection ~ 3600 2120
+Wire Wire Line
+ 3970 1920 3970 1470
+Wire Wire Line
+ 3300 2380 3120 2380
+Wire Wire Line
+ 3190 2580 3190 2380
+Connection ~ 3190 2380
+Wire Wire Line
+ 2890 2780 2730 2780
+Wire Wire Line
+ 2730 2780 2730 3180
+Wire Wire Line
+ 1900 2580 1900 3180
+Wire Wire Line
+ 1900 2170 1700 2170
+Wire Wire Line
+ 1700 2170 1700 2830
+Wire Wire Line
+ 3600 3050 3670 3050
+Wire Wire Line
+ 3600 2580 3600 3180
+Connection ~ 3600 3050
+Wire Wire Line
+ 3970 2730 3970 2850
+Wire Wire Line
+ 3970 2320 3970 2430
+Wire Wire Line
+ 3970 3250 3970 3560
+Wire Wire Line
+ 1700 3560 9420 3560
+Wire Wire Line
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+Wire Wire Line
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+$Comp
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+Wire Wire Line
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+Connection ~ 3970 5900
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+U 1 1 6782F80A
+P 9070 1270
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+$Comp
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+U 1 1 6782F810
+P 8440 1270
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+$Comp
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+U 1 1 6782F816
+P 7570 1270
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+$Comp
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+U 1 1 6782F81C
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+$Comp
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 8150 2380 60 0000 C CNN
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+$Comp
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+U 1 1 6782F851
+P 7620 2380
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+P 7250 2120
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+P 7150 2580
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+$Comp
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+U 1 1 6782F869
+P 8440 3280
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+ 1 8440 3280
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+$Comp
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+U 1 1 6782F86F
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+Wire Wire Line
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+Connection ~ 7520 2120
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+P 9790 2460
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+ -1 0 0 -1
+$EndComp
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+Connection ~ 9220 2750
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+Connection ~ 9420 2460
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+U 9 1 6782F8AB
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+ 9 6800 2790
+ 1 0 0 1
+$EndComp
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+Connection ~ 7150 2790
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+L resistor R24
+U 1 1 6782F8B3
+P 9070 4380
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+ 1 9070 4380
+ 0 -1 1 0
+$EndComp
+$Comp
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+U 1 1 6782F8B9
+P 8440 4380
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+ 1 8440 4380
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 6782F8BF
+P 7570 4380
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+ 1 7570 4380
+ 0 -1 1 0
+$EndComp
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+U 1 1 6782F8C5
+P 7200 4380
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+U 1 1 6782F8CB
+P 9020 5180
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+P 9420 6090
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+ 1 9420 6090
+ 0 1 -1 0
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+U 1 1 6782F8DD
+P 9220 6440
+F 0 "D14" H 9220 6540 50 0000 C CNN
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+ 1 9220 6440
+ 0 1 -1 0
+$EndComp
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+U 1 1 6782F8E8
+P 8490 5690
+F 0 "Q24" H 8390 5740 50 0000 R CNN
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+F 2 "" H 8690 5790 29 0000 C CNN
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+ 1 8490 5690
+ -1 0 0 -1
+$EndComp
+$Comp
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+U 1 1 6782F8EE
+P 8030 5890
+F 0 "Q22" H 7930 5940 50 0000 R CNN
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+F 2 "" H 8230 5990 29 0000 C CNN
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+ 1 8030 5890
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D12
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+F 0 "D12" H 8150 5590 50 0000 C CNN
+F 1 "eSim_Diode" H 8150 5390 50 0000 C CNN
+F 2 "" H 8150 5490 60 0000 C CNN
+F 3 "" H 8150 5490 60 0000 C CNN
+ 1 8150 5490
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q20
+U 1 1 6782F8FA
+P 7620 5490
+F 0 "Q20" H 7520 5540 50 0000 R CNN
+F 1 "eSim_NPN" H 7570 5640 50 0000 R CNN
+F 2 "" H 7820 5590 29 0000 C CNN
+F 3 "" H 7620 5490 60 0000 C CNN
+ 1 7620 5490
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 6782F900
+P 7250 5230
+F 0 "Q17" H 7150 5280 50 0000 R CNN
+F 1 "eSim_NPN" H 7200 5380 50 0000 R CNN
+F 2 "" H 7450 5330 29 0000 C CNN
+F 3 "" H 7250 5230 60 0000 C CNN
+ 1 7250 5230
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q18
+U 1 1 6782F906
+P 7250 6160
+F 0 "Q18" H 7150 6210 50 0000 R CNN
+F 1 "eSim_NPN" H 7200 6310 50 0000 R CNN
+F 2 "" H 7450 6260 29 0000 C CNN
+F 3 "" H 7250 6160 60 0000 C CNN
+ 1 7250 6160
+ -1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D10
+U 1 1 6782F90C
+P 7150 5690
+F 0 "D10" H 7150 5790 50 0000 C CNN
+F 1 "eSim_Diode" H 7150 5590 50 0000 C CNN
+F 2 "" H 7150 5690 60 0000 C CNN
+F 3 "" H 7150 5690 60 0000 C CNN
+ 1 7150 5690
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R22
+U 1 1 6782F912
+P 8440 6390
+F 0 "R22" H 8490 6520 50 0000 C CNN
+F 1 "800" H 8490 6340 50 0000 C CNN
+F 2 "" H 8490 6370 30 0000 C CNN
+F 3 "" V 8490 6440 30 0000 C CNN
+ 1 8440 6390
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R18
+U 1 1 6782F918
+P 7570 6390
+F 0 "R18" H 7620 6520 50 0000 C CNN
+F 1 "1k" H 7620 6340 50 0000 C CNN
+F 2 "" H 7620 6370 30 0000 C CNN
+F 3 "" V 7620 6440 30 0000 C CNN
+ 1 7570 6390
+ 0 -1 1 0
+$EndComp
+Wire Wire Line
+ 8300 5490 8390 5490
+Wire Wire Line
+ 8390 5490 8390 4580
+Wire Wire Line
+ 9020 4980 9020 4580
+Wire Wire Line
+ 7450 5230 7520 5230
+Wire Wire Line
+ 7520 4580 7520 5290
+Connection ~ 7520 5230
+Wire Wire Line
+ 7150 5030 7150 4580
+Wire Wire Line
+ 7820 5490 8000 5490
+Wire Wire Line
+ 7930 5690 7930 5490
+Connection ~ 7930 5490
+Wire Wire Line
+ 8230 5890 8390 5890
+Wire Wire Line
+ 8390 5890 8390 6290
+Wire Wire Line
+ 9220 5690 9220 6290
+Wire Wire Line
+ 9220 5280 9420 5280
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7520 6160
+Wire Wire Line
+ 7150 5840 7150 5960
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9220 6670
+Wire Wire Line
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+Connection ~ 8390 6670
+Wire Wire Line
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+Connection ~ 7520 6670
+Wire Wire Line
+ 7930 6090 7930 6670
+Connection ~ 7930 6670
+Wire Wire Line
+ 7150 4180 7150 4280
+Wire Wire Line
+ 9020 4180 9020 4280
+Wire Wire Line
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+Connection ~ 8390 4180
+Wire Wire Line
+ 7520 4280 7520 4180
+Connection ~ 7520 4180
+$Comp
+L PORT U1
+U 13 1 6782F944
+P 9790 5570
+F 0 "U1" H 9840 5670 30 0000 C CNN
+F 1 "PORT" H 9790 5570 30 0000 C CNN
+F 2 "" H 9790 5570 60 0000 C CNN
+F 3 "" H 9790 5570 60 0000 C CNN
+ 13 9790 5570
+ -1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6782F94A
+P 9790 5860
+F 0 "U1" H 9840 5960 30 0000 C CNN
+F 1 "PORT" H 9790 5860 30 0000 C CNN
+F 2 "" H 9790 5860 60 0000 C CNN
+F 3 "" H 9790 5860 60 0000 C CNN
+ 14 9790 5860
+ -1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9540 5860 9220 5860
+Connection ~ 9220 5860
+Wire Wire Line
+ 9540 5570 9420 5570
+Connection ~ 9420 5570
+$Comp
+L PORT U1
+U 10 1 6782F954
+P 6800 5900
+F 0 "U1" H 6850 6000 30 0000 C CNN
+F 1 "PORT" H 6800 5900 30 0000 C CNN
+F 2 "" H 6800 5900 60 0000 C CNN
+F 3 "" H 6800 5900 60 0000 C CNN
+ 10 6800 5900
+ 1 0 0 1
+$EndComp
+Wire Wire Line
+ 7050 5900 7150 5900
+Connection ~ 7150 5900
+$Comp
+L PORT U1
+U 7 1 6783256E
+P 5300 620
+F 0 "U1" H 5350 720 30 0000 C CNN
+F 1 "PORT" H 5300 620 30 0000 C CNN
+F 2 "" H 5300 620 60 0000 C CNN
+F 3 "" H 5300 620 60 0000 C CNN
+ 7 5300 620
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 678327B9
+P 5740 620
+F 0 "U1" H 5790 720 30 0000 C CNN
+F 1 "PORT" H 5740 620 30 0000 C CNN
+F 2 "" H 5740 620 60 0000 C CNN
+F 3 "" H 5740 620 60 0000 C CNN
+ 8 5740 620
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5300 870 5300 4180
+Connection ~ 3970 1070
+Connection ~ 5300 1070
+Connection ~ 7150 1070
+Connection ~ 3970 4180
+Connection ~ 5300 4180
+Connection ~ 7150 4180
+Wire Wire Line
+ 5740 870 5740 6670
+Connection ~ 3970 3560
+Connection ~ 5740 3560
+Connection ~ 7150 3560
+Connection ~ 3970 6670
+Connection ~ 5740 6670
+Connection ~ 7150 6670
+$Comp
+L GNDPWR #PWR01
+U 1 1 6783B5E4
+P 2940 3630
+F 0 "#PWR01" H 2940 3430 50 0001 C CNN
+F 1 "GNDPWR" H 2940 3500 50 0000 C CNN
+F 2 "" H 2940 3580 50 0001 C CNN
+F 3 "" H 2940 3580 50 0001 C CNN
+ 1 2940 3630
+ 1 0 0 -1
+$EndComp
+$Comp
+L GNDPWR #PWR02
+U 1 1 6783B6EC
+P 2920 6750
+F 0 "#PWR02" H 2920 6550 50 0001 C CNN
+F 1 "GNDPWR" H 2920 6620 50 0000 C CNN
+F 2 "" H 2920 6700 50 0001 C CNN
+F 3 "" H 2920 6700 50 0001 C CNN
+ 1 2920 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L GNDPWR #PWR03
+U 1 1 6783BB21
+P 8140 6740
+F 0 "#PWR03" H 8140 6540 50 0001 C CNN
+F 1 "GNDPWR" H 8140 6610 50 0000 C CNN
+F 2 "" H 8140 6690 50 0001 C CNN
+F 3 "" H 8140 6690 50 0001 C CNN
+ 1 8140 6740
+ 1 0 0 -1
+$EndComp
+$Comp
+L GNDPWR #PWR04
+U 1 1 6783BFA8
+P 8150 3630
+F 0 "#PWR04" H 8150 3430 50 0001 C CNN
+F 1 "GNDPWR" H 8150 3500 50 0000 C CNN
+F 2 "" H 8150 3580 50 0001 C CNN
+F 3 "" H 8150 3580 50 0001 C CNN
+ 1 8150 3630
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8150 3630 8150 3560
+Connection ~ 8150 3560
+Wire Wire Line
+ 2940 3630 2940 3560
+Connection ~ 2940 3560
+Wire Wire Line
+ 2920 6750 2920 6670
+Connection ~ 2920 6670
+Wire Wire Line
+ 8140 6740 8140 6670
+Connection ~ 8140 6670
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub new file mode 100644 index 00000000..75d406e7 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit.sub @@ -0,0 +1,76 @@ +* Subcircuit SN7408_Subcircuit
+.subckt SN7408_Subcircuit net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7408_subcircuit\sn7408_subcircuit.cir
+.include NPN.lib
+.include D.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_d5-pad1_ 2k
+r7 net-_r1-pad1_ net-_q11-pad2_ 1.6k
+r11 net-_r1-pad1_ net-_q11-pad1_ 130
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q1-pad1_ net-_q1-pad2_ net-_d3-pad2_ Q2N2222
+d1 gndpwr net-_d1-pad2_ 1N4148
+d3 gndpwr net-_d3-pad2_ 1N4148
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q7 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+q9 net-_q11-pad2_ net-_d5-pad2_ net-_q12-pad2_ Q2N2222
+q11 net-_q11-pad1_ net-_q11-pad2_ net-_d7-pad1_ Q2N2222
+q12 net-_d7-pad2_ net-_q12-pad2_ gndpwr Q2N2222
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+r4 net-_q5-pad3_ gndpwr 800
+r8 net-_q12-pad2_ gndpwr 1k
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r5 net-_r1-pad1_ net-_d6-pad1_ 2k
+r9 net-_r1-pad1_ net-_q10-pad1_ 1.6k
+r12 net-_r1-pad1_ net-_q13-pad1_ 130
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q3-pad1_ net-_q3-pad2_ net-_d4-pad2_ Q2N2222
+d2 gndpwr net-_d2-pad2_ 1N4148
+d4 gndpwr net-_d4-pad2_ 1N4148
+q6 net-_d6-pad1_ net-_q3-pad1_ net-_q6-pad3_ Q2N2222
+q8 net-_d6-pad2_ net-_q6-pad3_ gndpwr Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+q10 net-_q10-pad1_ net-_d6-pad2_ net-_q10-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q10-pad1_ net-_d8-pad1_ Q2N2222
+q14 net-_d8-pad2_ net-_q10-pad3_ gndpwr Q2N2222
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+r6 net-_q6-pad3_ gndpwr 800
+r10 net-_q10-pad3_ gndpwr 1k
+r23 net-_r1-pad1_ net-_q25-pad2_ 4k
+r19 net-_r1-pad1_ net-_d11-pad1_ 2k
+r15 net-_r1-pad1_ net-_q15-pad2_ 1.6k
+r13 net-_r1-pad1_ net-_q15-pad1_ 130
+q25 net-_q23-pad2_ net-_q25-pad2_ net-_d15-pad2_ Q2N2222
+q26 net-_q23-pad2_ net-_q25-pad2_ net-_d13-pad2_ Q2N2222
+d15 gndpwr net-_d15-pad2_ 1N4148
+d13 gndpwr net-_d13-pad2_ 1N4148
+q23 net-_d11-pad1_ net-_q23-pad2_ net-_q21-pad2_ Q2N2222
+q21 net-_d11-pad2_ net-_q21-pad2_ gndpwr Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+q19 net-_q15-pad2_ net-_d11-pad2_ net-_q16-pad2_ Q2N2222
+q15 net-_q15-pad1_ net-_q15-pad2_ net-_d9-pad1_ Q2N2222
+q16 net-_d9-pad2_ net-_q16-pad2_ gndpwr Q2N2222
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+r20 net-_q21-pad2_ gndpwr 800
+r16 net-_q16-pad2_ gndpwr 1k
+r24 net-_r1-pad1_ net-_q27-pad2_ 4k
+r21 net-_r1-pad1_ net-_d12-pad1_ 2k
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r14 net-_r1-pad1_ net-_q17-pad1_ 130
+q27 net-_q24-pad2_ net-_q27-pad2_ net-_d16-pad2_ Q2N2222
+q28 net-_q24-pad2_ net-_q27-pad2_ net-_d14-pad2_ Q2N2222
+d16 gndpwr net-_d16-pad2_ 1N4148
+d14 gndpwr net-_d14-pad2_ 1N4148
+q24 net-_d12-pad1_ net-_q24-pad2_ net-_q22-pad2_ Q2N2222
+q22 net-_d12-pad2_ net-_q22-pad2_ gndpwr Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+q20 net-_q17-pad2_ net-_d12-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d10-pad1_ Q2N2222
+q18 net-_d10-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+r22 net-_q22-pad2_ gndpwr 800
+r18 net-_q18-pad2_ gndpwr 1k
+* Control Statements
+
+.ends SN7408_Subcircuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml new file mode 100644 index 00000000..d363fca4 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/SN7408_Subcircuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><d15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d15><d13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d13><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><d11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28><d16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d16><d14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d14><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><d12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><d10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7408/analysis b/library/SubcircuitLibrary/SN7408/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7408/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7432/D.lib b/library/SubcircuitLibrary/SN7432/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN7432/NPN.lib b/library/SubcircuitLibrary/SN7432/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib new file mode 100644 index 00000000..0f688db8 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir new file mode 100644 index 00000000..71880368 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir @@ -0,0 +1,87 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN7432_Subcirrcuit\SN7432_Subcirrcuit.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 01/10/25 23:23:51
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ Net-_D2-Pad2_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q4-Pad2_ Net-_D4-Pad2_ eSim_NPN
+Q7 Net-_D6-Pad1_ Net-_Q3-Pad1_ Net-_Q10-Pad2_ eSim_NPN
+Q8 Net-_D6-Pad1_ Net-_Q4-Pad1_ Net-_Q10-Pad2_ eSim_NPN
+D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode
+R2 Net-_R1-Pad1_ Net-_Q3-Pad2_ 4k
+R4 Net-_R1-Pad1_ Net-_Q4-Pad2_ 2k
+R7 Net-_R1-Pad1_ Net-_D6-Pad1_ 2.5k
+Q10 Net-_D6-Pad2_ Net-_Q10-Pad2_ GNDPWR eSim_NPN
+Q12 Net-_Q12-Pad1_ Net-_D6-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q15 Net-_Q15-Pad1_ Net-_Q12-Pad1_ Net-_D8-Pad1_ eSim_NPN
+R11 Net-_R1-Pad1_ Net-_Q12-Pad1_ 1.6k
+R14 Net-_R1-Pad1_ Net-_Q15-Pad1_ 130
+D4 GNDPWR Net-_D4-Pad2_ eSim_Diode
+D2 GNDPWR Net-_D2-Pad2_ eSim_Diode
+R8 Net-_Q10-Pad2_ GNDPWR 1k
+R12 Net-_Q12-Pad3_ GNDPWR 1k
+D8 Net-_D8-Pad1_ Net-_D8-Pad2_ eSim_Diode
+Q16 Net-_D8-Pad2_ Net-_Q12-Pad3_ GNDPWR eSim_NPN
+Q29 Net-_Q25-Pad2_ Net-_Q29-Pad2_ Net-_D15-Pad2_ eSim_NPN
+Q30 Net-_Q26-Pad2_ Net-_Q30-Pad2_ Net-_D13-Pad2_ eSim_NPN
+Q25 Net-_D11-Pad1_ Net-_Q25-Pad2_ Net-_Q23-Pad2_ eSim_NPN
+Q26 Net-_D11-Pad1_ Net-_Q26-Pad2_ Net-_Q23-Pad2_ eSim_NPN
+D11 Net-_D11-Pad1_ Net-_D11-Pad2_ eSim_Diode
+R27 Net-_R1-Pad1_ Net-_Q29-Pad2_ 4k
+R25 Net-_R1-Pad1_ Net-_Q30-Pad2_ 2k
+R22 Net-_R1-Pad1_ Net-_D11-Pad1_ 2.5k
+Q23 Net-_D11-Pad2_ Net-_Q23-Pad2_ GNDPWR eSim_NPN
+Q21 Net-_Q17-Pad2_ Net-_D11-Pad2_ Net-_Q18-Pad2_ eSim_NPN
+Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_D9-Pad1_ eSim_NPN
+R17 Net-_R1-Pad1_ Net-_Q17-Pad2_ 1.6k
+R15 Net-_R1-Pad1_ Net-_Q17-Pad1_ 130
+D13 GNDPWR Net-_D13-Pad2_ eSim_Diode
+D15 GNDPWR Net-_D15-Pad2_ eSim_Diode
+R21 Net-_Q23-Pad2_ GNDPWR 1k
+R18 Net-_Q18-Pad2_ GNDPWR 1k
+D9 Net-_D9-Pad1_ Net-_D9-Pad2_ eSim_Diode
+Q18 Net-_D9-Pad2_ Net-_Q18-Pad2_ GNDPWR eSim_NPN
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad2_ eSim_NPN
+Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_D3-Pad2_ eSim_NPN
+Q5 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+Q6 Net-_D5-Pad1_ Net-_Q2-Pad1_ Net-_Q5-Pad3_ eSim_NPN
+D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k
+R3 Net-_R1-Pad1_ Net-_Q2-Pad2_ 2k
+R5 Net-_R1-Pad1_ Net-_D5-Pad1_ 2.5k
+Q9 Net-_D5-Pad2_ Net-_Q5-Pad3_ GNDPWR eSim_NPN
+Q11 Net-_Q11-Pad1_ Net-_D5-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q11-Pad1_ Net-_D7-Pad1_ eSim_NPN
+R9 Net-_R1-Pad1_ Net-_Q11-Pad1_ 1.6k
+R13 Net-_R1-Pad1_ Net-_Q13-Pad1_ 130
+D3 GNDPWR Net-_D3-Pad2_ eSim_Diode
+D1 GNDPWR Net-_D1-Pad2_ eSim_Diode
+R6 Net-_Q5-Pad3_ GNDPWR 1k
+R10 Net-_Q11-Pad3_ GNDPWR 1k
+D7 Net-_D7-Pad1_ Net-_D7-Pad2_ eSim_Diode
+Q14 Net-_D7-Pad2_ Net-_Q11-Pad3_ GNDPWR eSim_NPN
+Q31 Net-_Q27-Pad2_ Net-_Q31-Pad2_ Net-_D16-Pad2_ eSim_NPN
+Q32 Net-_Q28-Pad2_ Net-_Q32-Pad2_ Net-_D14-Pad2_ eSim_NPN
+Q27 Net-_D12-Pad1_ Net-_Q27-Pad2_ Net-_Q24-Pad2_ eSim_NPN
+Q28 Net-_D12-Pad1_ Net-_Q28-Pad2_ Net-_Q24-Pad2_ eSim_NPN
+D12 Net-_D12-Pad1_ Net-_D12-Pad2_ eSim_Diode
+R28 Net-_R1-Pad1_ Net-_Q31-Pad2_ 4k
+R26 Net-_R1-Pad1_ Net-_Q32-Pad2_ 2k
+R24 Net-_R1-Pad1_ Net-_D12-Pad1_ 2.5k
+Q24 Net-_D12-Pad2_ Net-_Q24-Pad2_ GNDPWR eSim_NPN
+Q22 Net-_Q19-Pad2_ Net-_D12-Pad2_ Net-_Q20-Pad2_ eSim_NPN
+Q19 Net-_Q19-Pad1_ Net-_Q19-Pad2_ Net-_D10-Pad1_ eSim_NPN
+R19 Net-_R1-Pad1_ Net-_Q19-Pad2_ 1.6k
+R16 Net-_R1-Pad1_ Net-_Q19-Pad1_ 130
+D14 GNDPWR Net-_D14-Pad2_ eSim_Diode
+D16 GNDPWR Net-_D16-Pad2_ eSim_Diode
+R23 Net-_Q24-Pad2_ GNDPWR 1k
+R20 Net-_Q20-Pad2_ GNDPWR 1k
+D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode
+Q20 Net-_D10-Pad2_ Net-_Q20-Pad2_ GNDPWR eSim_NPN
+U1 Net-_D1-Pad2_ Net-_D3-Pad2_ Net-_D2-Pad2_ Net-_D4-Pad2_ Net-_D7-Pad2_ Net-_D8-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_D9-Pad2_ Net-_D10-Pad2_ Net-_D15-Pad2_ Net-_D13-Pad2_ Net-_D16-Pad2_ Net-_D14-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out new file mode 100644 index 00000000..cb10dab9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.cir.out @@ -0,0 +1,90 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn7432_subcirrcuit\sn7432_subcirrcuit.cir
+
+.include NPN.lib
+.include D.lib
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222
+q7 net-_d6-pad1_ net-_q3-pad1_ net-_q10-pad2_ Q2N2222
+q8 net-_d6-pad1_ net-_q4-pad1_ net-_q10-pad2_ Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r4 net-_r1-pad1_ net-_q4-pad2_ 2k
+r7 net-_r1-pad1_ net-_d6-pad1_ 2.5k
+q10 net-_d6-pad2_ net-_q10-pad2_ gndpwr Q2N2222
+q12 net-_q12-pad1_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+r11 net-_r1-pad1_ net-_q12-pad1_ 1.6k
+r14 net-_r1-pad1_ net-_q15-pad1_ 130
+d4 gndpwr net-_d4-pad2_ 1N4148
+d2 gndpwr net-_d2-pad2_ 1N4148
+r8 net-_q10-pad2_ gndpwr 1k
+r12 net-_q12-pad3_ gndpwr 1k
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+q29 net-_q25-pad2_ net-_q29-pad2_ net-_d15-pad2_ Q2N2222
+q30 net-_q26-pad2_ net-_q30-pad2_ net-_d13-pad2_ Q2N2222
+q25 net-_d11-pad1_ net-_q25-pad2_ net-_q23-pad2_ Q2N2222
+q26 net-_d11-pad1_ net-_q26-pad2_ net-_q23-pad2_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+r27 net-_r1-pad1_ net-_q29-pad2_ 4k
+r25 net-_r1-pad1_ net-_q30-pad2_ 2k
+r22 net-_r1-pad1_ net-_d11-pad1_ 2.5k
+q23 net-_d11-pad2_ net-_q23-pad2_ gndpwr Q2N2222
+q21 net-_q17-pad2_ net-_d11-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad1_ Q2N2222
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r15 net-_r1-pad1_ net-_q17-pad1_ 130
+d13 gndpwr net-_d13-pad2_ 1N4148
+d15 gndpwr net-_d15-pad2_ 1N4148
+r21 net-_q23-pad2_ gndpwr 1k
+r18 net-_q18-pad2_ gndpwr 1k
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+q18 net-_d9-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d3-pad2_ Q2N2222
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q6 net-_d5-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_q2-pad2_ 2k
+r5 net-_r1-pad1_ net-_d5-pad1_ 2.5k
+q9 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+q11 net-_q11-pad1_ net-_d5-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+r9 net-_r1-pad1_ net-_q11-pad1_ 1.6k
+r13 net-_r1-pad1_ net-_q13-pad1_ 130
+d3 gndpwr net-_d3-pad2_ 1N4148
+d1 gndpwr net-_d1-pad2_ 1N4148
+r6 net-_q5-pad3_ gndpwr 1k
+r10 net-_q11-pad3_ gndpwr 1k
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+q31 net-_q27-pad2_ net-_q31-pad2_ net-_d16-pad2_ Q2N2222
+q32 net-_q28-pad2_ net-_q32-pad2_ net-_d14-pad2_ Q2N2222
+q27 net-_d12-pad1_ net-_q27-pad2_ net-_q24-pad2_ Q2N2222
+q28 net-_d12-pad1_ net-_q28-pad2_ net-_q24-pad2_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+r28 net-_r1-pad1_ net-_q31-pad2_ 4k
+r26 net-_r1-pad1_ net-_q32-pad2_ 2k
+r24 net-_r1-pad1_ net-_d12-pad1_ 2.5k
+q24 net-_d12-pad2_ net-_q24-pad2_ gndpwr Q2N2222
+q22 net-_q19-pad2_ net-_d12-pad2_ net-_q20-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q19-pad2_ net-_d10-pad1_ Q2N2222
+r19 net-_r1-pad1_ net-_q19-pad2_ 1.6k
+r16 net-_r1-pad1_ net-_q19-pad1_ 130
+d14 gndpwr net-_d14-pad2_ 1N4148
+d16 gndpwr net-_d16-pad2_ 1N4148
+r23 net-_q24-pad2_ gndpwr 1k
+r20 net-_q20-pad2_ gndpwr 1k
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+q20 net-_d10-pad2_ net-_q20-pad2_ gndpwr Q2N2222
+* u1 net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_ port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch new file mode 100644 index 00000000..50ece14b --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sch @@ -0,0 +1,1551 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN7432_Subcirrcuit-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q3
+U 1 1 6778E6CA
+P 1990 1910
+F 0 "Q3" H 1890 1960 50 0000 R CNN
+F 1 "eSim_NPN" H 1940 2060 50 0000 R CNN
+F 2 "" H 2190 2010 29 0000 C CNN
+F 3 "" H 1990 1910 60 0000 C CNN
+ 1 1990 1910
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q4
+U 1 1 6778E778
+P 1990 2640
+F 0 "Q4" H 1890 2690 50 0000 R CNN
+F 1 "eSim_NPN" H 1940 2790 50 0000 R CNN
+F 2 "" H 2190 2740 29 0000 C CNN
+F 3 "" H 1990 2640 60 0000 C CNN
+ 1 1990 2640
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 6778E848
+P 2690 2010
+F 0 "Q7" H 2590 2060 50 0000 R CNN
+F 1 "eSim_NPN" H 2640 2160 50 0000 R CNN
+F 2 "" H 2890 2110 29 0000 C CNN
+F 3 "" H 2690 2010 60 0000 C CNN
+ 1 2690 2010
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 6778E8D4
+P 2690 2740
+F 0 "Q8" H 2590 2790 50 0000 R CNN
+F 1 "eSim_NPN" H 2640 2890 50 0000 R CNN
+F 2 "" H 2890 2840 29 0000 C CNN
+F 3 "" H 2690 2740 60 0000 C CNN
+ 1 2690 2740
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D6
+U 1 1 6778E99C
+P 3170 2010
+F 0 "D6" H 3170 2110 50 0000 C CNN
+F 1 "eSim_Diode" H 3170 1910 50 0000 C CNN
+F 2 "" H 3170 2010 60 0000 C CNN
+F 3 "" H 3170 2010 60 0000 C CNN
+ 1 3170 2010
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 6778EA11
+P 1940 1320
+F 0 "R2" H 1990 1450 50 0000 C CNN
+F 1 "4k" H 1990 1270 50 0000 C CNN
+F 2 "" H 1990 1300 30 0000 C CNN
+F 3 "" V 1990 1370 30 0000 C CNN
+ 1 1940 1320
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R4
+U 1 1 6778EAB0
+P 2300 1320
+F 0 "R4" H 2350 1450 50 0000 C CNN
+F 1 "2k" H 2350 1270 50 0000 C CNN
+F 2 "" H 2350 1300 30 0000 C CNN
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+P 2930 1320
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+P 3700 1320
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+ 0 1 1 0
+$EndComp
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+U 1 1 6778EE89
+P 4160 1320
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+ 0 1 1 0
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+U 1 1 6778F0B3
+P 2940 3470
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+ 0 1 1 0
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+U 1 1 6778F17D
+P 3700 3460
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+ 0 1 1 0
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+P 3900 3770
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+ 1 0 0 -1
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+U 1 1 67790E8F
+P 4080 2480
+F 0 "D8" H 4080 2580 50 0000 C CNN
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+F 2 "" H 4080 2480 60 0000 C CNN
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+ 1 4080 2480
+ 0 1 1 0
+$EndComp
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+U 1 1 67790FAE
+P 3980 2980
+F 0 "Q16" H 3880 3030 50 0000 R CNN
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+F 2 "" H 4180 3080 29 0000 C CNN
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+ 1 3980 2980
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1990 1710 1990 1520
+Wire Wire Line
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+Wire Wire Line
+ 2350 1220 2350 1180
+Connection ~ 2350 1180
+Wire Wire Line
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+Connection ~ 2980 1180
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 1990 2280 1990 2440
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 2790 2540 2790 2500
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2980 2010
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2980 1720
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2910 2980
+Wire Wire Line
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+Connection ~ 2990 2980
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3450 2510
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3750 1180
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 3750 2980
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 1610 3760
+Wire Wire Line
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+Connection ~ 2990 3760
+Wire Wire Line
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+Connection ~ 3450 3760
+Wire Wire Line
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+Connection ~ 3750 3760
+Wire Wire Line
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+Connection ~ 3900 3760
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 1330 2010
+Wire Wire Line
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+Connection ~ 1610 2740
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+Wire Wire Line
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+Connection ~ 4080 2710
+Connection ~ 4080 3760
+Wire Wire Line
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+Wire Wire Line
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+U 1 1 677B2750
+P 9700 1910
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+U 1 1 677B2756
+P 9700 2640
+F 0 "Q30" H 9600 2690 50 0000 R CNN
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+U 1 1 677B275C
+P 9000 2010
+F 0 "Q25" H 8900 2060 50 0000 R CNN
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+F 2 "" H 9200 2110 29 0000 C CNN
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+U 1 1 677B2762
+P 9000 2740
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+U 1 1 677B2768
+P 8520 2010
+F 0 "D11" H 8520 2110 50 0000 C CNN
+F 1 "eSim_Diode" H 8520 1910 50 0000 C CNN
+F 2 "" H 8520 2010 60 0000 C CNN
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+$Comp
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+U 1 1 677B276E
+P 9750 1320
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+U 1 1 677B2774
+P 9390 1320
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+$Comp
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+U 1 1 677B277A
+P 8760 1320
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+U 1 1 677B2780
+P 8340 2980
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+U 1 1 677B2786
+P 8040 2510
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+F 2 "" H 8240 2610 29 0000 C CNN
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+U 1 1 677B278C
+P 7710 2010
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+$Comp
+L resistor R17
+U 1 1 677B2792
+P 7990 1320
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+U 1 1 677B2798
+P 7530 1320
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+F 3 "" V 7580 1370 30 0000 C CNN
+ 1 7530 1320
+ 0 -1 1 0
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+U 1 1 677B279E
+P 10080 3520
+F 0 "D13" H 10080 3620 50 0000 C CNN
+F 1 "eSim_Diode" H 10080 3420 50 0000 C CNN
+F 2 "" H 10080 3520 60 0000 C CNN
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+ 1 10080 3520
+ 0 1 -1 0
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+U 1 1 677B27A4
+P 10360 3230
+F 0 "D15" H 10360 3330 50 0000 C CNN
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+ 1 10360 3230
+ 0 1 -1 0
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+U 1 1 677B27AA
+P 8750 3470
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+ 1 8750 3470
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+U 1 1 677B27B0
+P 7990 3460
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+U 1 1 677B27B6
+P 7790 3770
+F 0 "#PWR3" H 7790 3570 50 0001 C CNN
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+ 1 7790 3770
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+P 7610 2480
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+ 1 7610 2480
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+U 1 1 677B27C2
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9340 1180
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+Connection ~ 8710 1180
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+U 1 1 677B410D
+P 1980 5260
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+U 1 1 677B412B
+P 1930 4670
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+U 1 1 677B4131
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+U 1 1 677B4137
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+U 1 1 677B4149
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+U 1 1 677B414F
+P 3690 4670
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+U 1 1 677B4155
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+F 0 "D3" H 1600 6970 50 0000 C CNN
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+ 1 1600 6870
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+P 1320 6580
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+L resistor R6
+U 1 1 677B4167
+P 2930 6820
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+ 0 1 1 0
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+L resistor R10
+U 1 1 677B416D
+P 3690 6810
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+ 0 1 1 0
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+U 1 1 677B4173
+P 3890 7120
+F 0 "#PWR1" H 3890 6920 50 0001 C CNN
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+F 2 "" H 3890 7070 50 0001 C CNN
+F 3 "" H 3890 7070 50 0001 C CNN
+ 1 3890 7120
+ 1 0 0 -1
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+L eSim_Diode D7
+U 1 1 677B4179
+P 4070 5830
+F 0 "D7" H 4070 5930 50 0000 C CNN
+F 1 "eSim_Diode" H 4070 5730 50 0000 C CNN
+F 2 "" H 4070 5830 60 0000 C CNN
+F 3 "" H 4070 5830 60 0000 C CNN
+ 1 4070 5830
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q14
+U 1 1 677B417F
+P 3970 6330
+F 0 "Q14" H 3870 6380 50 0000 R CNN
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+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+F 2 "" H 9950 5100 29 0000 C CNN
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+$EndComp
+$Comp
+L eSim_NPN Q32
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+$EndComp
+$Comp
+L eSim_NPN Q27
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+$EndComp
+$Comp
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+P 9800 4410
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+$EndComp
+$Comp
+L resistor R26
+U 1 1 677B5030
+P 9440 4410
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+$EndComp
+$Comp
+L resistor R24
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+L eSim_NPN Q24
+U 1 1 677B503C
+P 8390 6070
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+$EndComp
+$Comp
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+P 8090 5600
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+$EndComp
+$Comp
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+P 7760 5100
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+F 2 "" H 7960 5200 29 0000 C CNN
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+$EndComp
+$Comp
+L resistor R19
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+P 8040 4410
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+F 3 "" V 8090 4460 30 0000 C CNN
+ 1 8040 4410
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+$EndComp
+$Comp
+L resistor R16
+U 1 1 677B5054
+P 7580 4410
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+F 1 "130" H 7630 4360 50 0000 C CNN
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+ 1 7580 4410
+ 0 -1 1 0
+$EndComp
+$Comp
+L eSim_Diode D14
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+ 0 1 -1 0
+$EndComp
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+ 1 10410 6320
+ 0 1 -1 0
+$EndComp
+$Comp
+L resistor R23
+U 1 1 677B5066
+P 8800 6560
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+ 1 8800 6560
+ 0 -1 1 0
+$EndComp
+$Comp
+L resistor R20
+U 1 1 677B506C
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+ 1 8040 6550
+ 0 -1 1 0
+$EndComp
+$Comp
+L GNDPWR #PWR4
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+P 7840 6860
+F 0 "#PWR4" H 7840 6660 50 0001 C CNN
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+ 1 7840 6860
+ -1 0 0 -1
+$EndComp
+$Comp
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+ 1 7660 5570
+ 0 -1 1 0
+$EndComp
+$Comp
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+P 7760 6070
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+ -1 0 0 -1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9390 4270
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
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+U 7 1 678183F3
+P 6110 630
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+F 1 "PORT" H 6110 630 30 0000 C CNN
+F 2 "" H 6110 630 60 0000 C CNN
+F 3 "" H 6110 630 60 0000 C CNN
+ 7 6110 630
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
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+P 6460 630
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+F 3 "" H 6460 630 60 0000 C CNN
+ 8 6460 630
+ 0 1 1 0
+$EndComp
+$Comp
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+P 860 2010
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+F 3 "" H 860 2010 60 0000 C CNN
+ 3 860 2010
+ 1 0 0 -1
+$EndComp
+$Comp
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+P 860 2740
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+F 3 "" H 860 2740 60 0000 C CNN
+ 4 860 2740
+ 1 0 0 -1
+$EndComp
+$Comp
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+F 3 "" H 4460 2710 60 0000 C CNN
+ 6 4460 2710
+ -1 0 0 1
+$EndComp
+$Comp
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+F 3 "" H 850 5360 60 0000 C CNN
+ 1 850 5360
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
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+F 3 "" H 850 6090 60 0000 C CNN
+ 2 850 6090
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+$EndComp
+$Comp
+L PORT U1
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+F 3 "" H 4450 6060 60 0000 C CNN
+ 5 4450 6060
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
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+F 2 "" H 7230 2710 60 0000 C CNN
+F 3 "" H 7230 2710 60 0000 C CNN
+ 9 7230 2710
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6781AECD
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+F 1 "PORT" H 7280 5800 30 0000 C CNN
+F 2 "" H 7280 5800 60 0000 C CNN
+F 3 "" H 7280 5800 60 0000 C CNN
+ 10 7280 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6781B57A
+P 10830 2010
+F 0 "U1" H 10880 2110 30 0000 C CNN
+F 1 "PORT" H 10830 2010 30 0000 C CNN
+F 2 "" H 10830 2010 60 0000 C CNN
+F 3 "" H 10830 2010 60 0000 C CNN
+ 11 10830 2010
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6781BA07
+P 10830 2740
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+F 1 "PORT" H 10830 2740 30 0000 C CNN
+F 2 "" H 10830 2740 60 0000 C CNN
+F 3 "" H 10830 2740 60 0000 C CNN
+ 12 10830 2740
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6781C0E4
+P 10880 5100
+F 0 "U1" H 10930 5200 30 0000 C CNN
+F 1 "PORT" H 10880 5100 30 0000 C CNN
+F 2 "" H 10880 5100 60 0000 C CNN
+F 3 "" H 10880 5100 60 0000 C CNN
+ 13 10880 5100
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6781C506
+P 10880 5830
+F 0 "U1" H 10930 5930 30 0000 C CNN
+F 1 "PORT" H 10880 5830 30 0000 C CNN
+F 2 "" H 10880 5830 60 0000 C CNN
+F 3 "" H 10880 5830 60 0000 C CNN
+ 14 10880 5830
+ -1 0 0 1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub new file mode 100644 index 00000000..1d1d12c9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit.sub @@ -0,0 +1,84 @@ +* Subcircuit SN7432_Subcirrcuit
+.subckt SN7432_Subcirrcuit net-_d1-pad2_ net-_d3-pad2_ net-_d2-pad2_ net-_d4-pad2_ net-_d7-pad2_ net-_d8-pad2_ net-_r1-pad1_ gndpwr net-_d9-pad2_ net-_d10-pad2_ net-_d15-pad2_ net-_d13-pad2_ net-_d16-pad2_ net-_d14-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\sn7432_subcirrcuit\sn7432_subcirrcuit.cir
+.include NPN.lib
+.include D.lib
+q3 net-_q3-pad1_ net-_q3-pad2_ net-_d2-pad2_ Q2N2222
+q4 net-_q4-pad1_ net-_q4-pad2_ net-_d4-pad2_ Q2N2222
+q7 net-_d6-pad1_ net-_q3-pad1_ net-_q10-pad2_ Q2N2222
+q8 net-_d6-pad1_ net-_q4-pad1_ net-_q10-pad2_ Q2N2222
+d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148
+r2 net-_r1-pad1_ net-_q3-pad2_ 4k
+r4 net-_r1-pad1_ net-_q4-pad2_ 2k
+r7 net-_r1-pad1_ net-_d6-pad1_ 2.5k
+q10 net-_d6-pad2_ net-_q10-pad2_ gndpwr Q2N2222
+q12 net-_q12-pad1_ net-_d6-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_q15-pad1_ net-_q12-pad1_ net-_d8-pad1_ Q2N2222
+r11 net-_r1-pad1_ net-_q12-pad1_ 1.6k
+r14 net-_r1-pad1_ net-_q15-pad1_ 130
+d4 gndpwr net-_d4-pad2_ 1N4148
+d2 gndpwr net-_d2-pad2_ 1N4148
+r8 net-_q10-pad2_ gndpwr 1k
+r12 net-_q12-pad3_ gndpwr 1k
+d8 net-_d8-pad1_ net-_d8-pad2_ 1N4148
+q16 net-_d8-pad2_ net-_q12-pad3_ gndpwr Q2N2222
+q29 net-_q25-pad2_ net-_q29-pad2_ net-_d15-pad2_ Q2N2222
+q30 net-_q26-pad2_ net-_q30-pad2_ net-_d13-pad2_ Q2N2222
+q25 net-_d11-pad1_ net-_q25-pad2_ net-_q23-pad2_ Q2N2222
+q26 net-_d11-pad1_ net-_q26-pad2_ net-_q23-pad2_ Q2N2222
+d11 net-_d11-pad1_ net-_d11-pad2_ 1N4148
+r27 net-_r1-pad1_ net-_q29-pad2_ 4k
+r25 net-_r1-pad1_ net-_q30-pad2_ 2k
+r22 net-_r1-pad1_ net-_d11-pad1_ 2.5k
+q23 net-_d11-pad2_ net-_q23-pad2_ gndpwr Q2N2222
+q21 net-_q17-pad2_ net-_d11-pad2_ net-_q18-pad2_ Q2N2222
+q17 net-_q17-pad1_ net-_q17-pad2_ net-_d9-pad1_ Q2N2222
+r17 net-_r1-pad1_ net-_q17-pad2_ 1.6k
+r15 net-_r1-pad1_ net-_q17-pad1_ 130
+d13 gndpwr net-_d13-pad2_ 1N4148
+d15 gndpwr net-_d15-pad2_ 1N4148
+r21 net-_q23-pad2_ gndpwr 1k
+r18 net-_q18-pad2_ gndpwr 1k
+d9 net-_d9-pad1_ net-_d9-pad2_ 1N4148
+q18 net-_d9-pad2_ net-_q18-pad2_ gndpwr Q2N2222
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad2_ Q2N2222
+q2 net-_q2-pad1_ net-_q2-pad2_ net-_d3-pad2_ Q2N2222
+q5 net-_d5-pad1_ net-_q1-pad1_ net-_q5-pad3_ Q2N2222
+q6 net-_d5-pad1_ net-_q2-pad1_ net-_q5-pad3_ Q2N2222
+d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148
+r1 net-_r1-pad1_ net-_q1-pad2_ 4k
+r3 net-_r1-pad1_ net-_q2-pad2_ 2k
+r5 net-_r1-pad1_ net-_d5-pad1_ 2.5k
+q9 net-_d5-pad2_ net-_q5-pad3_ gndpwr Q2N2222
+q11 net-_q11-pad1_ net-_d5-pad2_ net-_q11-pad3_ Q2N2222
+q13 net-_q13-pad1_ net-_q11-pad1_ net-_d7-pad1_ Q2N2222
+r9 net-_r1-pad1_ net-_q11-pad1_ 1.6k
+r13 net-_r1-pad1_ net-_q13-pad1_ 130
+d3 gndpwr net-_d3-pad2_ 1N4148
+d1 gndpwr net-_d1-pad2_ 1N4148
+r6 net-_q5-pad3_ gndpwr 1k
+r10 net-_q11-pad3_ gndpwr 1k
+d7 net-_d7-pad1_ net-_d7-pad2_ 1N4148
+q14 net-_d7-pad2_ net-_q11-pad3_ gndpwr Q2N2222
+q31 net-_q27-pad2_ net-_q31-pad2_ net-_d16-pad2_ Q2N2222
+q32 net-_q28-pad2_ net-_q32-pad2_ net-_d14-pad2_ Q2N2222
+q27 net-_d12-pad1_ net-_q27-pad2_ net-_q24-pad2_ Q2N2222
+q28 net-_d12-pad1_ net-_q28-pad2_ net-_q24-pad2_ Q2N2222
+d12 net-_d12-pad1_ net-_d12-pad2_ 1N4148
+r28 net-_r1-pad1_ net-_q31-pad2_ 4k
+r26 net-_r1-pad1_ net-_q32-pad2_ 2k
+r24 net-_r1-pad1_ net-_d12-pad1_ 2.5k
+q24 net-_d12-pad2_ net-_q24-pad2_ gndpwr Q2N2222
+q22 net-_q19-pad2_ net-_d12-pad2_ net-_q20-pad2_ Q2N2222
+q19 net-_q19-pad1_ net-_q19-pad2_ net-_d10-pad1_ Q2N2222
+r19 net-_r1-pad1_ net-_q19-pad2_ 1.6k
+r16 net-_r1-pad1_ net-_q19-pad1_ 130
+d14 gndpwr net-_d14-pad2_ 1N4148
+d16 gndpwr net-_d16-pad2_ 1N4148
+r23 net-_q24-pad2_ gndpwr 1k
+r20 net-_q20-pad2_ gndpwr 1k
+d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148
+q20 net-_d10-pad2_ net-_q20-pad2_ gndpwr Q2N2222
+* Control Statements
+
+.ends SN7432_Subcirrcuit
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml new file mode 100644 index 00000000..40f426fc --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/SN7432_Subcirrcuit_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q29><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q29><q30><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q30><q25><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q26><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><d11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><q23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q23><q21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q21><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><d13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d13><d15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d15><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q31><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31><q32><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q32><q27><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q28><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q28><d12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><d14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d14><d16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d16><d10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><q20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN7432/analysis b/library/SubcircuitLibrary/SN7432/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN7432/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and-cache.lib b/library/SubcircuitLibrary/SN74351/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir b/library/SubcircuitLibrary/SN74351/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir.out b/library/SubcircuitLibrary/SN74351/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.pro b/library/SubcircuitLibrary/SN74351/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74351/3_and.sch b/library/SubcircuitLibrary/SN74351/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/3_and.sub b/library/SubcircuitLibrary/SN74351/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and-cache.lib b/library/SubcircuitLibrary/SN74351/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and-rescue.lib b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir b/library/SubcircuitLibrary/SN74351/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir.out b/library/SubcircuitLibrary/SN74351/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.pro b/library/SubcircuitLibrary/SN74351/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/5_and.sch b/library/SubcircuitLibrary/SN74351/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/5_and.sub b/library/SubcircuitLibrary/SN74351/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351-cache.lib b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib new file mode 100644 index 00000000..212e1ab7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir b/library/SubcircuitLibrary/SN74351/SN74351.cir new file mode 100644 index 00000000..f13d0354 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN74351\SN74351.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 22:36:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad6_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad1_ 5_and +X2 Net-_U1-Pad7_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad2_ 5_and +X3 Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad1_ 5_and +X4 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad2_ 5_and +X5 Net-_U1-Pad14_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad1_ 5_and +X6 Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad2_ 5_and +X7 Net-_U1-Pad12_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad1_ 5_and +X8 Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad2_ 5_and +X9 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad11_ Net-_U8-Pad1_ 5_and +X10 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U1-Pad12_ Net-_U8-Pad2_ 5_and +X11 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad13_ Net-_U10-Pad1_ 5_and +X12 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U10-Pad2_ 5_and +X13 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad15_ Net-_U12-Pad1_ 5_and +X14 Net-_U20-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad16_ Net-_U12-Pad2_ 5_and +X15 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad17_ Net-_U13-Pad1_ 5_and +X16 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad18_ Net-_U13-Pad2_ 5_and +U5 Net-_U1-Pad2_ Net-_U20-Pad1_ d_inverter +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad4_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad1_ d_and +U21 Net-_U20-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad19_ d_and +U18 Net-_U14-Pad3_ Net-_U16-Pad3_ Net-_U18-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U16-Pad1_ d_or +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U14-Pad2_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U14-Pad1_ d_or +U19 Net-_U15-Pad3_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_or +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U15-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U21-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir.out b/library/SubcircuitLibrary/SN74351/SN74351.cir.out new file mode 100644 index 00000000..07b597bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir.out @@ -0,0 +1,117 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir + +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.pro b/library/SubcircuitLibrary/SN74351/SN74351.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sch b/library/SubcircuitLibrary/SN74351/SN74351.sch new file mode 100644 index 00000000..1d50e5b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sch @@ -0,0 +1,1192 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN74351-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 5_and X1 +U 1 1 6795B96A +P 13150 2950 +F 0 "X1" H 13200 2850 60 0000 C CNN +F 1 "5_and" H 13250 3100 60 0000 C CNN +F 2 "" H 13150 2950 60 0000 C CNN +F 3 "" H 13150 2950 60 0000 C CNN + 1 13150 2950 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X2 +U 1 1 6795BA47 +P 13150 3650 +F 0 "X2" H 13200 3550 60 0000 C CNN +F 1 "5_and" H 13250 3800 60 0000 C CNN +F 2 "" H 13150 3650 60 0000 C CNN +F 3 "" H 13150 3650 60 0000 C CNN + 1 13150 3650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X3 +U 1 1 6795BAAC +P 13150 4350 +F 0 "X3" H 13200 4250 60 0000 C CNN +F 1 "5_and" H 13250 4500 60 0000 C CNN +F 2 "" H 13150 4350 60 0000 C CNN +F 3 "" H 13150 4350 60 0000 C CNN + 1 13150 4350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X4 +U 1 1 6795BAB2 +P 13150 5050 +F 0 "X4" H 13200 4950 60 0000 C CNN +F 1 "5_and" H 13250 5200 60 0000 C CNN +F 2 "" H 13150 5050 60 0000 C CNN +F 3 "" H 13150 5050 60 0000 C CNN + 1 13150 5050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X5 +U 1 1 6795BB3C +P 13150 5750 +F 0 "X5" H 13200 5650 60 0000 C CNN +F 1 "5_and" H 13250 5900 60 0000 C CNN +F 2 "" H 13150 5750 60 0000 C CNN +F 3 "" H 13150 5750 60 0000 C CNN + 1 13150 5750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X6 +U 1 1 6795BB42 +P 13150 6450 +F 0 "X6" H 13200 6350 60 0000 C CNN +F 1 "5_and" H 13250 6600 60 0000 C CNN +F 2 "" H 13150 6450 60 0000 C CNN +F 3 "" H 13150 6450 60 0000 C CNN + 1 13150 6450 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X7 +U 1 1 6795BB48 +P 13150 7150 +F 0 "X7" H 13200 7050 60 0000 C CNN +F 1 "5_and" H 13250 7300 60 0000 C CNN +F 2 "" H 13150 7150 60 0000 C CNN +F 3 "" H 13150 7150 60 0000 C CNN + 1 13150 7150 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X8 +U 1 1 6795BB4E +P 13150 7850 +F 0 "X8" H 13200 7750 60 0000 C CNN +F 1 "5_and" H 13250 8000 60 0000 C CNN +F 2 "" H 13150 7850 60 0000 C CNN +F 3 "" H 13150 7850 60 0000 C CNN + 1 13150 7850 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X9 +U 1 1 6795C4A6 +P 13200 9650 +F 0 "X9" H 13250 9550 60 0000 C CNN +F 1 "5_and" H 13300 9800 60 0000 C CNN +F 2 "" H 13200 9650 60 0000 C CNN +F 3 "" H 13200 9650 60 0000 C CNN + 1 13200 9650 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X10 +U 1 1 6795C4AC +P 13200 10350 +F 0 "X10" H 13250 10250 60 0000 C CNN +F 1 "5_and" H 13300 10500 60 0000 C CNN +F 2 "" H 13200 10350 60 0000 C CNN +F 3 "" H 13200 10350 60 0000 C CNN + 1 13200 10350 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X11 +U 1 1 6795C4B2 +P 13200 11050 +F 0 "X11" H 13250 10950 60 0000 C CNN +F 1 "5_and" H 13300 11200 60 0000 C CNN +F 2 "" H 13200 11050 60 0000 C CNN +F 3 "" H 13200 11050 60 0000 C CNN + 1 13200 11050 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X12 +U 1 1 6795C4B8 +P 13200 11750 +F 0 "X12" H 13250 11650 60 0000 C CNN +F 1 "5_and" H 13300 11900 60 0000 C CNN +F 2 "" H 13200 11750 60 0000 C CNN +F 3 "" H 13200 11750 60 0000 C CNN + 1 13200 11750 + 1 0 0 -1 +$EndComp +$Comp +L 5_and X13 +U 1 1 6795C4BE +P 13200 12450 +F 0 "X13" H 13250 12350 60 0000 C CNN +F 1 "5_and" H 13300 12600 60 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+Wire Wire Line + 17800 5400 17950 5400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sub b/library/SubcircuitLibrary/SN74351/SN74351.sub new file mode 100644 index 00000000..87054221 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sub @@ -0,0 +1,111 @@ +* Subcircuit SN74351 +.subckt SN74351 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends SN74351
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml new file mode 100644 index 00000000..77e9ef56 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u16><u14 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u6><u20 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u14 name="type">d_or<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u11 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u11><u9 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u9><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u6><u19 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u19><u17 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u15 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u15><u8 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u23></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/analysis b/library/SubcircuitLibrary/SN74351/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/D.lib b/library/SubcircuitLibrary/SN74LS00/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..68e79d37 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:38:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 130 +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 1k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..51032802 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..223fa915 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "4k" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "1.6k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "130" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "1k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..1a1d27ee --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NPN.lib b/library/SubcircuitLibrary/SN74LS00/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib new file mode 100644 index 00000000..37b0e2e1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib @@ -0,0 +1,60 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir new file mode 100644 index 00000000..4b046591 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS00\SN74LS00.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:31:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad14_ Nand_gate_final +X3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad14_ Nand_gate_final +X2 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ Net-_U1-Pad14_ Nand_gate_final +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad14_ Nand_gate_final +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out new file mode 100644 index 00000000..15fe255d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir + +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch new file mode 100644 index 00000000..8371e33e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch @@ -0,0 +1,304 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Nand_gate_final X1 +U 1 1 67705EB8 +P 4400 3550 +F 0 "X1" H 4400 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 3450 60 0000 C CNN +F 2 "" H 4400 3550 60 0001 C CNN +F 3 "" H 4400 3550 60 0001 C CNN + 1 4400 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X3 +U 1 1 67705EE5 +P 6950 3550 +F 0 "X3" H 6950 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 7000 3450 60 0000 C CNN +F 2 "" H 6950 3550 60 0001 C CNN +F 3 "" H 6950 3550 60 0001 C CNN + 1 6950 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X2 +U 1 1 67705EFE +P 4400 5100 +F 0 "X2" H 4400 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 5000 60 0000 C CNN +F 2 "" H 4400 5100 60 0001 C CNN +F 3 "" H 4400 5100 60 0001 C CNN + 1 4400 5100 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X4 +U 1 1 67705F23 +P 7050 5100 +F 0 "X4" H 7050 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 7100 5000 60 0000 C CNN +F 2 "" H 7050 5100 60 0001 C CNN +F 3 "" H 7050 5100 60 0001 C CNN + 1 7050 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 3050 6700 3050 +Connection ~ 4150 3050 +Wire Wire Line + 4150 4600 2900 4600 +Wire Wire Line + 2900 4600 2900 3050 +Connection ~ 2900 3050 +Wire Wire Line + 6800 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 3050 +Connection ~ 5550 3050 +Wire Wire Line + 3700 4950 3200 4950 +Wire Wire Line + 3200 4950 3200 5450 +Wire Wire Line + 3700 5250 3700 5500 +Wire Wire Line + 5200 5100 5200 5500 +Wire Wire Line + 5200 5500 5250 5500 +Wire Wire Line + 7850 5100 7850 5650 +Wire Wire Line + 7850 5650 7900 5650 +Wire Wire Line + 6350 5250 6350 5600 +Wire Wire Line + 6350 4950 6100 4950 +Wire Wire Line + 6100 4950 6100 5600 +Wire Wire Line + 6250 3700 6250 4050 +Wire Wire Line + 6250 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 4050 +Wire Wire Line + 7750 3550 7750 4000 +Wire Wire Line + 5200 3550 5200 4000 +Wire Wire Line + 3700 3700 3700 4100 +Wire Wire Line + 3700 3400 3400 3400 +Wire Wire Line + 3400 3400 3400 4100 +$Comp +L PORT U1 +U 2 1 6770609D +P 3700 4350 +F 0 "U1" H 3750 4450 30 0000 C CNN +F 1 "PORT" H 3700 4350 30 0000 C CNN +F 2 "" H 3700 4350 60 0000 C CNN +F 3 "" H 3700 4350 60 0000 C CNN + 2 3700 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677060F9 +P 5200 4250 +F 0 "U1" H 5250 4350 30 0000 C CNN +F 1 "PORT" H 5200 4250 30 0000 C CNN +F 2 "" H 5200 4250 60 0000 C CNN +F 3 "" H 5200 4250 60 0000 C CNN + 3 5200 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6770612A +P 6250 4300 +F 0 "U1" H 6300 4400 30 0000 C CNN +F 1 "PORT" H 6250 4300 30 0000 C CNN +F 2 "" H 6250 4300 60 0000 C CNN +F 3 "" H 6250 4300 60 0000 C CNN + 5 6250 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 67706169 +P 7250 4550 +F 0 "U1" H 7300 4650 30 0000 C CNN +F 1 "PORT" H 7250 4550 30 0000 C CNN +F 2 "" H 7250 4550 60 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 7 7250 4550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 677061B0 +P 3700 5750 +F 0 "U1" H 3750 5850 30 0000 C CNN +F 1 "PORT" H 3700 5750 30 0000 C CNN +F 2 "" H 3700 5750 60 0000 C CNN +F 3 "" H 3700 5750 60 0000 C CNN + 9 3700 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 677061E9 +P 7900 5900 +F 0 "U1" H 7950 6000 30 0000 C CNN +F 1 "PORT" H 7900 5900 30 0000 C CNN +F 2 "" H 7900 5900 60 0000 C CNN +F 3 "" H 7900 5900 60 0000 C CNN + 11 7900 5900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 677062AC +P 5250 5750 +F 0 "U1" H 5300 5850 30 0000 C CNN +F 1 "PORT" H 5250 5750 30 0000 C CNN +F 2 "" H 5250 5750 60 0000 C CNN +F 3 "" H 5250 5750 60 0000 C CNN + 8 5250 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 677062E7 +P 3200 5700 +F 0 "U1" H 3250 5800 30 0000 C CNN +F 1 "PORT" H 3200 5700 30 0000 C CNN +F 2 "" H 3200 5700 60 0000 C CNN +F 3 "" H 3200 5700 60 0000 C CNN + 10 3200 5700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 67706324 +P 6350 5850 +F 0 "U1" H 6400 5950 30 0000 C CNN +F 1 "PORT" H 6350 5850 30 0000 C CNN +F 2 "" H 6350 5850 60 0000 C CNN +F 3 "" H 6350 5850 60 0000 C CNN + 12 6350 5850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 67706363 +P 7750 4250 +F 0 "U1" H 7800 4350 30 0000 C CNN +F 1 "PORT" H 7750 4250 30 0000 C CNN +F 2 "" H 7750 4250 60 0000 C CNN +F 3 "" H 7750 4250 60 0000 C CNN + 6 7750 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 677063A4 +P 6000 4300 +F 0 "U1" H 6050 4400 30 0000 C CNN +F 1 "PORT" H 6000 4300 30 0000 C CNN +F 2 "" H 6000 4300 60 0000 C CNN +F 3 "" H 6000 4300 60 0000 C CNN + 4 6000 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 677063EF +P 3400 4350 +F 0 "U1" H 3450 4450 30 0000 C CNN +F 1 "PORT" H 3400 4350 30 0000 C CNN +F 2 "" H 3400 4350 60 0000 C CNN +F 3 "" H 3400 4350 60 0000 C CNN + 1 3400 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6770A61C +P 2500 3300 +F 0 "U1" H 2550 3400 30 0000 C CNN +F 1 "PORT" H 2500 3300 30 0000 C CNN +F 2 "" H 2500 3300 60 0000 C CNN +F 3 "" H 2500 3300 60 0000 C CNN + 14 2500 3300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6770A667 +P 6100 5850 +F 0 "U1" H 6150 5950 30 0000 C CNN +F 1 "PORT" H 6100 5850 30 0000 C CNN +F 2 "" H 6100 5850 60 0000 C CNN +F 3 "" H 6100 5850 60 0000 C CNN + 13 6100 5850 + 0 -1 -1 0 +$EndComp +NoConn ~ 7250 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub new file mode 100644 index 00000000..2ec1904f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub @@ -0,0 +1,11 @@ +* Subcircuit SN74LS00 +.subckt SN74LS00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* Control Statements + +.ends SN74LS00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml new file mode 100644 index 00000000..a24d9a30 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/analysis b/library/SubcircuitLibrary/SN74LS00/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS11/D.lib b/library/SubcircuitLibrary/SN74LS11/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74LS11/NPN.lib b/library/SubcircuitLibrary/SN74LS11/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib new file mode 100644 index 00000000..0d1f2ae8 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11-cache.lib @@ -0,0 +1,164 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GNDPWR
+#
+DEF GNDPWR #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -200 50 H I C CNN
+F1 "GNDPWR" 0 -130 50 H V C CNN
+F2 "" 0 -50 50 H I C CNN
+F3 "" 0 -50 50 H I C CNN
+DRAW
+P 2 0 1 0 0 -50 0 0 N
+P 3 0 1 8 -40 -50 -50 -80 -50 -80 N
+P 3 0 1 8 -20 -50 -30 -80 -30 -80 N
+P 3 0 1 8 0 -50 -10 -80 -10 -80 N
+P 3 0 1 8 20 -50 10 -80 10 -80 N
+P 3 0 1 8 40 -50 -40 -50 -40 -50 N
+P 4 0 1 8 40 -50 30 -80 30 -80 30 -80 N
+X GNDPWR 1 0 0 0 U 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_CP1
+#
+DEF eSim_CP1 C 0 10 N N 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_CP1" 25 -100 50 H V L CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+ALIAS capacitor_polarised
+$FPLIST
+ CP_*
+$ENDFPLIST
+DRAW
+A 0 -150 128 1287 513 0 1 20 N -80 -50 80 -50
+P 2 0 1 20 -80 30 80 30 N
+P 2 0 1 0 -70 90 -30 90 N
+P 2 0 1 0 -50 70 -50 110 N
+X ~ 1 0 150 110 D 50 50 1 1 P
+X ~ 2 0 -150 130 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# zener
+#
+DEF zener U 0 40 Y Y 1 F N
+F0 "U" -50 -100 60 H V C CNN
+F1 "zener" 0 100 60 H V C CNN
+F2 "" 50 0 60 H V C CNN
+F3 "" 50 0 60 H V C CNN
+DRAW
+P 2 0 1 0 100 -50 50 -100 N
+P 2 0 1 0 100 50 100 -50 N
+P 2 0 1 0 100 50 150 100 N
+P 4 0 1 0 0 50 0 -50 100 0 0 50 N
+X ~ IN -200 0 200 R 50 43 1 1 I
+X ~ OUT 300 0 200 L 50 43 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir new file mode 100644 index 00000000..e049f6b4 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir @@ -0,0 +1,77 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\Subcircuit_SN74LS11\Subcircuit_SN74LS11.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/10/25 19:11:48
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 20k
+R2 Net-_R1-Pad1_ Net-_Q1-Pad1_ 10k
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D1-Pad1_ eSim_NPN
+Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_C1-Pad1_ eSim_NPN
+Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q4-Pad3_ eSim_NPN
+R4 Net-_R1-Pad1_ Net-_Q2-Pad1_ 8k
+R7 Net-_R1-Pad1_ Net-_Q4-Pad1_ 120
+U2 GNDPWR Net-_U1-Pad1_ zener
+U3 GNDPWR Net-_U1-Pad2_ zener
+U4 GNDPWR Net-_U1-Pad3_ zener
+U7 Net-_Q1-Pad2_ Net-_U1-Pad3_ zener
+U6 Net-_Q1-Pad2_ Net-_U1-Pad2_ zener
+D1 Net-_D1-Pad1_ GNDPWR eSim_Diode
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10pF
+R3 Net-_C1-Pad1_ Net-_Q3-Pad2_ 1.5k
+R5 Net-_C1-Pad1_ Net-_Q3-Pad1_ 3k
+Q3 Net-_Q3-Pad1_ Net-_Q3-Pad2_ GNDPWR eSim_NPN
+Q6 Net-_C1-Pad2_ Net-_C1-Pad1_ GNDPWR eSim_NPN
+U9 Net-_R6-Pad2_ Net-_Q2-Pad1_ zener
+R6 Net-_C1-Pad2_ Net-_R6-Pad2_ 5k
+Q5 Net-_Q4-Pad1_ Net-_Q4-Pad3_ Net-_C1-Pad2_ eSim_NPN
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_C1-Pad2_ Net-_R1-Pad1_ GNDPWR Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_C2-Pad2_ Net-_C3-Pad2_ PORT
+U5 Net-_Q1-Pad2_ Net-_U1-Pad1_ zener
+R15 Net-_R1-Pad1_ Net-_Q13-Pad2_ 20k
+R16 Net-_R1-Pad1_ Net-_Q13-Pad1_ 10k
+Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_D3-Pad1_ eSim_NPN
+Q14 Net-_Q14-Pad1_ Net-_Q13-Pad1_ Net-_C3-Pad1_ eSim_NPN
+Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_Q16-Pad3_ eSim_NPN
+R18 Net-_R1-Pad1_ Net-_Q14-Pad1_ 8k
+R21 Net-_R1-Pad1_ Net-_Q16-Pad1_ 120
+U16 GNDPWR Net-_U1-Pad10_ zener
+U17 GNDPWR Net-_U1-Pad11_ zener
+U18 GNDPWR Net-_U1-Pad12_ zener
+U21 Net-_Q13-Pad2_ Net-_U1-Pad12_ zener
+U20 Net-_Q13-Pad2_ Net-_U1-Pad11_ zener
+D3 Net-_D3-Pad1_ GNDPWR eSim_Diode
+C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10pF
+R17 Net-_C3-Pad1_ Net-_Q15-Pad2_ 1.5k
+R19 Net-_C3-Pad1_ Net-_Q15-Pad1_ 3k
+Q15 Net-_Q15-Pad1_ Net-_Q15-Pad2_ GNDPWR eSim_NPN
+Q18 Net-_C3-Pad2_ Net-_C3-Pad1_ GNDPWR eSim_NPN
+U22 Net-_R20-Pad2_ Net-_Q14-Pad1_ zener
+R20 Net-_C3-Pad2_ Net-_R20-Pad2_ 5k
+Q17 Net-_Q16-Pad1_ Net-_Q16-Pad3_ Net-_C3-Pad2_ eSim_NPN
+U19 Net-_Q13-Pad2_ Net-_U1-Pad10_ zener
+R8 Net-_R1-Pad1_ Net-_Q7-Pad2_ 20k
+R9 Net-_R1-Pad1_ Net-_Q7-Pad1_ 10k
+Q7 Net-_Q7-Pad1_ Net-_Q7-Pad2_ Net-_D2-Pad1_ eSim_NPN
+Q8 Net-_Q10-Pad2_ Net-_Q7-Pad1_ Net-_C2-Pad1_ eSim_NPN
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN
+R11 Net-_R1-Pad1_ Net-_Q10-Pad2_ 8k
+R14 Net-_R1-Pad1_ Net-_Q10-Pad1_ 120
+U8 GNDPWR Net-_U1-Pad4_ zener
+U10 GNDPWR Net-_U1-Pad5_ zener
+U11 GNDPWR Net-_U1-Pad6_ zener
+U14 Net-_Q7-Pad2_ Net-_U1-Pad6_ zener
+U13 Net-_Q7-Pad2_ Net-_U1-Pad5_ zener
+D2 Net-_D2-Pad1_ GNDPWR eSim_Diode
+C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10pF
+R10 Net-_C2-Pad1_ Net-_Q9-Pad2_ 1.5k
+R12 Net-_C2-Pad1_ Net-_Q9-Pad1_ 3k
+Q9 Net-_Q9-Pad1_ Net-_Q9-Pad2_ GNDPWR eSim_NPN
+Q12 Net-_C2-Pad2_ Net-_C2-Pad1_ GNDPWR eSim_NPN
+U15 Net-_R13-Pad2_ Net-_Q10-Pad2_ zener
+R13 Net-_C2-Pad2_ Net-_R13-Pad2_ 5k
+Q11 Net-_Q10-Pad1_ Net-_Q10-Pad3_ Net-_C2-Pad2_ eSim_NPN
+U12 Net-_Q7-Pad2_ Net-_U1-Pad4_ zener
+
+.end
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out new file mode 100644 index 00000000..a8250b0d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.cir.out @@ -0,0 +1,143 @@ +* c:\fossee\esim\library\subcircuitlibrary\subcircuit_sn74ls11\subcircuit_sn74ls11.cir
+
+.include D.lib
+.include NPN.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 20k
+r2 net-_r1-pad1_ net-_q1-pad1_ 10k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+r4 net-_r1-pad1_ net-_q2-pad1_ 8k
+r7 net-_r1-pad1_ net-_q4-pad1_ 120
+* u2 gndpwr net-_u1-pad1_ zener
+* u3 gndpwr net-_u1-pad2_ zener
+* u4 gndpwr net-_u1-pad3_ zener
+* u7 net-_q1-pad2_ net-_u1-pad3_ zener
+* u6 net-_q1-pad2_ net-_u1-pad2_ zener
+d1 net-_d1-pad1_ gndpwr 1N4148
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r3 net-_c1-pad1_ net-_q3-pad2_ 1.5k
+r5 net-_c1-pad1_ net-_q3-pad1_ 3k
+q3 net-_q3-pad1_ net-_q3-pad2_ gndpwr Q2N2222
+q6 net-_c1-pad2_ net-_c1-pad1_ gndpwr Q2N2222
+* u9 net-_r6-pad2_ net-_q2-pad1_ zener
+r6 net-_c1-pad2_ net-_r6-pad2_ 5k
+q5 net-_q4-pad1_ net-_q4-pad3_ net-_c1-pad2_ Q2N2222
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_r1-pad1_ gndpwr net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_c2-pad2_ net-_c3-pad2_ port
+* u5 net-_q1-pad2_ net-_u1-pad1_ zener
+r15 net-_r1-pad1_ net-_q13-pad2_ 20k
+r16 net-_r1-pad1_ net-_q13-pad1_ 10k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d3-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_c3-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_q16-pad3_ Q2N2222
+r18 net-_r1-pad1_ net-_q14-pad1_ 8k
+r21 net-_r1-pad1_ net-_q16-pad1_ 120
+* u16 gndpwr net-_u1-pad10_ zener
+* u17 gndpwr net-_u1-pad11_ zener
+* u18 gndpwr net-_u1-pad12_ zener
+* u21 net-_q13-pad2_ net-_u1-pad12_ zener
+* u20 net-_q13-pad2_ net-_u1-pad11_ zener
+d3 net-_d3-pad1_ gndpwr 1N4148
+c3 net-_c3-pad1_ net-_c3-pad2_ 10pf
+r17 net-_c3-pad1_ net-_q15-pad2_ 1.5k
+r19 net-_c3-pad1_ net-_q15-pad1_ 3k
+q15 net-_q15-pad1_ net-_q15-pad2_ gndpwr Q2N2222
+q18 net-_c3-pad2_ net-_c3-pad1_ gndpwr Q2N2222
+* u22 net-_r20-pad2_ net-_q14-pad1_ zener
+r20 net-_c3-pad2_ net-_r20-pad2_ 5k
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_c3-pad2_ Q2N2222
+* u19 net-_q13-pad2_ net-_u1-pad10_ zener
+r8 net-_r1-pad1_ net-_q7-pad2_ 20k
+r9 net-_r1-pad1_ net-_q7-pad1_ 10k
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d2-pad1_ Q2N2222
+q8 net-_q10-pad2_ net-_q7-pad1_ net-_c2-pad1_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r11 net-_r1-pad1_ net-_q10-pad2_ 8k
+r14 net-_r1-pad1_ net-_q10-pad1_ 120
+* u8 gndpwr net-_u1-pad4_ zener
+* u10 gndpwr net-_u1-pad5_ zener
+* u11 gndpwr net-_u1-pad6_ zener
+* u14 net-_q7-pad2_ net-_u1-pad6_ zener
+* u13 net-_q7-pad2_ net-_u1-pad5_ zener
+d2 net-_d2-pad1_ gndpwr 1N4148
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r10 net-_c2-pad1_ net-_q9-pad2_ 1.5k
+r12 net-_c2-pad1_ net-_q9-pad1_ 3k
+q9 net-_q9-pad1_ net-_q9-pad2_ gndpwr Q2N2222
+q12 net-_c2-pad2_ net-_c2-pad1_ gndpwr Q2N2222
+* u15 net-_r13-pad2_ net-_q10-pad2_ zener
+r13 net-_c2-pad2_ net-_r13-pad2_ 5k
+q11 net-_q10-pad1_ net-_q10-pad3_ net-_c2-pad2_ Q2N2222
+* u12 net-_q7-pad2_ net-_u1-pad4_ zener
+a1 gndpwr net-_u1-pad1_ u2
+a2 gndpwr net-_u1-pad2_ u3
+a3 gndpwr net-_u1-pad3_ u4
+a4 net-_q1-pad2_ net-_u1-pad3_ u7
+a5 net-_q1-pad2_ net-_u1-pad2_ u6
+a6 net-_r6-pad2_ net-_q2-pad1_ u9
+a7 net-_q1-pad2_ net-_u1-pad1_ u5
+a8 gndpwr net-_u1-pad10_ u16
+a9 gndpwr net-_u1-pad11_ u17
+a10 gndpwr net-_u1-pad12_ u18
+a11 net-_q13-pad2_ net-_u1-pad12_ u21
+a12 net-_q13-pad2_ net-_u1-pad11_ u20
+a13 net-_r20-pad2_ net-_q14-pad1_ u22
+a14 net-_q13-pad2_ net-_u1-pad10_ u19
+a15 gndpwr net-_u1-pad4_ u8
+a16 gndpwr net-_u1-pad5_ u10
+a17 gndpwr net-_u1-pad6_ u11
+a18 net-_q7-pad2_ net-_u1-pad6_ u14
+a19 net-_q7-pad2_ net-_u1-pad5_ u13
+a20 net-_r13-pad2_ net-_q10-pad2_ u15
+a21 net-_q7-pad2_ net-_u1-pad4_ u12
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u21 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u20 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u22 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch new file mode 100644 index 00000000..0247342b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sch @@ -0,0 +1,1351 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
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+ 1 1500 3170
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+$EndComp
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+ 1 1830 2390
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+F 3 "" H 3470 2690 50 0001 C CNN
+ 1 3470 2690
+ 0 -1 -1 0
+$EndComp
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+ 1 4260 1920
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+L eSim_NPN Q16
+U 1 1 67AA7C05
+P 9760 1940
+F 0 "Q16" H 9660 1990 50 0000 R CNN
+F 1 "eSim_NPN" H 9710 2090 50 0000 R CNN
+F 2 "" H 9960 2040 29 0000 C CNN
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+ 1 9760 1940
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R18
+U 1 1 67AA7C0B
+P 9400 1380
+F 0 "R18" H 9450 1510 50 0000 C CNN
+F 1 "8k" H 9450 1330 50 0000 C CNN
+F 2 "" H 9450 1360 30 0000 C CNN
+F 3 "" V 9450 1430 30 0000 C CNN
+ 1 9400 1380
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R21
+U 1 1 67AA7C11
+P 10570 1380
+F 0 "R21" H 10620 1510 50 0000 C CNN
+F 1 "120" H 10620 1330 50 0000 C CNN
+F 2 "" H 10620 1360 30 0000 C CNN
+F 3 "" V 10620 1430 30 0000 C CNN
+ 1 10570 1380
+ 0 1 1 0
+$EndComp
+$Comp
+L zener U16
+U 1 1 67AA7C17
+P 7280 3420
+F 0 "U16" H 7230 3320 60 0000 C CNN
+F 1 "zener" H 7280 3520 60 0000 C CNN
+F 2 "" H 7330 3420 60 0000 C CNN
+F 3 "" H 7330 3420 60 0000 C CNN
+ 1 7280 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U17
+U 1 1 67AA7C1D
+P 7550 3420
+F 0 "U17" H 7500 3320 60 0000 C CNN
+F 1 "zener" H 7550 3520 60 0000 C CNN
+F 2 "" H 7600 3420 60 0000 C CNN
+F 3 "" H 7600 3420 60 0000 C CNN
+ 1 7550 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U18
+U 1 1 67AA7C23
+P 7760 3420
+F 0 "U18" H 7710 3320 60 0000 C CNN
+F 1 "zener" H 7760 3520 60 0000 C CNN
+F 2 "" H 7810 3420 60 0000 C CNN
+F 3 "" H 7810 3420 60 0000 C CNN
+ 1 7760 3420
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U21
+U 1 1 67AA7C29
+P 8090 2640
+F 0 "U21" H 8040 2540 60 0000 C CNN
+F 1 "zener" H 8090 2740 60 0000 C CNN
+F 2 "" H 8140 2640 60 0000 C CNN
+F 3 "" H 8140 2640 60 0000 C CNN
+ 1 8090 2640
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U20
+U 1 1 67AA7C2F
+P 8090 2390
+F 0 "U20" H 8040 2290 60 0000 C CNN
+F 1 "zener" H 8090 2490 60 0000 C CNN
+F 2 "" H 8140 2390 60 0000 C CNN
+F 3 "" H 8140 2390 60 0000 C CNN
+ 1 8090 2390
+ -1 0 0 1
+$EndComp
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+L eSim_Diode D3
+U 1 1 67AA7C35
+P 8810 3480
+F 0 "D3" H 8810 3580 50 0000 C CNN
+F 1 "eSim_Diode" H 8810 3380 50 0000 C CNN
+F 2 "" H 8810 3480 60 0000 C CNN
+F 3 "" H 8810 3480 60 0000 C CNN
+ 1 8810 3480
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor_polarised C3
+U 1 1 67AA7C3B
+P 9730 2940
+F 0 "C3" H 9755 3040 50 0000 L CNN
+F 1 "10pF" H 9755 2840 50 0000 L CNN
+F 2 "" H 9730 2940 50 0001 C CNN
+F 3 "" H 9730 2940 50 0001 C CNN
+ 1 9730 2940
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R17
+U 1 1 67AA7C41
+P 9140 3810
+F 0 "R17" H 9190 3940 50 0000 C CNN
+F 1 "1.5k" H 9190 3760 50 0000 C CNN
+F 2 "" H 9190 3790 30 0000 C CNN
+F 3 "" V 9190 3860 30 0000 C CNN
+ 1 9140 3810
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R19
+U 1 1 67AA7C47
+P 9680 3520
+F 0 "R19" H 9730 3650 50 0000 C CNN
+F 1 "3k" H 9730 3470 50 0000 C CNN
+F 2 "" H 9730 3500 30 0000 C CNN
+F 3 "" V 9730 3570 30 0000 C CNN
+ 1 9680 3520
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q15
+U 1 1 67AA7C4D
+P 9630 4080
+F 0 "Q15" H 9530 4130 50 0000 R CNN
+F 1 "eSim_NPN" H 9580 4230 50 0000 R CNN
+F 2 "" H 9830 4180 29 0000 C CNN
+F 3 "" H 9630 4080 60 0000 C CNN
+ 1 9630 4080
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q18
+U 1 1 67AA7C53
+P 10540 3370
+F 0 "Q18" H 10440 3420 50 0000 R CNN
+F 1 "eSim_NPN" H 10490 3520 50 0000 R CNN
+F 2 "" H 10740 3470 29 0000 C CNN
+F 3 "" H 10540 3370 60 0000 C CNN
+ 1 10540 3370
+ 1 0 0 -1
+$EndComp
+$Comp
+L zener U22
+U 1 1 67AA7C59
+P 9840 2600
+F 0 "U22" H 9790 2500 60 0000 C CNN
+F 1 "zener" H 9840 2700 60 0000 C CNN
+F 2 "" H 9890 2600 60 0000 C CNN
+F 3 "" H 9890 2600 60 0000 C CNN
+ 1 9840 2600
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R20
+U 1 1 67AA7C5F
+P 10400 2550
+F 0 "R20" H 10450 2680 50 0000 C CNN
+F 1 "5k" H 10450 2500 50 0000 C CNN
+F 2 "" H 10450 2530 30 0000 C CNN
+F 3 "" V 10450 2600 30 0000 C CNN
+ 1 10400 2550
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q17
+U 1 1 67AA7C65
+P 10520 2170
+F 0 "Q17" H 10420 2220 50 0000 R CNN
+F 1 "eSim_NPN" H 10470 2320 50 0000 R CNN
+F 2 "" H 10720 2270 29 0000 C CNN
+F 3 "" H 10520 2170 60 0000 C CNN
+ 1 10520 2170
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 67AA7C6B
+P 6890 2150
+F 0 "U1" H 6940 2250 30 0000 C CNN
+F 1 "PORT" H 6890 2150 30 0000 C CNN
+F 2 "" H 6890 2150 60 0000 C CNN
+F 3 "" H 6890 2150 60 0000 C CNN
+ 10 6890 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67AA7C71
+P 6890 2390
+F 0 "U1" H 6940 2490 30 0000 C CNN
+F 1 "PORT" H 6890 2390 30 0000 C CNN
+F 2 "" H 6890 2390 60 0000 C CNN
+F 3 "" H 6890 2390 60 0000 C CNN
+ 11 6890 2390
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 67AA7C77
+P 6890 2640
+F 0 "U1" H 6940 2740 30 0000 C CNN
+F 1 "PORT" H 6890 2640 30 0000 C CNN
+F 2 "" H 6890 2640 60 0000 C CNN
+F 3 "" H 6890 2640 60 0000 C CNN
+ 12 6890 2640
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 67AA7C7D
+P 11040 2600
+F 0 "U1" H 11090 2700 30 0000 C CNN
+F 1 "PORT" H 11040 2600 30 0000 C CNN
+F 2 "" H 11040 2600 60 0000 C CNN
+F 3 "" H 11040 2600 60 0000 C CNN
+ 14 11040 2600
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U19
+U 1 1 67AA7C83
+P 8090 2150
+F 0 "U19" H 8040 2050 60 0000 C CNN
+F 1 "zener" H 8090 2250 60 0000 C CNN
+F 2 "" H 8140 2150 60 0000 C CNN
+F 3 "" H 8140 2150 60 0000 C CNN
+ 1 8090 2150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7790 2390 7140 2390
+Wire Wire Line
+ 7790 2640 7140 2640
+Wire Wire Line
+ 8290 1570 8290 2810
+Wire Wire Line
+ 7790 2150 7140 2150
+Connection ~ 8290 2390
+Connection ~ 8290 2150
+Wire Wire Line
+ 8290 2810 8510 2810
+Connection ~ 8290 2640
+Wire Wire Line
+ 7760 3120 7760 2640
+Connection ~ 7760 2640
+Wire Wire Line
+ 7550 3120 7550 2390
+Connection ~ 7550 2390
+Wire Wire Line
+ 7280 3120 7280 2150
+Connection ~ 7280 2150
+$Comp
+L GNDPWR #PWR02
+U 1 1 67AA7C97
+P 10160 4410
+F 0 "#PWR02" H 10160 4210 50 0001 C CNN
+F 1 "GNDPWR" H 10160 4280 50 0000 C CNN
+F 2 "" H 10160 4360 50 0001 C CNN
+F 3 "" H 10160 4360 50 0001 C CNN
+ 1 10160 4410
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 10160 4410
+Wire Wire Line
+ 7550 4410 7550 3620
+Connection ~ 7760 4410
+Wire Wire Line
+ 7280 4410 7280 3620
+Connection ~ 7550 4410
+Wire Wire Line
+ 8810 3630 8810 4410
+Connection ~ 8810 4410
+Wire Wire Line
+ 8810 3010 8810 3330
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 8810 2390
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9450 1940
+Wire Wire Line
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+Wire Wire Line
+ 9330 2600 9330 1940
+Connection ~ 9330 1940
+Wire Wire Line
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+Wire Wire Line
+ 9190 2590 9190 3710
+Connection ~ 9190 2940
+Wire Wire Line
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+Connection ~ 9190 3370
+Wire Wire Line
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+Connection ~ 9730 3370
+Wire Wire Line
+ 9430 4080 9190 4080
+Wire Wire Line
+ 9190 4080 9190 4010
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 9730 4410
+Wire Wire Line
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+Wire Wire Line
+ 9860 2170 9860 2140
+Wire Wire Line
+ 10200 2600 10040 2600
+Wire Wire Line
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+Wire Wire Line
+ 10500 2600 10790 2600
+Connection ~ 10620 2600
+Wire Wire Line
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+Wire Wire Line
+ 10640 2660 10620 2660
+Wire Wire Line
+ 10620 1970 10620 1580
+Wire Wire Line
+ 10620 900 10620 1280
+Wire Wire Line
+ 10620 1160 8290 1160
+Wire Wire Line
+ 8290 1160 8290 1270
+Wire Wire Line
+ 8810 1270 8810 1160
+Connection ~ 8810 1160
+Wire Wire Line
+ 9450 1280 9450 1160
+Connection ~ 9450 1160
+Wire Wire Line
+ 9860 1740 10620 1740
+Connection ~ 10620 1740
+Wire Wire Line
+ 9880 2940 10640 2940
+Connection ~ 10640 2940
+$Comp
+L resistor R8
+U 1 1 67AA90A0
+P 4520 4430
+F 0 "R8" H 4570 4560 50 0000 C CNN
+F 1 "20k" H 4570 4380 50 0000 C CNN
+F 2 "" H 4570 4410 30 0000 C CNN
+F 3 "" V 4570 4480 30 0000 C CNN
+ 1 4520 4430
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R9
+U 1 1 67AA90A6
+P 5040 4430
+F 0 "R9" H 5090 4560 50 0000 C CNN
+F 1 "10k" H 5090 4380 50 0000 C CNN
+F 2 "" H 5090 4410 30 0000 C CNN
+F 3 "" V 5090 4480 30 0000 C CNN
+ 1 5040 4430
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q7
+U 1 1 67AA90AC
+P 4990 5870
+F 0 "Q7" H 4890 5920 50 0000 R CNN
+F 1 "eSim_NPN" H 4940 6020 50 0000 R CNN
+F 2 "" H 5190 5970 29 0000 C CNN
+F 3 "" H 4990 5870 60 0000 C CNN
+ 1 4990 5870
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q8
+U 1 1 67AA90B2
+P 5370 5450
+F 0 "Q8" H 5270 5500 50 0000 R CNN
+F 1 "eSim_NPN" H 5320 5600 50 0000 R CNN
+F 2 "" H 5570 5550 29 0000 C CNN
+F 3 "" H 5370 5450 60 0000 C CNN
+ 1 5370 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q10
+U 1 1 67AA90B8
+P 6040 5000
+F 0 "Q10" H 5940 5050 50 0000 R CNN
+F 1 "eSim_NPN" H 5990 5150 50 0000 R CNN
+F 2 "" H 6240 5100 29 0000 C CNN
+F 3 "" H 6040 5000 60 0000 C CNN
+ 1 6040 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 67AA90BE
+P 5680 4440
+F 0 "R11" H 5730 4570 50 0000 C CNN
+F 1 "8k" H 5730 4390 50 0000 C CNN
+F 2 "" H 5730 4420 30 0000 C CNN
+F 3 "" V 5730 4490 30 0000 C CNN
+ 1 5680 4440
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R14
+U 1 1 67AA90C4
+P 6850 4440
+F 0 "R14" H 6900 4570 50 0000 C CNN
+F 1 "120" H 6900 4390 50 0000 C CNN
+F 2 "" H 6900 4420 30 0000 C CNN
+F 3 "" V 6900 4490 30 0000 C CNN
+ 1 6850 4440
+ 0 1 1 0
+$EndComp
+$Comp
+L zener U8
+U 1 1 67AA90CA
+P 3560 6480
+F 0 "U8" H 3510 6380 60 0000 C CNN
+F 1 "zener" H 3560 6580 60 0000 C CNN
+F 2 "" H 3610 6480 60 0000 C CNN
+F 3 "" H 3610 6480 60 0000 C CNN
+ 1 3560 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U10
+U 1 1 67AA90D0
+P 3830 6480
+F 0 "U10" H 3780 6380 60 0000 C CNN
+F 1 "zener" H 3830 6580 60 0000 C CNN
+F 2 "" H 3880 6480 60 0000 C CNN
+F 3 "" H 3880 6480 60 0000 C CNN
+ 1 3830 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U11
+U 1 1 67AA90D6
+P 4040 6480
+F 0 "U11" H 3990 6380 60 0000 C CNN
+F 1 "zener" H 4040 6580 60 0000 C CNN
+F 2 "" H 4090 6480 60 0000 C CNN
+F 3 "" H 4090 6480 60 0000 C CNN
+ 1 4040 6480
+ 0 1 -1 0
+$EndComp
+$Comp
+L zener U14
+U 1 1 67AA90DC
+P 4370 5700
+F 0 "U14" H 4320 5600 60 0000 C CNN
+F 1 "zener" H 4370 5800 60 0000 C CNN
+F 2 "" H 4420 5700 60 0000 C CNN
+F 3 "" H 4420 5700 60 0000 C CNN
+ 1 4370 5700
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U13
+U 1 1 67AA90E2
+P 4370 5450
+F 0 "U13" H 4320 5350 60 0000 C CNN
+F 1 "zener" H 4370 5550 60 0000 C CNN
+F 2 "" H 4420 5450 60 0000 C CNN
+F 3 "" H 4420 5450 60 0000 C CNN
+ 1 4370 5450
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 67AA90E8
+P 5090 6540
+F 0 "D2" H 5090 6640 50 0000 C CNN
+F 1 "eSim_Diode" H 5090 6440 50 0000 C CNN
+F 2 "" H 5090 6540 60 0000 C CNN
+F 3 "" H 5090 6540 60 0000 C CNN
+ 1 5090 6540
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor_polarised C2
+U 1 1 67AA90EE
+P 6010 6000
+F 0 "C2" H 6035 6100 50 0000 L CNN
+F 1 "10pF" H 6035 5900 50 0000 L CNN
+F 2 "" H 6010 6000 50 0001 C CNN
+F 3 "" H 6010 6000 50 0001 C CNN
+ 1 6010 6000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L resistor R10
+U 1 1 67AA90F4
+P 5420 6870
+F 0 "R10" H 5470 7000 50 0000 C CNN
+F 1 "1.5k" H 5470 6820 50 0000 C CNN
+F 2 "" H 5470 6850 30 0000 C CNN
+F 3 "" V 5470 6920 30 0000 C CNN
+ 1 5420 6870
+ 0 1 1 0
+$EndComp
+$Comp
+L resistor R12
+U 1 1 67AA90FA
+P 5960 6580
+F 0 "R12" H 6010 6710 50 0000 C CNN
+F 1 "3k" H 6010 6530 50 0000 C CNN
+F 2 "" H 6010 6560 30 0000 C CNN
+F 3 "" V 6010 6630 30 0000 C CNN
+ 1 5960 6580
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_NPN Q9
+U 1 1 67AA9100
+P 5910 7140
+F 0 "Q9" H 5810 7190 50 0000 R CNN
+F 1 "eSim_NPN" H 5860 7290 50 0000 R CNN
+F 2 "" H 6110 7240 29 0000 C CNN
+F 3 "" H 5910 7140 60 0000 C CNN
+ 1 5910 7140
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q12
+U 1 1 67AA9106
+P 6820 6430
+F 0 "Q12" H 6720 6480 50 0000 R CNN
+F 1 "eSim_NPN" H 6770 6580 50 0000 R CNN
+F 2 "" H 7020 6530 29 0000 C CNN
+F 3 "" H 6820 6430 60 0000 C CNN
+ 1 6820 6430
+ 1 0 0 -1
+$EndComp
+$Comp
+L zener U15
+U 1 1 67AA910C
+P 6120 5660
+F 0 "U15" H 6070 5560 60 0000 C CNN
+F 1 "zener" H 6120 5760 60 0000 C CNN
+F 2 "" H 6170 5660 60 0000 C CNN
+F 3 "" H 6170 5660 60 0000 C CNN
+ 1 6120 5660
+ -1 0 0 1
+$EndComp
+$Comp
+L resistor R13
+U 1 1 67AA9112
+P 6680 5610
+F 0 "R13" H 6730 5740 50 0000 C CNN
+F 1 "5k" H 6730 5560 50 0000 C CNN
+F 2 "" H 6730 5590 30 0000 C CNN
+F 3 "" V 6730 5660 30 0000 C CNN
+ 1 6680 5610
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_NPN Q11
+U 1 1 67AA9118
+P 6800 5230
+F 0 "Q11" H 6700 5280 50 0000 R CNN
+F 1 "eSim_NPN" H 6750 5380 50 0000 R CNN
+F 2 "" H 7000 5330 29 0000 C CNN
+F 3 "" H 6800 5230 60 0000 C CNN
+ 1 6800 5230
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67AA911E
+P 3170 5210
+F 0 "U1" H 3220 5310 30 0000 C CNN
+F 1 "PORT" H 3170 5210 30 0000 C CNN
+F 2 "" H 3170 5210 60 0000 C CNN
+F 3 "" H 3170 5210 60 0000 C CNN
+ 4 3170 5210
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67AA9124
+P 3170 5450
+F 0 "U1" H 3220 5550 30 0000 C CNN
+F 1 "PORT" H 3170 5450 30 0000 C CNN
+F 2 "" H 3170 5450 60 0000 C CNN
+F 3 "" H 3170 5450 60 0000 C CNN
+ 5 3170 5450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67AA912A
+P 3170 5700
+F 0 "U1" H 3220 5800 30 0000 C CNN
+F 1 "PORT" H 3170 5700 30 0000 C CNN
+F 2 "" H 3170 5700 60 0000 C CNN
+F 3 "" H 3170 5700 60 0000 C CNN
+ 6 3170 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67AA9130
+P 7320 5660
+F 0 "U1" H 7370 5760 30 0000 C CNN
+F 1 "PORT" H 7320 5660 30 0000 C CNN
+F 2 "" H 7320 5660 60 0000 C CNN
+F 3 "" H 7320 5660 60 0000 C CNN
+ 13 7320 5660
+ -1 0 0 1
+$EndComp
+$Comp
+L zener U12
+U 1 1 67AA9136
+P 4370 5210
+F 0 "U12" H 4320 5110 60 0000 C CNN
+F 1 "zener" H 4370 5310 60 0000 C CNN
+F 2 "" H 4420 5210 60 0000 C CNN
+F 3 "" H 4420 5210 60 0000 C CNN
+ 1 4370 5210
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4070 5450 3420 5450
+Wire Wire Line
+ 4070 5700 3420 5700
+Wire Wire Line
+ 4570 4630 4570 5870
+Wire Wire Line
+ 4070 5210 3420 5210
+Connection ~ 4570 5450
+Connection ~ 4570 5210
+Wire Wire Line
+ 4570 5870 4790 5870
+Connection ~ 4570 5700
+Wire Wire Line
+ 4040 6180 4040 5700
+Connection ~ 4040 5700
+Wire Wire Line
+ 3830 6180 3830 5450
+Connection ~ 3830 5450
+Wire Wire Line
+ 3560 6180 3560 5210
+Connection ~ 3560 5210
+$Comp
+L GNDPWR #PWR03
+U 1 1 67AA914A
+P 6440 7470
+F 0 "#PWR03" H 6440 7270 50 0001 C CNN
+F 1 "GNDPWR" H 6440 7340 50 0000 C CNN
+F 2 "" H 6440 7420 50 0001 C CNN
+F 3 "" H 6440 7420 50 0001 C CNN
+ 1 6440 7470
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 6920 7470 6920 6630
+Wire Wire Line
+ 3560 7470 7600 7470
+Wire Wire Line
+ 4040 7470 4040 6680
+Connection ~ 6440 7470
+Wire Wire Line
+ 3830 7470 3830 6680
+Connection ~ 4040 7470
+Wire Wire Line
+ 3560 7470 3560 6680
+Connection ~ 3830 7470
+Wire Wire Line
+ 5090 6690 5090 7470
+Connection ~ 5090 7470
+Wire Wire Line
+ 5090 6070 5090 6390
+Wire Wire Line
+ 5170 5450 5090 5450
+Wire Wire Line
+ 5090 4630 5090 5670
+Connection ~ 5090 5450
+Wire Wire Line
+ 5470 5250 5470 5000
+Wire Wire Line
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+Wire Wire Line
+ 5730 4640 5730 5000
+Connection ~ 5730 5000
+Wire Wire Line
+ 5820 5660 5610 5660
+Wire Wire Line
+ 5610 5660 5610 5000
+Connection ~ 5610 5000
+Wire Wire Line
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+Wire Wire Line
+ 5470 5650 5470 6770
+Connection ~ 5470 6000
+Wire Wire Line
+ 6620 6430 5470 6430
+Connection ~ 5470 6430
+Wire Wire Line
+ 6010 6480 6010 6430
+Connection ~ 6010 6430
+Wire Wire Line
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+Wire Wire Line
+ 5470 7140 5470 7070
+Wire Wire Line
+ 6010 6780 6010 6940
+Wire Wire Line
+ 6010 7340 6010 7470
+Connection ~ 6010 7470
+Wire Wire Line
+ 6600 5230 6140 5230
+Wire Wire Line
+ 6140 5230 6140 5200
+Wire Wire Line
+ 6480 5660 6320 5660
+Wire Wire Line
+ 6900 5430 6900 5720
+Wire Wire Line
+ 6780 5660 7070 5660
+Connection ~ 6900 5660
+Wire Wire Line
+ 6920 6230 6920 5720
+Wire Wire Line
+ 6920 5720 6900 5720
+Wire Wire Line
+ 6900 5030 6900 4640
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 4570 4220 4570 4330
+Wire Wire Line
+ 5090 4330 5090 4220
+Connection ~ 5090 4220
+Wire Wire Line
+ 5730 4340 5730 4220
+Connection ~ 5730 4220
+Wire Wire Line
+ 6140 4800 6900 4800
+Connection ~ 6900 4800
+Wire Wire Line
+ 6160 6000 6920 6000
+Connection ~ 6920 6000
+$Comp
+L PORT U1
+U 8 1 67AAA48F
+P 5330 830
+F 0 "U1" H 5380 930 30 0000 C CNN
+F 1 "PORT" H 5330 830 30 0000 C CNN
+F 2 "" H 5330 830 60 0000 C CNN
+F 3 "" H 5330 830 60 0000 C CNN
+ 8 5330 830
+ 0 1 1 0
+$EndComp
+$Comp
+L PORT U1
+U 9 1 67AAA999
+P 5920 830
+F 0 "U1" H 5970 930 30 0000 C CNN
+F 1 "PORT" H 5920 830 30 0000 C CNN
+F 2 "" H 5920 830 60 0000 C CNN
+F 3 "" H 5920 830 60 0000 C CNN
+ 9 5920 830
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 5030 910 5030 1300
+Wire Wire Line
+ 5030 1300 5480 1300
+Wire Wire Line
+ 5330 1080 5330 3620
+Connection ~ 4360 910
+Wire Wire Line
+ 5330 3620 6900 3620
+Connection ~ 5330 1300
+Connection ~ 6900 4220
+Wire Wire Line
+ 10620 900 7960 900
+Wire Wire Line
+ 7960 900 7960 1750
+Wire Wire Line
+ 7960 1750 5480 1750
+Wire Wire Line
+ 5480 1750 5480 1300
+Connection ~ 10620 1160
+Wire Wire Line
+ 4520 4160 4520 3860
+Wire Wire Line
+ 4520 3860 5920 3860
+Wire Wire Line
+ 5920 3860 5920 1080
+Connection ~ 4380 4160
+Wire Wire Line
+ 10640 4750 7050 4750
+Wire Wire Line
+ 7050 4750 7050 2950
+Wire Wire Line
+ 7050 2950 5690 2950
+Connection ~ 5920 2950
+Connection ~ 10640 4410
+Wire Wire Line
+ 7600 7470 7600 4640
+Wire Wire Line
+ 7600 4640 7150 4640
+Wire Wire Line
+ 7150 4640 7150 2790
+Wire Wire Line
+ 7150 2790 5690 2790
+Wire Wire Line
+ 5690 2790 5690 2950
+Connection ~ 6920 7470
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub new file mode 100644 index 00000000..a2659577 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11.sub @@ -0,0 +1,137 @@ +* Subcircuit Subcircuit_SN74LS11
+.subckt Subcircuit_SN74LS11 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_c1-pad2_ net-_r1-pad1_ gndpwr net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_c2-pad2_ net-_c3-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\subcircuit_sn74ls11\subcircuit_sn74ls11.cir
+.include D.lib
+.include NPN.lib
+r1 net-_r1-pad1_ net-_q1-pad2_ 20k
+r2 net-_r1-pad1_ net-_q1-pad1_ 10k
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_d1-pad1_ Q2N2222
+q2 net-_q2-pad1_ net-_q1-pad1_ net-_c1-pad1_ Q2N2222
+q4 net-_q4-pad1_ net-_q2-pad1_ net-_q4-pad3_ Q2N2222
+r4 net-_r1-pad1_ net-_q2-pad1_ 8k
+r7 net-_r1-pad1_ net-_q4-pad1_ 120
+* u2 gndpwr net-_u1-pad1_ zener
+* u3 gndpwr net-_u1-pad2_ zener
+* u4 gndpwr net-_u1-pad3_ zener
+* u7 net-_q1-pad2_ net-_u1-pad3_ zener
+* u6 net-_q1-pad2_ net-_u1-pad2_ zener
+d1 net-_d1-pad1_ gndpwr 1N4148
+c1 net-_c1-pad1_ net-_c1-pad2_ 10pf
+r3 net-_c1-pad1_ net-_q3-pad2_ 1.5k
+r5 net-_c1-pad1_ net-_q3-pad1_ 3k
+q3 net-_q3-pad1_ net-_q3-pad2_ gndpwr Q2N2222
+q6 net-_c1-pad2_ net-_c1-pad1_ gndpwr Q2N2222
+* u9 net-_r6-pad2_ net-_q2-pad1_ zener
+r6 net-_c1-pad2_ net-_r6-pad2_ 5k
+q5 net-_q4-pad1_ net-_q4-pad3_ net-_c1-pad2_ Q2N2222
+* u5 net-_q1-pad2_ net-_u1-pad1_ zener
+r15 net-_r1-pad1_ net-_q13-pad2_ 20k
+r16 net-_r1-pad1_ net-_q13-pad1_ 10k
+q13 net-_q13-pad1_ net-_q13-pad2_ net-_d3-pad1_ Q2N2222
+q14 net-_q14-pad1_ net-_q13-pad1_ net-_c3-pad1_ Q2N2222
+q16 net-_q16-pad1_ net-_q14-pad1_ net-_q16-pad3_ Q2N2222
+r18 net-_r1-pad1_ net-_q14-pad1_ 8k
+r21 net-_r1-pad1_ net-_q16-pad1_ 120
+* u16 gndpwr net-_u1-pad10_ zener
+* u17 gndpwr net-_u1-pad11_ zener
+* u18 gndpwr net-_u1-pad12_ zener
+* u21 net-_q13-pad2_ net-_u1-pad12_ zener
+* u20 net-_q13-pad2_ net-_u1-pad11_ zener
+d3 net-_d3-pad1_ gndpwr 1N4148
+c3 net-_c3-pad1_ net-_c3-pad2_ 10pf
+r17 net-_c3-pad1_ net-_q15-pad2_ 1.5k
+r19 net-_c3-pad1_ net-_q15-pad1_ 3k
+q15 net-_q15-pad1_ net-_q15-pad2_ gndpwr Q2N2222
+q18 net-_c3-pad2_ net-_c3-pad1_ gndpwr Q2N2222
+* u22 net-_r20-pad2_ net-_q14-pad1_ zener
+r20 net-_c3-pad2_ net-_r20-pad2_ 5k
+q17 net-_q16-pad1_ net-_q16-pad3_ net-_c3-pad2_ Q2N2222
+* u19 net-_q13-pad2_ net-_u1-pad10_ zener
+r8 net-_r1-pad1_ net-_q7-pad2_ 20k
+r9 net-_r1-pad1_ net-_q7-pad1_ 10k
+q7 net-_q7-pad1_ net-_q7-pad2_ net-_d2-pad1_ Q2N2222
+q8 net-_q10-pad2_ net-_q7-pad1_ net-_c2-pad1_ Q2N2222
+q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222
+r11 net-_r1-pad1_ net-_q10-pad2_ 8k
+r14 net-_r1-pad1_ net-_q10-pad1_ 120
+* u8 gndpwr net-_u1-pad4_ zener
+* u10 gndpwr net-_u1-pad5_ zener
+* u11 gndpwr net-_u1-pad6_ zener
+* u14 net-_q7-pad2_ net-_u1-pad6_ zener
+* u13 net-_q7-pad2_ net-_u1-pad5_ zener
+d2 net-_d2-pad1_ gndpwr 1N4148
+c2 net-_c2-pad1_ net-_c2-pad2_ 10pf
+r10 net-_c2-pad1_ net-_q9-pad2_ 1.5k
+r12 net-_c2-pad1_ net-_q9-pad1_ 3k
+q9 net-_q9-pad1_ net-_q9-pad2_ gndpwr Q2N2222
+q12 net-_c2-pad2_ net-_c2-pad1_ gndpwr Q2N2222
+* u15 net-_r13-pad2_ net-_q10-pad2_ zener
+r13 net-_c2-pad2_ net-_r13-pad2_ 5k
+q11 net-_q10-pad1_ net-_q10-pad3_ net-_c2-pad2_ Q2N2222
+* u12 net-_q7-pad2_ net-_u1-pad4_ zener
+a1 gndpwr net-_u1-pad1_ u2
+a2 gndpwr net-_u1-pad2_ u3
+a3 gndpwr net-_u1-pad3_ u4
+a4 net-_q1-pad2_ net-_u1-pad3_ u7
+a5 net-_q1-pad2_ net-_u1-pad2_ u6
+a6 net-_r6-pad2_ net-_q2-pad1_ u9
+a7 net-_q1-pad2_ net-_u1-pad1_ u5
+a8 gndpwr net-_u1-pad10_ u16
+a9 gndpwr net-_u1-pad11_ u17
+a10 gndpwr net-_u1-pad12_ u18
+a11 net-_q13-pad2_ net-_u1-pad12_ u21
+a12 net-_q13-pad2_ net-_u1-pad11_ u20
+a13 net-_r20-pad2_ net-_q14-pad1_ u22
+a14 net-_q13-pad2_ net-_u1-pad10_ u19
+a15 gndpwr net-_u1-pad4_ u8
+a16 gndpwr net-_u1-pad5_ u10
+a17 gndpwr net-_u1-pad6_ u11
+a18 net-_q7-pad2_ net-_u1-pad6_ u14
+a19 net-_q7-pad2_ net-_u1-pad5_ u13
+a20 net-_r13-pad2_ net-_q10-pad2_ u15
+a21 net-_q7-pad2_ net-_u1-pad4_ u12
+* Schematic Name: zener, NgSpice Name: zener
+.model u2 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u4 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u7 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u6 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u9 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u5 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u16 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u17 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u18 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u21 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u20 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u22 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u19 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u8 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u10 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u11 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u14 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u13 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u15 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Schematic Name: zener, NgSpice Name: zener
+.model u12 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE )
+* Control Statements
+
+.ends Subcircuit_SN74LS11
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml new file mode 100644 index 00000000..088a27f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/Subcircuit_SN74LS11_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">zener<field1 name="Enter Breakdown Voltage (default=5.6)" /><field2 name="Enter Breakdown Current (default=2.0e-2)" /><field3 name="Enter Saturation Current (default=1.0e-12)" /><field4 name="Enter Forward Emission Coefficient (default=1.0)" /><field5 name="Enter Switch for Limiting (default=FALSE)" /></u2><u3 name="type">zener<field6 name="Enter Breakdown Voltage (default=5.6)" /><field7 name="Enter Breakdown Current (default=2.0e-2)" /><field8 name="Enter Saturation Current (default=1.0e-12)" /><field9 name="Enter Forward Emission Coefficient (default=1.0)" /><field10 name="Enter Switch for Limiting (default=FALSE)" /></u3><u4 name="type">zener<field11 name="Enter Breakdown Voltage (default=5.6)" /><field12 name="Enter Breakdown Current (default=2.0e-2)" /><field13 name="Enter Saturation Current (default=1.0e-12)" /><field14 name="Enter Forward Emission Coefficient (default=1.0)" /><field15 name="Enter Switch for Limiting (default=FALSE)" /></u4><u7 name="type">zener<field16 name="Enter Breakdown Voltage (default=5.6)" /><field17 name="Enter Breakdown Current (default=2.0e-2)" /><field18 name="Enter Saturation Current (default=1.0e-12)" /><field19 name="Enter Forward Emission Coefficient (default=1.0)" /><field20 name="Enter Switch for Limiting (default=FALSE)" /></u7><u6 name="type">zener<field21 name="Enter Breakdown Voltage (default=5.6)" /><field22 name="Enter Breakdown Current (default=2.0e-2)" /><field23 name="Enter Saturation Current (default=1.0e-12)" /><field24 name="Enter Forward Emission Coefficient (default=1.0)" /><field25 name="Enter Switch for Limiting (default=FALSE)" /></u6><u9 name="type">zener<field26 name="Enter Breakdown Voltage (default=5.6)" /><field27 name="Enter Breakdown Current (default=2.0e-2)" /><field28 name="Enter Saturation Current (default=1.0e-12)" /><field29 name="Enter Forward Emission Coefficient (default=1.0)" /><field30 name="Enter Switch for Limiting (default=FALSE)" /></u9><u5 name="type">zener<field31 name="Enter Breakdown Voltage (default=5.6)" /><field32 name="Enter Breakdown Current (default=2.0e-2)" /><field33 name="Enter Saturation Current (default=1.0e-12)" /><field34 name="Enter Forward Emission Coefficient (default=1.0)" /><field35 name="Enter Switch for Limiting (default=FALSE)" /></u5><u16 name="type">zener<field36 name="Enter Breakdown Voltage (default=5.6)" /><field37 name="Enter Breakdown Current (default=2.0e-2)" /><field38 name="Enter Saturation Current (default=1.0e-12)" /><field39 name="Enter Forward Emission Coefficient (default=1.0)" /><field40 name="Enter Switch for Limiting (default=FALSE)" /></u16><u17 name="type">zener<field41 name="Enter Breakdown Voltage (default=5.6)" /><field42 name="Enter Breakdown Current (default=2.0e-2)" /><field43 name="Enter Saturation Current (default=1.0e-12)" /><field44 name="Enter Forward Emission Coefficient (default=1.0)" /><field45 name="Enter Switch for Limiting (default=FALSE)" /></u17><u18 name="type">zener<field46 name="Enter Breakdown Voltage (default=5.6)" /><field47 name="Enter Breakdown Current (default=2.0e-2)" /><field48 name="Enter Saturation Current (default=1.0e-12)" /><field49 name="Enter Forward Emission Coefficient (default=1.0)" /><field50 name="Enter Switch for Limiting (default=FALSE)" /></u18><u21 name="type">zener<field51 name="Enter Breakdown Voltage (default=5.6)" /><field52 name="Enter Breakdown Current (default=2.0e-2)" /><field53 name="Enter Saturation Current (default=1.0e-12)" /><field54 name="Enter Forward Emission Coefficient (default=1.0)" /><field55 name="Enter Switch for Limiting (default=FALSE)" /></u21><u20 name="type">zener<field56 name="Enter Breakdown Voltage (default=5.6)" /><field57 name="Enter Breakdown Current (default=2.0e-2)" /><field58 name="Enter Saturation Current (default=1.0e-12)" /><field59 name="Enter Forward Emission Coefficient (default=1.0)" /><field60 name="Enter Switch for Limiting (default=FALSE)" /></u20><u22 name="type">zener<field61 name="Enter Breakdown Voltage (default=5.6)" /><field62 name="Enter Breakdown Current (default=2.0e-2)" /><field63 name="Enter Saturation Current (default=1.0e-12)" /><field64 name="Enter Forward Emission Coefficient (default=1.0)" /><field65 name="Enter Switch for Limiting (default=FALSE)" /></u22><u19 name="type">zener<field66 name="Enter Breakdown Voltage (default=5.6)" /><field67 name="Enter Breakdown Current (default=2.0e-2)" /><field68 name="Enter Saturation Current (default=1.0e-12)" /><field69 name="Enter Forward Emission Coefficient (default=1.0)" /><field70 name="Enter Switch for Limiting (default=FALSE)" /></u19><u8 name="type">zener<field71 name="Enter Breakdown Voltage (default=5.6)" /><field72 name="Enter Breakdown Current (default=2.0e-2)" /><field73 name="Enter Saturation Current (default=1.0e-12)" /><field74 name="Enter Forward Emission Coefficient (default=1.0)" /><field75 name="Enter Switch for Limiting (default=FALSE)" /></u8><u10 name="type">zener<field76 name="Enter Breakdown Voltage (default=5.6)" /><field77 name="Enter Breakdown Current (default=2.0e-2)" /><field78 name="Enter Saturation Current (default=1.0e-12)" /><field79 name="Enter Forward Emission Coefficient (default=1.0)" /><field80 name="Enter Switch for Limiting (default=FALSE)" /></u10><u11 name="type">zener<field81 name="Enter Breakdown Voltage (default=5.6)" /><field82 name="Enter Breakdown Current (default=2.0e-2)" /><field83 name="Enter Saturation Current (default=1.0e-12)" /><field84 name="Enter Forward Emission Coefficient (default=1.0)" /><field85 name="Enter Switch for Limiting (default=FALSE)" /></u11><u14 name="type">zener<field86 name="Enter Breakdown Voltage (default=5.6)" /><field87 name="Enter Breakdown Current (default=2.0e-2)" /><field88 name="Enter Saturation Current (default=1.0e-12)" /><field89 name="Enter Forward Emission Coefficient (default=1.0)" /><field90 name="Enter Switch for Limiting (default=FALSE)" /></u14><u13 name="type">zener<field91 name="Enter Breakdown Voltage (default=5.6)" /><field92 name="Enter Breakdown Current (default=2.0e-2)" /><field93 name="Enter Saturation Current (default=1.0e-12)" /><field94 name="Enter Forward Emission Coefficient (default=1.0)" /><field95 name="Enter Switch for Limiting (default=FALSE)" /></u13><u15 name="type">zener<field96 name="Enter Breakdown Voltage (default=5.6)" /><field97 name="Enter Breakdown Current (default=2.0e-2)" /><field98 name="Enter Saturation Current (default=1.0e-12)" /><field99 name="Enter Forward Emission Coefficient (default=1.0)" /><field100 name="Enter Switch for Limiting (default=FALSE)" /></u15><u12 name="type">zener<field101 name="Enter Breakdown Voltage (default=5.6)" /><field102 name="Enter Breakdown Current (default=2.0e-2)" /><field103 name="Enter Saturation Current (default=1.0e-12)" /><field104 name="Enter Forward Emission Coefficient (default=1.0)" /><field105 name="Enter Switch for Limiting (default=FALSE)" /></u12></model><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><q18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q17><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11></devicemodel><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS11/analysis b/library/SubcircuitLibrary/SN74LS11/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS11/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro new file mode 100644 index 00000000..06813ca7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib new file mode 100644 index 00000000..60f1a83d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib new file mode 100644 index 00000000..e3833051 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-4_and +# +DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir new file mode 100644 index 00000000..fdf2e107 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and +U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out new file mode 100644 index 00000000..f40e5bc6 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro new file mode 100644 index 00000000..b13a0a82 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=4_and-rescue +LibName2=texas +LibName3=intel +LibName4=audio +LibName5=interface +LibName6=digital-audio +LibName7=philips +LibName8=display +LibName9=cypress +LibName10=siliconi +LibName11=opto +LibName12=atmel +LibName13=contrib +LibName14=valves +LibName15=eSim_Analog +LibName16=eSim_Devices +LibName17=eSim_Digital +LibName18=eSim_Hybrid +LibName19=eSim_Miscellaneous +LibName20=eSim_Plot +LibName21=eSim_Power +LibName22=eSim_Sources +LibName23=eSim_Subckt +LibName24=eSim_User diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch new file mode 100644 index 00000000..f5e8febd --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2 +LIBS:4_and-rescue +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:4_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-4_and X1 +U 1 1 5C9A2915 +P 3700 3500 +F 0 "X1" H 4600 3800 60 0000 C CNN +F 1 "3_and" H 4650 4000 60 0000 C CNN +F 2 "" H 3700 3500 60 0000 C CNN +F 3 "" H 3700 3500 60 0000 C CNN + 1 3700 3500 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2940 +P 5450 3400 +F 0 "U2" H 5450 3400 60 0000 C CNN +F 1 "d_and" H 5500 3500 60 0000 C CNN +F 2 "" H 5450 3400 60 0000 C CNN +F 3 "" H 5450 3400 60 0000 C CNN + 1 5450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5000 3100 5000 3300 +Wire Wire Line + 4150 3000 4150 2700 +Wire Wire Line + 4150 2700 3200 2700 +Wire Wire Line + 4150 3100 4000 3100 +Wire Wire Line + 4000 3100 4000 3000 +Wire Wire Line + 4000 3000 3200 3000 +Wire Wire Line + 4150 3200 4150 3300 +Wire Wire Line + 4150 3300 3250 3300 +Wire Wire Line + 5000 3400 5000 3550 +Wire Wire Line + 5000 3550 3250 3550 +Wire Wire Line + 5900 3350 6500 3350 +$Comp +L PORT U1 +U 1 1 5C9A29B1 +P 2950 2700 +F 0 "U1" H 3000 2800 30 0000 C CNN +F 1 "PORT" H 2950 2700 30 0000 C CNN +F 2 "" H 2950 2700 60 0000 C CNN +F 3 "" H 2950 2700 60 0000 C CNN + 1 2950 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A29E9 +P 2950 3000 +F 0 "U1" H 3000 3100 30 0000 C CNN +F 1 "PORT" H 2950 3000 30 0000 C CNN +F 2 "" H 2950 3000 60 0000 C CNN +F 3 "" H 2950 3000 60 0000 C CNN + 2 2950 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A2A0D +P 3000 3300 +F 0 "U1" H 3050 3400 30 0000 C CNN +F 1 "PORT" H 3000 3300 30 0000 C CNN +F 2 "" H 3000 3300 60 0000 C CNN +F 3 "" H 3000 3300 60 0000 C CNN + 3 3000 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2A3C +P 3000 3550 +F 0 "U1" H 3050 3650 30 0000 C CNN +F 1 "PORT" H 3000 3550 30 0000 C CNN +F 2 "" H 3000 3550 60 0000 C CNN +F 3 "" H 3000 3550 60 0000 C CNN + 4 3000 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2A68 +P 6750 3350 +F 0 "U1" H 6800 3450 30 0000 C CNN +F 1 "PORT" H 6750 3350 30 0000 C CNN +F 2 "" H 6750 3350 60 0000 C CNN +F 3 "" H 6750 3350 60 0000 C CNN + 5 6750 3350 + -1 0 0 1 +$EndComp +Text Notes 3450 2650 0 60 ~ 12 +in1 +Text Notes 3450 2950 0 60 ~ 12 +in2 +Text Notes 3500 3300 0 60 ~ 12 +in3 +Text Notes 3500 3550 0 60 ~ 12 +in4 +Text Notes 6150 3350 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub new file mode 100644 index 00000000..8663f37e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and +.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and +* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and +a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib new file mode 100644 index 00000000..9e35c4fc --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC-cache.lib @@ -0,0 +1,232 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_8 +# +DEF adc_bridge_8 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_8" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -700 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X IN6 6 -600 -450 200 R 50 50 1 1 I +X IN7 7 -600 -550 200 R 50 50 1 1 I +X IN8 8 -600 -650 200 R 50 50 1 1 I +X OUT1 9 550 50 200 L 50 50 1 1 O +X OUT2 10 550 -50 200 L 50 50 1 1 O +X OUT3 11 550 -150 200 L 50 50 1 1 O +X OUT4 12 550 -250 200 L 50 50 1 1 O +X OUT5 13 550 -350 200 L 50 50 1 1 O +X OUT6 14 550 -450 200 L 50 50 1 1 O +X OUT7 15 550 -550 200 L 50 50 1 1 O +X OUT8 16 550 -650 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nor +# +DEF d_nor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nor" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir new file mode 100644 index 00000000..4ecebc03 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir @@ -0,0 +1,69 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS148_IC\SN74LS148_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/24 23:24:07 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U23 Net-_U11-Pad2_ Net-_U2-Pad9_ Net-_U23-Pad3_ d_nand +U24 Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U24-Pad3_ d_nand +U25 Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U25-Pad3_ d_nand +U26 Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U26-Pad3_ d_nand +U29 Net-_U23-Pad3_ Net-_U23-Pad3_ Net-_U29-Pad3_ d_nand +U30 Net-_U24-Pad3_ Net-_U24-Pad3_ Net-_U30-Pad3_ d_nand +U31 Net-_U25-Pad3_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_nand +U32 Net-_U26-Pad3_ Net-_U26-Pad3_ Net-_U32-Pad3_ d_nand +U41 Net-_U29-Pad3_ Net-_U30-Pad3_ Net-_U41-Pad3_ d_nand +U42 Net-_U31-Pad3_ Net-_U32-Pad3_ Net-_U42-Pad3_ d_nand +U48 Net-_U41-Pad3_ Net-_U41-Pad3_ Net-_U48-Pad3_ d_nand +U49 Net-_U42-Pad3_ Net-_U42-Pad3_ Net-_U49-Pad3_ d_nand +U50 Net-_U48-Pad3_ Net-_U49-Pad3_ Net-_U50-Pad3_ d_nand +U53 Net-_U51-Pad3_ Net-_U10-Pad2_ Net-_U52-Pad1_ d_nand +U5 Net-_U2-Pad9_ Net-_U5-Pad2_ d_inverter +X5 Net-_U5-Pad2_ Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad1_ 5_and +X2 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U35-Pad2_ 4_and +X1 Net-_U14-Pad1_ Net-_U15-Pad2_ Net-_U10-Pad2_ Net-_U36-Pad1_ 3_and +U16 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U16-Pad3_ d_and +U35 Net-_U35-Pad1_ Net-_U35-Pad2_ Net-_U35-Pad3_ d_nor +U36 Net-_U36-Pad1_ Net-_U16-Pad3_ Net-_U36-Pad3_ d_nor +U43 Net-_U35-Pad3_ Net-_U35-Pad3_ Net-_U43-Pad3_ d_nor +U44 Net-_U36-Pad3_ Net-_U36-Pad3_ Net-_U44-Pad3_ d_nor +U47 Net-_U43-Pad3_ Net-_U44-Pad3_ Net-_U47-Pad3_ d_nor +X3 Net-_U12-Pad1_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad1_ 4_and +X4 Net-_U4-Pad2_ Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U10-Pad2_ Net-_U27-Pad2_ 4_and +U17 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U17-Pad3_ d_and +U18 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U18-Pad3_ d_and +U27 Net-_U27-Pad1_ Net-_U27-Pad2_ Net-_U27-Pad3_ d_nor +U28 Net-_U17-Pad3_ Net-_U18-Pad3_ Net-_U28-Pad3_ d_nor +U37 Net-_U27-Pad3_ Net-_U27-Pad3_ Net-_U37-Pad3_ d_nor +U38 Net-_U28-Pad3_ Net-_U28-Pad3_ Net-_U38-Pad3_ d_nor +U45 Net-_U37-Pad3_ Net-_U38-Pad3_ Net-_U45-Pad3_ d_nor +U19 Net-_U13-Pad1_ Net-_U10-Pad2_ Net-_U19-Pad3_ d_and +U20 Net-_U14-Pad1_ Net-_U10-Pad2_ Net-_U20-Pad3_ d_and +U21 Net-_U15-Pad1_ Net-_U10-Pad2_ Net-_U21-Pad3_ d_and +U22 Net-_U16-Pad1_ Net-_U10-Pad2_ Net-_U22-Pad3_ d_and +U33 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U33-Pad3_ d_nor +U34 Net-_U21-Pad3_ Net-_U22-Pad3_ Net-_U34-Pad3_ d_nor +U39 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U39-Pad3_ d_nor +U40 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U40-Pad3_ d_nor +U46 Net-_U39-Pad3_ Net-_U40-Pad3_ Net-_U46-Pad3_ d_nor +U3 Net-_U2-Pad10_ Net-_U12-Pad1_ d_inverter +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter +U4 Net-_U2-Pad11_ Net-_U4-Pad2_ d_inverter +U6 Net-_U2-Pad12_ Net-_U13-Pad1_ d_inverter +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter +U7 Net-_U2-Pad13_ Net-_U14-Pad1_ d_inverter +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter +U8 Net-_U2-Pad14_ Net-_U15-Pad1_ d_inverter +U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter +U9 Net-_U2-Pad15_ Net-_U16-Pad1_ d_inverter +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter +U2 Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U2-Pad13_ Net-_U2-Pad14_ Net-_U2-Pad15_ Net-_U10-Pad1_ adc_bridge_8 +U11 Net-_U1-Pad9_ Net-_U11-Pad2_ adc_bridge_1 +U54 Net-_U52-Pad1_ Net-_U10-Pad2_ Net-_U52-Pad2_ d_nand +U52 Net-_U52-Pad1_ Net-_U52-Pad2_ Net-_U47-Pad3_ Net-_U45-Pad3_ Net-_U46-Pad3_ Net-_U1-Pad14_ Net-_U1-Pad13_ Net-_U1-Pad8_ Net-_U1-Pad7_ Net-_U1-Pad6_ dac_bridge_5 +U51 Net-_U50-Pad3_ Net-_U50-Pad3_ Net-_U51-Pad3_ d_nand +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out new file mode 100644 index 00000000..05b10ddb --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.cir.out @@ -0,0 +1,232 @@ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir + +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch new file mode 100644 index 00000000..f749910f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sch @@ -0,0 +1,1472 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN74LS148_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 31496 27559 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev 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Wire Line + 22800 10300 23800 10300 +Wire Wire Line + 23800 10300 23800 12050 +Wire Wire Line + 23800 12050 24700 12050 +Wire Wire Line + 22700 13300 23850 13300 +Wire Wire Line + 23850 13300 23850 12150 +Wire Wire Line + 23850 12150 24700 12150 +Wire Wire Line + 24700 12250 24050 12250 +Wire Wire Line + 24050 12250 24050 15450 +Wire Wire Line + 24050 15450 22750 15450 +Connection ~ 24000 7300 +Wire Wire Line + 24000 7250 24000 7350 +Wire Wire Line + 24000 7350 24050 7350 +Wire Wire Line + 24050 7250 24000 7250 +$Comp +L d_nand U51 +U 1 1 66771ED1 +P 24500 7350 +F 0 "U51" H 24500 7350 60 0000 C CNN +F 1 "d_nand" H 24550 7450 60 0000 C CNN +F 2 "" H 24500 7350 60 0000 C CNN +F 3 "" H 24500 7350 60 0000 C CNN + 1 24500 7350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 66773140 +P 6600 10800 +F 0 "U1" H 6650 10900 30 0000 C CNN +F 1 "PORT" H 6600 10800 30 0000 C CNN +F 2 "" H 6600 10800 60 0000 C CNN +F 3 "" H 6600 10800 60 0000 C CNN + 1 6600 10800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 10200 6850 10450 +Wire Wire Line + 6850 10450 7400 10450 +$Comp +L PORT U1 +U 2 1 66773392 +P 6250 10950 +F 0 "U1" H 6300 11050 30 0000 C CNN +F 1 "PORT" H 6250 10950 30 0000 C CNN +F 2 "" H 6250 10950 60 0000 C CNN +F 3 "" H 6250 10950 60 0000 C CNN + 2 6250 10950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6750 10400 6800 10400 +Wire Wire Line + 6800 10400 6800 10550 +Wire Wire Line + 6800 10550 7400 10550 +$Comp +L PORT U1 +U 3 1 667735C4 +P 6250 11150 +F 0 "U1" H 6300 11250 30 0000 C CNN +F 1 "PORT" H 6250 11150 30 0000 C CNN +F 2 "" H 6250 11150 60 0000 C CNN +F 3 "" H 6250 11150 60 0000 C CNN + 3 6250 11150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6700 10650 7400 10650 +$Comp +L PORT U1 +U 4 1 66773832 +P 6250 11350 +F 0 "U1" H 6300 11450 30 0000 C CNN +F 1 "PORT" H 6250 11350 30 0000 C CNN +F 2 "" H 6250 11350 60 0000 C CNN +F 3 "" H 6250 11350 60 0000 C CNN + 4 6250 11350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 10800 6850 10750 +Wire Wire Line + 6850 10750 7400 10750 +$Comp +L PORT U1 +U 5 1 66773B5C +P 6250 11550 +F 0 "U1" H 6300 11650 30 0000 C CNN +F 1 "PORT" H 6250 11550 30 0000 C CNN +F 2 "" H 6250 11550 60 0000 C CNN +F 3 "" H 6250 11550 60 0000 C CNN + 5 6250 11550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6500 10950 7000 10950 +Wire Wire Line + 7000 10950 7000 10850 +Wire Wire Line + 7000 10850 7400 10850 +$Comp +L PORT U1 +U 6 1 66773D97 +P 26400 12400 +F 0 "U1" H 26450 12500 30 0000 C CNN +F 1 "PORT" H 26400 12400 30 0000 C CNN +F 2 "" H 26400 12400 60 0000 C CNN +F 3 "" H 26400 12400 60 0000 C CNN + 6 26400 12400 + -1 0 0 1 +$EndComp +Wire Wire Line + 7400 10950 7100 10950 +Wire Wire Line + 7100 10950 7100 11150 +Wire Wire Line + 7100 11150 6500 11150 +$Comp +L PORT U1 +U 7 1 66773FE0 +P 26350 12200 +F 0 "U1" H 26400 12300 30 0000 C CNN +F 1 "PORT" H 26350 12200 30 0000 C CNN +F 2 "" H 26350 12200 60 0000 C CNN +F 3 "" H 26350 12200 60 0000 C CNN + 7 26350 12200 + -1 0 0 1 +$EndComp +Wire Wire Line + 6500 11350 7200 11350 +Wire Wire Line + 7200 11350 7200 11050 +Wire Wire Line + 7200 11050 7400 11050 +Wire Wire Line + 6500 11550 7350 11550 +Wire Wire Line + 7350 11550 7350 11150 +Wire Wire Line + 7350 11150 7400 11150 +Wire Wire Line + 26150 12400 26050 12400 +Wire Wire Line + 26050 12400 26050 12250 +Wire Wire Line + 26050 12250 25850 12250 +Wire Wire Line + 26100 12200 25900 12200 +Wire Wire Line + 25900 12200 25900 12150 +Wire Wire Line + 25900 12150 25850 12150 +$Comp +L PORT U1 +U 8 1 6677642A +P 26650 12050 +F 0 "U1" H 26700 12150 30 0000 C CNN +F 1 "PORT" H 26650 12050 30 0000 C CNN +F 2 "" H 26650 12050 60 0000 C CNN +F 3 "" H 26650 12050 60 0000 C CNN + 8 26650 12050 + -1 0 0 1 +$EndComp +Wire Wire Line + 26400 12050 25850 12050 +$Comp +L PORT U1 +U 9 1 66776C6A +P 13750 6250 +F 0 "U1" H 13800 6350 30 0000 C CNN +F 1 "PORT" H 13750 6250 30 0000 C CNN +F 2 "" H 13750 6250 60 0000 C CNN +F 3 "" H 13750 6250 60 0000 C CNN + 9 13750 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14000 6250 14150 6250 +$Comp +L PORT U1 +U 10 1 667774D7 +P 6600 10200 +F 0 "U1" H 6650 10300 30 0000 C CNN +F 1 "PORT" H 6600 10200 30 0000 C CNN +F 2 "" H 6600 10200 60 0000 C CNN +F 3 "" H 6600 10200 60 0000 C CNN + 10 6600 10200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6677758C +P 6500 10400 +F 0 "U1" H 6550 10500 30 0000 C CNN +F 1 "PORT" H 6500 10400 30 0000 C CNN +F 2 "" H 6500 10400 60 0000 C CNN +F 3 "" H 6500 10400 60 0000 C CNN + 11 6500 10400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6677763D +P 6450 10650 +F 0 "U1" H 6500 10750 30 0000 C CNN +F 1 "PORT" H 6450 10650 30 0000 C CNN +F 2 "" H 6450 10650 60 0000 C CNN +F 3 "" H 6450 10650 60 0000 C CNN + 12 6450 10650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 6677815E +P 26350 11900 +F 0 "U1" H 26400 12000 30 0000 C CNN +F 1 "PORT" H 26350 11900 30 0000 C CNN +F 2 "" H 26350 11900 60 0000 C CNN +F 3 "" H 26350 11900 60 0000 C CNN + 13 26350 11900 + -1 0 0 1 +$EndComp +Wire Wire Line + 25850 11950 26100 11950 +Wire Wire Line + 26100 11950 26100 11900 +$Comp +L PORT U1 +U 14 1 667783B7 +P 26350 11650 +F 0 "U1" H 26400 11750 30 0000 C CNN +F 1 "PORT" H 26350 11650 30 0000 C CNN +F 2 "" H 26350 11650 60 0000 C CNN +F 3 "" H 26350 11650 60 0000 C CNN + 14 26350 11650 + -1 0 0 1 +$EndComp +Wire Wire Line + 26100 11650 25950 11650 +Wire Wire Line + 25950 11650 25950 11850 +Wire Wire Line + 25950 11850 25850 11850 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub new file mode 100644 index 00000000..777e7e3f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC.sub @@ -0,0 +1,226 @@ +* Subcircuit SN74LS148_IC +.subckt SN74LS148_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\sn74ls148_ic\sn74ls148_ic.cir +.include 4_and.sub +.include 5_and.sub +.include 3_and.sub +* u23 net-_u11-pad2_ net-_u2-pad9_ net-_u23-pad3_ d_nand +* u24 net-_u2-pad10_ net-_u2-pad11_ net-_u24-pad3_ d_nand +* u25 net-_u2-pad12_ net-_u2-pad13_ net-_u25-pad3_ d_nand +* u26 net-_u2-pad14_ net-_u2-pad15_ net-_u26-pad3_ d_nand +* u29 net-_u23-pad3_ net-_u23-pad3_ net-_u29-pad3_ d_nand +* u30 net-_u24-pad3_ net-_u24-pad3_ net-_u30-pad3_ d_nand +* u31 net-_u25-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_nand +* u32 net-_u26-pad3_ net-_u26-pad3_ net-_u32-pad3_ d_nand +* u41 net-_u29-pad3_ net-_u30-pad3_ net-_u41-pad3_ d_nand +* u42 net-_u31-pad3_ net-_u32-pad3_ net-_u42-pad3_ d_nand +* u48 net-_u41-pad3_ net-_u41-pad3_ net-_u48-pad3_ d_nand +* u49 net-_u42-pad3_ net-_u42-pad3_ net-_u49-pad3_ d_nand +* u50 net-_u48-pad3_ net-_u49-pad3_ net-_u50-pad3_ d_nand +* u53 net-_u51-pad3_ net-_u10-pad2_ net-_u52-pad1_ d_nand +* u5 net-_u2-pad9_ net-_u5-pad2_ d_inverter +x5 net-_u5-pad2_ net-_u12-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad1_ 5_and +x2 net-_u4-pad2_ net-_u13-pad2_ net-_u15-pad2_ net-_u10-pad2_ net-_u35-pad2_ 4_and +x1 net-_u14-pad1_ net-_u15-pad2_ net-_u10-pad2_ net-_u36-pad1_ 3_and +* u16 net-_u16-pad1_ net-_u10-pad2_ net-_u16-pad3_ d_and +* u35 net-_u35-pad1_ net-_u35-pad2_ net-_u35-pad3_ d_nor +* u36 net-_u36-pad1_ net-_u16-pad3_ net-_u36-pad3_ d_nor +* u43 net-_u35-pad3_ net-_u35-pad3_ net-_u43-pad3_ d_nor +* u44 net-_u36-pad3_ net-_u36-pad3_ net-_u44-pad3_ d_nor +* u47 net-_u43-pad3_ net-_u44-pad3_ net-_u47-pad3_ d_nor +x3 net-_u12-pad1_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad1_ 4_and +x4 net-_u4-pad2_ net-_u13-pad2_ net-_u14-pad2_ net-_u10-pad2_ net-_u27-pad2_ 4_and +* u17 net-_u15-pad1_ net-_u10-pad2_ net-_u17-pad3_ d_and +* u18 net-_u16-pad1_ net-_u10-pad2_ net-_u18-pad3_ d_and +* u27 net-_u27-pad1_ net-_u27-pad2_ net-_u27-pad3_ d_nor +* u28 net-_u17-pad3_ net-_u18-pad3_ net-_u28-pad3_ d_nor +* u37 net-_u27-pad3_ net-_u27-pad3_ net-_u37-pad3_ d_nor +* u38 net-_u28-pad3_ net-_u28-pad3_ net-_u38-pad3_ d_nor +* u45 net-_u37-pad3_ net-_u38-pad3_ net-_u45-pad3_ d_nor +* u19 net-_u13-pad1_ net-_u10-pad2_ net-_u19-pad3_ d_and +* u20 net-_u14-pad1_ net-_u10-pad2_ net-_u20-pad3_ d_and +* u21 net-_u15-pad1_ net-_u10-pad2_ net-_u21-pad3_ d_and +* u22 net-_u16-pad1_ net-_u10-pad2_ net-_u22-pad3_ d_and +* u33 net-_u19-pad3_ net-_u20-pad3_ net-_u33-pad3_ d_nor +* u34 net-_u21-pad3_ net-_u22-pad3_ net-_u34-pad3_ d_nor +* u39 net-_u33-pad3_ net-_u33-pad3_ net-_u39-pad3_ d_nor +* u40 net-_u34-pad3_ net-_u34-pad3_ net-_u40-pad3_ d_nor +* u46 net-_u39-pad3_ net-_u40-pad3_ net-_u46-pad3_ d_nor +* u3 net-_u2-pad10_ net-_u12-pad1_ d_inverter +* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter +* u4 net-_u2-pad11_ net-_u4-pad2_ d_inverter +* u6 net-_u2-pad12_ net-_u13-pad1_ d_inverter +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +* u7 net-_u2-pad13_ net-_u14-pad1_ d_inverter +* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter +* u8 net-_u2-pad14_ net-_u15-pad1_ d_inverter +* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter +* u9 net-_u2-pad15_ net-_u16-pad1_ d_inverter +* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter +* u2 net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ adc_bridge_8 +* u11 net-_u1-pad9_ net-_u11-pad2_ adc_bridge_1 +* u54 net-_u52-pad1_ net-_u10-pad2_ net-_u52-pad2_ d_nand +* u52 net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ dac_bridge_5 +* u51 net-_u50-pad3_ net-_u50-pad3_ net-_u51-pad3_ d_nand +a1 [net-_u11-pad2_ net-_u2-pad9_ ] net-_u23-pad3_ u23 +a2 [net-_u2-pad10_ net-_u2-pad11_ ] net-_u24-pad3_ u24 +a3 [net-_u2-pad12_ net-_u2-pad13_ ] net-_u25-pad3_ u25 +a4 [net-_u2-pad14_ net-_u2-pad15_ ] net-_u26-pad3_ u26 +a5 [net-_u23-pad3_ net-_u23-pad3_ ] net-_u29-pad3_ u29 +a6 [net-_u24-pad3_ net-_u24-pad3_ ] net-_u30-pad3_ u30 +a7 [net-_u25-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31 +a8 [net-_u26-pad3_ net-_u26-pad3_ ] net-_u32-pad3_ u32 +a9 [net-_u29-pad3_ net-_u30-pad3_ ] net-_u41-pad3_ u41 +a10 [net-_u31-pad3_ net-_u32-pad3_ ] net-_u42-pad3_ u42 +a11 [net-_u41-pad3_ net-_u41-pad3_ ] net-_u48-pad3_ u48 +a12 [net-_u42-pad3_ net-_u42-pad3_ ] net-_u49-pad3_ u49 +a13 [net-_u48-pad3_ net-_u49-pad3_ ] net-_u50-pad3_ u50 +a14 [net-_u51-pad3_ net-_u10-pad2_ ] net-_u52-pad1_ u53 +a15 net-_u2-pad9_ net-_u5-pad2_ u5 +a16 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u16-pad3_ u16 +a17 [net-_u35-pad1_ net-_u35-pad2_ ] net-_u35-pad3_ u35 +a18 [net-_u36-pad1_ net-_u16-pad3_ ] net-_u36-pad3_ u36 +a19 [net-_u35-pad3_ net-_u35-pad3_ ] net-_u43-pad3_ u43 +a20 [net-_u36-pad3_ net-_u36-pad3_ ] net-_u44-pad3_ u44 +a21 [net-_u43-pad3_ net-_u44-pad3_ ] net-_u47-pad3_ u47 +a22 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u17-pad3_ u17 +a23 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u18-pad3_ u18 +a24 [net-_u27-pad1_ net-_u27-pad2_ ] net-_u27-pad3_ u27 +a25 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u28-pad3_ u28 +a26 [net-_u27-pad3_ net-_u27-pad3_ ] net-_u37-pad3_ u37 +a27 [net-_u28-pad3_ net-_u28-pad3_ ] net-_u38-pad3_ u38 +a28 [net-_u37-pad3_ net-_u38-pad3_ ] net-_u45-pad3_ u45 +a29 [net-_u13-pad1_ net-_u10-pad2_ ] net-_u19-pad3_ u19 +a30 [net-_u14-pad1_ net-_u10-pad2_ ] net-_u20-pad3_ u20 +a31 [net-_u15-pad1_ net-_u10-pad2_ ] net-_u21-pad3_ u21 +a32 [net-_u16-pad1_ net-_u10-pad2_ ] net-_u22-pad3_ u22 +a33 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u33-pad3_ u33 +a34 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u34-pad3_ u34 +a35 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u39-pad3_ u39 +a36 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u40-pad3_ u40 +a37 [net-_u39-pad3_ net-_u40-pad3_ ] net-_u46-pad3_ u46 +a38 net-_u2-pad10_ net-_u12-pad1_ u3 +a39 net-_u12-pad1_ net-_u12-pad2_ u12 +a40 net-_u2-pad11_ net-_u4-pad2_ u4 +a41 net-_u2-pad12_ net-_u13-pad1_ u6 +a42 net-_u13-pad1_ net-_u13-pad2_ u13 +a43 net-_u2-pad13_ net-_u14-pad1_ u7 +a44 net-_u14-pad1_ net-_u14-pad2_ u14 +a45 net-_u2-pad14_ net-_u15-pad1_ u8 +a46 net-_u15-pad1_ net-_u15-pad2_ u15 +a47 net-_u2-pad15_ net-_u16-pad1_ u9 +a48 net-_u10-pad1_ net-_u10-pad2_ u10 +a49 [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u2-pad13_ net-_u2-pad14_ net-_u2-pad15_ net-_u10-pad1_ ] u2 +a50 [net-_u1-pad9_ ] [net-_u11-pad2_ ] u11 +a51 [net-_u52-pad1_ net-_u10-pad2_ ] net-_u52-pad2_ u54 +a52 [net-_u52-pad1_ net-_u52-pad2_ net-_u47-pad3_ net-_u45-pad3_ net-_u46-pad3_ ] [net-_u1-pad14_ net-_u1-pad13_ net-_u1-pad8_ net-_u1-pad7_ net-_u1-pad6_ ] u52 +a53 [net-_u50-pad3_ net-_u50-pad3_ ] net-_u51-pad3_ u51 +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u23 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u25 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u26 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u29 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u30 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u48 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u49 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u50 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u53 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u35 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u36 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u43 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u44 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u47 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u17 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u28 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u37 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u38 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u45 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u22 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u33 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u34 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u39 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u40 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u46 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u54 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u52 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u51 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends SN74LS148_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml new file mode 100644 index 00000000..6d21696c --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/SN74LS148_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u23 name="type">d_nand<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u23><u24 name="type">d_nand<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_nand<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_nand<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u26><u29 name="type">d_nand<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u32><u41 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u41><u42 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u42><u48 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u48><u49 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u49><u50 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u50><u53 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u53><u5 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u5><u16 name="type">d_and<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u16><u35 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u35><u36 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u36><u43 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u44><u47 name="type">d_nor<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u47><u17 name="type">d_and<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_and<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u18><u27 name="type">d_nor<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_nor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u28><u37 name="type">d_nor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u37><u38 name="type">d_nor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u38><u45 name="type">d_nor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u45><u19 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_and<field94 name="Enter Rise Delay (default=1.0e-9)" /><field95 name="Enter Fall Delay (default=1.0e-9)" /><field96 name="Enter Input Load (default=1.0e-12)" /></u22><u33 name="type">d_nor<field97 name="Enter Rise Delay (default=1.0e-9)" /><field98 name="Enter Fall Delay (default=1.0e-9)" /><field99 name="Enter Input Load (default=1.0e-12)" /></u33><u34 name="type">d_nor<field100 name="Enter Rise Delay (default=1.0e-9)" /><field101 name="Enter Fall Delay (default=1.0e-9)" /><field102 name="Enter Input Load (default=1.0e-12)" /></u34><u39 name="type">d_nor<field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Fall Delay (default=1.0e-9)" /><field105 name="Enter Input Load (default=1.0e-12)" /></u39><u40 name="type">d_nor<field106 name="Enter Rise Delay (default=1.0e-9)" /><field107 name="Enter Fall Delay (default=1.0e-9)" /><field108 name="Enter Input Load (default=1.0e-12)" /></u40><u46 name="type">d_nor<field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /><field111 name="Enter Input Load (default=1.0e-12)" /></u46><u3 name="type">d_inverter<field112 name="Enter Rise Delay (default=1.0e-9)" /><field113 name="Enter Fall Delay (default=1.0e-9)" /><field114 name="Enter Input Load (default=1.0e-12)" /></u3><u12 name="type">d_inverter<field115 name="Enter Rise Delay (default=1.0e-9)" /><field116 name="Enter Fall Delay (default=1.0e-9)" /><field117 name="Enter Input Load (default=1.0e-12)" /></u12><u4 name="type">d_inverter<field118 name="Enter Rise Delay (default=1.0e-9)" /><field119 name="Enter Fall Delay (default=1.0e-9)" /><field120 name="Enter Input Load (default=1.0e-12)" /></u4><u6 name="type">d_inverter<field121 name="Enter Rise Delay (default=1.0e-9)" /><field122 name="Enter Fall Delay (default=1.0e-9)" /><field123 name="Enter Input Load (default=1.0e-12)" /></u6><u13 name="type">d_inverter<field124 name="Enter Rise Delay (default=1.0e-9)" /><field125 name="Enter Fall Delay (default=1.0e-9)" /><field126 name="Enter Input Load (default=1.0e-12)" /></u13><u7 name="type">d_inverter<field127 name="Enter Rise Delay (default=1.0e-9)" /><field128 name="Enter Fall Delay (default=1.0e-9)" /><field129 name="Enter Input Load (default=1.0e-12)" /></u7><u14 name="type">d_inverter<field130 name="Enter Rise Delay (default=1.0e-9)" /><field131 name="Enter Fall Delay (default=1.0e-9)" /><field132 name="Enter Input Load (default=1.0e-12)" /></u14><u8 name="type">d_inverter<field133 name="Enter Rise Delay (default=1.0e-9)" /><field134 name="Enter Fall Delay (default=1.0e-9)" /><field135 name="Enter Input Load (default=1.0e-12)" /></u8><u15 name="type">d_inverter<field136 name="Enter Rise Delay (default=1.0e-9)" /><field137 name="Enter Fall Delay (default=1.0e-9)" /><field138 name="Enter Input Load (default=1.0e-12)" /></u15><u9 name="type">d_inverter<field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /><field141 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_inverter<field142 name="Enter Rise Delay (default=1.0e-9)" /><field143 name="Enter Fall Delay (default=1.0e-9)" /><field144 name="Enter Input Load (default=1.0e-12)" /></u10><u2 name="type">adc_bridge<field145 name="Enter value for in_low (default=1.0)" /><field146 name="Enter value for in_high (default=2.0)" /><field147 name="Enter Rise Delay (default=1.0e-9)" /><field148 name="Enter Fall Delay (default=1.0e-9)" /></u2><u11 name="type">adc_bridge<field149 name="Enter value for in_low (default=1.0)" /><field150 name="Enter value for in_high (default=2.0)" /><field151 name="Enter Rise Delay (default=1.0e-9)" /><field152 name="Enter Fall Delay (default=1.0e-9)" /></u11><u54 name="type">d_nand<field153 name="Enter Rise Delay (default=1.0e-9)" /><field154 name="Enter Fall Delay (default=1.0e-9)" /><field155 name="Enter Input Load (default=1.0e-12)" /></u54><u52 name="type">dac_bridge<field156 name="Enter value for out_low (default=0.0)" /><field157 name="Enter value for out_high (default=5.0)" /><field158 name="Enter value for out_undef (default=0.5)" /><field159 name="Enter value for input load (default=1.0e-12)" /><field160 name="Enter the Rise Time (default=1.0e-9)" /><field161 name="Enter the Fall Time (default=1.0e-9)" /></u52><u51 name="type">d_nand<field162 name="Enter Rise Delay (default=1.0e-9)" /><field163 name="Enter Fall Delay (default=1.0e-9)" /><field164 name="Enter Input Load (default=1.0e-12)" /></u51></model><devicemodel /><subcircuit><x5><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x2><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x1><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x1><x3><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x3><x4><field>D:\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS148_sub/analysis b/library/SubcircuitLibrary/SN74LS148_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/NPN.lib b/library/SubcircuitLibrary/TL064_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TL064_sub/PJF.lib b/library/SubcircuitLibrary/TL064_sub/PJF.lib new file mode 100644 index 00000000..5589571d --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/PJF.lib @@ -0,0 +1,5 @@ +.model J2N3820 PJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) + diff --git a/library/SubcircuitLibrary/TL064_sub/PNP.lib b/library/SubcircuitLibrary/TL064_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib b/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib new file mode 100644 index 00000000..48972885 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PJF +# +DEF eSim_PJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_PJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_p +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 -45 0 -5 15 -5 -15 -45 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir new file mode 100644 index 00000000..9251e8d5 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir @@ -0,0 +1,175 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TL064_IC\TL064_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/13/24 19:04:31 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q2-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q4 Net-_Q2-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q15 Net-_Q14-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q17 Net-_Q14-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q3 Net-_J1-Pad1_ Net-_Q3-Pad2_ Net-_Q2-Pad1_ eSim_PNP +J2 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_p +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_p +J5 Net-_J1-Pad1_ Net-_J5-Pad2_ Net-_C1-Pad2_ jfet_p +J6 Net-_J1-Pad1_ Net-_J5-Pad2_ Net-_C1-Pad2_ jfet_p +Q1 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_C1-Pad2_ Net-_J1-Pad3_ Net-_Q6-Pad3_ eSim_NPN +R3 Net-_Q1-Pad3_ Net-_Q10-Pad3_ 34 +R5 Net-_Q6-Pad3_ Net-_Q10-Pad3_ 35 +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad1_ Net-_Q14-Pad3_ eSim_NPN +R9 Net-_Q14-Pad1_ Net-_Q19-Pad1_ 220 +R8 Net-_Q14-Pad3_ Net-_C1-Pad1_ 45k +Q13 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q16 Net-_C1-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +Q19 Net-_Q19-Pad1_ Net-_Q14-Pad3_ Net-_C1-Pad1_ eSim_NPN +Q10 Net-_C1-Pad2_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +R7 Net-_Q10-Pad2_ Net-_Q10-Pad3_ 7 +Q26 Net-_Q15-Pad3_ Net-_Q19-Pad1_ Net-_Q25-Pad2_ eSim_NPN +Q29 Net-_Q15-Pad3_ Net-_Q19-Pad1_ Net-_Q25-Pad2_ eSim_NPN +R15 Net-_Q25-Pad2_ Net-_Q28-Pad3_ 270 +Q28 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q28-Pad3_ eSim_PNP +Q30 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q28-Pad3_ eSim_PNP +R16 Net-_Q25-Pad3_ Net-_Q25-Pad2_ 64 +Q25 Net-_Q19-Pad1_ Net-_Q25-Pad2_ Net-_Q25-Pad3_ eSim_NPN +Q39 Net-_J11-Pad2_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q38 Net-_J9-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad2_ eSim_PNP +Q41 Net-_J11-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad2_ eSim_PNP +J9 Net-_J9-Pad1_ Net-_J11-Pad1_ Net-_J11-Pad3_ jfet_p +J11 Net-_J11-Pad1_ Net-_J11-Pad2_ Net-_J11-Pad3_ jfet_p +Q40 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q42 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q36 Net-_J11-Pad1_ Net-_Q35-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R19 Net-_J11-Pad3_ Net-_Q35-Pad1_ 3.5k +Q35 Net-_Q35-Pad1_ Net-_J11-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q49 Net-_Q15-Pad2_ Net-_Q15-Pad2_ Net-_Q3-Pad2_ eSim_NPN +Q50 Net-_Q10-Pad3_ Net-_J11-Pad2_ Net-_Q3-Pad2_ eSim_PNP +Q7 Net-_Q7-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q9 Net-_Q7-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q21 Net-_Q20-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q23 Net-_Q20-Pad1_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q8 Net-_J3-Pad1_ Net-_Q51-Pad3_ Net-_Q7-Pad1_ eSim_PNP +J4 Net-_J3-Pad1_ Net-_J3-Pad2_ Net-_J3-Pad3_ jfet_p +J3 Net-_J3-Pad1_ Net-_J3-Pad2_ Net-_J3-Pad3_ jfet_p +J7 Net-_J3-Pad1_ Net-_J7-Pad2_ Net-_C2-Pad2_ jfet_p +J8 Net-_J3-Pad1_ Net-_J7-Pad2_ Net-_C2-Pad2_ jfet_p +Q5 Net-_J3-Pad3_ Net-_J3-Pad3_ Net-_Q5-Pad3_ eSim_NPN +Q11 Net-_C2-Pad2_ Net-_J3-Pad3_ Net-_Q11-Pad3_ eSim_NPN +R4 Net-_Q5-Pad3_ Net-_Q10-Pad3_ 34 +R6 Net-_Q11-Pad3_ Net-_Q10-Pad3_ 35 +Q20 Net-_Q20-Pad1_ Net-_Q20-Pad1_ Net-_Q20-Pad3_ eSim_NPN +R12 Net-_Q20-Pad1_ Net-_Q24-Pad1_ 220 +R11 Net-_Q20-Pad3_ Net-_C2-Pad1_ 45k +Q18 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q12-Pad2_ eSim_NPN +Q22 Net-_C2-Pad1_ Net-_C2-Pad2_ Net-_Q12-Pad2_ eSim_NPN +Q24 Net-_Q24-Pad1_ Net-_Q20-Pad3_ Net-_C2-Pad1_ eSim_NPN +Q12 Net-_C2-Pad2_ Net-_Q12-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 10p +R10 Net-_Q12-Pad2_ Net-_Q10-Pad3_ 7 +Q31 Net-_Q15-Pad3_ Net-_Q24-Pad1_ Net-_Q27-Pad2_ eSim_NPN +Q33 Net-_Q15-Pad3_ Net-_Q24-Pad1_ Net-_Q27-Pad2_ eSim_NPN +R17 Net-_Q27-Pad2_ Net-_Q32-Pad3_ 270 +Q32 Net-_Q10-Pad3_ Net-_C2-Pad1_ Net-_Q32-Pad3_ eSim_PNP +Q34 Net-_Q10-Pad3_ Net-_C2-Pad1_ Net-_Q32-Pad3_ eSim_PNP +R18 Net-_Q27-Pad3_ Net-_Q27-Pad2_ 64 +Q27 Net-_Q24-Pad1_ Net-_Q27-Pad2_ Net-_Q27-Pad3_ eSim_NPN +Q45 Net-_J12-Pad2_ Net-_Q21-Pad2_ Net-_Q15-Pad3_ eSim_PNP +Q44 Net-_J10-Pad1_ Net-_J10-Pad2_ Net-_J12-Pad2_ eSim_PNP +Q47 Net-_J10-Pad2_ Net-_J10-Pad2_ Net-_J12-Pad2_ eSim_PNP +J10 Net-_J10-Pad1_ Net-_J10-Pad2_ Net-_J10-Pad3_ jfet_p +J12 Net-_J10-Pad2_ Net-_J12-Pad2_ Net-_J10-Pad3_ jfet_p +Q46 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q48 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q43 Net-_J10-Pad2_ Net-_Q37-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R20 Net-_J10-Pad3_ Net-_Q37-Pad1_ 3.5k +Q37 Net-_Q37-Pad1_ Net-_J10-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q51 Net-_Q21-Pad2_ Net-_Q21-Pad2_ Net-_Q51-Pad3_ eSim_NPN +Q52 Net-_Q10-Pad3_ Net-_J12-Pad2_ Net-_Q51-Pad3_ eSim_PNP +U1 Net-_Q25-Pad3_ Net-_J1-Pad2_ Net-_J5-Pad2_ Net-_Q15-Pad3_ Net-_J7-Pad2_ Net-_J3-Pad2_ Net-_Q27-Pad3_ Net-_Q80-Pad3_ Net-_J15-Pad2_ Net-_J19-Pad2_ Net-_Q10-Pad3_ Net-_J16-Pad2_ Net-_J13-Pad2_ Net-_Q77-Pad3_ PORT +Q54 Net-_Q54-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q56 Net-_Q54-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q67 Net-_Q66-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q69 Net-_Q66-Pad1_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q55 Net-_J13-Pad1_ Net-_Q101-Pad3_ Net-_Q54-Pad1_ eSim_PNP +J14 Net-_J13-Pad1_ Net-_J13-Pad2_ Net-_J13-Pad3_ jfet_p +J13 Net-_J13-Pad1_ Net-_J13-Pad2_ Net-_J13-Pad3_ jfet_p +J16 Net-_J13-Pad1_ Net-_J16-Pad2_ Net-_C3-Pad2_ jfet_p +J18 Net-_J13-Pad1_ Net-_J16-Pad2_ Net-_C3-Pad2_ jfet_p +Q53 Net-_J13-Pad3_ Net-_J13-Pad3_ Net-_Q53-Pad3_ eSim_NPN +Q58 Net-_C3-Pad2_ Net-_J13-Pad3_ Net-_Q58-Pad3_ eSim_NPN +R23 Net-_Q53-Pad3_ Net-_Q10-Pad3_ 34 +R25 Net-_Q58-Pad3_ Net-_Q10-Pad3_ 35 +Q66 Net-_Q66-Pad1_ Net-_Q66-Pad1_ Net-_Q66-Pad3_ eSim_NPN +R29 Net-_Q66-Pad1_ Net-_Q70-Pad1_ 220 +R28 Net-_Q66-Pad3_ Net-_C3-Pad1_ 45k +Q65 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q62-Pad2_ eSim_NPN +Q68 Net-_C3-Pad1_ Net-_C3-Pad2_ Net-_Q62-Pad2_ eSim_NPN +Q70 Net-_Q70-Pad1_ Net-_Q66-Pad3_ Net-_C3-Pad1_ eSim_NPN +Q62 Net-_C3-Pad2_ Net-_Q62-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C3 Net-_C3-Pad1_ Net-_C3-Pad2_ 10p +R27 Net-_Q62-Pad2_ Net-_Q10-Pad3_ 7 +Q78 Net-_Q15-Pad3_ Net-_Q70-Pad1_ Net-_Q77-Pad2_ eSim_NPN +Q81 Net-_Q15-Pad3_ Net-_Q70-Pad1_ Net-_Q77-Pad2_ eSim_NPN +R34 Net-_Q77-Pad2_ Net-_Q79-Pad3_ 270 +Q79 Net-_Q10-Pad3_ Net-_C3-Pad1_ Net-_Q79-Pad3_ eSim_PNP +Q82 Net-_Q10-Pad3_ Net-_C3-Pad1_ Net-_Q79-Pad3_ eSim_PNP +R36 Net-_Q77-Pad3_ Net-_Q77-Pad2_ 64 +Q77 Net-_Q70-Pad1_ Net-_Q77-Pad2_ Net-_Q77-Pad3_ eSim_NPN +Q91 Net-_J23-Pad2_ Net-_Q101-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q89 Net-_J21-Pad1_ Net-_J21-Pad2_ Net-_J23-Pad2_ eSim_PNP +Q93 Net-_J21-Pad2_ Net-_J21-Pad2_ Net-_J23-Pad2_ eSim_PNP +J21 Net-_J21-Pad1_ Net-_J21-Pad2_ Net-_J21-Pad3_ jfet_p +J23 Net-_J21-Pad2_ Net-_J23-Pad2_ Net-_J21-Pad3_ jfet_p +Q92 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q94 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +Q88 Net-_J21-Pad2_ Net-_Q87-Pad1_ Net-_Q10-Pad3_ eSim_NPN +R39 Net-_J21-Pad3_ Net-_Q87-Pad1_ 3.5k +Q87 Net-_Q87-Pad1_ Net-_J21-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q101 Net-_Q101-Pad1_ Net-_Q101-Pad1_ Net-_Q101-Pad3_ eSim_NPN +Q102 Net-_Q10-Pad3_ Net-_J23-Pad2_ Net-_Q101-Pad3_ eSim_PNP +Q59 Net-_Q59-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q61 Net-_Q59-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q73 Net-_Q72-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q75 Net-_Q72-Pad1_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q60 Net-_J15-Pad1_ Net-_Q103-Pad3_ Net-_Q59-Pad1_ eSim_PNP +J17 Net-_J15-Pad1_ Net-_J15-Pad2_ Net-_J15-Pad3_ jfet_p +J15 Net-_J15-Pad1_ Net-_J15-Pad2_ Net-_J15-Pad3_ jfet_p +J19 Net-_J15-Pad1_ Net-_J19-Pad2_ Net-_C4-Pad2_ jfet_p +J20 Net-_J15-Pad1_ Net-_J19-Pad2_ Net-_C4-Pad2_ jfet_p +Q57 Net-_J15-Pad3_ Net-_J15-Pad3_ Net-_Q57-Pad3_ eSim_NPN +Q63 Net-_C4-Pad2_ Net-_J15-Pad3_ Net-_Q63-Pad3_ eSim_NPN +R24 Net-_Q57-Pad3_ Net-_Q10-Pad3_ 34 +R26 Net-_Q63-Pad3_ Net-_Q10-Pad3_ 35 +Q72 Net-_Q72-Pad1_ Net-_Q72-Pad1_ Net-_Q72-Pad3_ eSim_NPN +R32 Net-_Q72-Pad1_ Net-_Q76-Pad1_ 220 +R31 Net-_Q72-Pad3_ Net-_C4-Pad1_ 45k +Q71 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q64-Pad2_ eSim_NPN +Q74 Net-_C4-Pad1_ Net-_C4-Pad2_ Net-_Q64-Pad2_ eSim_NPN +Q76 Net-_Q76-Pad1_ Net-_Q72-Pad3_ Net-_C4-Pad1_ eSim_NPN +Q64 Net-_C4-Pad2_ Net-_Q64-Pad2_ Net-_Q10-Pad3_ eSim_NPN +C4 Net-_C4-Pad1_ Net-_C4-Pad2_ 10p +R30 Net-_Q64-Pad2_ Net-_Q10-Pad3_ 7 +Q83 Net-_Q15-Pad3_ Net-_Q76-Pad1_ Net-_Q80-Pad2_ eSim_NPN +Q85 Net-_Q15-Pad3_ Net-_Q76-Pad1_ Net-_Q80-Pad2_ eSim_NPN +R37 Net-_Q80-Pad2_ Net-_Q84-Pad3_ 270 +Q84 Net-_Q10-Pad3_ Net-_C4-Pad1_ Net-_Q84-Pad3_ eSim_PNP +Q86 Net-_Q10-Pad3_ Net-_C4-Pad1_ Net-_Q84-Pad3_ eSim_PNP +R38 Net-_Q80-Pad3_ Net-_Q80-Pad2_ 64 +Q80 Net-_Q76-Pad1_ Net-_Q80-Pad2_ Net-_Q80-Pad3_ eSim_NPN +Q97 Net-_J24-Pad2_ Net-_Q103-Pad1_ Net-_Q15-Pad3_ eSim_PNP +Q96 Net-_J22-Pad1_ Net-_J22-Pad2_ Net-_J24-Pad2_ eSim_PNP +Q99 Net-_J22-Pad2_ Net-_J22-Pad2_ Net-_J24-Pad2_ eSim_PNP +J22 Net-_J22-Pad1_ Net-_J22-Pad2_ Net-_J22-Pad3_ jfet_p +J24 Net-_J22-Pad2_ Net-_J24-Pad2_ Net-_J22-Pad3_ jfet_p +Q98 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q100 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q95 Net-_J22-Pad2_ Net-_Q100-Pad2_ Net-_Q10-Pad3_ eSim_NPN +R40 Net-_J22-Pad3_ Net-_Q100-Pad2_ 3.5k +Q90 Net-_Q100-Pad2_ Net-_J22-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q103 Net-_Q103-Pad1_ Net-_Q103-Pad1_ Net-_Q103-Pad3_ eSim_NPN +Q104 Net-_Q10-Pad3_ Net-_J24-Pad2_ Net-_Q103-Pad3_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out new file mode 100644 index 00000000..6787b7e5 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.cir.out @@ -0,0 +1,179 @@ +* d:\fossee\esim\library\subcircuitlibrary\tl064_ic\tl064_ic.cir + +.include PJF.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q4 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q17 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q3 net-_j1-pad1_ net-_q3-pad2_ net-_q2-pad1_ Q2N2907A +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j5 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +j6 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +q1 net-_j1-pad3_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q10-pad3_ 34 +r5 net-_q6-pad3_ net-_q10-pad3_ 35 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q14-pad3_ Q2N2222 +r9 net-_q14-pad1_ net-_q19-pad1_ 220 +r8 net-_q14-pad3_ net-_c1-pad1_ 45k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q14-pad3_ net-_c1-pad1_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +r7 net-_q10-pad2_ net-_q10-pad3_ 7 +q26 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +q29 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +r15 net-_q25-pad2_ net-_q28-pad3_ 270 +q28 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +q30 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +r16 net-_q25-pad3_ net-_q25-pad2_ 64 +q25 net-_q19-pad1_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +q39 net-_j11-pad2_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q38 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +q41 net-_j11-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +j9 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad3_ J2N3820 +j11 net-_j11-pad1_ net-_j11-pad2_ net-_j11-pad3_ J2N3820 +q40 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q42 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q36 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +r19 net-_j11-pad3_ net-_q35-pad1_ 3.5k +q35 net-_q35-pad1_ net-_j11-pad3_ net-_q10-pad3_ Q2N2222 +q49 net-_q15-pad2_ net-_q15-pad2_ net-_q3-pad2_ Q2N2222 +q50 net-_q10-pad3_ net-_j11-pad2_ net-_q3-pad2_ Q2N2907A +q7 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q9 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q21 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q23 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q8 net-_j3-pad1_ net-_q51-pad3_ net-_q7-pad1_ Q2N2907A +j4 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j3 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j7 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +j8 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +q5 net-_j3-pad3_ net-_j3-pad3_ net-_q5-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_j3-pad3_ net-_q11-pad3_ Q2N2222 +r4 net-_q5-pad3_ net-_q10-pad3_ 34 +r6 net-_q11-pad3_ net-_q10-pad3_ 35 +q20 net-_q20-pad1_ net-_q20-pad1_ net-_q20-pad3_ Q2N2222 +r12 net-_q20-pad1_ net-_q24-pad1_ 220 +r11 net-_q20-pad3_ net-_c2-pad1_ 45k +q18 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q22 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad3_ net-_c2-pad1_ Q2N2222 +q12 net-_c2-pad2_ net-_q12-pad2_ net-_q10-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +r10 net-_q12-pad2_ net-_q10-pad3_ 7 +q31 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +q33 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +r17 net-_q27-pad2_ net-_q32-pad3_ 270 +q32 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +q34 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +r18 net-_q27-pad3_ net-_q27-pad2_ 64 +q27 net-_q24-pad1_ net-_q27-pad2_ net-_q27-pad3_ Q2N2222 +q45 net-_j12-pad2_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q44 net-_j10-pad1_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +q47 net-_j10-pad2_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +j10 net-_j10-pad1_ net-_j10-pad2_ net-_j10-pad3_ J2N3820 +j12 net-_j10-pad2_ net-_j12-pad2_ net-_j10-pad3_ J2N3820 +q46 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q48 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q43 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +r20 net-_j10-pad3_ net-_q37-pad1_ 3.5k +q37 net-_q37-pad1_ net-_j10-pad3_ net-_q10-pad3_ Q2N2222 +q51 net-_q21-pad2_ net-_q21-pad2_ net-_q51-pad3_ Q2N2222 +q52 net-_q10-pad3_ net-_j12-pad2_ net-_q51-pad3_ Q2N2907A +* u1 net-_q25-pad3_ net-_j1-pad2_ net-_j5-pad2_ net-_q15-pad3_ net-_j7-pad2_ net-_j3-pad2_ net-_q27-pad3_ net-_q80-pad3_ net-_j15-pad2_ net-_j19-pad2_ net-_q10-pad3_ net-_j16-pad2_ net-_j13-pad2_ net-_q77-pad3_ port +q54 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q56 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q67 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q69 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q55 net-_j13-pad1_ net-_q101-pad3_ net-_q54-pad1_ Q2N2907A +j14 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j13 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j16 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +j18 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +q53 net-_j13-pad3_ net-_j13-pad3_ net-_q53-pad3_ Q2N2222 +q58 net-_c3-pad2_ net-_j13-pad3_ net-_q58-pad3_ Q2N2222 +r23 net-_q53-pad3_ net-_q10-pad3_ 34 +r25 net-_q58-pad3_ net-_q10-pad3_ 35 +q66 net-_q66-pad1_ net-_q66-pad1_ net-_q66-pad3_ Q2N2222 +r29 net-_q66-pad1_ net-_q70-pad1_ 220 +r28 net-_q66-pad3_ net-_c3-pad1_ 45k +q65 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q68 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q70 net-_q70-pad1_ net-_q66-pad3_ net-_c3-pad1_ Q2N2222 +q62 net-_c3-pad2_ net-_q62-pad2_ net-_q10-pad3_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +r27 net-_q62-pad2_ net-_q10-pad3_ 7 +q78 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +q81 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +r34 net-_q77-pad2_ net-_q79-pad3_ 270 +q79 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +q82 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +r36 net-_q77-pad3_ net-_q77-pad2_ 64 +q77 net-_q70-pad1_ net-_q77-pad2_ net-_q77-pad3_ Q2N2222 +q91 net-_j23-pad2_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q89 net-_j21-pad1_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +q93 net-_j21-pad2_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +j21 net-_j21-pad1_ net-_j21-pad2_ net-_j21-pad3_ J2N3820 +j23 net-_j21-pad2_ net-_j23-pad2_ net-_j21-pad3_ J2N3820 +q92 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q94 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q88 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +r39 net-_j21-pad3_ net-_q87-pad1_ 3.5k +q87 net-_q87-pad1_ net-_j21-pad3_ net-_q10-pad3_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad1_ net-_q101-pad3_ Q2N2222 +q102 net-_q10-pad3_ net-_j23-pad2_ net-_q101-pad3_ Q2N2907A +q59 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q61 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q73 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q75 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q60 net-_j15-pad1_ net-_q103-pad3_ net-_q59-pad1_ Q2N2907A +j17 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j15 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j19 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +j20 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +q57 net-_j15-pad3_ net-_j15-pad3_ net-_q57-pad3_ Q2N2222 +q63 net-_c4-pad2_ net-_j15-pad3_ net-_q63-pad3_ Q2N2222 +r24 net-_q57-pad3_ net-_q10-pad3_ 34 +r26 net-_q63-pad3_ net-_q10-pad3_ 35 +q72 net-_q72-pad1_ net-_q72-pad1_ net-_q72-pad3_ Q2N2222 +r32 net-_q72-pad1_ net-_q76-pad1_ 220 +r31 net-_q72-pad3_ net-_c4-pad1_ 45k +q71 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q74 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q76 net-_q76-pad1_ net-_q72-pad3_ net-_c4-pad1_ Q2N2222 +q64 net-_c4-pad2_ net-_q64-pad2_ net-_q10-pad3_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +r30 net-_q64-pad2_ net-_q10-pad3_ 7 +q83 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +q85 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +r37 net-_q80-pad2_ net-_q84-pad3_ 270 +q84 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +q86 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +r38 net-_q80-pad3_ net-_q80-pad2_ 64 +q80 net-_q76-pad1_ net-_q80-pad2_ net-_q80-pad3_ Q2N2222 +q97 net-_j24-pad2_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q96 net-_j22-pad1_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +q99 net-_j22-pad2_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +j22 net-_j22-pad1_ net-_j22-pad2_ net-_j22-pad3_ J2N3820 +j24 net-_j22-pad2_ net-_j24-pad2_ net-_j22-pad3_ J2N3820 +q98 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q100 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q95 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +r40 net-_j22-pad3_ net-_q100-pad2_ 3.5k +q90 net-_q100-pad2_ net-_j22-pad3_ net-_q10-pad3_ Q2N2222 +q103 net-_q103-pad1_ net-_q103-pad1_ net-_q103-pad3_ Q2N2222 +q104 net-_q10-pad3_ net-_j24-pad2_ net-_q103-pad3_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro b/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch new file mode 100644 index 00000000..85273f71 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sch @@ -0,0 +1,3533 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TL064_IC-cache +EELAYER 25 0 +EELAYER END +$Descr User 47244 39370 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 668A6280 +P 4900 4400 +F 0 "Q2" H 4800 4450 50 0000 R CNN +F 1 "eSim_PNP" H 4850 4550 50 0000 R CNN +F 2 "" H 5100 4500 29 0000 C CNN +F 3 "" H 4900 4400 60 0000 C CNN + 1 4900 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 668A6281 +P 5350 4400 +F 0 "Q4" H 5250 4450 50 0000 R CNN +F 1 "eSim_PNP" H 5300 4550 50 0000 R CNN +F 2 "" H 5550 4500 29 0000 C CNN +F 3 "" H 5350 4400 60 0000 C CNN + 1 5350 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 668A6282 +P 8600 4450 +F 0 "Q15" H 8500 4500 50 0000 R CNN +F 1 "eSim_PNP" H 8550 4600 50 0000 R CNN +F 2 "" H 8800 4550 29 0000 C CNN +F 3 "" H 8600 4450 60 0000 C CNN + 1 8600 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 668A6283 +P 9050 4450 +F 0 "Q17" H 8950 4500 50 0000 R CNN +F 1 "eSim_PNP" H 9000 4600 50 0000 R CNN +F 2 "" H 9250 4550 29 0000 C CNN +F 3 "" H 9050 4450 60 0000 C CNN + 1 9050 4450 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q3 +U 1 1 668A6284 +P 5150 5600 +F 0 "Q3" H 5050 5650 50 0000 R CNN +F 1 "eSim_PNP" H 5100 5750 50 0000 R CNN +F 2 "" H 5350 5700 29 0000 C CNN +F 3 "" H 5150 5600 60 0000 C CNN + 1 5150 5600 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J2 +U 1 1 668A6285 +P 4700 6700 +F 0 "J2" H 4600 6750 50 0000 R CNN +F 1 "jfet_p" H 4650 6850 50 0000 R CNN +F 2 "" H 4900 6800 29 0000 C CNN +F 3 "" H 4700 6700 60 0000 C CNN + 1 4700 6700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J1 +U 1 1 668A6286 +P 3850 6700 +F 0 "J1" H 3750 6750 50 0000 R CNN +F 1 "jfet_p" H 3800 6850 50 0000 R CNN +F 2 "" H 4050 6800 29 0000 C CNN +F 3 "" H 3850 6700 60 0000 C CNN + 1 3850 6700 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J5 +U 1 1 668A6287 +P 5700 6700 +F 0 "J5" H 5600 6750 50 0000 R CNN +F 1 "jfet_p" H 5650 6850 50 0000 R CNN +F 2 "" H 5900 6800 29 0000 C CNN +F 3 "" H 5700 6700 60 0000 C CNN + 1 5700 6700 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J6 +U 1 1 668A6288 +P 6350 6700 +F 0 "J6" H 6250 6750 50 0000 R CNN +F 1 "jfet_p" H 6300 6850 50 0000 R CNN +F 2 "" H 6550 6800 29 0000 C CNN +F 3 "" H 6350 6700 60 0000 C CNN + 1 6350 6700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 668A6289 +P 4400 8400 +F 0 "Q1" H 4300 8450 50 0000 R CNN +F 1 "eSim_NPN" H 4350 8550 50 0000 R CNN +F 2 "" H 4600 8500 29 0000 C CNN +F 3 "" H 4400 8400 60 0000 C CNN + 1 4400 8400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 668A628A +P 5700 8400 +F 0 "Q6" H 5600 8450 50 0000 R CNN +F 1 "eSim_NPN" H 5650 8550 50 0000 R CNN +F 2 "" H 5900 8500 29 0000 C CNN +F 3 "" H 5700 8400 60 0000 C CNN + 1 5700 8400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 668A628B +P 4250 9600 +F 0 "R3" H 4300 9730 50 0000 C CNN +F 1 "34" H 4300 9550 50 0000 C CNN +F 2 "" H 4300 9580 30 0000 C CNN +F 3 "" V 4300 9650 30 0000 C CNN + 1 4250 9600 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 668A628C +P 5750 9600 +F 0 "R5" H 5800 9730 50 0000 C CNN +F 1 "35" H 5800 9550 50 0000 C CNN +F 2 "" H 5800 9580 30 0000 C CNN +F 3 "" V 5800 9650 30 0000 C CNN + 1 5750 9600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 668A628D +P 8450 5450 +F 0 "Q14" H 8350 5500 50 0000 R CNN +F 1 "eSim_NPN" H 8400 5600 50 0000 R CNN +F 2 "" H 8650 5550 29 0000 C CNN +F 3 "" H 8450 5450 60 0000 C CNN + 1 8450 5450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 668A628E +P 9300 5200 +F 0 "R9" H 9350 5330 50 0000 C CNN +F 1 "220" H 9350 5150 50 0000 C CNN +F 2 "" H 9350 5180 30 0000 C CNN +F 3 "" V 9350 5250 30 0000 C CNN + 1 9300 5200 + 0 1 1 0 +$EndComp +$Comp +L resistor R8 +U 1 1 668A628F +P 8500 6100 +F 0 "R8" H 8550 6230 50 0000 C CNN +F 1 "45k" H 8550 6050 50 0000 C CNN +F 2 "" H 8550 6080 30 0000 C CNN +F 3 "" V 8550 6150 30 0000 C CNN + 1 8500 6100 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 668A6290 +P 8200 7450 +F 0 "Q13" H 8100 7500 50 0000 R CNN +F 1 "eSim_NPN" H 8150 7600 50 0000 R CNN +F 2 "" H 8400 7550 29 0000 C CNN +F 3 "" H 8200 7450 60 0000 C CNN + 1 8200 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 668A6291 +P 8650 7450 +F 0 "Q16" H 8550 7500 50 0000 R CNN +F 1 "eSim_NPN" H 8600 7600 50 0000 R CNN +F 2 "" H 8850 7550 29 0000 C CNN +F 3 "" H 8650 7450 60 0000 C CNN + 1 8650 7450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 668A6292 +P 9250 5850 +F 0 "Q19" H 9150 5900 50 0000 R CNN +F 1 "eSim_NPN" H 9200 6000 50 0000 R CNN +F 2 "" H 9450 5950 29 0000 C CNN +F 3 "" H 9250 5850 60 0000 C CNN + 1 9250 5850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 668A6293 +P 6500 8900 +F 0 "Q10" H 6400 8950 50 0000 R CNN +F 1 "eSim_NPN" H 6450 9050 50 0000 R CNN +F 2 "" H 6700 9000 29 0000 C CNN +F 3 "" H 6500 8900 60 0000 C CNN + 1 6500 8900 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 668A6294 +P 6800 7700 +F 0 "C1" H 6825 7800 50 0000 L CNN +F 1 "10p" H 6825 7600 50 0000 L CNN +F 2 "" H 6838 7550 30 0000 C CNN +F 3 "" H 6800 7700 60 0000 C CNN + 1 6800 7700 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 668A6295 +P 8450 9300 +F 0 "R7" H 8500 9430 50 0000 C CNN +F 1 "7" H 8500 9250 50 0000 C CNN +F 2 "" H 8500 9280 30 0000 C CNN +F 3 "" V 8500 9350 30 0000 C CNN + 1 8450 9300 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q26 +U 1 1 668A6296 +P 11600 5600 +F 0 "Q26" H 11500 5650 50 0000 R CNN +F 1 "eSim_NPN" H 11550 5750 50 0000 R CNN +F 2 "" H 11800 5700 29 0000 C CNN +F 3 "" H 11600 5600 60 0000 C CNN + 1 11600 5600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q29 +U 1 1 668A6297 +P 12100 5600 +F 0 "Q29" H 12000 5650 50 0000 R CNN +F 1 "eSim_NPN" H 12050 5750 50 0000 R CNN +F 2 "" H 12300 5700 29 0000 C CNN +F 3 "" H 12100 5600 60 0000 C CNN + 1 12100 5600 + 1 0 0 -1 +$EndComp +$Comp +L resistor R15 +U 1 1 668A6298 +P 11950 6800 +F 0 "R15" H 12000 6930 50 0000 C CNN +F 1 "270" H 12000 6750 50 0000 C CNN +F 2 "" H 12000 6780 30 0000 C CNN +F 3 "" V 12000 6850 30 0000 C CNN + 1 11950 6800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 668A6299 +P 11800 7700 +F 0 "Q28" H 11700 7750 50 0000 R CNN +F 1 "eSim_PNP" H 11750 7850 50 0000 R CNN +F 2 "" H 12000 7800 29 0000 C CNN +F 3 "" H 11800 7700 60 0000 C CNN + 1 11800 7700 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q30 +U 1 1 668A629A +P 12200 7700 +F 0 "Q30" H 12100 7750 50 0000 R CNN +F 1 "eSim_PNP" H 12150 7850 50 0000 R CNN +F 2 "" H 12400 7800 29 0000 C CNN +F 3 "" H 12200 7700 60 0000 C CNN + 1 12200 7700 + 1 0 0 1 +$EndComp +$Comp +L resistor R16 +U 1 1 668A629B +P 12600 6350 +F 0 "R16" H 12650 6480 50 0000 C CNN +F 1 "64" H 12650 6300 50 0000 C CNN +F 2 "" H 12650 6330 30 0000 C CNN +F 3 "" V 12650 6400 30 0000 C CNN + 1 12600 6350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q25 +U 1 1 668A629D +P 10800 6200 +F 0 "Q25" H 10700 6250 50 0000 R CNN +F 1 "eSim_NPN" H 10750 6350 50 0000 R CNN +F 2 "" H 11000 6300 29 0000 C CNN +F 3 "" H 10800 6200 60 0000 C CNN + 1 10800 6200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q39 +U 1 1 668A629E +P 16200 4400 +F 0 "Q39" H 16100 4450 50 0000 R CNN +F 1 "eSim_PNP" H 16150 4550 50 0000 R CNN +F 2 "" H 16400 4500 29 0000 C CNN +F 3 "" H 16200 4400 60 0000 C CNN + 1 16200 4400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q38 +U 1 1 668A629F +P 16050 5300 +F 0 "Q38" H 15950 5350 50 0000 R CNN +F 1 "eSim_PNP" H 16000 5450 50 0000 R CNN +F 2 "" H 16250 5400 29 0000 C CNN +F 3 "" H 16050 5300 60 0000 C CNN + 1 16050 5300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q41 +U 1 1 668A62A0 +P 16450 5300 +F 0 "Q41" H 16350 5350 50 0000 R CNN +F 1 "eSim_PNP" H 16400 5450 50 0000 R CNN +F 2 "" H 16650 5400 29 0000 C CNN +F 3 "" H 16450 5300 60 0000 C CNN + 1 16450 5300 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J9 +U 1 1 668A62A1 +P 15800 6600 +F 0 "J9" H 15700 6650 50 0000 R CNN +F 1 "jfet_p" H 15750 6750 50 0000 R CNN +F 2 "" H 16000 6700 29 0000 C CNN +F 3 "" H 15800 6600 60 0000 C CNN + 1 15800 6600 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J11 +U 1 1 668A62A2 +P 17000 6600 +F 0 "J11" H 16900 6650 50 0000 R CNN +F 1 "jfet_p" H 16950 6750 50 0000 R CNN +F 2 "" H 17200 6700 29 0000 C CNN +F 3 "" H 17000 6600 60 0000 C CNN + 1 17000 6600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q40 +U 1 1 668A62A3 +P 16200 8050 +F 0 "Q40" H 16100 8100 50 0000 R CNN +F 1 "eSim_NPN" H 16150 8200 50 0000 R CNN +F 2 "" H 16400 8150 29 0000 C CNN +F 3 "" H 16200 8050 60 0000 C CNN + 1 16200 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q42 +U 1 1 668A62A4 +P 16650 8050 +F 0 "Q42" H 16550 8100 50 0000 R CNN +F 1 "eSim_NPN" H 16600 8200 50 0000 R CNN +F 2 "" H 16850 8150 29 0000 C CNN +F 3 "" H 16650 8050 60 0000 C CNN + 1 16650 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q36 +U 1 1 668A62A5 +P 15800 8050 +F 0 "Q36" H 15700 8100 50 0000 R CNN +F 1 "eSim_NPN" H 15750 8200 50 0000 R CNN +F 2 "" H 16000 8150 29 0000 C CNN +F 3 "" H 15800 8050 60 0000 C CNN + 1 15800 8050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 668A62A6 +P 15050 7450 +F 0 "R19" H 15100 7580 50 0000 C CNN +F 1 "3.5k" H 15100 7400 50 0000 C CNN +F 2 "" H 15100 7430 30 0000 C CNN +F 3 "" V 15100 7500 30 0000 C CNN + 1 15050 7450 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q35 +U 1 1 668A62A7 +P 15000 8500 +F 0 "Q35" H 14900 8550 50 0000 R CNN +F 1 "eSim_NPN" H 14950 8650 50 0000 R CNN +F 2 "" H 15200 8600 29 0000 C CNN +F 3 "" H 15000 8500 60 0000 C CNN + 1 15000 8500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q49 +U 1 1 668A62A8 +P 18900 4700 +F 0 "Q49" H 18800 4750 50 0000 R CNN +F 1 "eSim_NPN" H 18850 4850 50 0000 R CNN +F 2 "" H 19100 4800 29 0000 C CNN +F 3 "" H 18900 4700 60 0000 C CNN + 1 18900 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q50 +U 1 1 668A62A9 +P 18900 5650 +F 0 "Q50" H 18800 5700 50 0000 R CNN +F 1 "eSim_PNP" H 18850 5800 50 0000 R CNN +F 2 "" H 19100 5750 29 0000 C CNN +F 3 "" H 18900 5650 60 0000 C CNN + 1 18900 5650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 668A93A8 +P 5850 21300 +F 0 "Q7" H 5750 21350 50 0000 R CNN +F 1 "eSim_PNP" H 5800 21450 50 0000 R CNN +F 2 "" H 6050 21400 29 0000 C CNN +F 3 "" H 5850 21300 60 0000 C CNN + 1 5850 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 668A93AE +P 6300 21300 +F 0 "Q9" H 6200 21350 50 0000 R CNN +F 1 "eSim_PNP" H 6250 21450 50 0000 R CNN +F 2 "" H 6500 21400 29 0000 C CNN +F 3 "" H 6300 21300 60 0000 C CNN + 1 6300 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 668A93B4 +P 9550 21350 +F 0 "Q21" H 9450 21400 50 0000 R CNN +F 1 "eSim_PNP" H 9500 21500 50 0000 R CNN +F 2 "" H 9750 21450 29 0000 C CNN +F 3 "" H 9550 21350 60 0000 C CNN + 1 9550 21350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q23 +U 1 1 668A93BA +P 10000 21350 +F 0 "Q23" H 9900 21400 50 0000 R CNN +F 1 "eSim_PNP" H 9950 21500 50 0000 R CNN +F 2 "" H 10200 21450 29 0000 C CNN +F 3 "" H 10000 21350 60 0000 C CNN + 1 10000 21350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 668A93C0 +P 6100 22500 +F 0 "Q8" H 6000 22550 50 0000 R CNN +F 1 "eSim_PNP" H 6050 22650 50 0000 R CNN +F 2 "" H 6300 22600 29 0000 C CNN +F 3 "" H 6100 22500 60 0000 C CNN + 1 6100 22500 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J4 +U 1 1 668A93C6 +P 5650 23600 +F 0 "J4" H 5550 23650 50 0000 R CNN +F 1 "jfet_p" H 5600 23750 50 0000 R CNN +F 2 "" H 5850 23700 29 0000 C CNN +F 3 "" H 5650 23600 60 0000 C CNN + 1 5650 23600 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J3 +U 1 1 668A93CC +P 4800 23600 +F 0 "J3" H 4700 23650 50 0000 R CNN +F 1 "jfet_p" H 4750 23750 50 0000 R CNN +F 2 "" H 5000 23700 29 0000 C CNN +F 3 "" H 4800 23600 60 0000 C CNN + 1 4800 23600 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J7 +U 1 1 668A93D2 +P 6650 23600 +F 0 "J7" H 6550 23650 50 0000 R CNN +F 1 "jfet_p" H 6600 23750 50 0000 R CNN +F 2 "" H 6850 23700 29 0000 C CNN +F 3 "" H 6650 23600 60 0000 C CNN + 1 6650 23600 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J8 +U 1 1 668A93D8 +P 7300 23600 +F 0 "J8" H 7200 23650 50 0000 R CNN +F 1 "jfet_p" H 7250 23750 50 0000 R CNN +F 2 "" H 7500 23700 29 0000 C CNN +F 3 "" H 7300 23600 60 0000 C CNN + 1 7300 23600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 668A93DE +P 5350 25300 +F 0 "Q5" H 5250 25350 50 0000 R CNN +F 1 "eSim_NPN" H 5300 25450 50 0000 R CNN +F 2 "" H 5550 25400 29 0000 C CNN +F 3 "" H 5350 25300 60 0000 C CNN + 1 5350 25300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 668A93E4 +P 6650 25300 +F 0 "Q11" H 6550 25350 50 0000 R CNN +F 1 "eSim_NPN" H 6600 25450 50 0000 R CNN +F 2 "" H 6850 25400 29 0000 C CNN +F 3 "" H 6650 25300 60 0000 C CNN + 1 6650 25300 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 668A93EA +P 5200 26500 +F 0 "R4" H 5250 26630 50 0000 C CNN +F 1 "34" H 5250 26450 50 0000 C CNN +F 2 "" H 5250 26480 30 0000 C CNN +F 3 "" V 5250 26550 30 0000 C CNN + 1 5200 26500 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 668A93F0 +P 6700 26500 +F 0 "R6" H 6750 26630 50 0000 C CNN +F 1 "35" H 6750 26450 50 0000 C CNN +F 2 "" H 6750 26480 30 0000 C CNN +F 3 "" V 6750 26550 30 0000 C CNN + 1 6700 26500 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 668A93F6 +P 9400 22350 +F 0 "Q20" H 9300 22400 50 0000 R CNN +F 1 "eSim_NPN" H 9350 22500 50 0000 R CNN +F 2 "" H 9600 22450 29 0000 C CNN +F 3 "" H 9400 22350 60 0000 C CNN + 1 9400 22350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 668A93FC +P 10250 22100 +F 0 "R12" H 10300 22230 50 0000 C CNN +F 1 "220" H 10300 22050 50 0000 C CNN +F 2 "" H 10300 22080 30 0000 C CNN +F 3 "" V 10300 22150 30 0000 C CNN + 1 10250 22100 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 668A9402 +P 9450 23000 +F 0 "R11" H 9500 23130 50 0000 C CNN +F 1 "45k" H 9500 22950 50 0000 C CNN +F 2 "" H 9500 22980 30 0000 C CNN +F 3 "" V 9500 23050 30 0000 C CNN + 1 9450 23000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 668A9408 +P 9150 24350 +F 0 "Q18" H 9050 24400 50 0000 R CNN +F 1 "eSim_NPN" H 9100 24500 50 0000 R CNN +F 2 "" H 9350 24450 29 0000 C CNN +F 3 "" H 9150 24350 60 0000 C CNN + 1 9150 24350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q22 +U 1 1 668A940E +P 9600 24350 +F 0 "Q22" H 9500 24400 50 0000 R CNN +F 1 "eSim_NPN" H 9550 24500 50 0000 R CNN +F 2 "" H 9800 24450 29 0000 C CNN +F 3 "" H 9600 24350 60 0000 C CNN + 1 9600 24350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 668A9414 +P 10200 22750 +F 0 "Q24" H 10100 22800 50 0000 R CNN +F 1 "eSim_NPN" H 10150 22900 50 0000 R CNN +F 2 "" H 10400 22850 29 0000 C CNN +F 3 "" H 10200 22750 60 0000 C CNN + 1 10200 22750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 668A941A +P 7450 25800 +F 0 "Q12" H 7350 25850 50 0000 R CNN +F 1 "eSim_NPN" H 7400 25950 50 0000 R CNN +F 2 "" H 7650 25900 29 0000 C CNN +F 3 "" H 7450 25800 60 0000 C CNN + 1 7450 25800 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 668A9420 +P 7750 24600 +F 0 "C2" H 7775 24700 50 0000 L CNN +F 1 "10p" H 7775 24500 50 0000 L CNN +F 2 "" H 7788 24450 30 0000 C CNN +F 3 "" H 7750 24600 60 0000 C CNN + 1 7750 24600 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 668A9426 +P 9400 26200 +F 0 "R10" H 9450 26330 50 0000 C CNN +F 1 "7" H 9450 26150 50 0000 C CNN +F 2 "" H 9450 26180 30 0000 C CNN +F 3 "" V 9450 26250 30 0000 C CNN + 1 9400 26200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 668A942C +P 12550 22500 +F 0 "Q31" H 12450 22550 50 0000 R CNN +F 1 "eSim_NPN" H 12500 22650 50 0000 R CNN +F 2 "" H 12750 22600 29 0000 C CNN +F 3 "" H 12550 22500 60 0000 C CNN + 1 12550 22500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q33 +U 1 1 668A9432 +P 13050 22500 +F 0 "Q33" H 12950 22550 50 0000 R CNN +F 1 "eSim_NPN" H 13000 22650 50 0000 R CNN +F 2 "" H 13250 22600 29 0000 C CNN +F 3 "" H 13050 22500 60 0000 C CNN + 1 13050 22500 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 668A9438 +P 12900 23700 +F 0 "R17" H 12950 23830 50 0000 C CNN +F 1 "270" H 12950 23650 50 0000 C CNN +F 2 "" H 12950 23680 30 0000 C CNN +F 3 "" V 12950 23750 30 0000 C CNN + 1 12900 23700 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 668A943E +P 12750 24600 +F 0 "Q32" H 12650 24650 50 0000 R CNN +F 1 "eSim_PNP" H 12700 24750 50 0000 R CNN +F 2 "" H 12950 24700 29 0000 C CNN +F 3 "" H 12750 24600 60 0000 C CNN + 1 12750 24600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q34 +U 1 1 668A9444 +P 13150 24600 +F 0 "Q34" H 13050 24650 50 0000 R CNN +F 1 "eSim_PNP" H 13100 24750 50 0000 R CNN +F 2 "" H 13350 24700 29 0000 C CNN +F 3 "" H 13150 24600 60 0000 C CNN + 1 13150 24600 + 1 0 0 1 +$EndComp +$Comp +L resistor R18 +U 1 1 668A944A +P 13550 23250 +F 0 "R18" H 13600 23380 50 0000 C CNN +F 1 "64" H 13600 23200 50 0000 C CNN +F 2 "" H 13600 23230 30 0000 C CNN +F 3 "" V 13600 23300 30 0000 C CNN + 1 13550 23250 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 668A9456 +P 11750 23100 +F 0 "Q27" H 11650 23150 50 0000 R CNN +F 1 "eSim_NPN" H 11700 23250 50 0000 R CNN +F 2 "" H 11950 23200 29 0000 C CNN +F 3 "" H 11750 23100 60 0000 C CNN + 1 11750 23100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 668A945D +P 17150 21300 +F 0 "Q45" H 17050 21350 50 0000 R CNN +F 1 "eSim_PNP" H 17100 21450 50 0000 R CNN +F 2 "" H 17350 21400 29 0000 C CNN +F 3 "" H 17150 21300 60 0000 C CNN + 1 17150 21300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q44 +U 1 1 668A9463 +P 17000 22200 +F 0 "Q44" H 16900 22250 50 0000 R CNN +F 1 "eSim_PNP" H 16950 22350 50 0000 R CNN +F 2 "" H 17200 22300 29 0000 C CNN +F 3 "" H 17000 22200 60 0000 C CNN + 1 17000 22200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q47 +U 1 1 668A9469 +P 17400 22200 +F 0 "Q47" H 17300 22250 50 0000 R CNN +F 1 "eSim_PNP" H 17350 22350 50 0000 R CNN +F 2 "" H 17600 22300 29 0000 C CNN +F 3 "" H 17400 22200 60 0000 C CNN + 1 17400 22200 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J10 +U 1 1 668A946F +P 16750 23500 +F 0 "J10" H 16650 23550 50 0000 R CNN +F 1 "jfet_p" H 16700 23650 50 0000 R CNN +F 2 "" H 16950 23600 29 0000 C CNN +F 3 "" H 16750 23500 60 0000 C CNN + 1 16750 23500 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J12 +U 1 1 668A9475 +P 17950 23500 +F 0 "J12" H 17850 23550 50 0000 R CNN +F 1 "jfet_p" H 17900 23650 50 0000 R CNN +F 2 "" H 18150 23600 29 0000 C CNN +F 3 "" H 17950 23500 60 0000 C CNN + 1 17950 23500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q46 +U 1 1 668A947B +P 17150 24950 +F 0 "Q46" H 17050 25000 50 0000 R CNN +F 1 "eSim_NPN" H 17100 25100 50 0000 R CNN +F 2 "" H 17350 25050 29 0000 C CNN +F 3 "" H 17150 24950 60 0000 C CNN + 1 17150 24950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q48 +U 1 1 668A9481 +P 17600 24950 +F 0 "Q48" H 17500 25000 50 0000 R CNN +F 1 "eSim_NPN" H 17550 25100 50 0000 R CNN +F 2 "" H 17800 25050 29 0000 C CNN +F 3 "" H 17600 24950 60 0000 C CNN + 1 17600 24950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q43 +U 1 1 668A9487 +P 16750 24950 +F 0 "Q43" H 16650 25000 50 0000 R CNN +F 1 "eSim_NPN" H 16700 25100 50 0000 R CNN +F 2 "" H 16950 25050 29 0000 C CNN +F 3 "" H 16750 24950 60 0000 C CNN + 1 16750 24950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R20 +U 1 1 668A948D +P 16000 24350 +F 0 "R20" H 16050 24480 50 0000 C CNN +F 1 "3.5k" H 16050 24300 50 0000 C CNN +F 2 "" H 16050 24330 30 0000 C CNN +F 3 "" V 16050 24400 30 0000 C CNN + 1 16000 24350 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q37 +U 1 1 668A9493 +P 15950 25400 +F 0 "Q37" H 15850 25450 50 0000 R CNN +F 1 "eSim_NPN" H 15900 25550 50 0000 R CNN +F 2 "" H 16150 25500 29 0000 C CNN +F 3 "" H 15950 25400 60 0000 C CNN + 1 15950 25400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q51 +U 1 1 668A9499 +P 19850 21600 +F 0 "Q51" H 19750 21650 50 0000 R CNN +F 1 "eSim_NPN" H 19800 21750 50 0000 R CNN +F 2 "" H 20050 21700 29 0000 C CNN +F 3 "" H 19850 21600 60 0000 C CNN + 1 19850 21600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q52 +U 1 1 668A949F +P 19850 22550 +F 0 "Q52" H 19750 22600 50 0000 R CNN +F 1 "eSim_PNP" H 19800 22700 50 0000 R CNN +F 2 "" H 20050 22650 29 0000 C CNN +F 3 "" H 19850 22550 60 0000 C CNN + 1 19850 22550 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 668AF097 +P 17700 3650 +F 0 "U1" H 17750 3750 30 0000 C CNN +F 1 "PORT" H 17700 3650 30 0000 C CNN +F 2 "" H 17700 3650 60 0000 C CNN +F 3 "" H 17700 3650 60 0000 C CNN + 4 17700 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 668BFB6F +P 13750 6400 +F 0 "U1" H 13800 6500 30 0000 C CNN +F 1 "PORT" H 13750 6400 30 0000 C CNN +F 2 "" H 13750 6400 60 0000 C CNN +F 3 "" H 13750 6400 60 0000 C CNN + 1 13750 6400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 668C172A +P 1250 6700 +F 0 "U1" H 1300 6800 30 0000 C CNN +F 1 "PORT" H 1250 6700 30 0000 C CNN +F 2 "" H 1250 6700 60 0000 C CNN +F 3 "" H 1250 6700 60 0000 C CNN + 2 1250 6700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 668C2142 +P 7150 6700 +F 0 "U1" H 7200 6800 30 0000 C CNN +F 1 "PORT" H 7150 6700 30 0000 C CNN +F 2 "" H 7150 6700 60 0000 C CNN +F 3 "" H 7150 6700 60 0000 C CNN + 3 7150 6700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 668C5033 +P 2200 23600 +F 0 "U1" H 2250 23700 30 0000 C CNN +F 1 "PORT" H 2200 23600 30 0000 C CNN +F 2 "" H 2200 23600 60 0000 C CNN +F 3 "" H 2200 23600 60 0000 C CNN + 6 2200 23600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 668C6285 +P 8100 23600 +F 0 "U1" H 8150 23700 30 0000 C CNN +F 1 "PORT" H 8100 23600 30 0000 C CNN +F 2 "" H 8100 23600 60 0000 C CNN +F 3 "" H 8100 23600 60 0000 C CNN + 5 8100 23600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 668C7455 +P 14700 23300 +F 0 "U1" H 14750 23400 30 0000 C CNN +F 1 "PORT" H 14700 23300 30 0000 C CNN +F 2 "" H 14700 23300 60 0000 C CNN +F 3 "" H 14700 23300 60 0000 C CNN + 7 14700 23300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 668D0777 +P 20750 10300 +F 0 "U1" H 20800 10400 30 0000 C CNN +F 1 "PORT" H 20750 10300 30 0000 C CNN +F 2 "" H 20750 10300 60 0000 C CNN +F 3 "" H 20750 10300 60 0000 C CNN + 11 20750 10300 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q54 +U 1 1 668A7956 +P 27050 5000 +F 0 "Q54" H 26950 5050 50 0000 R CNN +F 1 "eSim_PNP" H 27000 5150 50 0000 R CNN +F 2 "" H 27250 5100 29 0000 C CNN +F 3 "" H 27050 5000 60 0000 C CNN + 1 27050 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q56 +U 1 1 668A795C +P 27500 5000 +F 0 "Q56" H 27400 5050 50 0000 R CNN +F 1 "eSim_PNP" H 27450 5150 50 0000 R CNN +F 2 "" H 27700 5100 29 0000 C CNN +F 3 "" H 27500 5000 60 0000 C CNN + 1 27500 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q67 +U 1 1 668A7962 +P 30750 5050 +F 0 "Q67" H 30650 5100 50 0000 R CNN +F 1 "eSim_PNP" H 30700 5200 50 0000 R CNN +F 2 "" H 30950 5150 29 0000 C CNN +F 3 "" H 30750 5050 60 0000 C CNN + 1 30750 5050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q69 +U 1 1 668A7968 +P 31200 5050 +F 0 "Q69" H 31100 5100 50 0000 R CNN +F 1 "eSim_PNP" H 31150 5200 50 0000 R CNN +F 2 "" H 31400 5150 29 0000 C CNN +F 3 "" H 31200 5050 60 0000 C CNN + 1 31200 5050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q55 +U 1 1 668A796E +P 27300 6200 +F 0 "Q55" H 27200 6250 50 0000 R CNN +F 1 "eSim_PNP" H 27250 6350 50 0000 R CNN +F 2 "" H 27500 6300 29 0000 C CNN +F 3 "" H 27300 6200 60 0000 C CNN + 1 27300 6200 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J14 +U 1 1 668A7974 +P 26850 7300 +F 0 "J14" H 26750 7350 50 0000 R CNN +F 1 "jfet_p" H 26800 7450 50 0000 R CNN +F 2 "" H 27050 7400 29 0000 C CNN +F 3 "" H 26850 7300 60 0000 C CNN + 1 26850 7300 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J13 +U 1 1 668A797A +P 26000 7300 +F 0 "J13" H 25900 7350 50 0000 R CNN +F 1 "jfet_p" H 25950 7450 50 0000 R CNN +F 2 "" H 26200 7400 29 0000 C CNN +F 3 "" H 26000 7300 60 0000 C CNN + 1 26000 7300 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J16 +U 1 1 668A7980 +P 27850 7300 +F 0 "J16" H 27750 7350 50 0000 R CNN +F 1 "jfet_p" H 27800 7450 50 0000 R CNN +F 2 "" H 28050 7400 29 0000 C CNN +F 3 "" H 27850 7300 60 0000 C CNN + 1 27850 7300 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J18 +U 1 1 668A7986 +P 28500 7300 +F 0 "J18" H 28400 7350 50 0000 R CNN +F 1 "jfet_p" H 28450 7450 50 0000 R CNN +F 2 "" H 28700 7400 29 0000 C CNN +F 3 "" H 28500 7300 60 0000 C CNN + 1 28500 7300 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q53 +U 1 1 668A798C +P 26550 9000 +F 0 "Q53" H 26450 9050 50 0000 R CNN +F 1 "eSim_NPN" H 26500 9150 50 0000 R CNN +F 2 "" H 26750 9100 29 0000 C CNN +F 3 "" H 26550 9000 60 0000 C CNN + 1 26550 9000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q58 +U 1 1 668A7992 +P 27850 9000 +F 0 "Q58" H 27750 9050 50 0000 R CNN +F 1 "eSim_NPN" H 27800 9150 50 0000 R CNN +F 2 "" H 28050 9100 29 0000 C CNN +F 3 "" H 27850 9000 60 0000 C CNN + 1 27850 9000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R23 +U 1 1 668A7998 +P 26400 10200 +F 0 "R23" H 26450 10330 50 0000 C CNN +F 1 "34" H 26450 10150 50 0000 C CNN +F 2 "" H 26450 10180 30 0000 C CNN +F 3 "" V 26450 10250 30 0000 C CNN + 1 26400 10200 + 0 1 1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 668A799E +P 27900 10200 +F 0 "R25" H 27950 10330 50 0000 C CNN +F 1 "35" H 27950 10150 50 0000 C CNN +F 2 "" H 27950 10180 30 0000 C CNN +F 3 "" V 27950 10250 30 0000 C CNN + 1 27900 10200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q66 +U 1 1 668A79A4 +P 30600 6050 +F 0 "Q66" H 30500 6100 50 0000 R CNN +F 1 "eSim_NPN" H 30550 6200 50 0000 R CNN +F 2 "" H 30800 6150 29 0000 C CNN +F 3 "" H 30600 6050 60 0000 C CNN + 1 30600 6050 + 1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 668A79AA +P 31450 5800 +F 0 "R29" H 31500 5930 50 0000 C CNN +F 1 "220" H 31500 5750 50 0000 C CNN +F 2 "" H 31500 5780 30 0000 C CNN +F 3 "" V 31500 5850 30 0000 C CNN + 1 31450 5800 + 0 1 1 0 +$EndComp +$Comp +L resistor R28 +U 1 1 668A79B0 +P 30650 6700 +F 0 "R28" H 30700 6830 50 0000 C CNN +F 1 "45k" H 30700 6650 50 0000 C CNN +F 2 "" H 30700 6680 30 0000 C CNN +F 3 "" V 30700 6750 30 0000 C CNN + 1 30650 6700 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q65 +U 1 1 668A79B6 +P 30350 8050 +F 0 "Q65" H 30250 8100 50 0000 R CNN +F 1 "eSim_NPN" H 30300 8200 50 0000 R CNN +F 2 "" H 30550 8150 29 0000 C CNN +F 3 "" H 30350 8050 60 0000 C CNN + 1 30350 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q68 +U 1 1 668A79BC +P 30800 8050 +F 0 "Q68" H 30700 8100 50 0000 R CNN +F 1 "eSim_NPN" H 30750 8200 50 0000 R CNN +F 2 "" H 31000 8150 29 0000 C CNN +F 3 "" H 30800 8050 60 0000 C CNN + 1 30800 8050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q70 +U 1 1 668A79C2 +P 31400 6450 +F 0 "Q70" H 31300 6500 50 0000 R CNN +F 1 "eSim_NPN" H 31350 6600 50 0000 R CNN +F 2 "" H 31600 6550 29 0000 C CNN +F 3 "" H 31400 6450 60 0000 C CNN + 1 31400 6450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q62 +U 1 1 668A79C8 +P 28650 9500 +F 0 "Q62" H 28550 9550 50 0000 R CNN +F 1 "eSim_NPN" H 28600 9650 50 0000 R CNN +F 2 "" H 28850 9600 29 0000 C CNN +F 3 "" H 28650 9500 60 0000 C CNN + 1 28650 9500 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C3 +U 1 1 668A79CE +P 28950 8300 +F 0 "C3" H 28975 8400 50 0000 L CNN +F 1 "10p" H 28975 8200 50 0000 L CNN +F 2 "" H 28988 8150 30 0000 C CNN +F 3 "" H 28950 8300 60 0000 C CNN + 1 28950 8300 + 0 1 1 0 +$EndComp +$Comp +L resistor R27 +U 1 1 668A79D4 +P 30600 9900 +F 0 "R27" H 30650 10030 50 0000 C CNN +F 1 "7" H 30650 9850 50 0000 C CNN +F 2 "" H 30650 9880 30 0000 C CNN +F 3 "" V 30650 9950 30 0000 C CNN + 1 30600 9900 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q78 +U 1 1 668A79DA +P 33750 6200 +F 0 "Q78" H 33650 6250 50 0000 R CNN +F 1 "eSim_NPN" H 33700 6350 50 0000 R CNN +F 2 "" H 33950 6300 29 0000 C CNN +F 3 "" H 33750 6200 60 0000 C CNN + 1 33750 6200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q81 +U 1 1 668A79E0 +P 34250 6200 +F 0 "Q81" H 34150 6250 50 0000 R CNN +F 1 "eSim_NPN" H 34200 6350 50 0000 R CNN +F 2 "" H 34450 6300 29 0000 C CNN +F 3 "" H 34250 6200 60 0000 C CNN + 1 34250 6200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R34 +U 1 1 668A79E6 +P 34100 7400 +F 0 "R34" H 34150 7530 50 0000 C CNN +F 1 "270" H 34150 7350 50 0000 C CNN +F 2 "" H 34150 7380 30 0000 C CNN +F 3 "" V 34150 7450 30 0000 C CNN + 1 34100 7400 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q79 +U 1 1 668A79EC +P 33950 8300 +F 0 "Q79" H 33850 8350 50 0000 R CNN +F 1 "eSim_PNP" H 33900 8450 50 0000 R CNN +F 2 "" H 34150 8400 29 0000 C CNN +F 3 "" H 33950 8300 60 0000 C CNN + 1 33950 8300 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q82 +U 1 1 668A79F2 +P 34350 8300 +F 0 "Q82" H 34250 8350 50 0000 R CNN +F 1 "eSim_PNP" H 34300 8450 50 0000 R CNN +F 2 "" H 34550 8400 29 0000 C CNN +F 3 "" H 34350 8300 60 0000 C CNN + 1 34350 8300 + 1 0 0 1 +$EndComp +$Comp +L resistor R36 +U 1 1 668A79F8 +P 34750 6950 +F 0 "R36" H 34800 7080 50 0000 C CNN +F 1 "64" H 34800 6900 50 0000 C CNN +F 2 "" H 34800 6930 30 0000 C CNN +F 3 "" V 34800 7000 30 0000 C CNN + 1 34750 6950 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q77 +U 1 1 668A79FE +P 32950 6800 +F 0 "Q77" H 32850 6850 50 0000 R CNN +F 1 "eSim_NPN" H 32900 6950 50 0000 R CNN +F 2 "" H 33150 6900 29 0000 C CNN +F 3 "" H 32950 6800 60 0000 C CNN + 1 32950 6800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q91 +U 1 1 668A7A04 +P 38350 5000 +F 0 "Q91" H 38250 5050 50 0000 R CNN +F 1 "eSim_PNP" H 38300 5150 50 0000 R CNN +F 2 "" H 38550 5100 29 0000 C CNN +F 3 "" H 38350 5000 60 0000 C CNN + 1 38350 5000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q89 +U 1 1 668A7A0A +P 38200 5900 +F 0 "Q89" H 38100 5950 50 0000 R CNN +F 1 "eSim_PNP" H 38150 6050 50 0000 R CNN +F 2 "" H 38400 6000 29 0000 C CNN +F 3 "" H 38200 5900 60 0000 C CNN + 1 38200 5900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q93 +U 1 1 668A7A10 +P 38600 5900 +F 0 "Q93" H 38500 5950 50 0000 R CNN +F 1 "eSim_PNP" H 38550 6050 50 0000 R CNN +F 2 "" H 38800 6000 29 0000 C CNN +F 3 "" H 38600 5900 60 0000 C CNN + 1 38600 5900 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J21 +U 1 1 668A7A16 +P 37950 7200 +F 0 "J21" H 37850 7250 50 0000 R CNN +F 1 "jfet_p" H 37900 7350 50 0000 R CNN +F 2 "" H 38150 7300 29 0000 C CNN +F 3 "" H 37950 7200 60 0000 C CNN + 1 37950 7200 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J23 +U 1 1 668A7A1C +P 39150 7200 +F 0 "J23" H 39050 7250 50 0000 R CNN +F 1 "jfet_p" H 39100 7350 50 0000 R CNN +F 2 "" H 39350 7300 29 0000 C CNN +F 3 "" H 39150 7200 60 0000 C CNN + 1 39150 7200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q92 +U 1 1 668A7A22 +P 38350 8650 +F 0 "Q92" H 38250 8700 50 0000 R CNN +F 1 "eSim_NPN" H 38300 8800 50 0000 R CNN +F 2 "" H 38550 8750 29 0000 C CNN +F 3 "" H 38350 8650 60 0000 C CNN + 1 38350 8650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q94 +U 1 1 668A7A28 +P 38800 8650 +F 0 "Q94" H 38700 8700 50 0000 R CNN +F 1 "eSim_NPN" H 38750 8800 50 0000 R CNN +F 2 "" H 39000 8750 29 0000 C CNN +F 3 "" H 38800 8650 60 0000 C CNN + 1 38800 8650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q88 +U 1 1 668A7A2E +P 37950 8650 +F 0 "Q88" H 37850 8700 50 0000 R CNN +F 1 "eSim_NPN" H 37900 8800 50 0000 R CNN +F 2 "" H 38150 8750 29 0000 C CNN +F 3 "" H 37950 8650 60 0000 C CNN + 1 37950 8650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R39 +U 1 1 668A7A34 +P 37200 8050 +F 0 "R39" H 37250 8180 50 0000 C CNN +F 1 "3.5k" H 37250 8000 50 0000 C CNN +F 2 "" H 37250 8030 30 0000 C CNN +F 3 "" V 37250 8100 30 0000 C CNN + 1 37200 8050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q87 +U 1 1 668A7A3A +P 37150 9100 +F 0 "Q87" H 37050 9150 50 0000 R CNN +F 1 "eSim_NPN" H 37100 9250 50 0000 R CNN +F 2 "" H 37350 9200 29 0000 C CNN +F 3 "" H 37150 9100 60 0000 C CNN + 1 37150 9100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q101 +U 1 1 668A7A40 +P 41050 5300 +F 0 "Q101" H 40950 5350 50 0000 R CNN +F 1 "eSim_NPN" H 41000 5450 50 0000 R CNN +F 2 "" H 41250 5400 29 0000 C CNN +F 3 "" H 41050 5300 60 0000 C CNN + 1 41050 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q102 +U 1 1 668A7A46 +P 41050 6250 +F 0 "Q102" H 40950 6300 50 0000 R CNN +F 1 "eSim_PNP" H 41000 6400 50 0000 R CNN +F 2 "" H 41250 6350 29 0000 C CNN +F 3 "" H 41050 6250 60 0000 C CNN + 1 41050 6250 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 668A7B49 +P 35900 7000 +F 0 "U1" H 35950 7100 30 0000 C CNN +F 1 "PORT" H 35900 7000 30 0000 C CNN +F 2 "" H 35900 7000 60 0000 C CNN +F 3 "" H 35900 7000 60 0000 C CNN + 14 35900 7000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 13 1 668A7B4F +P 23400 7300 +F 0 "U1" H 23450 7400 30 0000 C CNN +F 1 "PORT" H 23400 7300 30 0000 C CNN +F 2 "" H 23400 7300 60 0000 C CNN +F 3 "" H 23400 7300 60 0000 C CNN + 13 23400 7300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 668A7B55 +P 29300 7300 +F 0 "U1" H 29350 7400 30 0000 C CNN +F 1 "PORT" H 29300 7300 30 0000 C CNN +F 2 "" H 29300 7300 60 0000 C CNN +F 3 "" H 29300 7300 60 0000 C CNN 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15700 7050 14950 7050 +Wire Wire Line + 15700 6800 15700 7050 +Connection ~ 15100 7250 +Wire Wire Line + 14650 8500 14650 7250 +Wire Wire Line + 14800 8500 14650 8500 +Connection ~ 12100 10300 +Wire Wire Line + 15100 10300 15100 8700 +Wire Wire Line + 15100 7650 15100 8300 +Wire Wire Line + 15100 7250 15100 7350 +Wire Wire Line + 14650 7250 16900 7250 +Wire Wire Line + 16900 7250 16900 6800 +Connection ~ 16650 6600 +Wire Wire Line + 16650 6600 16000 6600 +Connection ~ 16650 5800 +Wire Wire Line + 16350 5800 16650 5800 +Wire Wire Line + 16350 5500 16350 5800 +Connection ~ 16650 6250 +Wire Wire Line + 16650 6250 16900 6250 +Wire Wire Line + 16900 6250 16900 6400 +Connection ~ 16650 7750 +Wire Wire Line + 16650 7750 16650 5300 +Wire Wire Line + 16650 5300 16250 5300 +Connection ~ 16300 7750 +Wire Wire Line + 16300 7850 16300 7750 +Wire Wire Line + 16750 7750 16750 7850 +Wire Wire Line + 15900 7750 16750 7750 +Wire Wire Line + 15900 7850 15900 7750 +Connection ~ 16000 8050 +Wire Wire Line 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9500 +Wire Wire Line + 8500 8500 8500 9200 +Connection ~ 5800 10300 +Wire Wire Line + 6400 10300 6400 9100 +Connection ~ 8550 6950 +Wire Wire Line + 7150 6950 8550 6950 +Wire Wire Line + 7150 7700 7150 6950 +Wire Wire Line + 6950 7700 7150 7700 +Connection ~ 6400 7700 +Wire Wire Line + 6400 7700 6400 8700 +Connection ~ 5800 7700 +Wire Wire Line + 5800 7700 6650 7700 +Wire Wire Line + 8450 7450 8000 7450 +Wire Wire Line + 8750 7800 8750 7650 +Wire Wire Line + 8300 7650 8300 8500 +Connection ~ 8550 5850 +Wire Wire Line + 9050 5850 8550 5850 +Wire Wire Line + 9350 5400 9350 5650 +Wire Wire Line + 8550 5650 8550 6000 +Wire Wire Line + 8750 7200 8750 7250 +Wire Wire Line + 8300 7250 8300 7200 +Connection ~ 8550 5000 +Wire Wire Line + 8100 5450 8100 5000 +Wire Wire Line + 8250 5450 8100 5450 +Connection ~ 8900 4750 +Connection ~ 8900 5000 +Wire Wire Line + 8900 5000 8900 4750 +Wire Wire Line + 9150 4750 9150 4650 +Wire Wire Line + 8700 4750 9150 4750 +Wire Wire Line + 8700 4650 8700 4750 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Line + 17850 24150 17850 23700 +Connection ~ 17600 23500 +Wire Wire Line + 17600 23500 16950 23500 +Connection ~ 17600 22700 +Wire Wire Line + 17300 22700 17600 22700 +Wire Wire Line + 17300 22400 17300 22700 +Connection ~ 17600 23150 +Wire Wire Line + 17600 23150 17850 23150 +Wire Wire Line + 17850 23150 17850 23300 +Connection ~ 17600 24650 +Wire Wire Line + 17600 24650 17600 22200 +Wire Wire Line + 17600 22200 17200 22200 +Connection ~ 17250 24650 +Wire Wire Line + 17250 24750 17250 24650 +Wire Wire Line + 17700 24650 17700 24750 +Wire Wire Line + 16850 24650 17700 24650 +Wire Wire Line + 16850 24750 16850 24650 +Connection ~ 16950 24950 +Wire Wire Line + 16050 24950 17400 24950 +Wire Wire Line + 16650 22850 16650 23300 +Wire Wire Line + 16900 22850 16650 22850 +Wire Wire Line + 16900 22400 16900 22850 +Connection ~ 17050 21950 +Wire Wire Line + 17050 21500 17050 21950 +Wire Wire Line + 17300 21950 17300 22000 +Wire Wire Line + 16900 21950 17300 21950 +Wire Wire Line + 16900 22000 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H 31650 21400 60 0000 C CNN + 1 31650 21400 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q60 +U 1 1 668B1BFE +P 27750 22550 +F 0 "Q60" H 27650 22600 50 0000 R CNN +F 1 "eSim_PNP" H 27700 22700 50 0000 R CNN +F 2 "" H 27950 22650 29 0000 C CNN +F 3 "" H 27750 22550 60 0000 C CNN + 1 27750 22550 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J17 +U 1 1 668B1C04 +P 27300 23650 +F 0 "J17" H 27200 23700 50 0000 R CNN +F 1 "jfet_p" H 27250 23800 50 0000 R CNN +F 2 "" H 27500 23750 29 0000 C CNN +F 3 "" H 27300 23650 60 0000 C CNN + 1 27300 23650 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J15 +U 1 1 668B1C0A +P 26450 23650 +F 0 "J15" H 26350 23700 50 0000 R CNN +F 1 "jfet_p" H 26400 23800 50 0000 R CNN +F 2 "" H 26650 23750 29 0000 C CNN +F 3 "" H 26450 23650 60 0000 C CNN + 1 26450 23650 + 1 0 0 -1 +$EndComp +$Comp +L jfet_p J19 +U 1 1 668B1C10 +P 28300 23650 +F 0 "J19" H 28200 23700 50 0000 R CNN +F 1 "jfet_p" H 28250 23800 50 0000 R CNN +F 2 "" H 28500 23750 29 0000 C CNN +F 3 "" H 28300 23650 60 0000 C CNN + 1 28300 23650 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J20 +U 1 1 668B1C16 +P 28950 23650 +F 0 "J20" H 28850 23700 50 0000 R CNN +F 1 "jfet_p" H 28900 23800 50 0000 R CNN +F 2 "" H 29150 23750 29 0000 C CNN +F 3 "" H 28950 23650 60 0000 C CNN + 1 28950 23650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q57 +U 1 1 668B1C1C +P 27000 25350 +F 0 "Q57" H 26900 25400 50 0000 R CNN +F 1 "eSim_NPN" H 26950 25500 50 0000 R CNN +F 2 "" H 27200 25450 29 0000 C CNN +F 3 "" H 27000 25350 60 0000 C CNN + 1 27000 25350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q63 +U 1 1 668B1C22 +P 28300 25350 +F 0 "Q63" H 28200 25400 50 0000 R CNN +F 1 "eSim_NPN" H 28250 25500 50 0000 R CNN +F 2 "" H 28500 25450 29 0000 C CNN +F 3 "" H 28300 25350 60 0000 C CNN + 1 28300 25350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R24 +U 1 1 668B1C28 +P 26850 26550 +F 0 "R24" H 26900 26680 50 0000 C CNN +F 1 "34" H 26900 26500 50 0000 C CNN +F 2 "" H 26900 26530 30 0000 C CNN +F 3 "" V 26900 26600 30 0000 C CNN + 1 26850 26550 + 0 1 1 0 +$EndComp +$Comp +L resistor R26 +U 1 1 668B1C2E +P 28350 26550 +F 0 "R26" H 28400 26680 50 0000 C CNN +F 1 "35" H 28400 26500 50 0000 C CNN +F 2 "" H 28400 26530 30 0000 C CNN +F 3 "" V 28400 26600 30 0000 C CNN + 1 28350 26550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q72 +U 1 1 668B1C34 +P 31050 22400 +F 0 "Q72" H 30950 22450 50 0000 R CNN +F 1 "eSim_NPN" H 31000 22550 50 0000 R CNN +F 2 "" H 31250 22500 29 0000 C CNN +F 3 "" H 31050 22400 60 0000 C CNN + 1 31050 22400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R32 +U 1 1 668B1C3A +P 31900 22150 +F 0 "R32" H 31950 22280 50 0000 C CNN +F 1 "220" H 31950 22100 50 0000 C CNN +F 2 "" H 31950 22130 30 0000 C CNN +F 3 "" V 31950 22200 30 0000 C CNN + 1 31900 22150 + 0 1 1 0 +$EndComp +$Comp +L resistor R31 +U 1 1 668B1C40 +P 31100 23050 +F 0 "R31" H 31150 23180 50 0000 C CNN +F 1 "45k" H 31150 23000 50 0000 C CNN +F 2 "" H 31150 23030 30 0000 C CNN +F 3 "" V 31150 23100 30 0000 C CNN + 1 31100 23050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q71 +U 1 1 668B1C46 +P 30800 24400 +F 0 "Q71" H 30700 24450 50 0000 R CNN +F 1 "eSim_NPN" H 30750 24550 50 0000 R CNN +F 2 "" H 31000 24500 29 0000 C CNN +F 3 "" H 30800 24400 60 0000 C CNN + 1 30800 24400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q74 +U 1 1 668B1C4C +P 31250 24400 +F 0 "Q74" H 31150 24450 50 0000 R CNN +F 1 "eSim_NPN" H 31200 24550 50 0000 R CNN +F 2 "" H 31450 24500 29 0000 C CNN +F 3 "" H 31250 24400 60 0000 C CNN + 1 31250 24400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q76 +U 1 1 668B1C52 +P 31850 22800 +F 0 "Q76" H 31750 22850 50 0000 R CNN +F 1 "eSim_NPN" H 31800 22950 50 0000 R CNN +F 2 "" H 32050 22900 29 0000 C CNN +F 3 "" H 31850 22800 60 0000 C CNN + 1 31850 22800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q64 +U 1 1 668B1C58 +P 29100 25850 +F 0 "Q64" H 29000 25900 50 0000 R CNN +F 1 "eSim_NPN" H 29050 26000 50 0000 R CNN +F 2 "" H 29300 25950 29 0000 C CNN +F 3 "" H 29100 25850 60 0000 C CNN + 1 29100 25850 + -1 0 0 -1 +$EndComp +$Comp +L capacitor C4 +U 1 1 668B1C5E +P 29400 24650 +F 0 "C4" H 29425 24750 50 0000 L CNN +F 1 "10p" H 29425 24550 50 0000 L CNN +F 2 "" H 29438 24500 30 0000 C CNN +F 3 "" H 29400 24650 60 0000 C CNN + 1 29400 24650 + 0 1 1 0 +$EndComp +$Comp +L resistor R30 +U 1 1 668B1C64 +P 31050 26250 +F 0 "R30" H 31100 26380 50 0000 C CNN +F 1 "7" H 31100 26200 50 0000 C CNN +F 2 "" H 31100 26230 30 0000 C CNN +F 3 "" V 31100 26300 30 0000 C CNN + 1 31050 26250 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q83 +U 1 1 668B1C6A +P 34200 22550 +F 0 "Q83" H 34100 22600 50 0000 R CNN +F 1 "eSim_NPN" H 34150 22700 50 0000 R CNN +F 2 "" H 34400 22650 29 0000 C CNN +F 3 "" H 34200 22550 60 0000 C CNN + 1 34200 22550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q85 +U 1 1 668B1C70 +P 34700 22550 +F 0 "Q85" H 34600 22600 50 0000 R CNN +F 1 "eSim_NPN" H 34650 22700 50 0000 R CNN +F 2 "" H 34900 22650 29 0000 C CNN +F 3 "" H 34700 22550 60 0000 C CNN + 1 34700 22550 + 1 0 0 -1 +$EndComp +$Comp +L resistor R37 +U 1 1 668B1C76 +P 34550 23750 +F 0 "R37" H 34600 23880 50 0000 C CNN +F 1 "270" H 34600 23700 50 0000 C CNN +F 2 "" H 34600 23730 30 0000 C CNN +F 3 "" V 34600 23800 30 0000 C CNN + 1 34550 23750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q84 +U 1 1 668B1C7C +P 34400 24650 +F 0 "Q84" H 34300 24700 50 0000 R CNN +F 1 "eSim_PNP" H 34350 24800 50 0000 R CNN +F 2 "" H 34600 24750 29 0000 C CNN +F 3 "" H 34400 24650 60 0000 C CNN + 1 34400 24650 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q86 +U 1 1 668B1C82 +P 34800 24650 +F 0 "Q86" H 34700 24700 50 0000 R CNN +F 1 "eSim_PNP" H 34750 24800 50 0000 R CNN +F 2 "" H 35000 24750 29 0000 C CNN +F 3 "" H 34800 24650 60 0000 C CNN + 1 34800 24650 + 1 0 0 1 +$EndComp +$Comp +L resistor R38 +U 1 1 668B1C88 +P 35200 23300 +F 0 "R38" H 35250 23430 50 0000 C CNN +F 1 "64" H 35250 23250 50 0000 C CNN +F 2 "" H 35250 23280 30 0000 C CNN +F 3 "" V 35250 23350 30 0000 C CNN + 1 35200 23300 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q80 +U 1 1 668B1C8E +P 33400 23150 +F 0 "Q80" H 33300 23200 50 0000 R CNN +F 1 "eSim_NPN" H 33350 23300 50 0000 R CNN +F 2 "" H 33600 23250 29 0000 C CNN +F 3 "" H 33400 23150 60 0000 C CNN + 1 33400 23150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q97 +U 1 1 668B1C94 +P 38800 21350 +F 0 "Q97" H 38700 21400 50 0000 R CNN +F 1 "eSim_PNP" H 38750 21500 50 0000 R CNN +F 2 "" H 39000 21450 29 0000 C CNN +F 3 "" H 38800 21350 60 0000 C CNN + 1 38800 21350 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q96 +U 1 1 668B1C9A +P 38650 22250 +F 0 "Q96" H 38550 22300 50 0000 R CNN +F 1 "eSim_PNP" H 38600 22400 50 0000 R CNN +F 2 "" H 38850 22350 29 0000 C CNN +F 3 "" H 38650 22250 60 0000 C CNN + 1 38650 22250 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q99 +U 1 1 668B1CA0 +P 39050 22250 +F 0 "Q99" H 38950 22300 50 0000 R CNN +F 1 "eSim_PNP" H 39000 22400 50 0000 R CNN +F 2 "" H 39250 22350 29 0000 C CNN +F 3 "" H 39050 22250 60 0000 C CNN + 1 39050 22250 + -1 0 0 1 +$EndComp +$Comp +L jfet_p J22 +U 1 1 668B1CA6 +P 38400 23550 +F 0 "J22" H 38300 23600 50 0000 R CNN +F 1 "jfet_p" H 38350 23700 50 0000 R CNN +F 2 "" H 38600 23650 29 0000 C CNN +F 3 "" H 38400 23550 60 0000 C CNN + 1 38400 23550 + -1 0 0 -1 +$EndComp +$Comp +L jfet_p J24 +U 1 1 668B1CAC +P 39600 23550 +F 0 "J24" H 39500 23600 50 0000 R CNN +F 1 "jfet_p" H 39550 23700 50 0000 R CNN +F 2 "" H 39800 23650 29 0000 C CNN +F 3 "" H 39600 23550 60 0000 C CNN + 1 39600 23550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q98 +U 1 1 668B1CB2 +P 38800 25000 +F 0 "Q98" H 38700 25050 50 0000 R CNN +F 1 "eSim_NPN" H 38750 25150 50 0000 R CNN +F 2 "" H 39000 25100 29 0000 C CNN +F 3 "" H 38800 25000 60 0000 C CNN + 1 38800 25000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q100 +U 1 1 668B1CB8 +P 39250 25000 +F 0 "Q100" H 39150 25050 50 0000 R CNN +F 1 "eSim_NPN" H 39200 25150 50 0000 R CNN +F 2 "" H 39450 25100 29 0000 C CNN +F 3 "" H 39250 25000 60 0000 C CNN + 1 39250 25000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q95 +U 1 1 668B1CBE +P 38400 25000 +F 0 "Q95" H 38300 25050 50 0000 R CNN +F 1 "eSim_NPN" H 38350 25150 50 0000 R CNN +F 2 "" H 38600 25100 29 0000 C CNN +F 3 "" H 38400 25000 60 0000 C CNN + 1 38400 25000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R40 +U 1 1 668B1CC4 +P 37650 24400 +F 0 "R40" H 37700 24530 50 0000 C CNN +F 1 "3.5k" H 37700 24350 50 0000 C CNN +F 2 "" H 37700 24380 30 0000 C CNN +F 3 "" V 37700 24450 30 0000 C CNN + 1 37650 24400 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q90 +U 1 1 668B1CCA +P 37600 25450 +F 0 "Q90" H 37500 25500 50 0000 R CNN +F 1 "eSim_NPN" H 37550 25600 50 0000 R CNN +F 2 "" H 37800 25550 29 0000 C CNN +F 3 "" H 37600 25450 60 0000 C CNN + 1 37600 25450 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q103 +U 1 1 668B1CD0 +P 41500 21650 +F 0 "Q103" H 41400 21700 50 0000 R CNN +F 1 "eSim_NPN" H 41450 21800 50 0000 R CNN +F 2 "" H 41700 21750 29 0000 C CNN +F 3 "" H 41500 21650 60 0000 C CNN + 1 41500 21650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q104 +U 1 1 668B1CD6 +P 41500 22600 +F 0 "Q104" H 41400 22650 50 0000 R CNN +F 1 "eSim_PNP" H 41450 22750 50 0000 R CNN +F 2 "" H 41700 22700 29 0000 C CNN +F 3 "" H 41500 22600 60 0000 C CNN + 1 41500 22600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 9 1 668B1CE8 +P 23850 23650 +F 0 "U1" H 23900 23750 30 0000 C CNN +F 1 "PORT" H 23850 23650 30 0000 C CNN +F 2 "" H 23850 23650 60 0000 C CNN +F 3 "" H 23850 23650 60 0000 C CNN + 9 23850 23650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 668B1CEE +P 29750 23650 +F 0 "U1" H 29800 23750 30 0000 C CNN +F 1 "PORT" H 29750 23650 30 0000 C CNN +F 2 "" H 29750 23650 60 0000 C CNN +F 3 "" H 29750 23650 60 0000 C CNN + 10 29750 23650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 668B1CF4 +P 36350 23350 +F 0 "U1" H 36400 23450 30 0000 C CNN +F 1 "PORT" H 36350 23350 30 0000 C CNN +F 2 "" H 36350 23350 60 0000 C CNN +F 3 "" H 36350 23350 60 0000 C CNN + 8 36350 23350 + -1 0 0 1 +$EndComp +Connection ~ 34600 24250 +Wire Wire Line + 34500 24250 34600 24250 +Wire Wire Line + 34600 23950 34600 24300 +Wire Wire Line + 34600 24300 34900 24300 +Connection ~ 30900 24750 +Wire Wire Line + 31350 24750 30900 24750 +Wire Wire Line + 30900 25450 31100 25450 +Connection ~ 31150 24150 +Wire Wire Line + 31150 23250 31150 24150 +Wire Wire Line + 30900 24150 31350 24150 +Connection ~ 27850 21100 +Wire Wire Line + 27400 21100 27850 21100 +Connection ~ 31550 21050 +Wire Wire Line + 31500 21050 31550 21050 +Wire Wire Line + 31500 21150 31500 21050 +Wire Wire Line + 31300 21150 31500 21150 +Wire Wire Line + 31550 20750 31550 21150 +Wire Wire Line + 31550 21150 31750 21150 +Connection ~ 29000 25100 +Wire Wire Line + 30600 25100 29000 25100 +Wire Wire Line + 30600 24400 30600 25100 +Connection ~ 34600 23150 +Wire Wire Line + 33600 23150 34600 23150 +Connection ~ 29150 23650 +Wire Wire Line + 24100 23650 27100 23650 +Connection ~ 26250 23650 +Connection ~ 41600 27250 +Connection ~ 38700 20750 +Connection ~ 40950 21350 +Wire Wire Line + 40950 21350 40950 21650 +Wire Wire Line + 40950 21650 41300 21650 +Connection ~ 41600 22050 +Wire Wire Line + 29500 22550 27950 22550 +Wire Wire Line + 29500 22050 29500 22550 +Wire Wire Line + 41600 22050 29500 22050 +Connection ~ 39350 27250 +Wire Wire Line + 41600 27250 41600 22800 +Connection ~ 39800 22600 +Wire Wire Line + 41300 22600 39800 22600 +Wire Wire Line + 41600 21850 41600 22400 +Connection ~ 39000 21350 +Wire Wire Line + 41600 21350 41600 21450 +Connection ~ 38700 21800 +Wire Wire Line + 39800 21800 38700 21800 +Wire Wire Line + 39800 21800 39800 23550 +Connection ~ 39350 25500 +Wire Wire Line + 39350 25500 38500 25500 +Wire Wire Line + 38500 25500 38500 25200 +Connection ~ 39350 25350 +Wire Wire Line + 38900 25350 39350 25350 +Wire Wire Line + 38900 25200 38900 25350 +Connection ~ 37700 27250 +Wire Wire Line + 39350 27250 39350 25200 +Connection ~ 38200 25000 +Connection ~ 37700 25000 +Connection ~ 37550 24200 +Wire Wire Line + 37550 24000 37550 24200 +Wire Wire Line + 38300 24000 37550 24000 +Wire Wire Line + 38300 23750 38300 24000 +Connection ~ 37700 24200 +Wire Wire Line + 37250 25450 37250 24200 +Wire Wire Line + 37400 25450 37250 25450 +Connection ~ 34700 27250 +Wire Wire Line + 37700 27250 37700 25650 +Wire Wire Line + 37700 24600 37700 25250 +Wire Wire Line + 37700 24200 37700 24300 +Wire Wire Line + 37250 24200 39500 24200 +Wire Wire Line + 39500 24200 39500 23750 +Connection ~ 39250 23550 +Wire Wire Line + 39250 23550 38600 23550 +Connection ~ 39250 22750 +Wire Wire Line + 38950 22750 39250 22750 +Wire Wire Line + 38950 22450 38950 22750 +Connection ~ 39250 23200 +Wire Wire Line + 39250 23200 39500 23200 +Wire Wire Line + 39500 23200 39500 23350 +Connection ~ 39250 24700 +Wire Wire Line + 39250 24700 39250 22250 +Wire Wire Line + 39250 22250 38850 22250 +Connection ~ 38900 24700 +Wire Wire Line + 38900 24800 38900 24700 +Wire Wire Line + 39350 24700 39350 24800 +Wire Wire Line + 38500 24700 39350 24700 +Wire Wire Line + 38500 24800 38500 24700 +Connection ~ 38600 25000 +Wire Wire Line + 37700 25000 39050 25000 +Wire Wire Line + 38300 22900 38300 23350 +Wire Wire Line + 38550 22900 38300 22900 +Wire Wire Line + 38550 22450 38550 22900 +Connection ~ 38700 22000 +Wire Wire Line + 38700 21550 38700 22000 +Wire Wire Line + 38950 22000 38950 22050 +Wire Wire Line + 38550 22000 38950 22000 +Wire Wire Line + 38550 22050 38550 22000 +Connection ~ 31450 21400 +Wire Wire Line + 31900 21400 31900 21350 +Wire Wire Line + 31900 21350 41600 21350 +Connection ~ 34550 20750 +Connection ~ 31000 21400 +Wire Wire Line + 28150 21350 28150 21400 +Connection ~ 35700 23350 +Wire Wire Line + 35700 23550 35700 23350 +Wire Wire Line + 33300 23550 35700 23550 +Wire Wire Line + 33300 23350 33300 23550 +Connection ~ 33300 22550 +Wire Wire Line + 33300 22950 33300 22550 +Connection ~ 31950 24050 +Wire Wire Line + 31950 23000 31950 24050 +Connection ~ 34000 22550 +Connection ~ 31950 22550 +Wire Wire Line + 35300 23350 36100 23350 +Connection ~ 34600 23350 +Wire Wire Line + 34600 23350 35000 23350 +Connection ~ 34700 24900 +Connection ~ 31100 27250 +Wire Wire Line + 34700 27250 34700 24900 +Connection ~ 34200 24650 +Connection ~ 31150 24050 +Wire Wire Line + 31150 24050 33750 24050 +Wire Wire Line + 33750 24050 33750 24650 +Wire Wire Line + 34900 24900 34900 24850 +Wire Wire Line + 34500 24900 34900 24900 +Wire Wire Line + 34500 24850 34500 24900 +Wire Wire Line + 34900 24300 34900 24450 +Wire Wire Line + 34500 24250 34500 24450 +Wire Wire Line + 33750 24650 34600 24650 +Connection ~ 34600 22850 +Wire Wire Line + 34600 22850 34600 23650 +Wire Wire Line + 34800 22850 34800 22750 +Wire Wire Line + 34300 22850 34800 22850 +Wire Wire Line + 34300 22750 34300 22850 +Connection ~ 34550 22250 +Connection ~ 31550 20750 +Wire Wire Line + 34550 20750 34550 22250 +Wire Wire Line + 34800 22250 34800 22350 +Wire Wire Line + 34300 22250 34800 22250 +Wire Wire Line + 34300 22350 34300 22250 +Wire Wire Line + 31950 22550 34500 22550 +Connection ~ 31100 25850 +Wire Wire Line + 29300 25850 31100 25850 +Connection ~ 29000 27250 +Wire Wire Line + 31100 27250 31100 26450 +Wire Wire Line + 31100 25450 31100 26150 +Connection ~ 28400 27250 +Wire Wire Line + 29000 27250 29000 26050 +Connection ~ 31150 23900 +Wire Wire Line + 29750 23900 31150 23900 +Wire Wire Line + 29750 24650 29750 23900 +Wire Wire Line + 29550 24650 29750 24650 +Connection ~ 29000 24650 +Wire Wire Line + 29000 24650 29000 25650 +Connection ~ 28400 24650 +Wire Wire Line + 28400 24650 29250 24650 +Wire Wire Line + 31050 24400 30600 24400 +Wire Wire Line + 31350 24750 31350 24600 +Wire Wire Line + 30900 24600 30900 25450 +Connection ~ 31150 22800 +Wire Wire Line + 31650 22800 31150 22800 +Wire Wire Line + 31950 22350 31950 22600 +Wire Wire Line + 31150 22600 31150 22950 +Wire Wire Line + 31350 24150 31350 24200 +Wire Wire Line + 30900 24200 30900 24150 +Connection ~ 31150 21950 +Wire Wire Line + 30700 22400 30700 21950 +Wire Wire Line + 30850 22400 30700 22400 +Connection ~ 31500 21700 +Connection ~ 31500 21950 +Wire Wire Line + 31500 21950 31500 21700 +Wire Wire Line + 31750 21700 31750 21600 +Wire Wire Line + 31300 21700 31750 21700 +Wire Wire Line + 31300 21600 31300 21700 +Wire Wire Line + 31950 21950 31950 22050 +Wire Wire Line + 30700 21950 31950 21950 +Wire Wire Line + 31150 22200 31150 21950 +Wire Wire Line + 28400 27250 28400 26750 +Wire Wire Line + 26900 27250 43700 27250 +Wire Wire Line + 26900 26750 26900 27250 +Wire Wire Line + 28400 25550 28400 26450 +Wire Wire Line + 26900 25550 26900 26450 +Connection ~ 26900 24700 +Connection ~ 27650 25350 +Wire Wire Line + 27650 24700 27650 25350 +Wire Wire Line + 26900 24700 27650 24700 +Wire Wire Line + 27200 25350 28100 25350 +Connection ~ 26900 23950 +Wire Wire Line + 26900 23950 26900 25150 +Connection ~ 28400 24000 +Wire Wire Line + 28400 24000 28400 25150 +Wire Wire Line + 28850 24000 28850 23850 +Wire Wire Line + 28200 24000 28850 24000 +Wire Wire Line + 28200 23850 28200 24000 +Wire Wire Line + 27400 23950 27400 23850 +Wire Wire Line + 26550 23950 27400 23950 +Wire Wire Line + 26550 23850 26550 23950 +Connection ~ 27650 23350 +Wire Wire Line + 27650 23350 27650 22750 +Wire Wire Line + 28850 23350 28850 23450 +Connection ~ 27400 23350 +Connection ~ 28200 23350 +Wire Wire Line + 28200 23350 28200 23450 +Wire Wire Line + 26550 23350 26550 23450 +Wire Wire Line + 26550 23350 28850 23350 +Wire Wire Line + 27400 23350 27400 23450 +Wire Wire Line + 28500 23650 29500 23650 +Connection ~ 27650 21600 +Wire Wire Line + 27650 22350 27650 21600 +Wire Wire Line + 27850 21600 27850 21550 +Wire Wire Line + 27400 21600 27850 21600 +Wire Wire Line + 27400 21550 27400 21600 +Wire Wire Line + 27850 20750 39300 20750 +Wire Wire Line + 31300 21150 31300 21200 +Wire Wire Line + 31750 21150 31750 21200 +Wire Wire Line + 28150 21400 31900 21400 +Wire Wire Line + 27850 20750 27850 21150 +Wire Wire Line + 27400 21150 27400 21100 +Wire Wire Line + 27700 21350 28150 21350 +Wire Wire Line + 39300 20750 39300 17000 +Wire Wire Line + 38700 21150 38700 20750 +Wire Wire Line + 43700 27250 43700 14550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub new file mode 100644 index 00000000..28e70962 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC.sub @@ -0,0 +1,173 @@ +* Subcircuit TL064_IC +.subckt TL064_IC net-_q25-pad3_ net-_j1-pad2_ net-_j5-pad2_ net-_q15-pad3_ net-_j7-pad2_ net-_j3-pad2_ net-_q27-pad3_ net-_q80-pad3_ net-_j15-pad2_ net-_j19-pad2_ net-_q10-pad3_ net-_j16-pad2_ net-_j13-pad2_ net-_q77-pad3_ +* d:\fossee\esim\library\subcircuitlibrary\tl064_ic\tl064_ic.cir +.include PJF.lib +.include NPN.lib +.include PNP.lib +q2 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q4 net-_q2-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q15 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q17 net-_q14-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q3 net-_j1-pad1_ net-_q3-pad2_ net-_q2-pad1_ Q2N2907A +j2 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3820 +j5 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +j6 net-_j1-pad1_ net-_j5-pad2_ net-_c1-pad2_ J2N3820 +q1 net-_j1-pad3_ net-_j1-pad3_ net-_q1-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_j1-pad3_ net-_q6-pad3_ Q2N2222 +r3 net-_q1-pad3_ net-_q10-pad3_ 34 +r5 net-_q6-pad3_ net-_q10-pad3_ 35 +q14 net-_q14-pad1_ net-_q14-pad1_ net-_q14-pad3_ Q2N2222 +r9 net-_q14-pad1_ net-_q19-pad1_ 220 +r8 net-_q14-pad3_ net-_c1-pad1_ 45k +q13 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q16 net-_c1-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +q19 net-_q19-pad1_ net-_q14-pad3_ net-_c1-pad1_ Q2N2222 +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +r7 net-_q10-pad2_ net-_q10-pad3_ 7 +q26 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +q29 net-_q15-pad3_ net-_q19-pad1_ net-_q25-pad2_ Q2N2222 +r15 net-_q25-pad2_ net-_q28-pad3_ 270 +q28 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +q30 net-_q10-pad3_ net-_c1-pad1_ net-_q28-pad3_ Q2N2907A +r16 net-_q25-pad3_ net-_q25-pad2_ 64 +q25 net-_q19-pad1_ net-_q25-pad2_ net-_q25-pad3_ Q2N2222 +q39 net-_j11-pad2_ net-_q15-pad2_ net-_q15-pad3_ Q2N2907A +q38 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +q41 net-_j11-pad1_ net-_j11-pad1_ net-_j11-pad2_ Q2N2907A +j9 net-_j9-pad1_ net-_j11-pad1_ net-_j11-pad3_ J2N3820 +j11 net-_j11-pad1_ net-_j11-pad2_ net-_j11-pad3_ J2N3820 +q40 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q42 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +q36 net-_j11-pad1_ net-_q35-pad1_ net-_q10-pad3_ Q2N2222 +r19 net-_j11-pad3_ net-_q35-pad1_ 3.5k +q35 net-_q35-pad1_ net-_j11-pad3_ net-_q10-pad3_ Q2N2222 +q49 net-_q15-pad2_ net-_q15-pad2_ net-_q3-pad2_ Q2N2222 +q50 net-_q10-pad3_ net-_j11-pad2_ net-_q3-pad2_ Q2N2907A +q7 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q9 net-_q7-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q21 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q23 net-_q20-pad1_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q8 net-_j3-pad1_ net-_q51-pad3_ net-_q7-pad1_ Q2N2907A +j4 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j3 net-_j3-pad1_ net-_j3-pad2_ net-_j3-pad3_ J2N3820 +j7 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +j8 net-_j3-pad1_ net-_j7-pad2_ net-_c2-pad2_ J2N3820 +q5 net-_j3-pad3_ net-_j3-pad3_ net-_q5-pad3_ Q2N2222 +q11 net-_c2-pad2_ net-_j3-pad3_ net-_q11-pad3_ Q2N2222 +r4 net-_q5-pad3_ net-_q10-pad3_ 34 +r6 net-_q11-pad3_ net-_q10-pad3_ 35 +q20 net-_q20-pad1_ net-_q20-pad1_ net-_q20-pad3_ Q2N2222 +r12 net-_q20-pad1_ net-_q24-pad1_ 220 +r11 net-_q20-pad3_ net-_c2-pad1_ 45k +q18 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q22 net-_c2-pad1_ net-_c2-pad2_ net-_q12-pad2_ Q2N2222 +q24 net-_q24-pad1_ net-_q20-pad3_ net-_c2-pad1_ Q2N2222 +q12 net-_c2-pad2_ net-_q12-pad2_ net-_q10-pad3_ Q2N2222 +c2 net-_c2-pad1_ net-_c2-pad2_ 10p +r10 net-_q12-pad2_ net-_q10-pad3_ 7 +q31 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +q33 net-_q15-pad3_ net-_q24-pad1_ net-_q27-pad2_ Q2N2222 +r17 net-_q27-pad2_ net-_q32-pad3_ 270 +q32 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +q34 net-_q10-pad3_ net-_c2-pad1_ net-_q32-pad3_ Q2N2907A +r18 net-_q27-pad3_ net-_q27-pad2_ 64 +q27 net-_q24-pad1_ net-_q27-pad2_ net-_q27-pad3_ Q2N2222 +q45 net-_j12-pad2_ net-_q21-pad2_ net-_q15-pad3_ Q2N2907A +q44 net-_j10-pad1_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +q47 net-_j10-pad2_ net-_j10-pad2_ net-_j12-pad2_ Q2N2907A +j10 net-_j10-pad1_ net-_j10-pad2_ net-_j10-pad3_ J2N3820 +j12 net-_j10-pad2_ net-_j12-pad2_ net-_j10-pad3_ J2N3820 +q46 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q48 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +q43 net-_j10-pad2_ net-_q37-pad1_ net-_q10-pad3_ Q2N2222 +r20 net-_j10-pad3_ net-_q37-pad1_ 3.5k +q37 net-_q37-pad1_ net-_j10-pad3_ net-_q10-pad3_ Q2N2222 +q51 net-_q21-pad2_ net-_q21-pad2_ net-_q51-pad3_ Q2N2222 +q52 net-_q10-pad3_ net-_j12-pad2_ net-_q51-pad3_ Q2N2907A +q54 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q56 net-_q54-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q67 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q69 net-_q66-pad1_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q55 net-_j13-pad1_ net-_q101-pad3_ net-_q54-pad1_ Q2N2907A +j14 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j13 net-_j13-pad1_ net-_j13-pad2_ net-_j13-pad3_ J2N3820 +j16 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +j18 net-_j13-pad1_ net-_j16-pad2_ net-_c3-pad2_ J2N3820 +q53 net-_j13-pad3_ net-_j13-pad3_ net-_q53-pad3_ Q2N2222 +q58 net-_c3-pad2_ net-_j13-pad3_ net-_q58-pad3_ Q2N2222 +r23 net-_q53-pad3_ net-_q10-pad3_ 34 +r25 net-_q58-pad3_ net-_q10-pad3_ 35 +q66 net-_q66-pad1_ net-_q66-pad1_ net-_q66-pad3_ Q2N2222 +r29 net-_q66-pad1_ net-_q70-pad1_ 220 +r28 net-_q66-pad3_ net-_c3-pad1_ 45k +q65 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q68 net-_c3-pad1_ net-_c3-pad2_ net-_q62-pad2_ Q2N2222 +q70 net-_q70-pad1_ net-_q66-pad3_ net-_c3-pad1_ Q2N2222 +q62 net-_c3-pad2_ net-_q62-pad2_ net-_q10-pad3_ Q2N2222 +c3 net-_c3-pad1_ net-_c3-pad2_ 10p +r27 net-_q62-pad2_ net-_q10-pad3_ 7 +q78 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +q81 net-_q15-pad3_ net-_q70-pad1_ net-_q77-pad2_ Q2N2222 +r34 net-_q77-pad2_ net-_q79-pad3_ 270 +q79 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +q82 net-_q10-pad3_ net-_c3-pad1_ net-_q79-pad3_ Q2N2907A +r36 net-_q77-pad3_ net-_q77-pad2_ 64 +q77 net-_q70-pad1_ net-_q77-pad2_ net-_q77-pad3_ Q2N2222 +q91 net-_j23-pad2_ net-_q101-pad1_ net-_q15-pad3_ Q2N2907A +q89 net-_j21-pad1_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +q93 net-_j21-pad2_ net-_j21-pad2_ net-_j23-pad2_ Q2N2907A +j21 net-_j21-pad1_ net-_j21-pad2_ net-_j21-pad3_ J2N3820 +j23 net-_j21-pad2_ net-_j23-pad2_ net-_j21-pad3_ J2N3820 +q92 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q94 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +q88 net-_j21-pad2_ net-_q87-pad1_ net-_q10-pad3_ Q2N2222 +r39 net-_j21-pad3_ net-_q87-pad1_ 3.5k +q87 net-_q87-pad1_ net-_j21-pad3_ net-_q10-pad3_ Q2N2222 +q101 net-_q101-pad1_ net-_q101-pad1_ net-_q101-pad3_ Q2N2222 +q102 net-_q10-pad3_ net-_j23-pad2_ net-_q101-pad3_ Q2N2907A +q59 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q61 net-_q59-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q73 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q75 net-_q72-pad1_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q60 net-_j15-pad1_ net-_q103-pad3_ net-_q59-pad1_ Q2N2907A +j17 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j15 net-_j15-pad1_ net-_j15-pad2_ net-_j15-pad3_ J2N3820 +j19 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +j20 net-_j15-pad1_ net-_j19-pad2_ net-_c4-pad2_ J2N3820 +q57 net-_j15-pad3_ net-_j15-pad3_ net-_q57-pad3_ Q2N2222 +q63 net-_c4-pad2_ net-_j15-pad3_ net-_q63-pad3_ Q2N2222 +r24 net-_q57-pad3_ net-_q10-pad3_ 34 +r26 net-_q63-pad3_ net-_q10-pad3_ 35 +q72 net-_q72-pad1_ net-_q72-pad1_ net-_q72-pad3_ Q2N2222 +r32 net-_q72-pad1_ net-_q76-pad1_ 220 +r31 net-_q72-pad3_ net-_c4-pad1_ 45k +q71 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q74 net-_c4-pad1_ net-_c4-pad2_ net-_q64-pad2_ Q2N2222 +q76 net-_q76-pad1_ net-_q72-pad3_ net-_c4-pad1_ Q2N2222 +q64 net-_c4-pad2_ net-_q64-pad2_ net-_q10-pad3_ Q2N2222 +c4 net-_c4-pad1_ net-_c4-pad2_ 10p +r30 net-_q64-pad2_ net-_q10-pad3_ 7 +q83 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +q85 net-_q15-pad3_ net-_q76-pad1_ net-_q80-pad2_ Q2N2222 +r37 net-_q80-pad2_ net-_q84-pad3_ 270 +q84 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +q86 net-_q10-pad3_ net-_c4-pad1_ net-_q84-pad3_ Q2N2907A +r38 net-_q80-pad3_ net-_q80-pad2_ 64 +q80 net-_q76-pad1_ net-_q80-pad2_ net-_q80-pad3_ Q2N2222 +q97 net-_j24-pad2_ net-_q103-pad1_ net-_q15-pad3_ Q2N2907A +q96 net-_j22-pad1_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +q99 net-_j22-pad2_ net-_j22-pad2_ net-_j24-pad2_ Q2N2907A +j22 net-_j22-pad1_ net-_j22-pad2_ net-_j22-pad3_ J2N3820 +j24 net-_j22-pad2_ net-_j24-pad2_ net-_j22-pad3_ J2N3820 +q98 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q100 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +q95 net-_j22-pad2_ net-_q100-pad2_ net-_q10-pad3_ Q2N2222 +r40 net-_j22-pad3_ net-_q100-pad2_ 3.5k +q90 net-_q100-pad2_ net-_j22-pad3_ net-_q10-pad3_ Q2N2222 +q103 net-_q103-pad1_ net-_q103-pad1_ net-_q103-pad3_ Q2N2222 +q104 net-_q10-pad3_ net-_j24-pad2_ net-_q103-pad3_ Q2N2907A +* Control Statements + +.ends TL064_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml b/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml new file mode 100644 index 00000000..91ee9448 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/TL064_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q15><q17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q17><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q3><j2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j2><j1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j1><j5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j5><j6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j6><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><q14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><q13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><q19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q19><q10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><q26><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q26><q29><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q29><q28><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q28><q30><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q30><q25><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q25><q39><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q39><q38><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q38><q41><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q41><j9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j9><j11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j11><q40><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q40><q42><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q42><q36><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q36><q35><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q35><q49><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q49><q50><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q50><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><q9><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q9><q21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q21><q23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q23><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><j4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j4><j3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j3><j7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j7><j8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j8><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q11><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q20><q18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q18><q22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q22><q24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q24><q12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q31><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q31><q33><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q33><q32><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q32><q34><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q34><q27><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q27><q45><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q45><q44><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q44><q47><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q47><j10><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j10><j12><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j12><q46><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q46><q48><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q48><q43><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q43><q37><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q37><q51><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q51><q52><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q52><q54><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q54><q56><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q56><q67><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q67><q69><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q69><q55><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q55><j14><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j14><j13><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j13><j16><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j16><j18><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j18><q53><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q53><q58><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q58><q66><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q66><q65><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q65><q68><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q68><q70><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q70><q62><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q62><q78><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q78><q81><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q81><q79><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q79><q82><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q82><q77><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q77><q91><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q91><q89><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q89><q93><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q93><j21><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j21><j23><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j23><q92><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q92><q94><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q94><q88><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q88><q87><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q87><q101><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q101><q102><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q102><q59><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q59><q61><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q61><q73><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q73><q75><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q75><q60><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q60><j17><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j17><j15><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j15><j19><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j19><j20><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j20><q57><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q57><q63><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q63><q72><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q72><q71><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q71><q74><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q74><q76><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q76><q64><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q64><q83><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q83><q85><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q85><q84><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q84><q86><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q86><q80><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q80><q97><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q97><q96><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q96><q99><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q99><j22><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j22><j24><field>D:\FOSSEE\eSim\library\deviceModelLibrary\JFET\PJF.lib</field></j24><q98><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q98><q100><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q100><q95><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q95><q90><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q90><q103><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q103><q104><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q104></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL064_sub/analysis b/library/SubcircuitLibrary/TL064_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TL064_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/D.lib b/library/SubcircuitLibrary/TL331_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TL331_sub/NPN.lib b/library/SubcircuitLibrary/TL331_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TL331_sub/PNP.lib b/library/SubcircuitLibrary/TL331_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib b/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib new file mode 100644 index 00000000..da24d97c --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331-cache.lib @@ -0,0 +1,160 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.cir b/library/SubcircuitLibrary/TL331_sub/TL331.cir new file mode 100644 index 00000000..83280b33 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.cir @@ -0,0 +1,28 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TL331\TL331.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/12/24 00:57:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ 10u +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 80u +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ 10u +Q2 Net-_Q2-Pad1_ Net-_D1-Pad2_ Net-_I2-Pad2_ eSim_PNP +Q5 Net-_Q4-Pad1_ Net-_D3-Pad2_ Net-_I2-Pad2_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 GND Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 GND Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_PNP +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 80u +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q7 Net-_I4-Pad2_ Net-_Q4-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_I4-Pad2_ Net-_Q3-Pad3_ eSim_NPN +R1 Net-_I1-Pad1_ Net-_Q8-Pad1_ 300 +I1 Net-_I1-Pad1_ Net-_D2-Pad1_ 80u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 80u +U1 Net-_D1-Pad1_ Net-_D4-Pad1_ Net-_Q3-Pad3_ Net-_I1-Pad1_ Net-_Q8-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.cir.out b/library/SubcircuitLibrary/TL331_sub/TL331.cir.out new file mode 100644 index 00000000..c83f3e00 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.cir.out @@ -0,0 +1,32 @@ +* d:\fossee\esim\library\subcircuitlibrary\tl331\tl331.cir + +.include PNP.lib +.include NPN.lib +.include D.lib +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +q5 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 gnd net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q3-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_i1-pad1_ net-_q8-pad1_ 300 +i1 net-_i1-pad1_ net-_d2-pad1_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 80u +* u1 net-_d1-pad1_ net-_d4-pad1_ net-_q3-pad3_ net-_i1-pad1_ net-_q8-pad1_ port +.tran 0e-00 0e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.pro b/library/SubcircuitLibrary/TL331_sub/TL331.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.sch b/library/SubcircuitLibrary/TL331_sub/TL331.sch new file mode 100644 index 00000000..118b584f --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.sch @@ -0,0 +1,417 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TL331-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_Diode D2 +U 1 1 6668A495 +P 4700 2900 +F 0 "D2" H 4700 3000 50 0000 C CNN +F 1 "10u" H 4700 2800 50 0000 C CIN +F 2 "" H 4700 2900 60 0000 C CNN +F 3 "" H 4700 2900 60 0000 C CNN + 1 4700 2900 + 0 1 1 0 +$EndComp +$Comp +L dc I2 +U 1 1 6668A496 +P 5900 2050 +F 0 "I2" H 5700 2150 60 0000 C CNN +F 1 "80u" H 5700 2000 60 0000 C CNN +F 2 "R1" H 5600 2050 60 0000 C CNN +F 3 "" H 5900 2050 60 0000 C CNN + 1 5900 2050 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6668A497 +P 6900 2800 +F 0 "D3" H 6900 2900 50 0000 C CNN +F 1 "10u" H 6900 2700 50 0000 C CNN +F 2 "" H 6900 2800 60 0000 C CNN +F 3 "" H 6900 2800 60 0000 C CNN + 1 6900 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6668A498 +P 5300 3100 +F 0 "Q2" H 5200 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5250 3250 50 0000 R CNN +F 2 "" H 5500 3200 29 0000 C CNN +F 3 "" H 5300 3100 60 0000 C CNN + 1 5300 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 6668A499 +P 6500 3100 +F 0 "Q5" H 6400 3150 50 0000 R CNN +F 1 "eSim_PNP" H 6450 3250 50 0000 R CNN +F 2 "" H 6700 3200 29 0000 C CNN +F 3 "" H 6500 3100 60 0000 C CNN + 1 6500 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6668A49A +P 4200 3100 +F 0 "D1" H 4200 3200 50 0000 C CNN +F 1 "eSim_Diode" H 4200 3000 50 0000 C CNN +F 2 "" H 4200 3100 60 0000 C CNN +F 3 "" H 4200 3100 60 0000 C CNN + 1 4200 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6668A49B +P 4600 3450 +F 0 "Q1" H 4500 3500 50 0000 R CNN +F 1 "eSim_PNP" H 4550 3600 50 0000 R CNN +F 2 "" H 4800 3550 29 0000 C CNN +F 3 "" H 4600 3450 60 0000 C CNN + 1 4600 3450 + 1 0 0 1 +$EndComp +$Comp +L GND #PWR1 +U 1 1 6668A49C +P 4700 3950 +F 0 "#PWR1" H 4700 3700 50 0001 C CNN +F 1 "GND" H 4700 3800 50 0000 C CNN +F 2 "" H 4700 3950 50 0001 C CNN +F 3 "" H 4700 3950 50 0001 C CNN + 1 4700 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6668A49D +P 7400 3100 +F 0 "D4" H 7400 3200 50 0000 C CNN +F 1 "eSim_Diode" H 7400 3000 50 0000 C CNN +F 2 "" H 7400 3100 60 0000 C CNN +F 3 "" H 7400 3100 60 0000 C CNN + 1 7400 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6668A49E +P 7000 3500 +F 0 "Q6" H 6900 3550 50 0000 R CNN +F 1 "eSim_PNP" H 6950 3650 50 0000 R CNN +F 2 "" H 7200 3600 29 0000 C CNN +F 3 "" H 7000 3500 60 0000 C CNN + 1 7000 3500 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR2 +U 1 1 6668A4A1 +P 6900 4000 +F 0 "#PWR2" H 6900 3750 50 0001 C CNN +F 1 "GND" H 6900 3850 50 0000 C CNN +F 2 "" H 6900 4000 50 0001 C CNN +F 3 "" H 6900 4000 50 0001 C CNN + 1 6900 4000 + 1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 6668A4A2 +P 8600 2550 +F 0 "I4" H 8400 2650 60 0000 C CNN +F 1 "80u" H 8400 2500 60 0000 C CNN +F 2 "R1" H 8300 2550 60 0000 C CNN +F 3 "" H 8600 2550 60 0000 C CNN + 1 8600 2550 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6668A4A3 +P 5500 5500 +F 0 "Q3" H 5400 5550 50 0000 R CNN +F 1 "eSim_NPN" H 5450 5650 50 0000 R CNN +F 2 "" H 5700 5600 29 0000 C CNN +F 3 "" H 5500 5500 60 0000 C CNN + 1 5500 5500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6668A4A4 +P 6300 5500 +F 0 "Q4" H 6200 5550 50 0000 R CNN +F 1 "eSim_NPN" H 6250 5650 50 0000 R CNN +F 2 "" H 6500 5600 29 0000 C CNN +F 3 "" H 6300 5500 60 0000 C CNN + 1 6300 5500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6668A4A5 +P 8300 4900 +F 0 "Q7" H 8200 4950 50 0000 R CNN +F 1 "eSim_NPN" H 8250 5050 50 0000 R CNN +F 2 "" H 8500 5000 29 0000 C CNN +F 3 "" H 8300 4900 60 0000 C CNN + 1 8300 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 6668A4A6 +P 9000 4200 +F 0 "Q8" H 8900 4250 50 0000 R CNN +F 1 "eSim_NPN" H 8950 4350 50 0000 R CNN +F 2 "" H 9200 4300 29 0000 C CNN +F 3 "" H 9000 4200 60 0000 C CNN + 1 9000 4200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6668A4AE +P 9150 3000 +F 0 "R1" H 9200 3130 50 0000 C CNN +F 1 "300" H 9200 2950 50 0000 C CNN +F 2 "" H 9200 2980 30 0000 C CNN +F 3 "" V 9200 3050 30 0000 C CNN + 1 9150 3000 + 0 1 1 0 +$EndComp +Wire Wire Line + 5400 2900 6400 2900 +Wire Wire Line + 5900 2500 5900 2900 +Connection ~ 5900 2900 +Wire Wire Line + 4350 3100 5100 3100 +Wire Wire Line + 4700 3050 4700 3250 +Connection ~ 4700 3100 +Wire Wire Line + 4050 3450 4050 3100 +Connection ~ 4050 3450 +Wire Wire Line + 4700 3650 4700 3950 +Wire Wire Line + 7550 3100 7650 3100 +Wire Wire Line + 7650 3100 7650 4800 +Wire Wire Line + 7200 3500 7650 3500 +Connection ~ 7650 3500 +Wire Wire Line + 6900 3700 6900 4000 +Wire Wire Line + 5400 3300 5400 5300 +Wire Wire Line + 6400 3300 6400 5300 +Wire Wire Line + 5700 5500 6100 5500 +Wire Wire Line + 5400 5000 5900 5000 +Wire Wire Line + 5900 5000 5900 5500 +Connection ~ 5900 5500 +Connection ~ 5400 5000 +Wire Wire Line + 8600 4700 8400 4700 +Wire Wire Line + 8800 4200 8600 4200 +Connection ~ 8600 4200 +Wire Wire Line + 8100 4900 6400 4900 +Connection ~ 6400 4900 +Wire Wire Line + 9100 5800 9100 4400 +Wire Wire Line + 8400 5800 8400 5100 +Connection ~ 8600 1600 +Wire Wire Line + 8600 1600 8600 2100 +Wire Wire Line + 8600 3000 8600 4700 +Wire Wire Line + 5400 5700 5400 5800 +Wire Wire Line + 5400 5800 9400 5800 +Connection ~ 9100 5800 +Connection ~ 8400 5800 +Wire Wire Line + 6400 5700 6400 5800 +Connection ~ 6400 5800 +Wire Wire Line + 3800 3450 4400 3450 +Wire Wire Line + 9200 3200 9200 4000 +Connection ~ 9200 4000 +Wire Wire Line + 9200 1600 9200 2900 +Connection ~ 9200 1600 +Wire Wire Line + 4700 2500 4700 2750 +$Comp +L dc I1 +U 1 1 6668A4AF +P 4950 2050 +F 0 "I1" H 4750 2150 60 0000 C CNN +F 1 "80u" H 4750 2000 60 0000 C CNN +F 2 "R1" H 4650 2050 60 0000 C CNN +F 3 "" H 4950 2050 60 0000 C CNN + 1 4950 2050 + -1 0 0 -1 +$EndComp +Connection ~ 5900 1600 +Wire Wire Line + 4950 2500 4700 2500 +$Comp +L dc I3 +U 1 1 6668A4B0 +P 6900 2100 +F 0 "I3" H 6700 2200 60 0000 C CNN +F 1 "80u" H 6700 2050 60 0000 C CNN +F 2 "R1" H 6600 2100 60 0000 C CNN +F 3 "" H 6900 2100 60 0000 C CNN + 1 6900 2100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6900 1600 6900 1650 +Connection ~ 6900 1600 +Wire Wire Line + 6900 2650 6900 2550 +Wire Wire Line + 6900 3100 6700 3100 +Wire Wire Line + 6900 2950 6900 3300 +Connection ~ 6900 3100 +Wire Wire Line + 7250 3100 7250 3000 +Wire Wire Line + 7250 3000 6900 3000 +Connection ~ 6900 3000 +Wire Wire Line + 4950 1600 9550 1600 +$Comp +L PORT U1 +U 1 1 6668A70E +P 3550 3450 +F 0 "U1" H 3600 3550 30 0000 C CNN +F 1 "PORT" H 3550 3450 30 0000 C CNN +F 2 "" H 3550 3450 60 0000 C CNN +F 3 "" H 3550 3450 60 0000 C CNN + 1 3550 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 6668AEAF +P 9650 5800 +F 0 "U1" H 9700 5900 30 0000 C CNN +F 1 "PORT" H 9650 5800 30 0000 C CNN +F 2 "" H 9650 5800 60 0000 C CNN +F 3 "" H 9650 5800 60 0000 C CNN + 3 9650 5800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 6668B053 +P 3600 4800 +F 0 "U1" H 3650 4900 30 0000 C CNN +F 1 "PORT" H 3600 4800 30 0000 C CNN +F 2 "" H 3600 4800 60 0000 C CNN +F 3 "" H 3600 4800 60 0000 C CNN + 2 3600 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7650 4800 3850 4800 +$Comp +L PORT U1 +U 4 1 6668B3C5 +P 9800 1600 +F 0 "U1" H 9850 1700 30 0000 C CNN +F 1 "PORT" H 9800 1600 30 0000 C CNN +F 2 "" H 9800 1600 60 0000 C CNN +F 3 "" H 9800 1600 60 0000 C CNN + 4 9800 1600 + -1 0 0 1 +$EndComp +Wire Wire Line + 9100 4000 9700 4000 +$Comp +L PORT U1 +U 5 1 6668B51E +P 9950 4000 +F 0 "U1" H 10000 4100 30 0000 C CNN +F 1 "PORT" H 9950 4000 30 0000 C CNN +F 2 "" H 9950 4000 60 0000 C CNN +F 3 "" H 9950 4000 60 0000 C CNN + 5 9950 4000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TL331_sub/TL331.sub b/library/SubcircuitLibrary/TL331_sub/TL331.sub new file mode 100644 index 00000000..32456e21 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331.sub @@ -0,0 +1,26 @@ +* Subcircuit TL331 +.subckt TL331 net-_d1-pad1_ net-_d4-pad1_ net-_q3-pad3_ net-_i1-pad1_ net-_q8-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\tl331\tl331.cir +.include PNP.lib +.include NPN.lib +.include D.lib +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +i2 net-_i1-pad1_ net-_i2-pad2_ 80u +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +q5 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 gnd net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 gnd net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +i4 net-_i1-pad1_ net-_i4-pad2_ 80u +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q4 net-_q4-pad1_ net-_q2-pad1_ net-_q3-pad3_ Q2N2222 +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q3-pad3_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q3-pad3_ Q2N2222 +r1 net-_i1-pad1_ net-_q8-pad1_ 300 +i1 net-_i1-pad1_ net-_d2-pad1_ 80u +i3 net-_i1-pad1_ net-_d3-pad1_ 80u +* Control Statements + +.ends TL331
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml b/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml new file mode 100644 index 00000000..a8bf8200 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/TL331_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i2 name="Source type">80u</i2><i4 name="Source type">80u</i4><i1 name="Source type">80u</i1><i3 name="Source type">80u</i3></source><model /><devicemodel><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q5><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">ns</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TL331_sub/analysis b/library/SubcircuitLibrary/TL331_sub/analysis new file mode 100644 index 00000000..657c34c3 --- /dev/null +++ b/library/SubcircuitLibrary/TL331_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-09 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/D.lib b/library/SubcircuitLibrary/TS391_sub/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/TS391_sub/NPN.lib b/library/SubcircuitLibrary/TS391_sub/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/TS391_sub/PNP.lib b/library/SubcircuitLibrary/TS391_sub/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib b/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib new file mode 100644 index 00000000..4e32f85d --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# dc +# +DEF dc I 0 40 Y Y 1 F N +F0 "I" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +P 2 0 1 0 0 -100 0 -100 N +P 2 0 1 0 0 100 -50 50 N +P 2 0 1 0 0 100 0 -100 N +P 2 0 1 0 0 100 50 50 N +X ~ 1 0 450 300 D 50 50 1 1 P +X ~ 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir new file mode 100644 index 00000000..80ee839f --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir @@ -0,0 +1,29 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\TS391_IC\TS391_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/22/24 20:07:00 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +I1 Net-_I1-Pad1_ Net-_D2-Pad1_ 3.5u +I2 Net-_I1-Pad1_ Net-_I2-Pad2_ 100u +I3 Net-_I1-Pad1_ Net-_D3-Pad1_ 3.5u +I4 Net-_I1-Pad1_ Net-_I4-Pad2_ 100u +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q4 Net-_Q4-Pad1_ Net-_D3-Pad2_ Net-_I2-Pad2_ eSim_PNP +Q2 Net-_Q2-Pad1_ Net-_D1-Pad2_ Net-_I2-Pad2_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q1 Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q3 Net-_Q2-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q5 Net-_Q4-Pad1_ Net-_Q2-Pad1_ Net-_Q1-Pad1_ eSim_NPN +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q6 Net-_Q1-Pad1_ Net-_D4-Pad1_ Net-_D3-Pad2_ eSim_PNP +Q7 Net-_I4-Pad2_ Net-_Q4-Pad1_ Net-_Q1-Pad1_ eSim_NPN +Q8 Net-_Q8-Pad1_ Net-_I4-Pad2_ Net-_Q1-Pad1_ eSim_NPN +R2 Net-_I1-Pad1_ Net-_Q8-Pad1_ 3.5k +R1 Net-_R1-Pad1_ Net-_D4-Pad1_ 1k +U1 Net-_Q8-Pad1_ Net-_Q1-Pad1_ Net-_R1-Pad1_ Net-_D1-Pad1_ Net-_I1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out new file mode 100644 index 00000000..f88d796d --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.cir.out @@ -0,0 +1,33 @@ +* d:\fossee\esim\library\subcircuitlibrary\ts391_ic\ts391_ic.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +i1 net-_i1-pad1_ net-_d2-pad1_ 3.5u +i2 net-_i1-pad1_ net-_i2-pad2_ 100u +i3 net-_i1-pad1_ net-_d3-pad1_ 3.5u +i4 net-_i1-pad1_ net-_i4-pad2_ 100u +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q1-pad1_ net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q8-pad1_ 3.5k +r1 net-_r1-pad1_ net-_d4-pad1_ 1k +* u1 net-_q8-pad1_ net-_q1-pad1_ net-_r1-pad1_ net-_d1-pad1_ net-_i1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro b/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch new file mode 100644 index 00000000..ff55972c --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sch @@ -0,0 +1,451 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:TS391-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dc I1 +U 1 1 6676E0A1 +P 3550 1900 +F 0 "I1" H 3350 2000 60 0000 C CNN +F 1 "3.5u" H 3350 1850 60 0000 C CNN +F 2 "R1" H 3250 1900 60 0000 C CNN +F 3 "" H 3550 1900 60 0000 C CNN + 1 3550 1900 + 1 0 0 -1 +$EndComp +$Comp +L dc I2 +U 1 1 6676E0A2 +P 4750 2100 +F 0 "I2" H 4550 2200 60 0000 C CNN +F 1 "100u" H 4550 2050 60 0000 C CNN +F 2 "R1" H 4450 2100 60 0000 C CNN +F 3 "" H 4750 2100 60 0000 C CNN + 1 4750 2100 + 1 0 0 -1 +$EndComp +$Comp +L dc I3 +U 1 1 6676E0A3 +P 5750 1900 +F 0 "I3" H 5550 2000 60 0000 C CNN +F 1 "3.5u" H 5550 1850 60 0000 C CNN +F 2 "R1" H 5450 1900 60 0000 C CNN +F 3 "" H 5750 1900 60 0000 C CNN + 1 5750 1900 + 1 0 0 -1 +$EndComp +$Comp +L dc I4 +U 1 1 6676E0A4 +P 6850 2100 +F 0 "I4" H 6650 2200 60 0000 C CNN +F 1 "100u" H 6650 2050 60 0000 C CNN +F 2 "R1" H 6550 2100 60 0000 C CNN +F 3 "" H 6850 2100 60 0000 C CNN + 1 6850 2100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6676E0A5 +P 3550 2650 +F 0 "D2" H 3550 2750 50 0000 C CNN +F 1 "eSim_Diode" H 3550 2550 50 0000 C CNN +F 2 "" H 3550 2650 60 0000 C CNN +F 3 "" H 3550 2650 60 0000 C CNN + 1 3550 2650 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6676E0A6 +P 5200 3000 +F 0 "Q4" H 5100 3050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 3150 50 0000 R CNN +F 2 "" H 5400 3100 29 0000 C CNN +F 3 "" H 5200 3000 60 0000 C CNN + 1 5200 3000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 6676E0A7 +P 4450 3000 +F 0 "Q2" H 4350 3050 50 0000 R CNN +F 1 "eSim_PNP" H 4400 3150 50 0000 R CNN +F 2 "" H 4650 3100 29 0000 C CNN +F 3 "" H 4450 3000 60 0000 C CNN + 1 4450 3000 + 1 0 0 1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6676E0A8 +P 3150 2900 +F 0 "D1" H 3150 3000 50 0000 C CNN +F 1 "eSim_Diode" H 3150 2800 50 0000 C CNN +F 2 "" H 3150 2900 60 0000 C CNN +F 3 "" H 3150 2900 60 0000 C CNN + 1 3150 2900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q1 +U 1 1 6676E0A9 +P 3350 3350 +F 0 "Q1" H 3250 3400 50 0000 R CNN +F 1 "eSim_PNP" H 3300 3500 50 0000 R CNN +F 2 "" H 3550 3450 29 0000 C CNN +F 3 "" H 3350 3350 60 0000 C CNN + 1 3350 3350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6676E0AA +P 4550 4350 +F 0 "Q3" H 4450 4400 50 0000 R CNN +F 1 "eSim_NPN" H 4500 4500 50 0000 R CNN +F 2 "" H 4750 4450 29 0000 C CNN +F 3 "" H 4550 4350 60 0000 C CNN + 1 4550 4350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6676E0AB +P 5250 4350 +F 0 "Q5" H 5150 4400 50 0000 R CNN +F 1 "eSim_NPN" H 5200 4500 50 0000 R CNN +F 2 "" H 5450 4450 29 0000 C CNN +F 3 "" H 5250 4350 60 0000 C CNN + 1 5250 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6676E0AC +P 5750 2700 +F 0 "D3" H 5750 2800 50 0000 C CNN +F 1 "eSim_Diode" H 5750 2600 50 0000 C CNN +F 2 "" H 5750 2700 60 0000 C CNN +F 3 "" H 5750 2700 60 0000 C CNN + 1 5750 2700 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6676E0AD +P 6150 2950 +F 0 "D4" H 6150 3050 50 0000 C CNN +F 1 "eSim_Diode" H 6150 2850 50 0000 C CNN +F 2 "" H 6150 2950 60 0000 C CNN +F 3 "" H 6150 2950 60 0000 C CNN + 1 6150 2950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6676E0AE +P 5950 3350 +F 0 "Q6" H 5850 3400 50 0000 R CNN +F 1 "eSim_PNP" H 5900 3500 50 0000 R CNN +F 2 "" H 6150 3450 29 0000 C CNN +F 3 "" H 5950 3350 60 0000 C CNN + 1 5950 3350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 6676E0AF +P 6750 3750 +F 0 "Q7" H 6650 3800 50 0000 R CNN +F 1 "eSim_NPN" H 6700 3900 50 0000 R CNN +F 2 "" H 6950 3850 29 0000 C CNN +F 3 "" H 6750 3750 60 0000 C CNN + 1 6750 3750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 6676E0B0 +P 7250 2950 +F 0 "Q8" H 7150 3000 50 0000 R CNN +F 1 "eSim_NPN" H 7200 3100 50 0000 R CNN +F 2 "" H 7450 3050 29 0000 C CNN +F 3 "" H 7250 2950 60 0000 C CNN + 1 7250 2950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 6676E0BC +P 7400 1350 +F 0 "R2" H 7450 1480 50 0000 C CNN +F 1 "3.5k" H 7450 1300 50 0000 C CNN +F 2 "" H 7450 1330 30 0000 C CNN +F 3 "" V 7450 1400 30 0000 C CNN + 1 7400 1350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4550 2800 4550 2750 +Wire Wire Line + 4550 2750 5100 2750 +Wire Wire Line + 5100 2750 5100 2800 +Wire Wire Line + 4750 2550 4750 2750 +Connection ~ 4750 2750 +Wire Wire Line + 3450 3000 4250 3000 +Wire Wire Line + 3450 3000 3450 3150 +Wire Wire Line + 3550 2800 3550 3000 +Connection ~ 3550 3000 +Wire Wire Line + 3300 2900 3550 2900 +Connection ~ 3550 2900 +Wire Wire Line + 3550 2500 3550 2350 +Wire Wire Line + 3150 3350 2850 3350 +Wire Wire Line + 2850 3350 2850 2900 +Wire Wire Line + 2100 2900 3000 2900 +Wire Wire Line + 4750 4350 5050 4350 +Wire Wire Line + 4550 3200 4550 4050 +Wire Wire Line + 4550 4050 4450 4050 +Wire Wire Line + 4450 4050 4450 4150 +Wire Wire Line + 5100 3200 5100 4050 +Wire Wire Line + 5100 4050 5350 4050 +Wire Wire Line + 5350 4050 5350 4150 +Wire Wire Line + 4550 3900 4850 3900 +Wire Wire Line + 4850 3900 4850 4350 +Connection ~ 4850 4350 +Connection ~ 4550 3900 +Wire Wire Line + 5750 2550 5750 2350 +Wire Wire Line + 5850 3000 5850 3150 +Wire Wire Line + 5400 3000 5850 3000 +Wire Wire Line + 5750 2850 5750 3000 +Connection ~ 5750 3000 +Wire Wire Line + 6000 2950 5750 2950 +Connection ~ 5750 2950 +Wire Wire Line + 3550 1450 3550 1100 +Wire Wire Line + 3550 1100 6850 1100 +Wire Wire Line + 6850 1100 6850 1650 +Wire Wire Line + 5750 1450 5750 1100 +Connection ~ 5750 1100 +Wire Wire Line + 4750 1650 4750 1100 +Connection ~ 4750 1100 +Wire Wire Line + 6550 3750 5100 3750 +Connection ~ 5100 3750 +Wire Wire Line + 6850 2550 6850 3550 +Wire Wire Line + 4450 4550 4450 4850 +Wire Wire Line + 4450 4850 7250 4850 +Wire Wire Line + 6850 4850 6850 3950 +Wire Wire Line + 5350 4550 5350 4850 +Connection ~ 5350 4850 +Wire Wire Line + 6300 2950 6450 2950 +Wire Wire Line + 6450 2950 6450 4100 +Wire Wire Line + 6450 3350 6150 3350 +Connection ~ 6850 4850 +Wire Wire Line + 5150 750 5150 1100 +Connection ~ 5150 1100 +Wire Wire Line + 3450 3550 3450 5000 +Wire Wire Line + 3450 5000 6900 5000 +Wire Wire Line + 6900 5000 6900 4850 +Connection ~ 6900 4850 +Wire Wire Line + 5850 3550 5850 5100 +Wire Wire Line + 5850 5100 7000 5100 +Wire Wire Line + 7000 5100 7000 4850 +Connection ~ 7000 4850 +Wire Wire Line + 7050 2950 6850 2950 +Connection ~ 6850 2950 +Wire Wire Line + 7350 3150 7350 4100 +Wire Wire Line + 7350 4100 6950 4100 +Wire Wire Line + 6950 4100 6950 4850 +Connection ~ 6950 4850 +Wire Wire Line + 1750 4100 2300 4100 +Connection ~ 6450 3350 +Connection ~ 2850 2900 +Wire Wire Line + 7600 1300 7600 2750 +Connection ~ 7600 2750 +Wire Wire Line + 7300 1300 7100 1300 +Wire Wire Line + 7100 1300 7100 550 +Wire Wire Line + 7100 550 5050 550 +Wire Wire Line + 5050 550 5050 900 +Wire Wire Line + 5050 900 5150 900 +Connection ~ 5150 900 +Wire Wire Line + 6450 4100 2600 4100 +$Comp +L resistor R1 +U 1 1 6676E0BD +P 2400 4150 +F 0 "R1" H 2450 4280 50 0000 C CNN +F 1 "1k" H 2450 4100 50 0000 C CNN +F 2 "" H 2450 4130 30 0000 C CNN +F 3 "" V 2450 4200 30 0000 C CNN + 1 2400 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6676E26F +P 8150 2750 +F 0 "U1" H 8200 2850 30 0000 C CNN +F 1 "PORT" H 8150 2750 30 0000 C CNN +F 2 "" H 8150 2750 60 0000 C CNN +F 3 "" H 8150 2750 60 0000 C CNN + 1 8150 2750 + -1 0 0 1 +$EndComp +Wire Wire Line + 7350 2750 7900 2750 +$Comp +L PORT U1 +U 2 1 6676E663 +P 7500 4850 +F 0 "U1" H 7550 4950 30 0000 C CNN +F 1 "PORT" H 7500 4850 30 0000 C CNN +F 2 "" H 7500 4850 60 0000 C CNN +F 3 "" H 7500 4850 60 0000 C CNN + 2 7500 4850 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 6676E958 +P 1500 4100 +F 0 "U1" H 1550 4200 30 0000 C CNN +F 1 "PORT" H 1500 4100 30 0000 C CNN +F 2 "" H 1500 4100 60 0000 C CNN +F 3 "" H 1500 4100 60 0000 C CNN + 3 1500 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 6676ED45 +P 5400 750 +F 0 "U1" H 5450 850 30 0000 C CNN +F 1 "PORT" H 5400 750 30 0000 C CNN +F 2 "" H 5400 750 60 0000 C CNN +F 3 "" H 5400 750 60 0000 C CNN + 5 5400 750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 6676FEAD +P 1850 2900 +F 0 "U1" H 1900 3000 30 0000 C CNN +F 1 "PORT" H 1850 2900 30 0000 C CNN +F 2 "" H 1850 2900 60 0000 C CNN +F 3 "" H 1850 2900 60 0000 C CNN + 4 1850 2900 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub new file mode 100644 index 00000000..fbdbaba2 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC.sub @@ -0,0 +1,27 @@ +* Subcircuit TS391_IC +.subckt TS391_IC net-_q8-pad1_ net-_q1-pad1_ net-_r1-pad1_ net-_d1-pad1_ net-_i1-pad1_ +* d:\fossee\esim\library\subcircuitlibrary\ts391_ic\ts391_ic.cir +.include NPN.lib +.include PNP.lib +.include D.lib +i1 net-_i1-pad1_ net-_d2-pad1_ 3.5u +i2 net-_i1-pad1_ net-_i2-pad2_ 100u +i3 net-_i1-pad1_ net-_d3-pad1_ 3.5u +i4 net-_i1-pad1_ net-_i4-pad2_ 100u +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +q4 net-_q4-pad1_ net-_d3-pad2_ net-_i2-pad2_ Q2N2907A +q2 net-_q2-pad1_ net-_d1-pad2_ net-_i2-pad2_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q3 net-_q2-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +q5 net-_q4-pad1_ net-_q2-pad1_ net-_q1-pad1_ Q2N2222 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad2_ 1N4148 +q6 net-_q1-pad1_ net-_d4-pad1_ net-_d3-pad2_ Q2N2907A +q7 net-_i4-pad2_ net-_q4-pad1_ net-_q1-pad1_ Q2N2222 +q8 net-_q8-pad1_ net-_i4-pad2_ net-_q1-pad1_ Q2N2222 +r2 net-_i1-pad1_ net-_q8-pad1_ 3.5k +r1 net-_r1-pad1_ net-_d4-pad1_ 1k +* Control Statements + +.ends TS391_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml b/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml new file mode 100644 index 00000000..8353f882 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/TS391_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><i1 name="Source type">3.5u</i1><i2 name="Source type">100u</i2><i3 name="Source type">3.5u</i3><i4 name="Source type">100u</i4></source><model /><devicemodel><d2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><q2><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><d1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q1><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d3><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d4><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q6><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q7><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q8><field>D:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/TS391_sub/analysis b/library/SubcircuitLibrary/TS391_sub/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/TS391_sub/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/D.lib b/library/SubcircuitLibrary/ca3080/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ca3080/NPN.lib b/library/SubcircuitLibrary/ca3080/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/PNP.lib b/library/SubcircuitLibrary/ca3080/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/analysis b/library/SubcircuitLibrary/ca3080/analysis new file mode 100644 index 00000000..85e6f838 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/analysis @@ -0,0 +1 @@ +.tran 2e-00 6e-00 1e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080-cache.lib b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib new file mode 100644 index 00000000..21197049 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir b/library/SubcircuitLibrary/ca3080/ca3080.cir new file mode 100644 index 00000000..4666a808 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir @@ -0,0 +1,28 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ca3080\ca3080.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 11/23/24 19:02:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q1 Net-_D2-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q5 Net-_D4-Pad1_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_Q11-Pad2_ Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_PNP +Q4 Net-_Q11-Pad2_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_PNP +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q8 Net-_Q10-Pad1_ Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q7 Net-_D4-Pad1_ Net-_D5-Pad2_ Net-_D3-Pad1_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q10 Net-_Q10-Pad1_ Net-_D4-Pad2_ Net-_D5-Pad2_ eSim_PNP +D5 Net-_D3-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q9 Net-_Q11-Pad2_ Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_D6-Pad1_ eSim_NPN +U1 ? Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q10-Pad1_ Net-_D3-Pad1_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir.out b/library/SubcircuitLibrary/ca3080/ca3080.cir.out new file mode 100644 index 00000000..8c0a7960 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* u1 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? port +.tran 2e-00 6e-00 1e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.pro b/library/SubcircuitLibrary/ca3080/ca3080.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sch b/library/SubcircuitLibrary/ca3080/ca3080.sch new file mode 100644 index 00000000..4f206f03 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sch @@ -0,0 +1,445 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ca3080-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 6739CE3D +P 3000 2900 +F 0 "Q2" H 2900 2950 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3050 50 0000 R CNN +F 2 "" H 3200 3000 29 0000 C CNN +F 3 "" H 3000 2900 60 0000 C CNN + 1 3000 2900 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6739CEC7 +P 2800 4200 +F 0 "Q1" H 2700 4250 50 0000 R CNN +F 1 "eSim_NPN" H 2750 4350 50 0000 R CNN +F 2 "" H 3000 4300 29 0000 C CNN +F 3 "" H 2800 4200 60 0000 C CNN + 1 2800 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6739CEE0 +P 4300 4200 +F 0 "Q5" H 4200 4250 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4350 50 0000 R CNN +F 2 "" H 4500 4300 29 0000 C CNN +F 3 "" H 4300 4200 60 0000 C CNN + 1 4300 4200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6739D026 +P 5000 3100 +F 0 "Q6" H 4900 3150 50 0000 R CNN +F 1 "eSim_PNP" H 4950 3250 50 0000 R CNN +F 2 "" H 5200 3200 29 0000 C CNN +F 3 "" H 5000 3100 60 0000 C CNN + 1 5000 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6739D114 +P 4150 3400 +F 0 "Q4" H 4050 3450 50 0000 R CNN +F 1 "eSim_PNP" H 4100 3550 50 0000 R CNN +F 2 "" H 4350 3500 29 0000 C CNN +F 3 "" H 4150 3400 60 0000 C CNN + 1 4150 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6739D123 +P 3850 3100 +F 0 "D2" H 3850 3200 50 0000 C CNN +F 1 "eSim_Diode" H 3850 3000 50 0000 C CNN +F 2 "" H 3850 3100 60 0000 C CNN +F 3 "" H 3850 3100 60 0000 C CNN + 1 3850 3100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6739D928 +P 5100 2550 +F 0 "D3" H 5100 2650 50 0000 C CNN +F 1 "eSim_Diode" H 5100 2450 50 0000 C CNN +F 2 "" H 5100 2550 60 0000 C CNN +F 3 "" H 5100 2550 60 0000 C CNN + 1 5100 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6739DE31 +P 2900 5150 +F 0 "D1" H 2900 5250 50 0000 C CNN +F 1 "eSim_Diode" H 2900 5050 50 0000 C CNN +F 2 "" H 2900 5150 60 0000 C CNN +F 3 "" H 2900 5150 60 0000 C CNN + 1 2900 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6739DE58 +P 3450 4950 +F 0 "Q3" H 3350 5000 50 0000 R CNN +F 1 "eSim_NPN" H 3400 5100 50 0000 R CNN +F 2 "" H 3650 5050 29 0000 C CNN +F 3 "" H 3450 4950 60 0000 C CNN + 1 3450 4950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6739E7CF +P 6400 3950 +F 0 "Q8" H 6300 4000 50 0000 R CNN +F 1 "eSim_PNP" H 6350 4100 50 0000 R CNN +F 2 "" H 6600 4050 29 0000 C CNN +F 3 "" H 6400 3950 60 0000 C CNN + 1 6400 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6739E976 +P 5700 3100 +F 0 "Q7" H 5600 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5650 3250 50 0000 R CNN +F 2 "" H 5900 3200 29 0000 C CNN +F 3 "" H 5700 3100 60 0000 C CNN + 1 5700 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6739E9A5 +P 5950 3650 +F 0 "D4" H 5950 3750 50 0000 C CNN +F 1 "eSim_Diode" H 5950 3550 50 0000 C CNN +F 2 "" H 5950 3650 60 0000 C CNN +F 3 "" H 5950 3650 60 0000 C CNN + 1 5950 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4400 4200 4400 +Wire Wire Line + 2900 4000 2900 3100 +Wire Wire Line + 4000 3100 4800 3100 +Wire Wire Line + 3950 3400 2900 3400 +Connection ~ 2900 3400 +Wire Wire Line + 3700 3100 3400 3100 +Wire Wire Line + 3400 3100 3400 3400 +Connection ~ 3400 3400 +Wire Wire Line + 4250 3200 4250 3100 +Connection ~ 4250 3100 +Wire Wire Line + 5100 3300 5100 4750 +Wire Wire Line + 5100 3600 4250 3600 +Wire Wire Line + 4500 4200 4500 4600 +Wire Wire Line + 4500 4600 2500 4600 +Wire Wire Line + 2600 4200 2500 4200 +Wire Wire Line + 3200 2900 5100 2900 +Wire Wire Line + 5100 2900 5100 2700 +Wire Wire Line + 2900 2700 2900 2300 +Wire Wire Line + 2900 2300 7950 2300 +Wire Wire Line + 5100 2300 5100 2400 +Wire Wire Line + 2900 5000 2900 4950 +Wire Wire Line + 2500 4950 3250 4950 +Wire Wire Line + 3550 4750 3550 4400 +Connection ~ 3550 4400 +Wire Wire Line + 2900 5300 2900 5550 +Wire Wire Line + 2900 5550 8000 5550 +Wire Wire Line + 3550 5150 3550 5550 +Connection ~ 3550 5550 +Wire Wire Line + 4200 4000 4200 3950 +Wire Wire Line + 4200 3950 6200 3950 +Wire Wire Line + 5600 3300 5600 3950 +Connection ~ 5600 3950 +Wire Wire Line + 5800 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 3950 +Connection ~ 5700 3950 +Wire Wire Line + 6100 3650 7150 3650 +Wire Wire Line + 6500 3650 6500 3750 +Wire Wire Line + 5600 2300 5600 2900 +Connection ~ 5100 2300 +$Comp +L eSim_PNP Q10 +U 1 1 6739F10B +P 7350 3650 +F 0 "Q10" H 7250 3700 50 0000 R CNN +F 1 "eSim_PNP" H 7300 3800 50 0000 R CNN +F 2 "" H 7550 3750 29 0000 C CNN +F 3 "" H 7350 3650 60 0000 C CNN + 1 7350 3650 + 1 0 0 1 +$EndComp +Connection ~ 6500 3650 +$Comp +L eSim_Diode D5 +U 1 1 6739F185 +P 7450 2750 +F 0 "D5" H 7450 2850 50 0000 C CNN +F 1 "eSim_Diode" H 7450 2650 50 0000 C CNN +F 2 "" H 7450 2750 60 0000 C CNN +F 3 "" H 7450 2750 60 0000 C CNN + 1 7450 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6739F3EA +P 7450 5150 +F 0 "D6" H 7450 5250 50 0000 C CNN +F 1 "eSim_Diode" H 7450 5050 50 0000 C CNN +F 2 "" H 7450 5150 60 0000 C CNN +F 3 "" H 7450 5150 60 0000 C CNN + 1 7450 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6739F41F +P 6700 4950 +F 0 "Q9" H 6600 5000 50 0000 R CNN +F 1 "eSim_NPN" H 6650 5100 50 0000 R CNN +F 2 "" H 6900 5050 29 0000 C CNN +F 3 "" H 6700 4950 60 0000 C CNN + 1 6700 4950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6739F984 +P 7350 4650 +F 0 "Q11" H 7250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 7300 4800 50 0000 R CNN +F 2 "" H 7550 4750 29 0000 C CNN +F 3 "" H 7350 4650 60 0000 C CNN + 1 7350 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 3850 7450 4450 +Wire Wire Line + 6500 4150 7450 4150 +Connection ~ 7450 4150 +Wire Wire Line + 7450 4850 7450 5000 +Wire Wire Line + 6900 4950 7450 4950 +Connection ~ 7450 4950 +Wire Wire Line + 7450 5300 7450 5550 +Connection ~ 7450 5550 +Wire Wire Line + 6600 5150 6600 5550 +Connection ~ 6600 5550 +Wire Wire Line + 7450 2300 7450 2600 +Connection ~ 5600 2300 +Wire Wire Line + 5900 3100 7450 3100 +Connection ~ 7450 3100 +Wire Wire Line + 5100 4750 6600 4750 +Connection ~ 5100 3600 +Wire Wire Line + 7150 4650 6600 4650 +Wire Wire Line + 6600 4650 6600 4750 +Wire Wire Line + 7450 4350 7950 4350 +Connection ~ 7450 4350 +Connection ~ 7450 2300 +Connection ~ 2900 4950 +$Comp +L PORT U1 +U 7 1 673A5D57 +P 8200 2300 +F 0 "U1" H 8250 2400 30 0000 C CNN +F 1 "PORT" H 8200 2300 30 0000 C CNN +F 2 "" H 8200 2300 60 0000 C CNN +F 3 "" H 8200 2300 60 0000 C CNN + 7 8200 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 673A5F78 +P 8200 4350 +F 0 "U1" H 8250 4450 30 0000 C CNN +F 1 "PORT" H 8200 4350 30 0000 C CNN +F 2 "" H 8200 4350 60 0000 C CNN +F 3 "" H 8200 4350 60 0000 C CNN + 6 8200 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 673A669D +P 2250 4200 +F 0 "U1" H 2300 4300 30 0000 C CNN +F 1 "PORT" H 2250 4200 30 0000 C CNN +F 2 "" H 2250 4200 60 0000 C CNN +F 3 "" H 2250 4200 60 0000 C CNN + 2 2250 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 673A66F6 +P 2250 4600 +F 0 "U1" H 2300 4700 30 0000 C CNN +F 1 "PORT" H 2250 4600 30 0000 C CNN +F 2 "" H 2250 4600 60 0000 C CNN +F 3 "" H 2250 4600 60 0000 C CNN + 3 2250 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 673A7187 +P 2150 1850 +F 0 "U1" H 2200 1950 30 0000 C CNN +F 1 "PORT" H 2150 1850 30 0000 C CNN +F 2 "" H 2150 1850 60 0000 C CNN +F 3 "" H 2150 1850 60 0000 C CNN + 1 2150 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 6000 7700 6000 +NoConn ~ 7700 6000 +Wire Wire Line + 2400 1850 2650 1850 +NoConn ~ 2650 1850 +Wire Wire Line + 7450 2900 7450 3450 +$Comp +L PORT U1 +U 5 1 673A9E14 +P 2250 4950 +F 0 "U1" H 2300 5050 30 0000 C CNN +F 1 "PORT" H 2250 4950 30 0000 C CNN +F 2 "" H 2250 4950 60 0000 C CNN +F 3 "" H 2250 4950 60 0000 C CNN + 5 2250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 673AA0F8 +P 8250 5550 +F 0 "U1" H 8300 5650 30 0000 C CNN +F 1 "PORT" H 8250 5550 30 0000 C CNN +F 2 "" H 8250 5550 60 0000 C CNN +F 3 "" H 8250 5550 60 0000 C CNN + 4 8250 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 673AA6CB +P 8150 6000 +F 0 "U1" H 8200 6100 30 0000 C CNN +F 1 "PORT" H 8150 6000 30 0000 C CNN +F 2 "" H 8150 6000 60 0000 C CNN +F 3 "" H 8150 6000 60 0000 C CNN + 8 8150 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sub b/library/SubcircuitLibrary/ca3080/ca3080.sub new file mode 100644 index 00000000..263cea77 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sub @@ -0,0 +1,26 @@ +* Subcircuit ca3080 +.subckt ca3080 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* Control Statements + +.ends ca3080
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml new file mode 100644 index 00000000..6442215a --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">2</field2><field3 name="Stop Time">6</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/D.lib b/library/SubcircuitLibrary/mc1489/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir b/library/SubcircuitLibrary/mc1489/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.pro b/library/SubcircuitLibrary/mc1489/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sch b/library/SubcircuitLibrary/mc1489/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sub b/library/SubcircuitLibrary/mc1489/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/NPN.lib b/library/SubcircuitLibrary/mc1489/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489/analysis b/library/SubcircuitLibrary/mc1489/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489-cache.lib b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib new file mode 100644 index 00000000..cfb8337e --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# MC1489_0 +# +DEF MC1489_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "MC1489_0" 0 -100 60 H V C CNN +F2 "" 0 -100 60 H I C CNN +F3 "" 0 -100 60 H I C CNN +DRAW +S -500 150 550 -300 0 1 0 N +X input 1 -700 -100 200 R 50 50 1 1 I +X response_ctrl 2 750 -200 200 L 50 50 1 1 I +X vcc 3 0 -500 200 U 50 50 1 1 O +X out 4 300 350 200 D 50 50 1 1 I +X gnd 5 -300 350 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir b/library/SubcircuitLibrary/mc1489/mc1489.cir new file mode 100644 index 00000000..06b9edbc --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489\mc1489.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 20:02:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad3_ gnd MC1489_0 +X3 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad8_ gnd MC1489_0 +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad6_ gnd MC1489_0 +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad11_ gnd MC1489_0 + +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir.out b/library/SubcircuitLibrary/mc1489/mc1489.cir.out new file mode 100644 index 00000000..7e7b7cd0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir + +.include MC1489_0.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.pro b/library/SubcircuitLibrary/mc1489/mc1489.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sch b/library/SubcircuitLibrary/mc1489/mc1489.sch new file mode 100644 index 00000000..98f81be3 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sch @@ -0,0 +1,313 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:mc1489-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5550 4150 5550 4900 +Wire Wire Line + 7700 4200 7700 4850 +Wire Wire Line + 7700 4850 7750 4850 +Wire Wire Line + 5550 4500 7700 4500 +Connection ~ 7700 4500 +Connection ~ 5550 4500 +Wire Wire Line + 8050 5700 8050 5900 +Wire Wire Line + 8050 5900 8150 5900 +Wire Wire Line + 7400 3350 7400 3200 +Wire Wire Line + 5250 3300 5250 3050 +Wire Wire Line + 5850 5750 5850 5950 +Text GLabel 5850 5950 3 60 Input ~ 0 +gnd +Text GLabel 8150 5900 2 60 Input ~ 0 +gnd +Text GLabel 7400 3200 0 60 Input ~ 0 +gnd +Text GLabel 5250 3050 0 60 Input ~ 0 +gnd +Wire Wire Line + 4850 3750 4600 3750 +Wire Wire Line + 4800 5200 4550 5200 +Wire Wire Line + 5250 5750 5000 5750 +Wire Wire Line + 6250 5300 6250 5200 +Wire Wire Line + 7000 5150 7000 5050 +Wire Wire Line + 7450 5700 7300 5700 +Wire Wire Line + 8450 5250 8450 5050 +Wire Wire Line + 8450 3900 8450 4000 +Wire Wire Line + 7000 3800 7000 3950 +Wire Wire Line + 8000 3350 8150 3350 +Wire Wire Line + 5850 3300 5950 3300 +Wire Wire Line + 6300 3850 6300 3700 +$Comp +L PORT U1 +U 3 1 679A35F2 +P 6200 3300 +F 0 "U1" H 6250 3400 30 0000 C CNN +F 1 "PORT" H 6200 3300 30 0000 C CNN +F 2 "" H 6200 3300 60 0000 C CNN +F 3 "" H 6200 3300 60 0000 C CNN + 3 6200 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A361D +P 4750 5750 +F 0 "U1" H 4800 5850 30 0000 C CNN +F 1 "PORT" H 4750 5750 30 0000 C CNN +F 2 "" H 4750 5750 60 0000 C CNN +F 3 "" H 4750 5750 60 0000 C CNN + 6 4750 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A363E +P 6000 5200 +F 0 "U1" H 6050 5300 30 0000 C CNN +F 1 "PORT" H 6000 5200 30 0000 C CNN +F 2 "" H 6000 5200 60 0000 C CNN +F 3 "" H 6000 5200 60 0000 C CNN + 4 6000 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A3661 +P 4300 5200 +F 0 "U1" H 4350 5300 30 0000 C CNN +F 1 "PORT" H 4300 5200 30 0000 C CNN +F 2 "" H 4300 5200 60 0000 C CNN +F 3 "" H 4300 5200 60 0000 C CNN + 5 4300 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3686 +P 4350 3750 +F 0 "U1" H 4400 3850 30 0000 C CNN +F 1 "PORT" H 4350 3750 30 0000 C CNN +F 2 "" H 4350 3750 60 0000 C CNN +F 3 "" H 4350 3750 60 0000 C CNN + 1 4350 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A36AD +P 6050 3700 +F 0 "U1" H 6100 3800 30 0000 C CNN +F 1 "PORT" H 6050 3700 30 0000 C CNN +F 2 "" H 6050 3700 60 0000 C CNN +F 3 "" H 6050 3700 60 0000 C CNN + 2 6050 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A36D6 +P 4900 3250 +F 0 "U1" H 4950 3350 30 0000 C CNN +F 1 "PORT" H 4900 3250 30 0000 C CNN +F 2 "" H 4900 3250 60 0000 C CNN +F 3 "" H 4900 3250 60 0000 C CNN + 7 4900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A3701 +P 6750 3950 +F 0 "U1" H 6800 4050 30 0000 C CNN +F 1 "PORT" H 6750 3950 30 0000 C CNN +F 2 "" H 6750 3950 60 0000 C CNN +F 3 "" H 6750 3950 60 0000 C CNN + 10 6750 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A372E +P 6750 5050 +F 0 "U1" H 6800 5150 30 0000 C CNN +F 1 "PORT" H 6750 5050 30 0000 C CNN +F 2 "" H 6750 5050 60 0000 C CNN +F 3 "" H 6750 5050 60 0000 C CNN + 12 6750 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A375D +P 7050 5700 +F 0 "U1" H 7100 5800 30 0000 C CNN +F 1 "PORT" H 7050 5700 30 0000 C CNN +F 2 "" H 7050 5700 60 0000 C CNN +F 3 "" H 7050 5700 60 0000 C CNN + 11 7050 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A3796 +P 8200 5050 +F 0 "U1" H 8250 5150 30 0000 C CNN +F 1 "PORT" H 8200 5050 30 0000 C CNN +F 2 "" H 8200 5050 60 0000 C CNN +F 3 "" H 8200 5050 60 0000 C CNN + 13 8200 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 679A37C9 +P 8200 4000 +F 0 "U1" H 8250 4100 30 0000 C CNN +F 1 "PORT" H 8200 4000 30 0000 C CNN +F 2 "" H 8200 4000 60 0000 C CNN +F 3 "" H 8200 4000 60 0000 C CNN + 9 8200 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A37FE +P 8400 3350 +F 0 "U1" H 8450 3450 30 0000 C CNN +F 1 "PORT" H 8400 3350 30 0000 C CNN +F 2 "" H 8400 3350 60 0000 C CNN +F 3 "" H 8400 3350 60 0000 C CNN + 8 8400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 679A3835 +P 6650 4900 +F 0 "U1" H 6700 5000 30 0000 C CNN +F 1 "PORT" H 6650 4900 30 0000 C CNN +F 2 "" H 6650 4900 60 0000 C CNN +F 3 "" H 6650 4900 60 0000 C CNN + 14 6650 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5150 3250 5250 3250 +Connection ~ 5250 3250 +Wire Wire Line + 6650 4650 6650 4500 +Connection ~ 6650 4500 +$Comp +L MC1489_0 X1 +U 1 1 679A3C30 +P 5550 3650 +F 0 "X1" H 5550 3650 60 0000 C CNN +F 1 "MC1489_0" H 5550 3550 60 0000 C CNN +F 2 "" H 5550 3550 60 0001 C CNN +F 3 "" H 5550 3550 60 0001 C CNN + 1 5550 3650 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X3 +U 1 1 679A3C93 +P 7700 3700 +F 0 "X3" H 7700 3700 60 0000 C CNN +F 1 "MC1489_0" H 7700 3600 60 0000 C CNN +F 2 "" H 7700 3600 60 0001 C CNN +F 3 "" H 7700 3600 60 0001 C CNN + 1 7700 3700 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X2 +U 1 1 679A3FCC +P 5550 5400 +F 0 "X2" H 5550 5400 60 0000 C CNN +F 1 "MC1489_0" H 5550 5300 60 0000 C CNN +F 2 "" H 5550 5300 60 0001 C CNN +F 3 "" H 5550 5300 60 0001 C CNN + 1 5550 5400 + -1 0 0 1 +$EndComp +$Comp +L MC1489_0 X4 +U 1 1 679A4021 +P 7750 5350 +F 0 "X4" H 7750 5350 60 0000 C CNN +F 1 "MC1489_0" H 7750 5250 60 0000 C CNN +F 2 "" H 7750 5250 60 0001 C CNN +F 3 "" H 7750 5250 60 0001 C CNN + 1 7750 5350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sub b/library/SubcircuitLibrary/mc1489/mc1489.sub new file mode 100644 index 00000000..49e98c90 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sub @@ -0,0 +1,11 @@ +* Subcircuit mc1489 +.subckt mc1489 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir +.include MC1489_0.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +* Control Statements + +.ends mc1489
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml new file mode 100644 index 00000000..e3de6ceb --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/D.lib b/library/SubcircuitLibrary/mc1489A_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489A_0/NPN.lib b/library/SubcircuitLibrary/mc1489A_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489A_0/analysis b/library/SubcircuitLibrary/mc1489A_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir new file mode 100644 index 00000000..7b3d76c7 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489A_0\mc1489A_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 01:16:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 1.6K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out new file mode 100644 index 00000000..6fa09c26 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch new file mode 100644 index 00000000..d247d45d --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "1.6K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub new file mode 100644 index 00000000..e9ebfc80 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub @@ -0,0 +1,18 @@ +* Subcircuit mc1489A_0 +.subckt mc1489A_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* Control Statements + +.ends mc1489A_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/NPN.lib b/library/SubcircuitLibrary/tda7050/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/PNP.lib b/library/SubcircuitLibrary/tda7050/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/analysis b/library/SubcircuitLibrary/tda7050/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741-cache.lib b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib new file mode 100644 index 00000000..1ac4cbd4 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-lm_741 +# +DEF eSim_NPN-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-lm_741 +# +DEF eSim_PNP-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir b/library/SubcircuitLibrary/tda7050/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir.out b/library/SubcircuitLibrary/tda7050/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.pro b/library/SubcircuitLibrary/tda7050/lm_741.pro new file mode 100644 index 00000000..e6fc25cb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.pro @@ -0,0 +1,45 @@ +update=11/23/24 18:57:50 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=lm_741-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sch b/library/SubcircuitLibrary/tda7050/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 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+$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sub b/library/SubcircuitLibrary/tda7050/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/npn_1.lib b/library/SubcircuitLibrary/tda7050/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/pnp_1.lib b/library/SubcircuitLibrary/tda7050/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050-cache.lib b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib new file mode 100644 index 00000000..5b8e3633 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir b/library/SubcircuitLibrary/tda7050/tda7050.cir new file mode 100644 index 00000000..3cb98116 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tda7050\tda7050.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/08/25 21:45:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad5_ ? Net-_U1-Pad7_ Net-_U1-Pad8_ ? lm_741 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +X2 ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad8_ ? Net-_U1-Pad6_ Net-_U1-Pad5_ ? lm_741 + +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir.out b/library/SubcircuitLibrary/tda7050/tda7050.cir.out new file mode 100644 index 00000000..dbb02840 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir.out @@ -0,0 +1,15 @@ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir + +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.pro b/library/SubcircuitLibrary/tda7050/tda7050.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sch b/library/SubcircuitLibrary/tda7050/tda7050.sch new file mode 100644 index 00000000..2a82e7a3 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tda7050-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6000 2750 +Wire Wire Line + 5750 2750 6100 2750 +Wire Wire Line + 5500 4950 5600 4950 +Wire Wire Line + 6700 3500 6700 3450 +Wire Wire Line + 5750 2750 5750 4350 +Wire Wire Line + 5750 3950 6000 3950 +Wire Wire Line + 6000 3950 6000 3900 +Wire Wire Line + 5750 4350 6000 4350 +Connection ~ 5750 3950 +Wire Wire Line + 6000 2950 5300 2950 +$Comp +L lm_741 X1 +U 1 1 678D14D5 +P 6150 3450 +F 0 "X1" H 5950 3450 60 0000 C CNN +F 1 "lm_741" H 6050 3200 60 0000 C CNN +F 2 "" H 6150 3450 60 0000 C CNN +F 3 "" H 6150 3450 60 0000 C CNN + 1 6150 3450 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 679DC622 +P 6350 2750 +F 0 "U1" H 6400 2850 30 0000 C CNN +F 1 "PORT" H 6350 2750 30 0000 C CNN +F 2 "" H 6350 2750 60 0000 C CNN +F 3 "" H 6350 2750 60 0000 C CNN + 8 6350 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679DC653 +P 5500 5500 +F 0 "U1" H 5550 5600 30 0000 C CNN +F 1 "PORT" H 5500 5500 30 0000 C CNN +F 2 "" H 5500 5500 60 0000 C CNN +F 3 "" H 5500 5500 60 0000 C CNN + 5 5500 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679DC678 +P 5300 4700 +F 0 "U1" H 5350 4800 30 0000 C CNN +F 1 "PORT" H 5300 4700 30 0000 C CNN +F 2 "" H 5300 4700 60 0000 C CNN +F 3 "" H 5300 4700 60 0000 C CNN + 4 5300 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679DC69F +P 7000 4800 +F 0 "U1" H 7050 4900 30 0000 C CNN +F 1 "PORT" H 7000 4800 30 0000 C CNN +F 2 "" H 7000 4800 60 0000 C CNN +F 3 "" H 7000 4800 60 0000 C CNN + 6 7000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 679DC6C8 +P 5250 4950 +F 0 "U1" H 5300 5050 30 0000 C CNN +F 1 "PORT" H 5250 4950 30 0000 C CNN +F 2 "" H 5250 4950 60 0000 C CNN +F 3 "" H 5250 4950 60 0000 C CNN + 3 5250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679DC6F3 +P 6950 3500 +F 0 "U1" H 7000 3600 30 0000 C CNN +F 1 "PORT" H 6950 3500 30 0000 C CNN +F 2 "" H 6950 3500 60 0000 C CNN +F 3 "" H 6950 3500 60 0000 C CNN + 7 6950 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679DC720 +P 5300 3600 +F 0 "U1" H 5350 3700 30 0000 C CNN +F 1 "PORT" H 5300 3600 30 0000 C CNN +F 2 "" H 5300 3600 60 0000 C CNN +F 3 "" H 5300 3600 60 0000 C CNN + 2 5300 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679DC74F +P 5150 3350 +F 0 "U1" H 5200 3450 30 0000 C CNN +F 1 "PORT" H 5150 3350 30 0000 C CNN +F 2 "" H 5150 3350 60 0000 C CNN +F 3 "" H 5150 3350 60 0000 C CNN + 1 5150 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2950 5300 5350 +Wire Wire Line + 5300 5350 6000 5350 +Connection ~ 6000 5350 +Wire Wire Line + 5750 5500 5900 5500 +Wire Wire Line + 5900 5500 5900 5400 +Wire Wire Line + 5900 5400 6000 5400 +Connection ~ 6000 5400 +$Comp +L lm_741 X2 +U 1 1 678D14EC +P 6150 4800 +F 0 "X2" H 5950 4800 60 0000 C CNN +F 1 "lm_741" H 6050 4550 60 0000 C CNN +F 2 "" H 6150 4800 60 0000 C CNN +F 3 "" H 6150 4800 60 0000 C CNN + 1 6150 4800 + 1 0 0 1 +$EndComp +Wire Wire Line + 5550 3600 5600 3600 +Wire Wire Line + 5550 4700 5600 4700 +Wire Wire Line + 6000 5400 6000 5250 +Wire Wire Line + 5400 3350 5600 3350 +Wire Wire Line + 6750 4800 6700 4800 +Wire Wire Line + 6000 3000 6000 2950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sub b/library/SubcircuitLibrary/tda7050/tda7050.sub new file mode 100644 index 00000000..a4faab2c --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sub @@ -0,0 +1,9 @@ +* Subcircuit tda7050 +.subckt tda7050 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +* Control Statements + +.ends tda7050
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml new file mode 100644 index 00000000..08c5b203 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x2></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/browser/User-Manual/eSim.html b/library/browser/User-Manual/eSim.html index 79afa31e..712ecbaf 100644 --- a/library/browser/User-Manual/eSim.html +++ b/library/browser/User-Manual/eSim.html @@ -28,7 +28,7 @@ src="figures/logo-trimmed.png" alt="PIC" <span class="cmbx-12x-x-144">eSim User Manual</span><br /> <span -class="cmr-10">version 1.0.0</span><br /> +class="cmr-10">version 2.4.0</span><br /> <span class="cmbx-10">Prepared By:</span><br /> <span @@ -3565,7 +3565,8 @@ href="http://www.scilab.org/" class="url" >http://www.scilab.org/</a> [4]<span class="bibsp">   </span></span><a id="XGARUDA"></a>(2013, May). [Online]. Available: <a -href="http://scilab-test.garudaindia.in/scilab_in/,
http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> +href="http://scilab-test.garudaindia.in/scilab_in/, + http://scilab-test.garudaindia.in/cloud" class="url" >http://scilab-test.garudaindia.in/scilab_in/,http://scilab-test.garudaindia.in/cloud</a> </p> <p class="bibitem" ><span class="biblabel"> [5]<span class="bibsp">   </span></span><a |