diff options
Diffstat (limited to 'library')
128 files changed, 9490 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/MC1489_0/D.lib b/library/SubcircuitLibrary/MC1489_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC1489_0/NPN.lib b/library/SubcircuitLibrary/MC1489_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/MC1489_0/analysis b/library/SubcircuitLibrary/MC1489_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC1489_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..895e7634 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:44:11 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 500 +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 60k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 10k +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 10k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..2c658aae --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..99c63cf9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "500" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "60k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "10k" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "10k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..544c5e10 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 500 +r2 net-_r1-pad1_ net-_q3-pad1_ 60k +r4 net-_q4-pad1_ net-_r1-pad1_ 10k +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 10k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/NAND_GATE_FINAL/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 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150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/D.lib b/library/SubcircuitLibrary/SN55188/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188/NPN.lib b/library/SubcircuitLibrary/SN55188/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/PNP.lib b/library/SubcircuitLibrary/SN55188/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188/SN55188-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib new file mode 100644 index 00000000..e532722e --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188-cache.lib @@ -0,0 +1,62 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# SN55188_0 +# +DEF SN55188_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "SN55188_0" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -400 200 450 -300 0 1 0 N +X Vcc+ 1 -600 100 200 R 50 50 1 1 I +X A 2 -100 400 200 D 50 50 1 1 I +X B 3 200 400 200 D 50 50 1 1 I +X gnd 4 0 -500 200 U 50 50 1 1 I +X Vcc- 5 -600 -200 200 R 50 50 1 1 I +X OUTPUT 6 650 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir b/library/SubcircuitLibrary/SN55188/SN55188.cir new file mode 100644 index 00000000..d12a8992 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188\SN55188.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 00:32:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X2 Vcc+ Net-_U1-Pad2_ Net-_U1-Pad2_ gnd Vcc- Net-_U1-Pad3_ SN55188_0 +X3 Vcc+ Net-_U1-Pad9_ Net-_U1-Pad10_ gnd Vcc- Net-_U1-Pad8_ SN55188_0 +X1 Vcc+ Net-_U1-Pad4_ Net-_U1-Pad5_ gnd Vcc- Net-_U1-Pad6_ SN55188_0 +X4 Vcc+ Net-_U1-Pad12_ Net-_U1-Pad13_ gnd Vcc- Net-_U1-Pad11_ SN55188_0 +U1 Vcc- Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Vcc+ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.cir.out b/library/SubcircuitLibrary/SN55188/SN55188.cir.out new file mode 100644 index 00000000..70d80115 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir + +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* u1 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188.pro b/library/SubcircuitLibrary/SN55188/SN55188.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sch b/library/SubcircuitLibrary/SN55188/SN55188.sch new file mode 100644 index 00000000..55a59692 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sch @@ -0,0 +1,347 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L SN55188_0 X2 +U 1 1 679A4CEC +P 5350 3700 +F 0 "X2" H 5350 3700 60 0000 C CNN +F 1 "SN55188_0" H 5350 3600 60 0000 C CNN +F 2 "" H 5350 3700 60 0001 C CNN +F 3 "" H 5350 3700 60 0001 C CNN + 1 5350 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X3 +U 1 1 679A4D5D +P 7150 3700 +F 0 "X3" H 7150 3700 60 0000 C CNN +F 1 "SN55188_0" H 7150 3600 60 0000 C CNN +F 2 "" H 7150 3700 60 0001 C CNN +F 3 "" H 7150 3700 60 0001 C CNN + 1 7150 3700 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X1 +U 1 1 679A4D76 +P 5300 5100 +F 0 "X1" H 5300 5100 60 0000 C CNN +F 1 "SN55188_0" H 5300 5000 60 0000 C CNN +F 2 "" H 5300 5100 60 0001 C CNN +F 3 "" H 5300 5100 60 0001 C CNN + 1 5300 5100 + 1 0 0 -1 +$EndComp +$Comp +L SN55188_0 X4 +U 1 1 679A4D97 +P 7200 5150 +F 0 "X4" H 7200 5150 60 0000 C CNN +F 1 "SN55188_0" H 7200 5050 60 0000 C CNN +F 2 "" H 7200 5150 60 0001 C CNN +F 3 "" H 7200 5150 60 0001 C CNN + 1 7200 5150 + 1 0 0 -1 +$EndComp +Text GLabel 5500 4200 2 60 Input ~ 0 +gnd +Text GLabel 5450 5600 2 60 Input ~ 0 +gnd +Text GLabel 7350 5650 2 60 Input ~ 0 +gnd +Text GLabel 7300 4200 2 60 Input ~ 0 +gnd +Text GLabel 4600 3600 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 4800 0 60 Input ~ 0 +Vcc+ +Text GLabel 6550 3400 0 60 Input ~ 0 +Vcc+ +Text GLabel 6600 4850 0 60 Input ~ 0 +Vcc+ +Text GLabel 4700 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 6600 5550 0 60 Input ~ 0 +Vcc- +Text GLabel 4600 3900 0 60 Input ~ 0 +Vcc- +Text GLabel 6550 4100 0 60 Input ~ 0 +Vcc- +$Comp +L PORT U1 +U 14 1 679A4FA0 +P 6150 3550 +F 0 "U1" H 6200 3650 30 0000 C CNN +F 1 "PORT" H 6150 3550 30 0000 C CNN +F 2 "" H 6150 3550 60 0000 C CNN +F 3 "" H 6150 3550 60 0000 C CNN + 14 6150 3550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A4FBF +P 7700 4600 +F 0 "U1" H 7750 4700 30 0000 C CNN +F 1 "PORT" H 7700 4600 30 0000 C CNN +F 2 "" H 7700 4600 60 0000 C CNN +F 3 "" H 7700 4600 60 0000 C CNN + 13 7700 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A4FF6 +P 6350 5150 +F 0 "U1" H 6400 5250 30 0000 C CNN +F 1 "PORT" H 6350 5150 30 0000 C CNN +F 2 "" H 6350 5150 60 0000 C CNN +F 3 "" H 6350 5150 60 0000 C CNN + 6 6350 5150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A5019 +P 6750 4200 +F 0 "U1" H 6800 4300 30 0000 C CNN +F 1 "PORT" H 6750 4200 30 0000 C CNN +F 2 "" H 6750 4200 60 0000 C CNN +F 3 "" H 6750 4200 60 0000 C CNN + 7 6750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A503E +P 7850 4000 +F 0 "U1" H 7900 4100 30 0000 C CNN +F 1 "PORT" H 7850 4000 30 0000 C CNN +F 2 "" H 7850 4000 60 0000 C CNN +F 3 "" H 7850 4000 60 0000 C CNN + 8 7850 4000 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 679A5065 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 9 6750 3150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A508E +P 7650 3150 +F 0 "U1" H 7700 3250 30 0000 C CNN +F 1 "PORT" H 7650 3150 30 0000 C CNN +F 2 "" H 7650 3150 60 0000 C CNN +F 3 "" H 7650 3150 60 0000 C CNN + 10 7650 3150 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A50B9 +P 8250 5200 +F 0 "U1" H 8300 5300 30 0000 C CNN +F 1 "PORT" H 8250 5200 30 0000 C CNN +F 2 "" H 8250 5200 60 0000 C CNN +F 3 "" H 8250 5200 60 0000 C CNN + 11 8250 5200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A50E6 +P 4850 4450 +F 0 "U1" H 4900 4550 30 0000 C CNN +F 1 "PORT" H 4850 4450 30 0000 C CNN +F 2 "" H 4850 4450 60 0000 C CNN +F 3 "" H 4850 4450 60 0000 C CNN + 4 4850 4450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A5115 +P 5850 4450 +F 0 "U1" H 5900 4550 30 0000 C CNN +F 1 "PORT" H 5850 4450 30 0000 C CNN +F 2 "" H 5850 4450 60 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 5 5850 4450 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A5146 +P 6800 4600 +F 0 "U1" H 6850 4700 30 0000 C CNN +F 1 "PORT" H 6800 4600 30 0000 C CNN +F 2 "" H 6800 4600 60 0000 C CNN +F 3 "" H 6800 4600 60 0000 C CNN + 12 6800 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A5179 +P 6300 3750 +F 0 "U1" H 6350 3850 30 0000 C CNN +F 1 "PORT" H 6300 3750 30 0000 C CNN +F 2 "" H 6300 3750 60 0000 C CNN +F 3 "" H 6300 3750 60 0000 C CNN + 3 6300 3750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A51C2 +P 5100 3000 +F 0 "U1" H 5150 3100 30 0000 C CNN +F 1 "PORT" H 5100 3000 30 0000 C CNN +F 2 "" H 5100 3000 60 0000 C CNN +F 3 "" H 5100 3000 60 0000 C CNN + 2 5100 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A51F9 +P 6200 3950 +F 0 "U1" H 6250 4050 30 0000 C CNN +F 1 "PORT" H 6200 3950 30 0000 C CNN +F 2 "" H 6200 3950 60 0000 C CNN +F 3 "" H 6200 3950 60 0000 C CNN + 1 6200 3950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 5600 5450 5600 +Wire Wire Line + 7200 5650 7350 5650 +Wire Wire Line + 7000 4200 7300 4200 +Wire Wire Line + 5350 4200 5500 4200 +Wire Wire Line + 4750 3600 4600 3600 +Wire Wire Line + 4750 3900 4600 3900 +Wire Wire Line + 6550 3600 6550 3400 +Wire Wire Line + 6550 3900 6550 4100 +Wire Wire Line + 6600 5050 6600 4850 +Wire Wire Line + 6600 5350 6600 5550 +Wire Wire Line + 4700 5300 4700 5550 +Wire Wire Line + 4700 5000 4700 4800 +Wire Wire Line + 5250 3300 5550 3300 +Wire Wire Line + 5350 3300 5350 3000 +Connection ~ 5350 3300 +Wire Wire Line + 6450 3950 6550 3950 +Connection ~ 6550 3950 +Wire Wire Line + 6400 3550 6550 3550 +Connection ~ 6550 3550 +Connection ~ 7150 4200 +Wire Wire Line + 7050 3300 7050 3150 +Wire Wire Line + 7050 3150 7000 3150 +Wire Wire Line + 7350 3300 7350 3150 +Wire Wire Line + 7350 3150 7400 3150 +Wire Wire Line + 7100 4750 7100 4600 +Wire Wire Line + 7100 4600 7050 4600 +Wire Wire Line + 7400 4750 7400 4600 +Wire Wire Line + 7400 4600 7450 4600 +Wire Wire Line + 5200 4700 5200 4450 +Wire Wire Line + 5200 4450 5100 4450 +Wire Wire Line + 5500 4700 5500 4450 +Wire Wire Line + 5500 4450 5600 4450 +Wire Wire Line + 7800 3750 7850 3750 +Wire Wire Line + 7850 5200 8000 5200 +Wire Wire Line + 5950 5150 6100 5150 +Wire Wire Line + 6000 3750 6050 3750 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188.sub b/library/SubcircuitLibrary/SN55188/SN55188.sub new file mode 100644 index 00000000..eedf8204 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188.sub @@ -0,0 +1,11 @@ +* Subcircuit SN55188 +.subckt SN55188 vcc- net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ vcc+ +* c:\fossee\esim\library\subcircuitlibrary\sn55188\sn55188.cir +.include SN55188_0.sub +x2 vcc+ net-_u1-pad2_ net-_u1-pad2_ gnd vcc- net-_u1-pad3_ SN55188_0 +x3 vcc+ net-_u1-pad9_ net-_u1-pad10_ gnd vcc- net-_u1-pad8_ SN55188_0 +x1 vcc+ net-_u1-pad4_ net-_u1-pad5_ gnd vcc- net-_u1-pad6_ SN55188_0 +x4 vcc+ net-_u1-pad12_ net-_u1-pad13_ gnd vcc- net-_u1-pad11_ SN55188_0 +* Control Statements + +.ends SN55188
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir b/library/SubcircuitLibrary/SN55188/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.pro b/library/SubcircuitLibrary/SN55188/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sch b/library/SubcircuitLibrary/SN55188/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0.sub b/library/SubcircuitLibrary/SN55188/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml new file mode 100644 index 00000000..61a626af --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/SN55188_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x2><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x3><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x1><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188/analysis b/library/SubcircuitLibrary/SN55188/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/D.lib b/library/SubcircuitLibrary/SN55188_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN55188_0/NPN.lib b/library/SubcircuitLibrary/SN55188_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/PNP.lib b/library/SubcircuitLibrary/SN55188_0/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib new file mode 100644 index 00000000..fa8f67b2 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir new file mode 100644 index 00000000..f4dc9203 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir @@ -0,0 +1,33 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN55188_0\SN55188_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 19:31:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_D4-Pad2_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_D9-Pad1_ eSim_NPN +Q3 Net-_D5-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +Q5 Net-_D5-Pad2_ Net-_Q3-Pad3_ Net-_Q2-Pad2_ eSim_NPN +R3 Net-_Q1-Pad1_ Net-_D9-Pad1_ 10k +R1 Net-_D4-Pad2_ Net-_Q1-Pad2_ 3.6k +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +D3 Net-_D1-Pad1_ Net-_D3-Pad2_ eSim_Diode +R2 Net-_D8-Pad2_ Net-_D1-Pad1_ 8.2k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad1_ Net-_D2-Pad2_ eSim_Diode +Q4 Net-_D8-Pad2_ Net-_D5-Pad1_ Net-_Q4-Pad3_ eSim_NPN +R4 Net-_D8-Pad2_ Net-_D5-Pad1_ 6.2k +R6 Net-_Q4-Pad3_ Net-_D6-Pad2_ 70 +D6 Net-_D5-Pad2_ Net-_D6-Pad2_ eSim_Diode +D7 Net-_D6-Pad2_ Net-_D5-Pad2_ eSim_Diode +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +R7 Net-_Q2-Pad2_ Net-_D9-Pad1_ 70 +R5 Net-_Q3-Pad3_ Net-_D9-Pad1_ 3.7k +D9 Net-_D9-Pad1_ Net-_D6-Pad2_ eSim_Diode +R8 Net-_D6-Pad2_ Net-_R8-Pad2_ 300 +D8 Net-_D6-Pad2_ Net-_D8-Pad2_ eSim_Diode +U1 Net-_D8-Pad2_ Net-_D1-Pad2_ Net-_D2-Pad2_ Net-_Q1-Pad2_ Net-_D9-Pad1_ Net-_R8-Pad2_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out new file mode 100644 index 00000000..e8b8112c --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.cir.out @@ -0,0 +1,37 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* u1 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch new file mode 100644 index 00000000..d377648b --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sch @@ -0,0 +1,482 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:SN55188_0-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q1 +U 1 1 679A4558 +P 5150 3900 +F 0 "Q1" H 5050 3950 50 0000 R CNN +F 1 "eSim_PNP" H 5100 4050 50 0000 R CNN +F 2 "" H 5350 4000 29 0000 C CNN +F 3 "" H 5150 3900 60 0000 C CNN + 1 5150 3900 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A45B5 +P 6150 5150 +F 0 "Q2" H 6050 5200 50 0000 R CNN +F 1 "eSim_NPN" H 6100 5300 50 0000 R CNN +F 2 "" H 6350 5250 29 0000 C CNN +F 3 "" H 6150 5150 60 0000 C CNN + 1 6150 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A45D0 +P 6500 4500 +F 0 "Q3" H 6400 4550 50 0000 R CNN +F 1 "eSim_NPN" H 6450 4650 50 0000 R CNN +F 2 "" H 6700 4600 29 0000 C CNN +F 3 "" H 6500 4500 60 0000 C CNN + 1 6500 4500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 679A45F1 +P 7650 4750 +F 0 "Q5" H 7550 4800 50 0000 R CNN +F 1 "eSim_NPN" H 7600 4900 50 0000 R CNN +F 2 "" H 7850 4850 29 0000 C CNN +F 3 "" H 7650 4750 60 0000 C CNN + 1 7650 4750 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 679A462D +P 5200 4900 +F 0 "R3" H 5250 5030 50 0000 C CNN +F 1 "10k" H 5250 4850 50 0000 C CNN +F 2 "" H 5250 4880 30 0000 C CNN +F 3 "" V 5250 4950 30 0000 C CNN + 1 5200 4900 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 679A468F +P 4700 3600 +F 0 "R1" H 4750 3730 50 0000 C CNN +F 1 "3.6k" H 4750 3550 50 0000 C CNN +F 2 "" H 4750 3580 30 0000 C CNN +F 3 "" V 4750 3650 30 0000 C CNN + 1 4700 3600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 679A46FA +P 5250 3150 +F 0 "D4" H 5250 3250 50 0000 C CNN +F 1 "eSim_Diode" H 5250 3050 50 0000 C CNN +F 2 "" H 5250 3150 60 0000 C CNN +F 3 "" H 5250 3150 60 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 679A4721 +P 5250 2750 +F 0 "D3" H 5250 2850 50 0000 C CNN +F 1 "eSim_Diode" H 5250 2650 50 0000 C CNN +F 2 "" H 5250 2750 60 0000 C CNN +F 3 "" H 5250 2750 60 0000 C CNN + 1 5250 2750 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 679A492E +P 5200 2000 +F 0 "R2" H 5250 2130 50 0000 C CNN +F 1 "8.2k" H 5250 1950 50 0000 C CNN +F 2 "" H 5250 1980 30 0000 C CNN +F 3 "" V 5250 2050 30 0000 C CNN + 1 5200 2000 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 679A4971 +P 4650 2300 +F 0 "D1" H 4650 2400 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2200 50 0000 C CNN +F 2 "" H 4650 2300 60 0000 C CNN +F 3 "" H 4650 2300 60 0000 C CNN + 1 4650 2300 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 679A49A2 +P 4650 2550 +F 0 "D2" H 4650 2650 50 0000 C CNN +F 1 "eSim_Diode" H 4650 2450 50 0000 C CNN +F 2 "" H 4650 2550 60 0000 C CNN +F 3 "" H 4650 2550 60 0000 C CNN + 1 4650 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 679A4B4C +P 7050 2200 +F 0 "Q4" H 6950 2250 50 0000 R CNN +F 1 "eSim_NPN" H 7000 2350 50 0000 R CNN +F 2 "" H 7250 2300 29 0000 C CNN +F 3 "" H 7050 2200 60 0000 C CNN + 1 7050 2200 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 679A4B8A +P 6350 1950 +F 0 "R4" H 6400 2080 50 0000 C CNN +F 1 "6.2k" H 6400 1900 50 0000 C CNN +F 2 "" H 6400 1930 30 0000 C CNN +F 3 "" V 6400 2000 30 0000 C CNN + 1 6350 1950 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A4C18 +P 7100 2800 +F 0 "R6" H 7150 2930 50 0000 C CNN +F 1 "70" H 7150 2750 50 0000 C CNN +F 2 "" H 7150 2780 30 0000 C CNN +F 3 "" V 7150 2850 30 0000 C CNN + 1 7100 2800 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 679A4CD7 +P 7150 3200 +F 0 "D6" H 7150 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7150 3100 50 0000 C CNN +F 2 "" H 7150 3200 60 0000 C CNN +F 3 "" H 7150 3200 60 0000 C CNN + 1 7150 3200 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 679A4D12 +P 7950 3200 +F 0 "D7" H 7950 3300 50 0000 C CNN +F 1 "eSim_Diode" H 7950 3100 50 0000 C CNN +F 2 "" H 7950 3200 60 0000 C CNN +F 3 "" H 7950 3200 60 0000 C CNN + 1 7950 3200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 679A4DFD +P 6900 3350 +F 0 "D5" H 6900 3450 50 0000 C CNN +F 1 "eSim_Diode" H 6900 3250 50 0000 C CNN +F 2 "" H 6900 3350 60 0000 C CNN +F 3 "" H 6900 3350 60 0000 C CNN + 1 6900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5250 4100 5250 4800 +Wire Wire Line + 5250 5100 5250 5350 +Wire Wire Line + 4350 5350 8450 5350 +Wire Wire Line + 6300 4500 5250 4500 +Connection ~ 5250 4500 +Wire Wire Line + 6050 4950 6050 4500 +Connection ~ 6050 4500 +Connection ~ 5250 5350 +Wire Wire Line + 4750 3800 4750 3900 +Wire Wire Line + 4250 3900 4950 3900 +Wire Wire Line + 4750 3500 4750 3400 +Wire Wire Line + 4750 3400 5250 3400 +Wire Wire Line + 5250 3300 5250 3700 +Connection ~ 4750 3900 +Wire Wire Line + 5250 2900 5250 3000 +Connection ~ 5250 3400 +Wire Wire Line + 5250 2600 5250 2200 +Wire Wire Line + 4800 2550 5250 2550 +Connection ~ 5250 2550 +Wire Wire Line + 4800 2300 5250 2300 +Connection ~ 5250 2300 +Wire Wire Line + 4500 2300 4100 2300 +Wire Wire Line + 4500 2550 4100 2550 +Wire Wire Line + 5250 1900 5250 1700 +Wire Wire Line + 4100 1700 8100 1700 +Wire Wire Line + 7150 1700 7150 2000 +Connection ~ 5250 1700 +Wire Wire Line + 6400 1850 6400 1700 +Connection ~ 6400 1700 +Wire Wire Line + 6400 2150 6400 3350 +Wire Wire Line + 6400 2200 6850 2200 +Wire Wire Line + 7150 2400 7150 2700 +Wire Wire Line + 7150 3000 8750 3000 +Wire Wire Line + 7050 3350 7950 3350 +Wire Wire Line + 7150 3050 7150 3000 +Wire Wire Line + 7950 3050 7950 3000 +Connection ~ 7950 3000 +Wire Wire Line + 6400 3350 6750 3350 +Wire Wire Line + 6700 3350 6700 3500 +Connection ~ 7150 3350 +Connection ~ 6700 3350 +Connection ~ 6400 2200 +Connection ~ 5250 4200 +Wire Wire Line + 6600 4300 6600 3500 +Wire Wire Line + 6600 3500 6700 3500 +$Comp +L resistor R7 +U 1 1 679A536E +P 7700 5100 +F 0 "R7" H 7750 5230 50 0000 C CNN +F 1 "70" H 7750 5050 50 0000 C CNN +F 2 "" H 7750 5080 30 0000 C CNN +F 3 "" V 7750 5150 30 0000 C CNN + 1 7700 5100 + 0 1 1 0 +$EndComp +Wire Wire Line + 7750 5350 7750 5300 +Connection ~ 6050 5350 +Wire Wire Line + 7750 5000 7750 4950 +Wire Wire Line + 6350 5150 7550 5150 +Wire Wire Line + 7550 5150 7550 5000 +Wire Wire Line + 7550 5000 7750 5000 +Wire Wire Line + 6600 4700 6600 4800 +Wire Wire Line + 6600 4800 7450 4800 +Wire Wire Line + 7450 4800 7450 4750 +$Comp +L resistor R5 +U 1 1 679A55E9 +P 7000 5000 +F 0 "R5" H 7050 5130 50 0000 C CNN +F 1 "3.7k" H 7050 4950 50 0000 C CNN +F 2 "" H 7050 4980 30 0000 C CNN +F 3 "" V 7050 5050 30 0000 C CNN + 1 7000 5000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7050 4900 7050 4800 +Connection ~ 7050 4800 +Wire Wire Line + 7050 5200 7050 5350 +Connection ~ 7050 5350 +$Comp +L eSim_Diode D9 +U 1 1 679A5738 +P 8450 4050 +F 0 "D9" H 8450 4150 50 0000 C CNN +F 1 "eSim_Diode" H 8450 3950 50 0000 C CNN +F 2 "" H 8450 4050 60 0000 C CNN +F 3 "" H 8450 4050 60 0000 C CNN + 1 8450 4050 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8450 5350 8450 4200 +Connection ~ 7750 5350 +Wire Wire Line + 8450 3900 8450 3000 +Connection ~ 8450 3000 +$Comp +L resistor R8 +U 1 1 679A5A13 +P 8850 3050 +F 0 "R8" H 8900 3180 50 0000 C CNN +F 1 "300" H 8900 3000 50 0000 C CNN +F 2 "" H 8900 3030 30 0000 C CNN +F 3 "" V 8900 3100 30 0000 C CNN + 1 8850 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3000 9250 3000 +$Comp +L eSim_Diode D8 +U 1 1 679A5C7A +P 8100 2150 +F 0 "D8" H 8100 2250 50 0000 C CNN +F 1 "eSim_Diode" H 8100 2050 50 0000 C CNN +F 2 "" H 8100 2150 60 0000 C CNN +F 3 "" H 8100 2150 60 0000 C CNN + 1 8100 2150 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 8100 2300 8100 3000 +Connection ~ 8100 3000 +Wire Wire Line + 8100 1700 8100 2000 +Connection ~ 7150 1700 +$Comp +L PORT U1 +U 2 1 679A6ACB +P 3850 2300 +F 0 "U1" H 3900 2400 30 0000 C CNN +F 1 "PORT" H 3850 2300 30 0000 C CNN +F 2 "" H 3850 2300 60 0000 C CNN +F 3 "" H 3850 2300 60 0000 C CNN + 2 3850 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A6B0E +P 4000 3900 +F 0 "U1" H 4050 4000 30 0000 C CNN +F 1 "PORT" H 4000 3900 30 0000 C CNN +F 2 "" H 4000 3900 60 0000 C CNN +F 3 "" H 4000 3900 60 0000 C CNN + 4 4000 3900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 679A6B53 +P 3850 2550 +F 0 "U1" H 3900 2650 30 0000 C CNN +F 1 "PORT" H 3850 2550 30 0000 C CNN +F 2 "" H 3850 2550 60 0000 C CNN +F 3 "" H 3850 2550 60 0000 C CNN + 3 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A6BB3 +P 3850 1700 +F 0 "U1" H 3900 1800 30 0000 C CNN +F 1 "PORT" H 3850 1700 30 0000 C CNN +F 2 "" H 3850 1700 60 0000 C CNN +F 3 "" H 3850 1700 60 0000 C CNN + 1 3850 1700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A6BFC +P 4100 5350 +F 0 "U1" H 4150 5450 30 0000 C CNN +F 1 "PORT" H 4100 5350 30 0000 C CNN +F 2 "" H 4100 5350 60 0000 C CNN +F 3 "" H 4100 5350 60 0000 C CNN + 5 4100 5350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A6C47 +P 9500 3000 +F 0 "U1" H 9550 3100 30 0000 C CNN +F 1 "PORT" H 9500 3000 30 0000 C CNN +F 2 "" H 9500 3000 60 0000 C CNN +F 3 "" H 9500 3000 60 0000 C CNN + 6 9500 3000 + -1 0 0 1 +$EndComp +Wire Wire Line + 7950 3350 7950 4550 +Wire Wire Line + 7950 4550 7750 4550 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub new file mode 100644 index 00000000..c9c0104a --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0.sub @@ -0,0 +1,31 @@ +* Subcircuit SN55188_0 +.subckt SN55188_0 net-_d8-pad2_ net-_d1-pad2_ net-_d2-pad2_ net-_q1-pad2_ net-_d9-pad1_ net-_r8-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\sn55188_0\sn55188_0.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_d4-pad2_ Q2N2907A +q2 net-_q1-pad1_ net-_q2-pad2_ net-_d9-pad1_ Q2N2222 +q3 net-_d5-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +q5 net-_d5-pad2_ net-_q3-pad3_ net-_q2-pad2_ Q2N2222 +r3 net-_q1-pad1_ net-_d9-pad1_ 10k +r1 net-_d4-pad2_ net-_q1-pad2_ 3.6k +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +d3 net-_d1-pad1_ net-_d3-pad2_ 1N4148 +r2 net-_d8-pad2_ net-_d1-pad1_ 8.2k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad1_ net-_d2-pad2_ 1N4148 +q4 net-_d8-pad2_ net-_d5-pad1_ net-_q4-pad3_ Q2N2222 +r4 net-_d8-pad2_ net-_d5-pad1_ 6.2k +r6 net-_q4-pad3_ net-_d6-pad2_ 70 +d6 net-_d5-pad2_ net-_d6-pad2_ 1N4148 +d7 net-_d6-pad2_ net-_d5-pad2_ 1N4148 +d5 net-_d5-pad1_ net-_d5-pad2_ 1N4148 +r7 net-_q2-pad2_ net-_d9-pad1_ 70 +r5 net-_q3-pad3_ net-_d9-pad1_ 3.7k +d9 net-_d9-pad1_ net-_d6-pad2_ 1N4148 +r8 net-_d6-pad2_ net-_r8-pad2_ 300 +d8 net-_d6-pad2_ net-_d8-pad2_ 1N4148 +* Control Statements + +.ends SN55188_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml new file mode 100644 index 00000000..5ada64f3 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/SN55188_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN55188_0/analysis b/library/SubcircuitLibrary/SN55188_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN55188_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/D.lib b/library/SubcircuitLibrary/SN74LS00/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib new file mode 100644 index 00000000..26ac6e60 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL-cache.lib @@ -0,0 +1,120 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir new file mode 100644 index 00000000..68e79d37 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL\NAND_GATE_FINAL.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:38:44 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +R1 Net-_R1-Pad1_ Net-_Q1-Pad2_ 4k +R2 Net-_R1-Pad1_ Net-_Q3-Pad1_ 1.6k +R4 Net-_Q4-Pad1_ Net-_R1-Pad1_ 130 +Q4 Net-_Q4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q1-Pad1_ Net-_Q3-Pad3_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q5 Net-_D1-Pad2_ Net-_Q3-Pad3_ GND eSim_NPN +R3 Net-_Q3-Pad3_ GND 1k +U1 Net-_Q1-Pad3_ Net-_Q2-Pad3_ Net-_D1-Pad2_ Net-_R1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out new file mode 100644 index 00000000..51032802 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir + +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* u1 net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch new file mode 100644 index 00000000..223fa915 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sch @@ -0,0 +1,284 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:NAND_GATE_FINAL-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q2 +U 1 1 67704AAF +P 3150 4650 +F 0 "Q2" H 3050 4700 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4800 50 0000 R CNN +F 2 "" H 3350 4750 29 0000 C CNN +F 3 "" H 3150 4650 60 0000 C CNN + 1 3150 4650 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 67704B0A +P 2350 4650 +F 0 "Q1" H 2250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 2300 4800 50 0000 R CNN +F 2 "" H 2550 4750 29 0000 C CNN +F 3 "" H 2350 4650 60 0000 C CNN + 1 2350 4650 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 67704BF2 +P 2700 3400 +F 0 "R1" H 2750 3530 50 0000 C CNN +F 1 "4k" H 2750 3350 50 0000 C CNN +F 2 "" H 2750 3380 30 0000 C CNN +F 3 "" V 2750 3450 30 0000 C CNN + 1 2700 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 67704C41 +P 3600 3400 +F 0 "R2" H 3650 3530 50 0000 C CNN +F 1 "1.6k" H 3650 3350 50 0000 C CNN +F 2 "" H 3650 3380 30 0000 C CNN +F 3 "" V 3650 3450 30 0000 C CNN + 1 3600 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 67704C62 +P 4650 3500 +F 0 "R4" H 4700 3630 50 0000 C CNN +F 1 "130" H 4700 3450 50 0000 C CNN +F 2 "" H 4700 3480 30 0000 C CNN +F 3 "" V 4700 3550 30 0000 C CNN + 1 4650 3500 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 67704C93 +P 4500 4050 +F 0 "Q4" H 4400 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4450 4200 50 0000 R CNN +F 2 "" H 4700 4150 29 0000 C CNN +F 3 "" H 4500 4050 60 0000 C CNN + 1 4500 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 67704CC8 +P 3900 4350 +F 0 "Q3" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 67704D0D +P 4600 4600 +F 0 "D1" H 4600 4700 50 0000 C CNN +F 1 "eSim_Diode" H 4600 4500 50 0000 C CNN +F 2 "" H 4600 4600 60 0000 C CNN +F 3 "" H 4600 4600 60 0000 C CNN + 1 4600 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 67704DC5 +P 4500 5250 +F 0 "Q5" H 4400 5300 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5400 50 0000 R CNN +F 2 "" H 4700 5350 29 0000 C CNN +F 3 "" H 4500 5250 60 0000 C CNN + 1 4500 5250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 67704DD6 +P 3950 5500 +F 0 "R3" H 4000 5630 50 0000 C CNN +F 1 "1k" V 4000 5450 50 0000 C CNN +F 2 "" H 4000 5480 30 0000 C CNN +F 3 "" V 4000 5550 30 0000 C CNN + 1 3950 5500 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 67705207 +P 2450 5250 +F 0 "U1" H 2500 5350 30 0000 C CNN +F 1 "PORT" H 2450 5250 30 0000 C CNN +F 2 "" H 2450 5250 60 0000 C CNN +F 3 "" H 2450 5250 60 0000 C CNN + 1 2450 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 67705289 +P 3050 5250 +F 0 "U1" H 3100 5350 30 0000 C CNN +F 1 "PORT" H 3050 5250 30 0000 C CNN +F 2 "" H 3050 5250 60 0000 C CNN +F 3 "" H 3050 5250 60 0000 C CNN + 2 3050 5250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677052CE +P 5300 4900 +F 0 "U1" H 5350 5000 30 0000 C CNN +F 1 "PORT" H 5300 4900 30 0000 C CNN +F 2 "" H 5300 4900 60 0000 C CNN +F 3 "" H 5300 4900 60 0000 C CNN + 3 5300 4900 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 67705545 +P 4750 5800 +F 0 "#PWR01" H 4750 5550 50 0001 C CNN +F 1 "GND" H 4750 5650 50 0000 C CNN +F 2 "" H 4750 5800 50 0001 C CNN +F 3 "" H 4750 5800 50 0001 C CNN + 1 4750 5800 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 3050 4450 2450 4450 +Wire Wire Line + 3350 4150 2150 4150 +Wire Wire Line + 3350 4650 3350 4150 +Wire Wire Line + 2150 4150 2150 4650 +Connection ~ 2750 4450 +Wire Wire Line + 4000 4550 4000 5400 +Wire Wire Line + 4300 5250 4000 5250 +Connection ~ 4000 5250 +Wire Wire Line + 4600 5050 4600 4750 +Wire Wire Line + 4600 4450 4600 4250 +Wire Wire Line + 4600 3850 4600 3600 +Wire Wire Line + 3650 4050 4300 4050 +Wire Wire Line + 4000 4050 4000 4150 +Wire Wire Line + 3650 4050 3650 3600 +Connection ~ 4000 4050 +Wire Wire Line + 2750 3300 2750 3050 +Wire Wire Line + 4600 3050 4600 3300 +Wire Wire Line + 3650 3300 3650 3050 +Connection ~ 3650 3050 +Wire Wire Line + 2450 4850 2450 5000 +Wire Wire Line + 3050 4850 3050 5000 +Wire Wire Line + 4000 5700 4000 5800 +Wire Wire Line + 4000 5800 4750 5800 +Wire Wire Line + 4600 4900 5050 4900 +Connection ~ 4600 4900 +Connection ~ 4600 5800 +Connection ~ 4600 3050 +Wire Wire Line + 4600 5800 4600 5450 +$Comp +L PORT U1 +U 4 1 677060E6 +P 4750 2700 +F 0 "U1" H 4800 2800 30 0000 C CNN +F 1 "PORT" H 4750 2700 30 0000 C CNN +F 2 "" H 4750 2700 60 0000 C CNN +F 3 "" H 4750 2700 60 0000 C CNN + 4 4750 2700 + 0 1 1 0 +$EndComp +Wire Wire Line + 4750 2950 4750 3050 +Connection ~ 4750 3050 +Wire Wire Line + 4750 3050 2750 3050 +Connection ~ 4600 3750 +Wire Wire Line + 2750 3600 2750 4150 +Connection ~ 2750 4150 +Wire Wire Line + 3700 4350 2750 4350 +Wire Wire Line + 2750 4350 2750 4450 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub new file mode 100644 index 00000000..1a1d27ee --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL.sub @@ -0,0 +1,18 @@ +* Subcircuit NAND_GATE_FINAL +.subckt NAND_GATE_FINAL net-_q1-pad3_ net-_q2-pad3_ net-_d1-pad2_ net-_r1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\nand_gate_final\nand_gate_final.cir +.include D.lib +.include NPN.lib +q2 net-_q1-pad1_ net-_q1-pad2_ net-_q2-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +r1 net-_r1-pad1_ net-_q1-pad2_ 4k +r2 net-_r1-pad1_ net-_q3-pad1_ 1.6k +r4 net-_q4-pad1_ net-_r1-pad1_ 130 +q4 net-_q4-pad1_ net-_q3-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q1-pad1_ net-_q3-pad3_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q5 net-_d1-pad2_ net-_q3-pad3_ gnd Q2N2222 +r3 net-_q3-pad3_ gnd 1k +* Control Statements + +.ends NAND_GATE_FINAL
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml new file mode 100644 index 00000000..0eb364f5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NAND_GATE_FINAL_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/NPN.lib b/library/SubcircuitLibrary/SN74LS00/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib new file mode 100644 index 00000000..37b0e2e1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00-cache.lib @@ -0,0 +1,60 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir new file mode 100644 index 00000000..4b046591 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\SN74LS00\SN74LS00.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/12/25 21:31:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad14_ Nand_gate_final +X3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad14_ Nand_gate_final +X2 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ Net-_U1-Pad14_ Nand_gate_final +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U1-Pad14_ Nand_gate_final +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ ? Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out new file mode 100644 index 00000000..15fe255d --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir + +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch new file mode 100644 index 00000000..8371e33e --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sch @@ -0,0 +1,304 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Nand_gate_final X1 +U 1 1 67705EB8 +P 4400 3550 +F 0 "X1" H 4400 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 3450 60 0000 C CNN +F 2 "" H 4400 3550 60 0001 C CNN +F 3 "" H 4400 3550 60 0001 C CNN + 1 4400 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X3 +U 1 1 67705EE5 +P 6950 3550 +F 0 "X3" H 6950 3550 60 0000 C CNN +F 1 "Nand_gate_final" H 7000 3450 60 0000 C CNN +F 2 "" H 6950 3550 60 0001 C CNN +F 3 "" H 6950 3550 60 0001 C CNN + 1 6950 3550 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X2 +U 1 1 67705EFE +P 4400 5100 +F 0 "X2" H 4400 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 4450 5000 60 0000 C CNN +F 2 "" H 4400 5100 60 0001 C CNN +F 3 "" H 4400 5100 60 0001 C CNN + 1 4400 5100 + 1 0 0 -1 +$EndComp +$Comp +L Nand_gate_final X4 +U 1 1 67705F23 +P 7050 5100 +F 0 "X4" H 7050 5100 60 0000 C CNN +F 1 "Nand_gate_final" H 7100 5000 60 0000 C CNN +F 2 "" H 7050 5100 60 0001 C CNN +F 3 "" H 7050 5100 60 0001 C CNN + 1 7050 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2500 3050 6700 3050 +Connection ~ 4150 3050 +Wire Wire Line + 4150 4600 2900 4600 +Wire Wire Line + 2900 4600 2900 3050 +Connection ~ 2900 3050 +Wire Wire Line + 6800 4600 5550 4600 +Wire Wire Line + 5550 4600 5550 3050 +Connection ~ 5550 3050 +Wire Wire Line + 3700 4950 3200 4950 +Wire Wire Line + 3200 4950 3200 5450 +Wire Wire Line + 3700 5250 3700 5500 +Wire Wire Line + 5200 5100 5200 5500 +Wire Wire Line + 5200 5500 5250 5500 +Wire Wire Line + 7850 5100 7850 5650 +Wire Wire Line + 7850 5650 7900 5650 +Wire Wire Line + 6350 5250 6350 5600 +Wire Wire Line + 6350 4950 6100 4950 +Wire Wire Line + 6100 4950 6100 5600 +Wire Wire Line + 6250 3700 6250 4050 +Wire Wire Line + 6250 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 4050 +Wire Wire Line + 7750 3550 7750 4000 +Wire Wire Line + 5200 3550 5200 4000 +Wire Wire Line + 3700 3700 3700 4100 +Wire Wire Line + 3700 3400 3400 3400 +Wire Wire Line + 3400 3400 3400 4100 +$Comp +L PORT U1 +U 2 1 6770609D +P 3700 4350 +F 0 "U1" H 3750 4450 30 0000 C CNN +F 1 "PORT" H 3700 4350 30 0000 C CNN +F 2 "" H 3700 4350 60 0000 C CNN +F 3 "" H 3700 4350 60 0000 C CNN + 2 3700 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 677060F9 +P 5200 4250 +F 0 "U1" H 5250 4350 30 0000 C CNN +F 1 "PORT" H 5200 4250 30 0000 C CNN +F 2 "" H 5200 4250 60 0000 C CNN +F 3 "" H 5200 4250 60 0000 C CNN + 3 5200 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 6770612A +P 6250 4300 +F 0 "U1" H 6300 4400 30 0000 C CNN +F 1 "PORT" H 6250 4300 30 0000 C CNN +F 2 "" H 6250 4300 60 0000 C CNN +F 3 "" H 6250 4300 60 0000 C CNN + 5 6250 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 67706169 +P 7250 4550 +F 0 "U1" H 7300 4650 30 0000 C CNN +F 1 "PORT" H 7250 4550 30 0000 C CNN +F 2 "" H 7250 4550 60 0000 C CNN +F 3 "" H 7250 4550 60 0000 C CNN + 7 7250 4550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 677061B0 +P 3700 5750 +F 0 "U1" H 3750 5850 30 0000 C CNN +F 1 "PORT" H 3700 5750 30 0000 C CNN +F 2 "" H 3700 5750 60 0000 C CNN +F 3 "" H 3700 5750 60 0000 C CNN + 9 3700 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 11 1 677061E9 +P 7900 5900 +F 0 "U1" H 7950 6000 30 0000 C CNN +F 1 "PORT" H 7900 5900 30 0000 C CNN +F 2 "" H 7900 5900 60 0000 C CNN +F 3 "" H 7900 5900 60 0000 C CNN + 11 7900 5900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 677062AC +P 5250 5750 +F 0 "U1" H 5300 5850 30 0000 C CNN +F 1 "PORT" H 5250 5750 30 0000 C CNN +F 2 "" H 5250 5750 60 0000 C CNN +F 3 "" H 5250 5750 60 0000 C CNN + 8 5250 5750 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 10 1 677062E7 +P 3200 5700 +F 0 "U1" H 3250 5800 30 0000 C CNN +F 1 "PORT" H 3200 5700 30 0000 C CNN +F 2 "" H 3200 5700 60 0000 C CNN +F 3 "" H 3200 5700 60 0000 C CNN + 10 3200 5700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 12 1 67706324 +P 6350 5850 +F 0 "U1" H 6400 5950 30 0000 C CNN +F 1 "PORT" H 6350 5850 30 0000 C CNN +F 2 "" H 6350 5850 60 0000 C CNN +F 3 "" H 6350 5850 60 0000 C CNN + 12 6350 5850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 67706363 +P 7750 4250 +F 0 "U1" H 7800 4350 30 0000 C CNN +F 1 "PORT" H 7750 4250 30 0000 C CNN +F 2 "" H 7750 4250 60 0000 C CNN +F 3 "" H 7750 4250 60 0000 C CNN + 6 7750 4250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 677063A4 +P 6000 4300 +F 0 "U1" H 6050 4400 30 0000 C CNN +F 1 "PORT" H 6000 4300 30 0000 C CNN +F 2 "" H 6000 4300 60 0000 C CNN +F 3 "" H 6000 4300 60 0000 C CNN + 4 6000 4300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 677063EF +P 3400 4350 +F 0 "U1" H 3450 4450 30 0000 C CNN +F 1 "PORT" H 3400 4350 30 0000 C CNN +F 2 "" H 3400 4350 60 0000 C CNN +F 3 "" H 3400 4350 60 0000 C CNN + 1 3400 4350 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 14 1 6770A61C +P 2500 3300 +F 0 "U1" H 2550 3400 30 0000 C CNN +F 1 "PORT" H 2500 3300 30 0000 C CNN +F 2 "" H 2500 3300 60 0000 C CNN +F 3 "" H 2500 3300 60 0000 C CNN + 14 2500 3300 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 13 1 6770A667 +P 6100 5850 +F 0 "U1" H 6150 5950 30 0000 C CNN +F 1 "PORT" H 6100 5850 30 0000 C CNN +F 2 "" H 6100 5850 60 0000 C CNN +F 3 "" H 6100 5850 60 0000 C CNN + 13 6100 5850 + 0 -1 -1 0 +$EndComp +NoConn ~ 7250 4300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub new file mode 100644 index 00000000..2ec1904f --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00.sub @@ -0,0 +1,11 @@ +* Subcircuit SN74LS00 +.subckt SN74LS00 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ ? net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\sn74ls00\sn74ls00.cir +.include NAND_GATE_FINAL.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad14_ NAND_GATE_FINAL +x3 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad14_ NAND_GATE_FINAL +x2 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ net-_u1-pad14_ NAND_GATE_FINAL +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad11_ net-_u1-pad14_ NAND_GATE_FINAL +* Control Statements + +.ends SN74LS00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml new file mode 100644 index 00000000..a24d9a30 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/SN74LS00_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NAND_GATE_FINAL</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/analysis b/library/SubcircuitLibrary/SN74LS00/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm new file mode 100644 index 00000000..1980d0d1 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.dcm @@ -0,0 +1,7 @@ +EESchema-DOCLIB Version 2.0 +# +$CMP SCR +D Thyristor +$ENDCMP +# +#End Doc Library diff --git a/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib new file mode 100644 index 00000000..32e7ba06 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS00/nand_gate_pakka.lib @@ -0,0 +1,756 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X A<B(in) 1 600 -100 200 L 50 50 1 1 I +X A=B(in) 2 600 -200 200 L 50 50 1 1 I +X A>B(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A<B(out) 14 600 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# LM555N +# +DEF LM555N X 0 40 Y Y 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "LM555N" 0 100 60 H V C CNN +F2 "" -50 0 60 H V C CNN +F3 "" -50 0 60 H V C CNN +DRAW +S 350 -400 -350 400 0 1 0 N +X GND 1 0 -600 200 U 50 50 1 1 W +X TR 2 -550 250 200 R 50 50 1 1 I +X Q 3 550 250 200 L 50 50 1 1 O +X R 4 -550 -250 200 R 50 50 1 1 I I +X CV 5 -550 0 200 R 50 50 1 1 I +X THR 6 550 -250 200 L 50 50 1 1 I +X DIS 7 550 0 200 L 50 50 1 1 I +X VCC 8 0 600 200 D 50 50 1 1 W +ENDDRAW +ENDDEF +# +# LM_7812 +# +DEF LM_7812 X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "LM_7812" 0 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 200 350 -200 0 1 0 N +X IN 1 -550 0 200 R 50 50 1 1 I +X GND 2 0 -400 200 U 50 50 1 1 I +X OUT 3 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# Lm_7805 +# +DEF Lm_7805 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Lm_7805" 50 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -350 100 350 -200 0 1 0 N +X Vin 1 -550 0 200 R 50 50 1 1 P +X GND 2 0 -400 200 U 50 50 1 1 P +X Vout 3 550 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# Nand_gate_final +# +DEF Nand_gate_final X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Nand_gate_final" 50 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -500 300 600 -300 0 1 0 N +X A 1 -700 150 200 R 50 50 1 1 I +X B 2 -700 -150 200 R 50 50 1 1 I +X C 3 800 0 200 L 50 50 1 1 I +X VCC 4 -250 500 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# OTA_CA3080 +# +DEF OTA_CA3080 X 0 40 Y Y 1 F N +F0 "X" 200 300 60 H V C CNN +F1 "OTA_CA3080" 50 0 60 H V C CNN +F2 "" 50 0 60 H I C CNN +F3 "" 50 0 60 H I C CNN +DRAW +C 200 -100 50 0 1 0 N +C 250 -100 50 0 1 0 N +P 6 0 1 0 -350 350 -350 -450 650 0 -350 450 -350 300 -350 350 N +X A 1 300 350 200 D 50 50 1 1 I +X B 2 -550 -300 200 R 50 50 1 1 I +X C 3 -550 250 200 R 50 50 1 1 I +X D 4 0 -500 200 U 50 50 1 1 I +X E 5 550 250 200 D 50 50 1 1 I +X F 6 850 0 200 L 50 50 1 1 O +X G 7 0 500 200 D 50 50 1 1 I +X H 8 300 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# SCR +# +DEF SCR X 0 10 Y N 1 F N +F0 "X" 150 200 50 H V C CNN +F1 "SCR" 150 -350 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 2 0 0 0 -200 -150 200 -150 N +P 2 0 1 0 0 -150 -200 -400 N +P 3 0 1 0 -150 100 150 100 0 -150 F +X A 1 0 400 300 D 60 60 1 1 I +X K 2 0 -550 400 U 60 70 1 1 I +X G 3 -350 -400 150 R 60 60 1 1 I +ENDDRAW +ENDDEF +# +# UJT +# +DEF UJT X 0 40 Y Y 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "UJT" 50 -50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +C -50 -50 206 0 1 0 N +P 2 0 1 0 -100 100 -100 -200 N +P 3 0 1 0 -250 0 -200 0 -100 -100 N +P 3 0 1 0 -200 -50 -150 -50 -150 0 N +P 3 0 1 0 -100 -150 0 -150 0 -250 N +P 3 0 1 0 -100 50 0 50 0 150 N +X E 1 -450 0 200 R 50 50 1 1 I +X B1 2 0 -450 200 U 50 50 1 1 B +X B2 3 0 350 200 D 50 50 1 1 B +ENDDRAW +ENDDEF +# +# eSim_74LS04 +# +DEF eSim_74LS04 X 0 40 Y Y 1 F N +F0 "X" 0 100 60 H V C CNN +F1 "eSim_74LS04" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S 350 500 -350 -500 0 1 0 N +X ~ 1 -550 450 200 R 50 50 1 1 P +X ~ 2 -550 300 200 R 50 50 1 1 P I +X ~ 3 -550 150 200 R 50 50 1 1 P +X ~ 4 -550 0 200 R 50 50 1 1 P I +X ~ 5 -550 -150 200 R 50 50 1 1 P +X ~ 6 -550 -300 200 R 50 50 1 1 P I +X GND 7 -550 -450 200 R 50 50 1 1 P +X ~ 8 550 -450 200 L 50 50 1 1 P I +X ~ 9 550 -300 200 L 50 50 1 1 P +X ~ 10 550 -150 200 L 50 50 1 1 P I +X ~ 11 550 0 200 L 50 50 1 1 P +X ~ 12 550 150 200 L 50 50 1 1 P I +X ~ 13 550 300 200 L 50 50 1 1 P +X VCC 14 550 450 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_sub +# +DEF full_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "full_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -550 650 450 -600 0 1 0 N +X A 1 -750 400 200 R 50 50 1 1 I +X B 2 -750 200 200 R 50 50 1 1 I +X BIN 3 -750 -200 200 R 50 50 1 1 I +X DIFF 4 650 450 200 L 50 50 1 1 O +X BORROW 5 650 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_sub +# +DEF half_sub X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "half_sub" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 300 300 -300 0 1 0 N +X A 1 -500 200 200 R 50 50 1 1 I +X B 2 -500 -100 200 R 50 50 1 1 I +X D 3 500 150 200 L 50 50 1 1 O +X BORROW 4 500 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# lm3909 +# +DEF lm3909 X 0 40 Y Y 1 F N +F0 "X" 0 -150 60 H V C CNN +F1 "lm3909" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -1000 400 1050 -450 0 1 0 N +X ~ 1 -750 -650 200 U 50 50 1 1 I +X ~ 2 -200 -650 200 U 50 50 1 1 I +X ~ 3 350 -650 200 U 50 50 1 1 I +X ~ 4 850 -650 200 U 50 50 1 1 I +X ~ 5 850 600 200 D 50 50 1 1 I +X ~ 6 350 600 200 D 50 50 1 1 I +X ~ 7 -200 600 200 D 50 50 1 1 I +X ~ 8 -750 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +# nand_ttl +# +DEF nand_ttl X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "nand_ttl" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A -580 156 1081 -250 -777 0 1 0 N 400 -300 -350 -900 +A -361 -420 770 90 892 0 1 0 N 400 -300 -350 350 +C 500 -300 112 0 1 0 N +P 2 0 1 0 -350 -300 -350 -900 N +P 2 0 1 0 -350 350 -350 -300 N +X A 1 -550 150 200 R 50 50 1 1 I +X B 2 -550 -650 200 R 50 50 1 1 I +X C 3 800 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ca3080/D.lib b/library/SubcircuitLibrary/ca3080/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/ca3080/NPN.lib b/library/SubcircuitLibrary/ca3080/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/PNP.lib b/library/SubcircuitLibrary/ca3080/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/ca3080/analysis b/library/SubcircuitLibrary/ca3080/analysis new file mode 100644 index 00000000..85e6f838 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/analysis @@ -0,0 +1 @@ +.tran 2e-00 6e-00 1e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080-cache.lib b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib new file mode 100644 index 00000000..21197049 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir b/library/SubcircuitLibrary/ca3080/ca3080.cir new file mode 100644 index 00000000..4666a808 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir @@ -0,0 +1,28 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ca3080\ca3080.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 11/23/24 19:02:23 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q2 Net-_D2-Pad1_ Net-_D3-Pad2_ Net-_D3-Pad1_ eSim_PNP +Q1 Net-_D2-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q5 Net-_D4-Pad1_ Net-_Q5-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q6 Net-_Q11-Pad2_ Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_PNP +Q4 Net-_Q11-Pad2_ Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_PNP +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q3 Net-_Q1-Pad3_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q8 Net-_Q10-Pad1_ Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_PNP +Q7 Net-_D4-Pad1_ Net-_D5-Pad2_ Net-_D3-Pad1_ eSim_PNP +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q10 Net-_Q10-Pad1_ Net-_D4-Pad2_ Net-_D5-Pad2_ eSim_PNP +D5 Net-_D3-Pad1_ Net-_D5-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q9 Net-_Q11-Pad2_ Net-_D6-Pad1_ Net-_D1-Pad2_ eSim_NPN +Q11 Net-_Q10-Pad1_ Net-_Q11-Pad2_ Net-_D6-Pad1_ eSim_NPN +U1 ? Net-_Q1-Pad2_ Net-_Q5-Pad2_ Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q10-Pad1_ Net-_D3-Pad1_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.cir.out b/library/SubcircuitLibrary/ca3080/ca3080.cir.out new file mode 100644 index 00000000..8c0a7960 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.cir.out @@ -0,0 +1,32 @@ +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir + +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* u1 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? port +.tran 2e-00 6e-00 1e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/ca3080/ca3080.pro b/library/SubcircuitLibrary/ca3080/ca3080.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sch b/library/SubcircuitLibrary/ca3080/ca3080.sch new file mode 100644 index 00000000..4f206f03 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sch @@ -0,0 +1,445 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:ca3080-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q2 +U 1 1 6739CE3D +P 3000 2900 +F 0 "Q2" H 2900 2950 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3050 50 0000 R CNN +F 2 "" H 3200 3000 29 0000 C CNN +F 3 "" H 3000 2900 60 0000 C CNN + 1 3000 2900 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 6739CEC7 +P 2800 4200 +F 0 "Q1" H 2700 4250 50 0000 R CNN +F 1 "eSim_NPN" H 2750 4350 50 0000 R CNN +F 2 "" H 3000 4300 29 0000 C CNN +F 3 "" H 2800 4200 60 0000 C CNN + 1 2800 4200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 6739CEE0 +P 4300 4200 +F 0 "Q5" H 4200 4250 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4350 50 0000 R CNN +F 2 "" H 4500 4300 29 0000 C CNN +F 3 "" H 4300 4200 60 0000 C CNN + 1 4300 4200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 6739D026 +P 5000 3100 +F 0 "Q6" H 4900 3150 50 0000 R CNN +F 1 "eSim_PNP" H 4950 3250 50 0000 R CNN +F 2 "" H 5200 3200 29 0000 C CNN +F 3 "" H 5000 3100 60 0000 C CNN + 1 5000 3100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 6739D114 +P 4150 3400 +F 0 "Q4" H 4050 3450 50 0000 R CNN +F 1 "eSim_PNP" H 4100 3550 50 0000 R CNN +F 2 "" H 4350 3500 29 0000 C CNN +F 3 "" H 4150 3400 60 0000 C CNN + 1 4150 3400 + 1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6739D123 +P 3850 3100 +F 0 "D2" H 3850 3200 50 0000 C CNN +F 1 "eSim_Diode" H 3850 3000 50 0000 C CNN +F 2 "" H 3850 3100 60 0000 C CNN +F 3 "" H 3850 3100 60 0000 C CNN + 1 3850 3100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6739D928 +P 5100 2550 +F 0 "D3" H 5100 2650 50 0000 C CNN +F 1 "eSim_Diode" H 5100 2450 50 0000 C CNN +F 2 "" H 5100 2550 60 0000 C CNN +F 3 "" H 5100 2550 60 0000 C CNN + 1 5100 2550 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6739DE31 +P 2900 5150 +F 0 "D1" H 2900 5250 50 0000 C CNN +F 1 "eSim_Diode" H 2900 5050 50 0000 C CNN +F 2 "" H 2900 5150 60 0000 C CNN +F 3 "" H 2900 5150 60 0000 C CNN + 1 2900 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6739DE58 +P 3450 4950 +F 0 "Q3" H 3350 5000 50 0000 R CNN +F 1 "eSim_NPN" H 3400 5100 50 0000 R CNN +F 2 "" H 3650 5050 29 0000 C CNN +F 3 "" H 3450 4950 60 0000 C CNN + 1 3450 4950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 6739E7CF +P 6400 3950 +F 0 "Q8" H 6300 4000 50 0000 R CNN +F 1 "eSim_PNP" H 6350 4100 50 0000 R CNN +F 2 "" H 6600 4050 29 0000 C CNN +F 3 "" H 6400 3950 60 0000 C CNN + 1 6400 3950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 6739E976 +P 5700 3100 +F 0 "Q7" H 5600 3150 50 0000 R CNN +F 1 "eSim_PNP" H 5650 3250 50 0000 R CNN +F 2 "" H 5900 3200 29 0000 C CNN +F 3 "" H 5700 3100 60 0000 C CNN + 1 5700 3100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6739E9A5 +P 5950 3650 +F 0 "D4" H 5950 3750 50 0000 C CNN +F 1 "eSim_Diode" H 5950 3550 50 0000 C CNN +F 2 "" H 5950 3650 60 0000 C CNN +F 3 "" H 5950 3650 60 0000 C CNN + 1 5950 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2900 4400 4200 4400 +Wire Wire Line + 2900 4000 2900 3100 +Wire Wire Line + 4000 3100 4800 3100 +Wire Wire Line + 3950 3400 2900 3400 +Connection ~ 2900 3400 +Wire Wire Line + 3700 3100 3400 3100 +Wire Wire Line + 3400 3100 3400 3400 +Connection ~ 3400 3400 +Wire Wire Line + 4250 3200 4250 3100 +Connection ~ 4250 3100 +Wire Wire Line + 5100 3300 5100 4750 +Wire Wire Line + 5100 3600 4250 3600 +Wire Wire Line + 4500 4200 4500 4600 +Wire Wire Line + 4500 4600 2500 4600 +Wire Wire Line + 2600 4200 2500 4200 +Wire Wire Line + 3200 2900 5100 2900 +Wire Wire Line + 5100 2900 5100 2700 +Wire Wire Line + 2900 2700 2900 2300 +Wire Wire Line + 2900 2300 7950 2300 +Wire Wire Line + 5100 2300 5100 2400 +Wire Wire Line + 2900 5000 2900 4950 +Wire Wire Line + 2500 4950 3250 4950 +Wire Wire Line + 3550 4750 3550 4400 +Connection ~ 3550 4400 +Wire Wire Line + 2900 5300 2900 5550 +Wire Wire Line + 2900 5550 8000 5550 +Wire Wire Line + 3550 5150 3550 5550 +Connection ~ 3550 5550 +Wire Wire Line + 4200 4000 4200 3950 +Wire Wire Line + 4200 3950 6200 3950 +Wire Wire Line + 5600 3300 5600 3950 +Connection ~ 5600 3950 +Wire Wire Line + 5800 3650 5700 3650 +Wire Wire Line + 5700 3650 5700 3950 +Connection ~ 5700 3950 +Wire Wire Line + 6100 3650 7150 3650 +Wire Wire Line + 6500 3650 6500 3750 +Wire Wire Line + 5600 2300 5600 2900 +Connection ~ 5100 2300 +$Comp +L eSim_PNP Q10 +U 1 1 6739F10B +P 7350 3650 +F 0 "Q10" H 7250 3700 50 0000 R CNN +F 1 "eSim_PNP" H 7300 3800 50 0000 R CNN +F 2 "" H 7550 3750 29 0000 C CNN +F 3 "" H 7350 3650 60 0000 C CNN + 1 7350 3650 + 1 0 0 1 +$EndComp +Connection ~ 6500 3650 +$Comp +L eSim_Diode D5 +U 1 1 6739F185 +P 7450 2750 +F 0 "D5" H 7450 2850 50 0000 C CNN +F 1 "eSim_Diode" H 7450 2650 50 0000 C CNN +F 2 "" H 7450 2750 60 0000 C CNN +F 3 "" H 7450 2750 60 0000 C CNN + 1 7450 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 6739F3EA +P 7450 5150 +F 0 "D6" H 7450 5250 50 0000 C CNN +F 1 "eSim_Diode" H 7450 5050 50 0000 C CNN +F 2 "" H 7450 5150 60 0000 C CNN +F 3 "" H 7450 5150 60 0000 C CNN + 1 7450 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 6739F41F +P 6700 4950 +F 0 "Q9" H 6600 5000 50 0000 R CNN +F 1 "eSim_NPN" H 6650 5100 50 0000 R CNN +F 2 "" H 6900 5050 29 0000 C CNN +F 3 "" H 6700 4950 60 0000 C CNN + 1 6700 4950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6739F984 +P 7350 4650 +F 0 "Q11" H 7250 4700 50 0000 R CNN +F 1 "eSim_NPN" H 7300 4800 50 0000 R CNN +F 2 "" H 7550 4750 29 0000 C CNN +F 3 "" H 7350 4650 60 0000 C CNN + 1 7350 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7450 3850 7450 4450 +Wire Wire Line + 6500 4150 7450 4150 +Connection ~ 7450 4150 +Wire Wire Line + 7450 4850 7450 5000 +Wire Wire Line + 6900 4950 7450 4950 +Connection ~ 7450 4950 +Wire Wire Line + 7450 5300 7450 5550 +Connection ~ 7450 5550 +Wire Wire Line + 6600 5150 6600 5550 +Connection ~ 6600 5550 +Wire Wire Line + 7450 2300 7450 2600 +Connection ~ 5600 2300 +Wire Wire Line + 5900 3100 7450 3100 +Connection ~ 7450 3100 +Wire Wire Line + 5100 4750 6600 4750 +Connection ~ 5100 3600 +Wire Wire Line + 7150 4650 6600 4650 +Wire Wire Line + 6600 4650 6600 4750 +Wire Wire Line + 7450 4350 7950 4350 +Connection ~ 7450 4350 +Connection ~ 7450 2300 +Connection ~ 2900 4950 +$Comp +L PORT U1 +U 7 1 673A5D57 +P 8200 2300 +F 0 "U1" H 8250 2400 30 0000 C CNN +F 1 "PORT" H 8200 2300 30 0000 C CNN +F 2 "" H 8200 2300 60 0000 C CNN +F 3 "" H 8200 2300 60 0000 C CNN + 7 8200 2300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 673A5F78 +P 8200 4350 +F 0 "U1" H 8250 4450 30 0000 C CNN +F 1 "PORT" H 8200 4350 30 0000 C CNN +F 2 "" H 8200 4350 60 0000 C CNN +F 3 "" H 8200 4350 60 0000 C CNN + 6 8200 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 673A669D +P 2250 4200 +F 0 "U1" H 2300 4300 30 0000 C CNN +F 1 "PORT" H 2250 4200 30 0000 C CNN +F 2 "" H 2250 4200 60 0000 C CNN +F 3 "" H 2250 4200 60 0000 C CNN + 2 2250 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 673A66F6 +P 2250 4600 +F 0 "U1" H 2300 4700 30 0000 C CNN +F 1 "PORT" H 2250 4600 30 0000 C CNN +F 2 "" H 2250 4600 60 0000 C CNN +F 3 "" H 2250 4600 60 0000 C CNN + 3 2250 4600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 673A7187 +P 2150 1850 +F 0 "U1" H 2200 1950 30 0000 C CNN +F 1 "PORT" H 2150 1850 30 0000 C CNN +F 2 "" H 2150 1850 60 0000 C CNN +F 3 "" H 2150 1850 60 0000 C CNN + 1 2150 1850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 6000 7700 6000 +NoConn ~ 7700 6000 +Wire Wire Line + 2400 1850 2650 1850 +NoConn ~ 2650 1850 +Wire Wire Line + 7450 2900 7450 3450 +$Comp +L PORT U1 +U 5 1 673A9E14 +P 2250 4950 +F 0 "U1" H 2300 5050 30 0000 C CNN +F 1 "PORT" H 2250 4950 30 0000 C CNN +F 2 "" H 2250 4950 60 0000 C CNN +F 3 "" H 2250 4950 60 0000 C CNN + 5 2250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 673AA0F8 +P 8250 5550 +F 0 "U1" H 8300 5650 30 0000 C CNN +F 1 "PORT" H 8250 5550 30 0000 C CNN +F 2 "" H 8250 5550 60 0000 C CNN +F 3 "" H 8250 5550 60 0000 C CNN + 4 8250 5550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 673AA6CB +P 8150 6000 +F 0 "U1" H 8200 6100 30 0000 C CNN +F 1 "PORT" H 8150 6000 30 0000 C CNN +F 2 "" H 8150 6000 60 0000 C CNN +F 3 "" H 8150 6000 60 0000 C CNN + 8 8150 6000 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/ca3080/ca3080.sub b/library/SubcircuitLibrary/ca3080/ca3080.sub new file mode 100644 index 00000000..263cea77 --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080.sub @@ -0,0 +1,26 @@ +* Subcircuit ca3080 +.subckt ca3080 ? net-_q1-pad2_ net-_q5-pad2_ net-_d1-pad2_ net-_d1-pad1_ net-_q10-pad1_ net-_d3-pad1_ ? +* c:\fossee\esim\library\subcircuitlibrary\ca3080\ca3080.cir +.include NPN.lib +.include PNP.lib +.include D.lib +q2 net-_d2-pad1_ net-_d3-pad2_ net-_d3-pad1_ Q2N2907A +q1 net-_d2-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q5 net-_d4-pad1_ net-_q5-pad2_ net-_q1-pad3_ Q2N2222 +q6 net-_q11-pad2_ net-_d2-pad2_ net-_d3-pad2_ Q2N2907A +q4 net-_q11-pad2_ net-_d2-pad1_ net-_d2-pad2_ Q2N2907A +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q3 net-_q1-pad3_ net-_d1-pad1_ net-_d1-pad2_ Q2N2222 +q8 net-_q10-pad1_ net-_d4-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_d4-pad1_ net-_d5-pad2_ net-_d3-pad1_ Q2N2907A +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q10 net-_q10-pad1_ net-_d4-pad2_ net-_d5-pad2_ Q2N2907A +d5 net-_d3-pad1_ net-_d5-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d1-pad2_ 1N4148 +q9 net-_q11-pad2_ net-_d6-pad1_ net-_d1-pad2_ Q2N2222 +q11 net-_q10-pad1_ net-_q11-pad2_ net-_d6-pad1_ Q2N2222 +* Control Statements + +.ends ca3080
\ No newline at end of file diff --git a/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml new file mode 100644 index 00000000..6442215a --- /dev/null +++ b/library/SubcircuitLibrary/ca3080/ca3080_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q2><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q6><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q4><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q8><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q7><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib</field></q10><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">1</field1><field2 name="Step Time">2</field2><field3 name="Stop Time">6</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/D.lib b/library/SubcircuitLibrary/mc1489/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir b/library/SubcircuitLibrary/mc1489/MC1489_0.cir new file mode 100644 index 00000000..fc367dfd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0\MC1489_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 19:55:03 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 6.7K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out new file mode 100644 index 00000000..f87cb465 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.pro b/library/SubcircuitLibrary/mc1489/MC1489_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sch b/library/SubcircuitLibrary/mc1489/MC1489_0.sch new file mode 100644 index 00000000..9370a9cd --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "6.7K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0.sub b/library/SubcircuitLibrary/mc1489/MC1489_0.sub new file mode 100644 index 00000000..3b1419b5 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0.sub @@ -0,0 +1,18 @@ +* Subcircuit MC1489_0 +.subckt MC1489_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489_0\mc1489_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 6.7k +* Control Statements + +.ends MC1489_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/MC1489_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/NPN.lib b/library/SubcircuitLibrary/mc1489/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489/analysis b/library/SubcircuitLibrary/mc1489/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489-cache.lib b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib new file mode 100644 index 00000000..cfb8337e --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# MC1489_0 +# +DEF MC1489_0 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "MC1489_0" 0 -100 60 H V C CNN +F2 "" 0 -100 60 H I C CNN +F3 "" 0 -100 60 H I C CNN +DRAW +S -500 150 550 -300 0 1 0 N +X input 1 -700 -100 200 R 50 50 1 1 I +X response_ctrl 2 750 -200 200 L 50 50 1 1 I +X vcc 3 0 -500 200 U 50 50 1 1 O +X out 4 300 350 200 D 50 50 1 1 I +X gnd 5 -300 350 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir b/library/SubcircuitLibrary/mc1489/mc1489.cir new file mode 100644 index 00000000..06b9edbc --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489\mc1489.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 01/29/25 20:02:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ gnd Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad3_ gnd MC1489_0 +X3 Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad14_ Net-_U1-Pad8_ gnd MC1489_0 +X2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad14_ Net-_U1-Pad6_ gnd MC1489_0 +X4 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U1-Pad11_ gnd MC1489_0 + +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.cir.out b/library/SubcircuitLibrary/mc1489/mc1489.cir.out new file mode 100644 index 00000000..7e7b7cd0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.cir.out @@ -0,0 +1,17 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir + +.include MC1489_0.sub +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489/mc1489.pro b/library/SubcircuitLibrary/mc1489/mc1489.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sch b/library/SubcircuitLibrary/mc1489/mc1489.sch new file mode 100644 index 00000000..98f81be3 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sch @@ -0,0 +1,313 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:mc1489-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5550 4150 5550 4900 +Wire Wire Line + 7700 4200 7700 4850 +Wire Wire Line + 7700 4850 7750 4850 +Wire Wire Line + 5550 4500 7700 4500 +Connection ~ 7700 4500 +Connection ~ 5550 4500 +Wire Wire Line + 8050 5700 8050 5900 +Wire Wire Line + 8050 5900 8150 5900 +Wire Wire Line + 7400 3350 7400 3200 +Wire Wire Line + 5250 3300 5250 3050 +Wire Wire Line + 5850 5750 5850 5950 +Text GLabel 5850 5950 3 60 Input ~ 0 +gnd +Text GLabel 8150 5900 2 60 Input ~ 0 +gnd +Text GLabel 7400 3200 0 60 Input ~ 0 +gnd +Text GLabel 5250 3050 0 60 Input ~ 0 +gnd +Wire Wire Line + 4850 3750 4600 3750 +Wire Wire Line + 4800 5200 4550 5200 +Wire Wire Line + 5250 5750 5000 5750 +Wire Wire Line + 6250 5300 6250 5200 +Wire Wire Line + 7000 5150 7000 5050 +Wire Wire Line + 7450 5700 7300 5700 +Wire Wire Line + 8450 5250 8450 5050 +Wire Wire Line + 8450 3900 8450 4000 +Wire Wire Line + 7000 3800 7000 3950 +Wire Wire Line + 8000 3350 8150 3350 +Wire Wire Line + 5850 3300 5950 3300 +Wire Wire Line + 6300 3850 6300 3700 +$Comp +L PORT U1 +U 3 1 679A35F2 +P 6200 3300 +F 0 "U1" H 6250 3400 30 0000 C CNN +F 1 "PORT" H 6200 3300 30 0000 C CNN +F 2 "" H 6200 3300 60 0000 C CNN +F 3 "" H 6200 3300 60 0000 C CNN + 3 6200 3300 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 679A361D +P 4750 5750 +F 0 "U1" H 4800 5850 30 0000 C CNN +F 1 "PORT" H 4750 5750 30 0000 C CNN +F 2 "" H 4750 5750 60 0000 C CNN +F 3 "" H 4750 5750 60 0000 C CNN + 6 4750 5750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A363E +P 6000 5200 +F 0 "U1" H 6050 5300 30 0000 C CNN +F 1 "PORT" H 6000 5200 30 0000 C CNN +F 2 "" H 6000 5200 60 0000 C CNN +F 3 "" H 6000 5200 60 0000 C CNN + 4 6000 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A3661 +P 4300 5200 +F 0 "U1" H 4350 5300 30 0000 C CNN +F 1 "PORT" H 4300 5200 30 0000 C CNN +F 2 "" H 4300 5200 60 0000 C CNN +F 3 "" H 4300 5200 60 0000 C CNN + 5 4300 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3686 +P 4350 3750 +F 0 "U1" H 4400 3850 30 0000 C CNN +F 1 "PORT" H 4350 3750 30 0000 C CNN +F 2 "" H 4350 3750 60 0000 C CNN +F 3 "" H 4350 3750 60 0000 C CNN + 1 4350 3750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A36AD +P 6050 3700 +F 0 "U1" H 6100 3800 30 0000 C CNN +F 1 "PORT" H 6050 3700 30 0000 C CNN +F 2 "" H 6050 3700 60 0000 C CNN +F 3 "" H 6050 3700 60 0000 C CNN + 2 6050 3700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679A36D6 +P 4900 3250 +F 0 "U1" H 4950 3350 30 0000 C CNN +F 1 "PORT" H 4900 3250 30 0000 C CNN +F 2 "" H 4900 3250 60 0000 C CNN +F 3 "" H 4900 3250 60 0000 C CNN + 7 4900 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 679A3701 +P 6750 3950 +F 0 "U1" H 6800 4050 30 0000 C CNN +F 1 "PORT" H 6750 3950 30 0000 C CNN +F 2 "" H 6750 3950 60 0000 C CNN +F 3 "" H 6750 3950 60 0000 C CNN + 10 6750 3950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 679A372E +P 6750 5050 +F 0 "U1" H 6800 5150 30 0000 C CNN +F 1 "PORT" H 6750 5050 30 0000 C CNN +F 2 "" H 6750 5050 60 0000 C CNN +F 3 "" H 6750 5050 60 0000 C CNN + 12 6750 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 679A375D +P 7050 5700 +F 0 "U1" H 7100 5800 30 0000 C CNN +F 1 "PORT" H 7050 5700 30 0000 C CNN +F 2 "" H 7050 5700 60 0000 C CNN +F 3 "" H 7050 5700 60 0000 C CNN + 11 7050 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 679A3796 +P 8200 5050 +F 0 "U1" H 8250 5150 30 0000 C CNN +F 1 "PORT" H 8200 5050 30 0000 C CNN +F 2 "" H 8200 5050 60 0000 C CNN +F 3 "" H 8200 5050 60 0000 C CNN + 13 8200 5050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 679A37C9 +P 8200 4000 +F 0 "U1" H 8250 4100 30 0000 C CNN +F 1 "PORT" H 8200 4000 30 0000 C CNN +F 2 "" H 8200 4000 60 0000 C CNN +F 3 "" H 8200 4000 60 0000 C CNN + 9 8200 4000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679A37FE +P 8400 3350 +F 0 "U1" H 8450 3450 30 0000 C CNN +F 1 "PORT" H 8400 3350 30 0000 C CNN +F 2 "" H 8400 3350 60 0000 C CNN +F 3 "" H 8400 3350 60 0000 C CNN + 8 8400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 679A3835 +P 6650 4900 +F 0 "U1" H 6700 5000 30 0000 C CNN +F 1 "PORT" H 6650 4900 30 0000 C CNN +F 2 "" H 6650 4900 60 0000 C CNN +F 3 "" H 6650 4900 60 0000 C CNN + 14 6650 4900 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5150 3250 5250 3250 +Connection ~ 5250 3250 +Wire Wire Line + 6650 4650 6650 4500 +Connection ~ 6650 4500 +$Comp +L MC1489_0 X1 +U 1 1 679A3C30 +P 5550 3650 +F 0 "X1" H 5550 3650 60 0000 C CNN +F 1 "MC1489_0" H 5550 3550 60 0000 C CNN +F 2 "" H 5550 3550 60 0001 C CNN +F 3 "" H 5550 3550 60 0001 C CNN + 1 5550 3650 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X3 +U 1 1 679A3C93 +P 7700 3700 +F 0 "X3" H 7700 3700 60 0000 C CNN +F 1 "MC1489_0" H 7700 3600 60 0000 C CNN +F 2 "" H 7700 3600 60 0001 C CNN +F 3 "" H 7700 3600 60 0001 C CNN + 1 7700 3700 + 1 0 0 -1 +$EndComp +$Comp +L MC1489_0 X2 +U 1 1 679A3FCC +P 5550 5400 +F 0 "X2" H 5550 5400 60 0000 C CNN +F 1 "MC1489_0" H 5550 5300 60 0000 C CNN +F 2 "" H 5550 5300 60 0001 C CNN +F 3 "" H 5550 5300 60 0001 C CNN + 1 5550 5400 + -1 0 0 1 +$EndComp +$Comp +L MC1489_0 X4 +U 1 1 679A4021 +P 7750 5350 +F 0 "X4" H 7750 5350 60 0000 C CNN +F 1 "MC1489_0" H 7750 5250 60 0000 C CNN +F 2 "" H 7750 5250 60 0001 C CNN +F 3 "" H 7750 5250 60 0001 C CNN + 1 7750 5350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489/mc1489.sub b/library/SubcircuitLibrary/mc1489/mc1489.sub new file mode 100644 index 00000000..49e98c90 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489.sub @@ -0,0 +1,11 @@ +* Subcircuit mc1489 +.subckt mc1489 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ gnd net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489\mc1489.cir +.include MC1489_0.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad14_ net-_u1-pad3_ gnd MC1489_0 +x3 net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad14_ net-_u1-pad8_ gnd MC1489_0 +x2 net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad14_ net-_u1-pad6_ gnd MC1489_0 +x4 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u1-pad11_ gnd MC1489_0 +* Control Statements + +.ends mc1489
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml new file mode 100644 index 00000000..e3de6ceb --- /dev/null +++ b/library/SubcircuitLibrary/mc1489/mc1489_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x3><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x2><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\MC1489_0</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/D.lib b/library/SubcircuitLibrary/mc1489A_0/D.lib new file mode 100644 index 00000000..f53bf3e0 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/mc1489A_0/NPN.lib b/library/SubcircuitLibrary/mc1489A_0/NPN.lib new file mode 100644 index 00000000..be5f3073 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/mc1489A_0/analysis b/library/SubcircuitLibrary/mc1489A_0/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib new file mode 100644 index 00000000..7e9c6731 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0-cache.lib @@ -0,0 +1,107 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir new file mode 100644 index 00000000..7b3d76c7 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir @@ -0,0 +1,21 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\mc1489A_0\mc1489A_0.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/09/25 01:16:43 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_D1-Pad2_ Net-_D1-Pad1_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q1-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q3 Net-_Q3-Pad1_ Net-_Q2-Pad1_ Net-_D1-Pad1_ eSim_NPN +R2 Net-_D1-Pad2_ Net-_D1-Pad1_ 10K +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +R5 Net-_R4-Pad1_ Net-_Q2-Pad1_ 5K +R4 Net-_R4-Pad1_ Net-_Q1-Pad1_ 9K +R6 Net-_R4-Pad1_ Net-_Q3-Pad1_ 1.7K +R1 Net-_R1-Pad1_ Net-_D1-Pad2_ 3.8K +R3 Net-_D1-Pad2_ Net-_Q1-Pad1_ 1.6K +U1 Net-_R1-Pad1_ Net-_D1-Pad2_ Net-_R4-Pad1_ Net-_Q3-Pad1_ Net-_D1-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out new file mode 100644 index 00000000..6fa09c26 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.cir.out @@ -0,0 +1,24 @@ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir + +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* u1 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch new file mode 100644 index 00000000..d247d45d --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sch @@ -0,0 +1,274 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 679A2F36 +P 5550 4050 +F 0 "Q1" H 5450 4100 50 0000 R CNN +F 1 "eSim_NPN" H 5500 4200 50 0000 R CNN +F 2 "" H 5750 4150 29 0000 C CNN +F 3 "" H 5550 4050 60 0000 C CNN + 1 5550 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 679A2F55 +P 6350 3850 +F 0 "Q2" H 6250 3900 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4000 50 0000 R CNN +F 2 "" H 6550 3950 29 0000 C CNN +F 3 "" H 6350 3850 60 0000 C CNN + 1 6350 3850 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 679A2F6E +P 7300 3650 +F 0 "Q3" H 7200 3700 50 0000 R CNN +F 1 "eSim_NPN" H 7250 3800 50 0000 R CNN +F 2 "" H 7500 3750 29 0000 C CNN +F 3 "" H 7300 3650 60 0000 C CNN + 1 7300 3650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5350 3850 6150 3850 +Wire Wire Line + 6450 3650 7100 3650 +$Comp +L resistor R2 +U 1 1 679A2F98 +P 4950 4300 +F 0 "R2" H 5000 4430 50 0000 C CNN +F 1 "10K" H 5000 4250 50 0000 C CNN +F 2 "" H 5000 4280 30 0000 C CNN +F 3 "" V 5000 4350 30 0000 C CNN + 1 4950 4300 + 0 1 1 0 +$EndComp +Wire Wire Line + 5000 3850 5000 4200 +Wire Wire Line + 3900 4050 5350 4050 +Wire Wire Line + 5000 4500 5000 4600 +Wire Wire Line + 4500 4600 8100 4600 +Wire Wire Line + 5650 4600 5650 4250 +Wire Wire Line + 6450 4600 6450 4050 +Connection ~ 5650 4600 +Wire Wire Line + 7400 4600 7400 3850 +Connection ~ 6450 4600 +$Comp +L eSim_Diode D1 +U 1 1 679A2FEE +P 4500 4350 +F 0 "D1" H 4500 4450 50 0000 C CNN +F 1 "eSim_Diode" H 4500 4250 50 0000 C CNN +F 2 "" H 4500 4350 60 0000 C CNN +F 3 "" H 4500 4350 60 0000 C CNN + 1 4500 4350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 4500 4500 4500 4600 +Connection ~ 5000 4600 +Wire Wire Line + 4500 4200 4500 4050 +Connection ~ 5000 4050 +$Comp +L resistor R5 +U 1 1 679A303B +P 6400 3150 +F 0 "R5" H 6450 3280 50 0000 C CNN +F 1 "5K" H 6450 3100 50 0000 C CNN +F 2 "" H 6450 3130 30 0000 C CNN +F 3 "" V 6450 3200 30 0000 C CNN + 1 6400 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 679A3060 +P 5600 3200 +F 0 "R4" H 5650 3330 50 0000 C CNN +F 1 "9K" H 5650 3150 50 0000 C CNN +F 2 "" H 5650 3180 30 0000 C CNN +F 3 "" V 5650 3250 30 0000 C CNN + 1 5600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 679A3095 +P 7350 3150 +F 0 "R6" H 7400 3280 50 0000 C CNN +F 1 "1.7K" H 7400 3100 50 0000 C CNN +F 2 "" H 7400 3130 30 0000 C CNN +F 3 "" V 7400 3200 30 0000 C CNN + 1 7350 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 5650 3400 5650 3850 +Wire Wire Line + 6450 3350 6450 3650 +Wire Wire Line + 7400 3350 7400 3450 +Wire Wire Line + 5650 3100 5650 2900 +Wire Wire Line + 5650 2900 7950 2900 +Wire Wire Line + 7400 2900 7400 3050 +Wire Wire Line + 6450 3050 6450 2900 +Connection ~ 6450 2900 +Connection ~ 7400 2900 +Wire Wire Line + 7400 3400 8000 3400 +Connection ~ 7400 3400 +Connection ~ 7400 4600 +Connection ~ 4500 4050 +$Comp +L resistor R1 +U 1 1 679A31DB +P 3700 4100 +F 0 "R1" H 3750 4230 50 0000 C CNN +F 1 "3.8K" H 3750 4050 50 0000 C CNN +F 2 "" H 3750 4080 30 0000 C CNN +F 3 "" V 3750 4150 30 0000 C CNN + 1 3700 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3600 4050 3400 4050 +Connection ~ 5650 3850 +$Comp +L resistor R3 +U 1 1 679A3264 +P 5150 3900 +F 0 "R3" H 5200 4030 50 0000 C CNN +F 1 "1.6K" H 5200 3850 50 0000 C CNN +F 2 "" H 5200 3880 30 0000 C CNN +F 3 "" V 5200 3950 30 0000 C CNN + 1 5150 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 3850 5050 3850 +Connection ~ 5000 3850 +$Comp +L PORT U1 +U 3 1 679A336F +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 3 8200 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 679A33BE +P 8250 3400 +F 0 "U1" H 8300 3500 30 0000 C CNN +F 1 "PORT" H 8250 3400 30 0000 C CNN +F 2 "" H 8250 3400 60 0000 C CNN +F 3 "" H 8250 3400 60 0000 C CNN + 4 8250 3400 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679A33F1 +P 8350 4600 +F 0 "U1" H 8400 4700 30 0000 C CNN +F 1 "PORT" H 8350 4600 30 0000 C CNN +F 2 "" H 8350 4600 60 0000 C CNN +F 3 "" H 8350 4600 60 0000 C CNN + 5 8350 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679A3424 +P 3150 3850 +F 0 "U1" H 3200 3950 30 0000 C CNN +F 1 "PORT" H 3150 3850 30 0000 C CNN +F 2 "" H 3150 3850 60 0000 C CNN +F 3 "" H 3150 3850 60 0000 C CNN + 2 3150 3850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679A3455 +P 3150 4050 +F 0 "U1" H 3200 4150 30 0000 C CNN +F 1 "PORT" H 3150 4050 30 0000 C CNN +F 2 "" H 3150 4050 60 0000 C CNN +F 3 "" H 3150 4050 60 0000 C CNN + 1 3150 4050 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub new file mode 100644 index 00000000..e9ebfc80 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0.sub @@ -0,0 +1,18 @@ +* Subcircuit mc1489A_0 +.subckt mc1489A_0 net-_r1-pad1_ net-_d1-pad2_ net-_r4-pad1_ net-_q3-pad1_ net-_d1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\mc1489a_0\mc1489a_0.cir +.include NPN.lib +.include D.lib +q1 net-_q1-pad1_ net-_d1-pad2_ net-_d1-pad1_ Q2N2222 +q2 net-_q2-pad1_ net-_q1-pad1_ net-_d1-pad1_ Q2N2222 +q3 net-_q3-pad1_ net-_q2-pad1_ net-_d1-pad1_ Q2N2222 +r2 net-_d1-pad2_ net-_d1-pad1_ 10k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +r5 net-_r4-pad1_ net-_q2-pad1_ 5k +r4 net-_r4-pad1_ net-_q1-pad1_ 9k +r6 net-_r4-pad1_ net-_q3-pad1_ 1.7k +r1 net-_r1-pad1_ net-_d1-pad2_ 3.8k +r3 net-_d1-pad2_ net-_q1-pad1_ 1.6k +* Control Statements + +.ends mc1489A_0
\ No newline at end of file diff --git a/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml new file mode 100644 index 00000000..09ac9336 --- /dev/null +++ b/library/SubcircuitLibrary/mc1489A_0/mc1489A_0_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/NPN.lib b/library/SubcircuitLibrary/tda7050/NPN.lib new file mode 100644 index 00000000..6509fe7a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p ++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/PNP.lib b/library/SubcircuitLibrary/tda7050/PNP.lib new file mode 100644 index 00000000..7edda0ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/tda7050/analysis b/library/SubcircuitLibrary/tda7050/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741-cache.lib b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib new file mode 100644 index 00000000..04e3fecd --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-cache.lib @@ -0,0 +1,119 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib new file mode 100644 index 00000000..1ac4cbd4 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741-rescue.lib @@ -0,0 +1,42 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# eSim_NPN-RESCUE-lm_741 +# +DEF eSim_NPN-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +# eSim_PNP-RESCUE-lm_741 +# +DEF eSim_PNP-RESCUE-lm_741 Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP-RESCUE-lm_741" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 C +X B 2 -200 0 225 R 50 50 1 1 I +X E 3 100 -200 100 U 50 50 1 1 E +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir b/library/SubcircuitLibrary/tda7050/lm_741.cir new file mode 100644 index 00000000..4a5917ea --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir @@ -0,0 +1,43 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN +Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP +Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN +Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k +R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k +R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN +R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k +R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k +R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN +Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k +R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50 +Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN +Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN +R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25 +R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50 +Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP +U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT + +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.cir.out b/library/SubcircuitLibrary/tda7050/lm_741.cir.out new file mode 100644 index 00000000..a00bd86a --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.cir.out @@ -0,0 +1,46 @@ +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir + +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/lm_741.pro b/library/SubcircuitLibrary/tda7050/lm_741.pro new file mode 100644 index 00000000..e6fc25cb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.pro @@ -0,0 +1,45 @@ +update=11/23/24 18:57:50 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=lm_741-rescue +LibName2=power +LibName3=eSim_Analog +LibName4=eSim_Devices +LibName5=eSim_Digital +LibName6=eSim_Hybrid +LibName7=eSim_Miscellaneous +LibName8=eSim_Plot +LibName9=eSim_Power +LibName10=eSim_User +LibName11=eSim_Sources +LibName12=eSim_Subckt diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sch b/library/SubcircuitLibrary/tda7050/lm_741.sch new file mode 100644 index 00000000..b017fd2b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sch @@ -0,0 +1,697 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:lm_741-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 5CE90A7B +P 2650 2700 +F 0 "Q1" H 2550 2750 50 0000 R CNN +F 1 "eSim_NPN" H 2600 2850 50 0000 R CNN +F 2 "" H 2850 2800 29 0000 C CNN +F 3 "" H 2650 2700 60 0000 C CNN + 1 2650 2700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 5CE90A7C +P 4300 2700 +F 0 "Q2" H 4200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 4250 2850 50 0000 R CNN +F 2 "" H 4500 2800 29 0000 C CNN +F 3 "" H 4300 2700 60 0000 C CNN + 1 4300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 5CE90A7D +P 3000 3200 +F 0 "Q6" H 2900 3250 50 0000 R CNN +F 1 "eSim_PNP" H 2950 3350 50 0000 R CNN +F 2 "" H 3200 3300 29 0000 C CNN +F 3 "" H 3000 3200 60 0000 C CNN + 1 3000 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 5CE90A7E +P 3950 3200 +F 0 "Q5" H 3850 3250 50 0000 R CNN +F 1 "eSim_PNP" H 3900 3350 50 0000 R CNN +F 2 "" H 4150 3300 29 0000 C CNN +F 3 "" H 3950 3200 60 0000 C CNN + 1 3950 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 5CE90A7F +P 3300 4000 +F 0 "Q3" H 3200 4050 50 0000 R CNN +F 1 "eSim_NPN" H 3250 4150 50 0000 R CNN +F 2 "" H 3500 4100 29 0000 C CNN +F 3 "" H 3300 4000 60 0000 C CNN + 1 3300 4000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 5CE90A80 +P 3850 2000 +F 0 "Q4" H 3750 2050 50 0000 R CNN +F 1 "eSim_PNP" H 3800 2150 50 0000 R CNN +F 2 "" H 4050 2100 29 0000 C CNN +F 3 "" H 3850 2000 60 0000 C CNN + 1 3850 2000 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 5CE90A81 +P 5200 2000 +F 0 "Q9" H 5100 2050 50 0000 R CNN +F 1 "eSim_PNP" H 5150 2150 50 0000 R CNN +F 2 "" H 5400 2100 29 0000 C CNN +F 3 "" H 5200 2000 60 0000 C CNN + 1 5200 2000 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 5CE90A82 +P 3950 4600 +F 0 "Q8" H 3850 4650 50 0000 R CNN +F 1 "eSim_NPN" H 3900 4750 50 0000 R CNN +F 2 "" H 4150 4700 29 0000 C CNN +F 3 "" H 3950 4600 60 0000 C CNN + 1 3950 4600 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 5CE90A83 +P 3000 4600 +F 0 "Q7" H 2900 4650 50 0000 R CNN +F 1 "eSim_NPN" H 2950 4750 50 0000 R CNN +F 2 "" H 3200 4700 29 0000 C CNN +F 3 "" H 3000 4600 60 0000 C CNN + 1 3000 4600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R1 +U 1 1 5CE90A84 +P 2850 5200 +F 0 "R1" H 2900 5330 50 0000 C CNN +F 1 "1k" H 2900 5250 50 0000 C CNN +F 2 "" H 2900 5180 30 0000 C CNN +F 3 "" V 2900 5250 30 0000 C CNN + 1 2850 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R2 +U 1 1 5CE90A85 +P 3550 5200 +F 0 "R2" H 3600 5330 50 0000 C CNN +F 1 "50k" H 3600 5250 50 0000 C CNN +F 2 "" H 3600 5180 30 0000 C CNN +F 3 "" V 3600 5250 30 0000 C CNN + 1 3550 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R3 +U 1 1 5CE90A86 +P 4000 5200 +F 0 "R3" H 4050 5330 50 0000 C CNN +F 1 "1k" H 4050 5250 50 0000 C CNN +F 2 "" H 4050 5180 30 0000 C CNN +F 3 "" V 4050 5250 30 0000 C CNN + 1 4000 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 5CE90A87 +P 6300 4700 +F 0 "Q12" H 6200 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6250 4850 50 0000 R CNN +F 2 "" H 6500 4800 29 0000 C CNN +F 3 "" H 6300 4700 60 0000 C CNN + 1 6300 4700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 5CE90A88 +P 5400 4700 +F 0 "Q13" H 5300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 5350 4850 50 0000 R CNN +F 2 "" H 5600 4800 29 0000 C CNN +F 3 "" H 5400 4700 60 0000 C CNN + 1 5400 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R4 +U 1 1 5CE90A89 +P 5250 5200 +F 0 "R4" H 5300 5330 50 0000 C CNN +F 1 "5k" H 5300 5250 50 0000 C CNN +F 2 "" H 5300 5180 30 0000 C CNN +F 3 "" V 5300 5250 30 0000 C CNN + 1 5250 5200 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R11 +U 1 1 5CE90A8A +P 6350 2750 +F 0 "R11" H 6400 2880 50 0000 C CNN +F 1 "39k" H 6400 2800 50 0000 C CNN +F 2 "" H 6400 2730 30 0000 C CNN +F 3 "" V 6400 2800 30 0000 C CNN + 1 6350 2750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q10 +U 1 1 5CE90A8B +P 6500 1950 +F 0 "Q10" H 6400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 6450 2100 50 0000 R CNN +F 2 "" H 6700 2050 29 0000 C CNN +F 3 "" H 6500 1950 60 0000 C CNN + 1 6500 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 5CE90A8C +P 7500 1950 +F 0 "Q11" H 7400 2000 50 0000 R CNN +F 1 "eSim_PNP" H 7450 2100 50 0000 R CNN +F 2 "" H 7700 2050 29 0000 C CNN +F 3 "" H 7500 1950 60 0000 C CNN + 1 7500 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 5CE90A8D +P 7500 3050 +F 0 "Q14" H 7400 3100 50 0000 R CNN +F 1 "eSim_NPN" H 7450 3200 50 0000 R CNN +F 2 "" H 7700 3150 29 0000 C CNN +F 3 "" H 7500 3050 60 0000 C CNN + 1 7500 3050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R8 +U 1 1 5CE90A8E +P 7300 2600 +F 0 "R8" H 7350 2730 50 0000 C CNN +F 1 "4.5k" H 7350 2650 50 0000 C CNN +F 2 "" H 7350 2580 30 0000 C CNN +F 3 "" V 7350 2650 30 0000 C CNN + 1 7300 2600 + -1 0 0 1 +$EndComp +$Comp +L eSim_R R7 +U 1 1 5CE90A8F +P 7300 3400 +F 0 "R7" H 7350 3530 50 0000 C CNN +F 1 "7.5k" H 7350 3450 50 0000 C CNN +F 2 "" H 7350 3380 30 0000 C CNN +F 3 "" V 7350 3450 30 0000 C CNN + 1 7300 3400 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5CE90A90 +P 6600 3200 +F 0 "C1" H 6625 3300 50 0000 L CNN +F 1 "30p" H 6625 3100 50 0000 L CNN +F 2 "" H 6638 3050 30 0000 C CNN +F 3 "" H 6600 3200 60 0000 C CNN + 1 6600 3200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 5CE90A91 +P 7050 3950 +F 0 "Q16" H 6950 4000 50 0000 R CNN +F 1 "eSim_NPN" H 7000 4100 50 0000 R CNN +F 2 "" H 7250 4050 29 0000 C CNN +F 3 "" H 7050 3950 60 0000 C CNN + 1 7050 3950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 5CE90A92 +P 7500 4300 +F 0 "Q15" H 7400 4350 50 0000 R CNN +F 1 "eSim_NPN" H 7450 4450 50 0000 R CNN +F 2 "" H 7700 4400 29 0000 C CNN +F 3 "" H 7500 4300 60 0000 C CNN + 1 7500 4300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_R R5 +U 1 1 5CE90A93 +P 7100 5050 +F 0 "R5" H 7150 5180 50 0000 C CNN +F 1 "50k" H 7150 5100 50 0000 C CNN +F 2 "" H 7150 5030 30 0000 C CNN +F 3 "" V 7150 5100 30 0000 C CNN + 1 7100 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R6 +U 1 1 5CE90A94 +P 7550 5050 +F 0 "R6" H 7600 5180 50 0000 C CNN +F 1 "50" H 7600 5100 50 0000 C CNN +F 2 "" H 7600 5030 30 0000 C CNN +F 3 "" V 7600 5100 30 0000 C CNN + 1 7550 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 5CE90A95 +P 6800 4700 +F 0 "Q17" H 6700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 6750 4850 50 0000 R CNN +F 2 "" H 7000 4800 29 0000 C CNN +F 3 "" H 6800 4700 60 0000 C CNN + 1 6800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 5CE90A96 +P 8800 2300 +F 0 "Q18" H 8700 2350 50 0000 R CNN +F 1 "eSim_NPN" H 8750 2450 50 0000 R CNN +F 2 "" H 9000 2400 29 0000 C CNN +F 3 "" H 8800 2300 60 0000 C CNN + 1 8800 2300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 5CE90A97 +P 8400 2750 +F 0 "Q20" H 8300 2800 50 0000 R CNN +F 1 "eSim_NPN" H 8350 2900 50 0000 R CNN +F 2 "" H 8600 2850 29 0000 C CNN +F 3 "" H 8400 2750 60 0000 C CNN + 1 8400 2750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_R R9 +U 1 1 5CE90A98 +P 8850 3000 +F 0 "R9" H 8900 3130 50 0000 C CNN +F 1 "25" H 8900 3050 50 0000 C CNN +F 2 "" H 8900 2980 30 0000 C CNN +F 3 "" V 8900 3050 30 0000 C CNN + 1 8850 3000 + 0 1 1 0 +$EndComp +$Comp +L eSim_R R10 +U 1 1 5CE90A99 +P 8850 3750 +F 0 "R10" H 8900 3880 50 0000 C CNN +F 1 "50" H 8900 3800 50 0000 C CNN +F 2 "" H 8900 3730 30 0000 C CNN +F 3 "" V 8900 3800 30 0000 C CNN + 1 8850 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q19 +U 1 1 5CE90A9A +P 8800 4600 +F 0 "Q19" H 8700 4650 50 0000 R CNN +F 1 "eSim_PNP" H 8750 4750 50 0000 R CNN +F 2 "" H 9000 4700 29 0000 C CNN +F 3 "" H 8800 4600 60 0000 C CNN + 1 8800 4600 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 5CE90A9B +P 1900 1200 +F 0 "U1" H 1950 1300 30 0000 C CNN +F 1 "PORT" H 1900 1200 30 0000 C CNN +F 2 "" H 1900 1200 60 0000 C CNN +F 3 "" H 1900 1200 60 0000 C CNN + 3 1900 1200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5CE90A9C +P 4500 1050 +F 0 "U1" H 4550 1150 30 0000 C CNN +F 1 "PORT" H 4500 1050 30 0000 C CNN +F 2 "" H 4500 1050 60 0000 C CNN +F 3 "" H 4500 1050 60 0000 C CNN + 2 4500 1050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 5CE90A9D +P 9750 1650 +F 0 "U1" H 9800 1750 30 0000 C CNN +F 1 "PORT" H 9750 1650 30 0000 C CNN +F 2 "" H 9750 1650 60 0000 C CNN +F 3 "" H 9750 1650 60 0000 C CNN + 7 9750 1650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 5CE90A9E +P 9750 3500 +F 0 "U1" H 9800 3600 30 0000 C CNN +F 1 "PORT" H 9750 3500 30 0000 C CNN +F 2 "" H 9750 3500 60 0000 C CNN +F 3 "" H 9750 3500 60 0000 C CNN + 6 9750 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 5CE90A9F +P 9700 5550 +F 0 "U1" H 9750 5650 30 0000 C CNN +F 1 "PORT" H 9700 5550 30 0000 C CNN +F 2 "" H 9700 5550 60 0000 C CNN +F 3 "" H 9700 5550 60 0000 C CNN + 4 9700 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 3200 3750 3200 +Wire Wire Line + 2750 2900 2750 2950 +Wire Wire Line + 2750 2950 2900 2950 +Wire Wire Line + 2900 2950 2900 3000 +Wire Wire Line + 4200 2900 4200 2950 +Wire Wire Line + 4200 2950 4050 2950 +Wire Wire Line + 4050 2950 4050 3000 +Wire Wire Line + 2900 3400 2900 4400 +Wire Wire Line + 2900 4000 3100 4000 +Wire Wire Line + 4200 2000 4200 2500 +Wire Wire Line + 4200 2350 2750 2350 +Wire Wire Line + 2750 2350 2750 2500 +Wire Wire Line + 5000 2000 4050 2000 +Connection ~ 4200 2350 +Connection ~ 4200 2000 +Wire Wire Line + 3750 2200 3750 2350 +Connection ~ 3750 2350 +Wire Wire Line + 3750 1800 3750 1650 +Wire Wire Line + 3400 1650 7600 1650 +Wire Wire Line + 3400 1650 3400 3800 +Wire Wire Line + 5300 1650 5300 1800 +Connection ~ 3750 1650 +Wire Wire Line + 5300 2200 5300 4500 +Wire Wire Line + 5300 3500 3650 3500 +Wire Wire Line + 3650 3500 3650 3200 +Connection ~ 3650 3200 +Connection ~ 2900 4000 +Wire Wire Line + 4050 4400 4050 3400 +Wire Wire Line + 3400 4200 3400 4600 +Wire Wire Line + 3200 4600 3750 4600 +Connection ~ 3400 4600 +Wire Wire Line + 4050 5100 4050 4800 +Wire Wire Line + 3600 5100 3600 4600 +Connection ~ 3600 4600 +Wire Wire Line + 2900 5100 2900 4800 +Wire Wire Line + 2900 5400 2900 5550 +Wire Wire Line + 2900 5550 9450 5550 +Wire Wire Line + 4050 5550 4050 5400 +Wire Wire Line + 3600 5400 3600 5550 +Connection ~ 3600 5550 +Wire Wire Line + 6100 4700 5600 4700 +Wire Wire Line + 6400 2950 6400 4500 +Wire Wire Line + 6400 4250 5900 4250 +Wire Wire Line + 5900 4250 5900 4700 +Connection ~ 5900 4700 +Wire Wire Line + 5300 5100 5300 4900 +Wire Wire Line + 5300 5550 5300 5400 +Connection ~ 4050 5550 +Wire Wire Line + 6400 5550 6400 4900 +Connection ~ 5300 5550 +Connection ~ 5300 3500 +Wire Wire Line + 6400 1650 6400 1750 +Connection ~ 5300 1650 +Wire Wire Line + 6400 2150 6400 2650 +Connection ~ 6400 4250 +Wire Wire Line + 6700 1950 7300 1950 +Wire Wire Line + 7000 1950 7000 2250 +Wire Wire Line + 7000 2250 6400 2250 +Connection ~ 6400 2250 +Wire Wire Line + 7600 1650 7600 1750 +Connection ~ 6400 1650 +Connection ~ 7000 1950 +Wire Wire Line + 7600 3250 7600 4100 +Wire Wire Line + 7600 3450 7400 3450 +Wire Wire Line + 6900 3450 7100 3450 +Wire Wire Line + 6900 2650 6900 3450 +Wire Wire Line + 6900 3050 7300 3050 +Wire Wire Line + 7600 2150 7600 2850 +Wire Wire Line + 7600 2650 7400 2650 +Wire Wire Line + 7100 2650 6900 2650 +Connection ~ 6900 3050 +Connection ~ 7600 2650 +Wire Wire Line + 7300 4300 7150 4300 +Wire Wire Line + 7150 4150 7150 4950 +Connection ~ 7600 3450 +Wire Wire Line + 7600 3700 7150 3700 +Wire Wire Line + 7150 3700 7150 3750 +Connection ~ 7600 3700 +Wire Wire Line + 6600 3050 6600 2450 +Wire Wire Line + 6600 2450 7600 2450 +Connection ~ 7600 2450 +Wire Wire Line + 6600 3350 6600 3950 +Wire Wire Line + 4050 3950 6850 3950 +Wire Wire Line + 6700 3950 6700 4500 +Connection ~ 6700 3950 +Wire Wire Line + 6700 4900 6700 5550 +Connection ~ 6400 5550 +Connection ~ 7150 4300 +Wire Wire Line + 7600 4950 7600 4500 +Wire Wire Line + 7000 4700 7600 4700 +Connection ~ 7600 4700 +Wire Wire Line + 7600 5550 7600 5250 +Connection ~ 6700 5550 +Wire Wire Line + 7150 5250 7150 5550 +Connection ~ 7150 5550 +Wire Wire Line + 7600 2300 8600 2300 +Wire Wire Line + 8300 2300 8300 2550 +Connection ~ 8300 2300 +Connection ~ 7600 2300 +Wire Wire Line + 8900 2100 8900 1650 +Wire Wire Line + 7550 1650 9500 1650 +Connection ~ 7550 1650 +Connection ~ 8900 1650 +Wire Wire Line + 8900 2500 8900 2900 +Wire Wire Line + 8900 2750 8600 2750 +Connection ~ 8900 2750 +Wire Wire Line + 8300 2950 8300 3350 +Wire Wire Line + 8300 3350 8900 3350 +Wire Wire Line + 8900 3200 8900 3650 +Wire Wire Line + 8900 4400 8900 3950 +Connection ~ 8900 3350 +Wire Wire Line + 8900 3500 9500 3500 +Connection ~ 8900 3500 +Wire Wire Line + 8900 5550 8900 4800 +Connection ~ 7600 5550 +Connection ~ 8900 5550 +Wire Wire Line + 8600 4600 8100 4600 +Wire Wire Line + 8100 4600 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +Connection ~ 4050 3950 +Connection ~ 6600 3950 +Wire Wire Line + 4500 2700 4750 2700 +Wire Wire Line + 4750 2700 4750 1050 +Wire Wire Line + 2450 2700 2150 2700 +Wire Wire Line + 2150 2700 2150 1200 +$Comp +L PORT U1 +U 5 1 5CE90AA0 +P 1850 4850 +F 0 "U1" H 1900 4950 30 0000 C CNN +F 1 "PORT" H 1850 4850 30 0000 C CNN +F 2 "" H 1850 4850 60 0000 C CNN +F 3 "" H 1850 4850 60 0000 C CNN + 5 1850 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5CE90AA1 +P 1850 5100 +F 0 "U1" H 1900 5200 30 0000 C CNN +F 1 "PORT" H 1850 5100 30 0000 C CNN +F 2 "" H 1850 5100 60 0000 C CNN +F 3 "" H 1850 5100 60 0000 C CNN + 1 1850 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2100 5100 2700 5100 +Wire Wire Line + 2700 5100 2700 5050 +Wire Wire Line + 2700 5050 2900 5050 +Connection ~ 2900 5050 +Wire Wire Line + 2100 4850 2550 4850 +Wire Wire Line + 2550 4850 2550 4900 +Wire Wire Line + 2550 4900 4050 4900 +Connection ~ 4050 4900 +$Comp +L PORT U1 +U 8 1 5CE9368F +P 9600 6050 +F 0 "U1" H 9650 6150 30 0000 C CNN +F 1 "PORT" H 9600 6050 30 0000 C CNN +F 2 "" H 9600 6050 60 0000 C CNN +F 3 "" H 9600 6050 60 0000 C CNN + 8 9600 6050 + -1 0 0 1 +$EndComp +Wire Wire Line + 9350 6050 9100 6050 +NoConn ~ 9100 6050 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/lm_741.sub b/library/SubcircuitLibrary/tda7050/lm_741.sub new file mode 100644 index 00000000..fa8d27b1 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741.sub @@ -0,0 +1,40 @@ +* Subcircuit lm_741 +.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? +* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir +.include npn_1.lib +.include pnp_1.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1 +q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1 +q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1 +q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1 +q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1 +q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1 +q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1 +q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1 +r1 net-_q7-pad3_ net-_q12-pad3_ 1k +r2 net-_q3-pad3_ net-_q12-pad3_ 50k +r3 net-_q8-pad3_ net-_q12-pad3_ 1k +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1 +q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1 +r4 net-_q13-pad3_ net-_q12-pad3_ 5k +r11 net-_q10-pad1_ net-_q12-pad1_ 39k +q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1 +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1 +r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k +r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1 +q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1 +r5 net-_q15-pad2_ net-_q12-pad3_ 50k +r6 net-_q15-pad3_ net-_q12-pad3_ 50 +q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1 +q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1 +q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1 +r9 net-_q18-pad3_ net-_q20-pad3_ 25 +r10 net-_q20-pad3_ net-_q19-pad3_ 50 +q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1 +* Control Statements + +.ends lm_741
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml new file mode 100644 index 00000000..b61322bb --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/lm_741_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/npn_1.lib b/library/SubcircuitLibrary/tda7050/npn_1.lib new file mode 100644 index 00000000..a1818ed8 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/npn_1.lib @@ -0,0 +1,29 @@ +.model npn_1 NPN( ++ Vtf=1.7 ++ Cjc=0.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.5p ++ Isc=0 ++ Xtb=1.5 ++ Rb=500 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=125 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/pnp_1.lib b/library/SubcircuitLibrary/tda7050/pnp_1.lib new file mode 100644 index 00000000..a4ee06da --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/pnp_1.lib @@ -0,0 +1,29 @@ +.model pnp_1 PNP( ++ Vtf=1.7 ++ Cjc=1.5p ++ Nc=2 ++ Tr=46.91n ++ Ne=1.307 ++ Cje=0.3p ++ Isc=0 ++ Xtb=1.5 ++ Rb=250 ++ Rc=1 ++ Tf=411.1p ++ Xti=3 ++ Ikr=0 ++ Bf=25 ++ Fc=.5 ++ Ise=14.34f ++ Br=6.092 ++ Ikf=.2847 ++ Mje=.377 ++ Mjc=.3416 ++ Vaf=74.03 ++ Vjc=.75 ++ Vje=.75 ++ Xtf=3 ++ Itf=.6 ++ Is=14.34f ++ Eg=1.11 +)
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050-cache.lib b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib new file mode 100644 index 00000000..5b8e3633 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050-cache.lib @@ -0,0 +1,64 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# lm_741 +# +DEF lm_741 X 0 40 Y Y 1 F N +F0 "X" -200 0 60 H V C CNN +F1 "lm_741" -100 -250 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N +X off_null 1 -50 400 200 D 50 38 1 1 I +X inv 2 -550 150 200 R 50 38 1 1 I +X non_inv 3 -550 -100 200 R 50 38 1 1 I +X v_neg 4 -150 -450 200 U 50 38 1 1 I +X off_null 5 50 350 200 D 50 38 1 1 I +X out 6 550 0 200 L 50 38 1 1 O +X v_pos 7 -150 450 200 D 50 38 1 1 I +X NC 8 150 -300 200 U 50 38 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir b/library/SubcircuitLibrary/tda7050/tda7050.cir new file mode 100644 index 00000000..3cb98116 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\tda7050\tda7050.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/08/25 21:45:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 ? Net-_U1-Pad2_ Net-_U1-Pad1_ Net-_U1-Pad5_ ? Net-_U1-Pad7_ Net-_U1-Pad8_ ? lm_741 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ PORT +X2 ? Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad8_ ? Net-_U1-Pad6_ Net-_U1-Pad5_ ? lm_741 + +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.cir.out b/library/SubcircuitLibrary/tda7050/tda7050.cir.out new file mode 100644 index 00000000..dbb02840 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.cir.out @@ -0,0 +1,15 @@ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir + +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ port +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/tda7050/tda7050.pro b/library/SubcircuitLibrary/tda7050/tda7050.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sch b/library/SubcircuitLibrary/tda7050/tda7050.sch new file mode 100644 index 00000000..2a82e7a3 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sch @@ -0,0 +1,209 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:tda7050-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 6000 2750 +Wire Wire Line + 5750 2750 6100 2750 +Wire Wire Line + 5500 4950 5600 4950 +Wire Wire Line + 6700 3500 6700 3450 +Wire Wire Line + 5750 2750 5750 4350 +Wire Wire Line + 5750 3950 6000 3950 +Wire Wire Line + 6000 3950 6000 3900 +Wire Wire Line + 5750 4350 6000 4350 +Connection ~ 5750 3950 +Wire Wire Line + 6000 2950 5300 2950 +$Comp +L lm_741 X1 +U 1 1 678D14D5 +P 6150 3450 +F 0 "X1" H 5950 3450 60 0000 C CNN +F 1 "lm_741" H 6050 3200 60 0000 C CNN +F 2 "" H 6150 3450 60 0000 C CNN +F 3 "" H 6150 3450 60 0000 C CNN + 1 6150 3450 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 679DC622 +P 6350 2750 +F 0 "U1" H 6400 2850 30 0000 C CNN +F 1 "PORT" H 6350 2750 30 0000 C CNN +F 2 "" H 6350 2750 60 0000 C CNN +F 3 "" H 6350 2750 60 0000 C CNN + 8 6350 2750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 679DC653 +P 5500 5500 +F 0 "U1" H 5550 5600 30 0000 C CNN +F 1 "PORT" H 5500 5500 30 0000 C CNN +F 2 "" H 5500 5500 60 0000 C CNN +F 3 "" H 5500 5500 60 0000 C CNN + 5 5500 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 679DC678 +P 5300 4700 +F 0 "U1" H 5350 4800 30 0000 C CNN +F 1 "PORT" H 5300 4700 30 0000 C CNN +F 2 "" H 5300 4700 60 0000 C CNN +F 3 "" H 5300 4700 60 0000 C CNN + 4 5300 4700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 679DC69F +P 7000 4800 +F 0 "U1" H 7050 4900 30 0000 C CNN +F 1 "PORT" H 7000 4800 30 0000 C CNN +F 2 "" H 7000 4800 60 0000 C CNN +F 3 "" H 7000 4800 60 0000 C CNN + 6 7000 4800 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 679DC6C8 +P 5250 4950 +F 0 "U1" H 5300 5050 30 0000 C CNN +F 1 "PORT" H 5250 4950 30 0000 C CNN +F 2 "" H 5250 4950 60 0000 C CNN +F 3 "" H 5250 4950 60 0000 C CNN + 3 5250 4950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679DC6F3 +P 6950 3500 +F 0 "U1" H 7000 3600 30 0000 C CNN +F 1 "PORT" H 6950 3500 30 0000 C CNN +F 2 "" H 6950 3500 60 0000 C CNN +F 3 "" H 6950 3500 60 0000 C CNN + 7 6950 3500 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 679DC720 +P 5300 3600 +F 0 "U1" H 5350 3700 30 0000 C CNN +F 1 "PORT" H 5300 3600 30 0000 C CNN +F 2 "" H 5300 3600 60 0000 C CNN +F 3 "" H 5300 3600 60 0000 C CNN + 2 5300 3600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 679DC74F +P 5150 3350 +F 0 "U1" H 5200 3450 30 0000 C CNN +F 1 "PORT" H 5150 3350 30 0000 C CNN +F 2 "" H 5150 3350 60 0000 C CNN +F 3 "" H 5150 3350 60 0000 C CNN + 1 5150 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2950 5300 5350 +Wire Wire Line + 5300 5350 6000 5350 +Connection ~ 6000 5350 +Wire Wire Line + 5750 5500 5900 5500 +Wire Wire Line + 5900 5500 5900 5400 +Wire Wire Line + 5900 5400 6000 5400 +Connection ~ 6000 5400 +$Comp +L lm_741 X2 +U 1 1 678D14EC +P 6150 4800 +F 0 "X2" H 5950 4800 60 0000 C CNN +F 1 "lm_741" H 6050 4550 60 0000 C CNN +F 2 "" H 6150 4800 60 0000 C CNN +F 3 "" H 6150 4800 60 0000 C CNN + 1 6150 4800 + 1 0 0 1 +$EndComp +Wire Wire Line + 5550 3600 5600 3600 +Wire Wire Line + 5550 4700 5600 4700 +Wire Wire Line + 6000 5400 6000 5250 +Wire Wire Line + 5400 3350 5600 3350 +Wire Wire Line + 6750 4800 6700 4800 +Wire Wire Line + 6000 3000 6000 2950 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/tda7050/tda7050.sub b/library/SubcircuitLibrary/tda7050/tda7050.sub new file mode 100644 index 00000000..a4faab2c --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050.sub @@ -0,0 +1,9 @@ +* Subcircuit tda7050 +.subckt tda7050 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ +* c:\fossee\esim\library\subcircuitlibrary\tda7050\tda7050.cir +.include lm_741.sub +x1 ? net-_u1-pad2_ net-_u1-pad1_ net-_u1-pad5_ ? net-_u1-pad7_ net-_u1-pad8_ ? lm_741 +x2 ? net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad8_ ? net-_u1-pad6_ net-_u1-pad5_ ? lm_741 +* Control Statements + +.ends tda7050
\ No newline at end of file diff --git a/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml new file mode 100644 index 00000000..08c5b203 --- /dev/null +++ b/library/SubcircuitLibrary/tda7050/tda7050_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel /><subcircuit><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x2></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file |