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path: root/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb
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Diffstat (limited to 'library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb')
-rw-r--r--library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb320
1 files changed, 320 insertions, 0 deletions
diff --git a/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb
new file mode 100644
index 00000000..d6ce37a3
--- /dev/null
+++ b/library/kicadLibrary/template/raspberrypi-gpio/raspberrypi-gpio.kicad_pcb
@@ -0,0 +1,320 @@
+(kicad_pcb (version 4) (host pcbnew 4.0.5)
+
+ (general
+ (links 0)
+ (no_connects 0)
+ (area 143.424999 124.924999 228.575001 181.075001)
+ (thickness 1.6)
+ (drawings 41)
+ (tracks 0)
+ (zones 0)
+ (modules 1)
+ (nets 27)
+ )
+
+ (page A3)
+ (title_block
+ (date "15 nov 2012")
+ )
+
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ )
+
+ (setup
+ (last_trace_width 0.2)
+ (trace_clearance 0.2)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.1524)
+ (segment_width 0.2)
+ (edge_width 0.15)
+ (via_size 0.9)
+ (via_drill 0.6)
+ (via_min_size 0.8)
+ (via_min_drill 0.5)
+ (uvia_size 0.5)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.5)
+ (uvia_min_drill 0.1)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1 1)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 1 1)
+ (pad_drill 0.6)
+ (pad_to_mask_clearance 0)
+ (aux_axis_origin 143.5 181)
+ (visible_elements 7FFFFFFF)
+ (pcbplotparams
+ (layerselection 0x00030_80000001)
+ (usegerberextensions true)
+ (excludeedgelayer true)
+ (linewidth 0.150000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (hpglpenoverlay 2)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 1)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 +5V)
+ (net 2 GND)
+ (net 3 +3V3)
+ (net 4 "/GPIO0(SDA)")
+ (net 5 "Net-(P1-Pad4)")
+ (net 6 "/GPIO1(SCL)")
+ (net 7 /GPIO4)
+ (net 8 /TXD)
+ (net 9 "Net-(P1-Pad9)")
+ (net 10 /RXD)
+ (net 11 /GPIO17)
+ (net 12 /GPIO18)
+ (net 13 /GPIO21)
+ (net 14 "Net-(P1-Pad14)")
+ (net 15 /GPIO22)
+ (net 16 /GPIO23)
+ (net 17 "Net-(P1-Pad17)")
+ (net 18 /GPIO24)
+ (net 19 "/GPIO10(MOSI)")
+ (net 20 "Net-(P1-Pad20)")
+ (net 21 "/GPIO9(MISO)")
+ (net 22 /GPIO25)
+ (net 23 "/GPIO11(SCLK)")
+ (net 24 "/GPIO8(CE0)")
+ (net 25 "Net-(P1-Pad25)")
+ (net 26 "/GPIO7(CE1)")
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.2)
+ (via_dia 0.9)
+ (via_drill 0.6)
+ (uvia_dia 0.5)
+ (uvia_drill 0.1)
+ (add_net +3V3)
+ (add_net +5V)
+ (add_net "/GPIO0(SDA)")
+ (add_net "/GPIO1(SCL)")
+ (add_net "/GPIO10(MOSI)")
+ (add_net "/GPIO11(SCLK)")
+ (add_net /GPIO17)
+ (add_net /GPIO18)
+ (add_net /GPIO21)
+ (add_net /GPIO22)
+ (add_net /GPIO23)
+ (add_net /GPIO24)
+ (add_net /GPIO25)
+ (add_net /GPIO4)
+ (add_net "/GPIO7(CE1)")
+ (add_net "/GPIO8(CE0)")
+ (add_net "/GPIO9(MISO)")
+ (add_net /RXD)
+ (add_net /TXD)
+ (add_net GND)
+ (add_net "Net-(P1-Pad14)")
+ (add_net "Net-(P1-Pad17)")
+ (add_net "Net-(P1-Pad20)")
+ (add_net "Net-(P1-Pad25)")
+ (add_net "Net-(P1-Pad4)")
+ (add_net "Net-(P1-Pad9)")
+ )
+
+ (net_class Power ""
+ (clearance 0.2)
+ (trace_width 0.5)
+ (via_dia 1)
+ (via_drill 0.7)
+ (uvia_dia 0.5)
+ (uvia_drill 0.1)
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_2x13 locked (layer F.Cu) (tedit 584FB37B) (tstamp 584FB325)
+ (at 145.75536 130.27914 90)
+ (descr "Through hole pin header")
+ (tags "pin header")
+ (path /50A55ABA)
+ (fp_text reference P1 (at 1.5875 32.6136 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value CONN_13X2 (at -2.37998 16.29664 180) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -1.75 -1.75) (end -1.75 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 4.3 -1.75) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 32.25) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.27 1.27) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 31.75) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
+ (pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 3 +3V3))
+ (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 +5V))
+ (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 "/GPIO0(SDA)"))
+ (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 "Net-(P1-Pad4)"))
+ (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 6 "/GPIO1(SCL)"))
+ (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 2 GND))
+ (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 7 /GPIO4))
+ (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 8 /TXD))
+ (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 9 "Net-(P1-Pad9)"))
+ (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 10 /RXD))
+ (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 11 /GPIO17))
+ (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 12 /GPIO18))
+ (pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 13 /GPIO21))
+ (pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 14 "Net-(P1-Pad14)"))
+ (pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 15 /GPIO22))
+ (pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 16 /GPIO23))
+ (pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 17 "Net-(P1-Pad17)"))
+ (pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 18 /GPIO24))
+ (pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 19 "/GPIO10(MOSI)"))
+ (pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 20 "Net-(P1-Pad20)"))
+ (pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 21 "/GPIO9(MISO)"))
+ (pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 22 /GPIO25))
+ (pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 23 "/GPIO11(SCLK)"))
+ (pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 24 "/GPIO8(CE0)"))
+ (pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 25 "Net-(P1-Pad25)"))
+ (pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 26 "/GPIO7(CE1)"))
+ (model Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl
+ (at (xyz 0.05 -0.6 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 90))
+ )
+ )
+
+ (gr_text "RASPBERRY-PI ADDON BOARD\nVIEW FROM TOP\nNOTE: P1 SHOULD BE FITTED ON THE REVERSE OF THE BOARD" (at 144 183.5) (layer Dwgs.User)
+ (effects (font (size 2 1.7) (thickness 0.12)) (justify left))
+ )
+ (dimension 56 (width 0.12) (layer Dwgs.User)
+ (gr_text "56.000 mm" (at 132 153 90) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (feature1 (pts (xy 143.5 125) (xy 131 125)))
+ (feature2 (pts (xy 143.5 181) (xy 131 181)))
+ (crossbar (pts (xy 133 181) (xy 133 125)))
+ (arrow1a (pts (xy 133 125) (xy 133.58642 126.126503)))
+ (arrow1b (pts (xy 133 125) (xy 132.41358 126.126503)))
+ (arrow2a (pts (xy 133 181) (xy 133.58642 179.873497)))
+ (arrow2b (pts (xy 133 181) (xy 132.41358 179.873497)))
+ )
+ (dimension 85 (width 0.12) (layer Dwgs.User)
+ (gr_text "85.000 mm" (at 186 113.000001) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (feature1 (pts (xy 228.5 125) (xy 228.5 112.000001)))
+ (feature2 (pts (xy 143.5 125) (xy 143.5 112.000001)))
+ (crossbar (pts (xy 143.5 114.000001) (xy 228.5 114.000001)))
+ (arrow1a (pts (xy 228.5 114.000001) (xy 227.373497 114.586421)))
+ (arrow1b (pts (xy 228.5 114.000001) (xy 227.373497 113.413581)))
+ (arrow2a (pts (xy 143.5 114.000001) (xy 144.626503 114.586421)))
+ (arrow2b (pts (xy 143.5 114.000001) (xy 144.626503 113.413581)))
+ )
+ (gr_text "RCA\nREMOVE WITH\nSTD HEADERS\n!NO TH ABOVE!" (at 188.5 118) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_text "1/8\" JACK\nOK WITH STD\nHEADERS\n!NO TH ABOVE!" (at 207.5 118) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_line (start 228.5 142) (end 228.5 125) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 217.5 142) (end 228.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 217.5 157) (end 217.5 142) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 228.5 157) (end 217.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 228.5 181) (end 228.5 157) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_text "DOUBLE USB\nCUTOUT FOR ALL\nBOARDS" (at 236.5 149) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_text "RJ45\nCUTOUT FOR STD\nHEADERS\n!NO TH ABOVE!" (at 236.5 170) (layer Dwgs.User)
+ (effects (font (size 1 1) (thickness 0.12)))
+ )
+ (gr_line (start 207.5 181) (end 228.5 162) (angle 90) (layer Dwgs.User) (width 0.2))
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+
+)
generated by cgit (git 2.34.1) at 2024-12-20 17:00:39 +0000