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Diffstat (limited to 'library/kicadLibrary/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb')
-rw-r--r--library/kicadLibrary/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb321
1 files changed, 321 insertions, 0 deletions
diff --git a/library/kicadLibrary/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb b/library/kicadLibrary/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb
new file mode 100644
index 00000000..26641eb4
--- /dev/null
+++ b/library/kicadLibrary/template/minnowboard-ls-lure/minnowboard-ls-lure.kicad_pcb
@@ -0,0 +1,321 @@
+(kicad_pcb (version 20160815) (host pcbnew no-vcs-found-7409~56~ubuntu16.10.1)
+
+ (general
+ (links 1)
+ (no_connects 1)
+ (area 38.235286 69.47162 197.449762 147.28)
+ (thickness 1.6)
+ (drawings 20)
+ (tracks 0)
+ (zones 0)
+ (modules 5)
+ (nets 26)
+ )
+
+ (page A4)
+ (layers
+ (0 F.Cu signal)
+ (31 B.Cu signal)
+ (32 B.Adhes user)
+ (33 F.Adhes user)
+ (34 B.Paste user)
+ (35 F.Paste user)
+ (36 B.SilkS user)
+ (37 F.SilkS user)
+ (38 B.Mask user)
+ (39 F.Mask user)
+ (40 Dwgs.User user)
+ (41 Cmts.User user)
+ (42 Eco1.User user)
+ (43 Eco2.User user)
+ (44 Edge.Cuts user)
+ (45 Margin user)
+ (46 B.CrtYd user)
+ (47 F.CrtYd user)
+ (48 B.Fab user)
+ (49 F.Fab user)
+ )
+
+ (setup
+ (last_trace_width 0.25)
+ (trace_clearance 0.2)
+ (zone_clearance 0.508)
+ (zone_45_only no)
+ (trace_min 0.2)
+ (segment_width 0.2)
+ (edge_width 0.2)
+ (via_size 0.6)
+ (via_drill 0.4)
+ (via_min_size 0.4)
+ (via_min_drill 0.3)
+ (uvia_size 0.3)
+ (uvia_drill 0.1)
+ (uvias_allowed no)
+ (uvia_min_size 0.2)
+ (uvia_min_drill 0.1)
+ (pcb_text_width 0.3)
+ (pcb_text_size 1.5 1.5)
+ (mod_edge_width 0.15)
+ (mod_text_size 1 1)
+ (mod_text_width 0.15)
+ (pad_size 3.302 3.302)
+ (pad_drill 3.302)
+ (pad_to_mask_clearance 0.0762)
+ (aux_axis_origin 96.52 144.78)
+ (grid_origin 96.52 144.78)
+ (visible_elements FFFFFF7F)
+ (pcbplotparams
+ (layerselection 0x000fc_80000001)
+ (usegerberextensions false)
+ (excludeedgelayer true)
+ (linewidth 0.100000)
+ (plotframeref false)
+ (viasonmask false)
+ (mode 1)
+ (useauxorigin false)
+ (hpglpennumber 1)
+ (hpglpenspeed 20)
+ (hpglpendiameter 15)
+ (psnegative false)
+ (psa4output false)
+ (plotreference true)
+ (plotvalue true)
+ (plotinvisibletext false)
+ (padsonsilk false)
+ (subtractmaskfromsilk false)
+ (outputformat 1)
+ (mirror false)
+ (drillshape 0)
+ (scaleselection 1)
+ (outputdirectory ""))
+ )
+
+ (net 0 "")
+ (net 1 GND)
+ (net 2 +5V)
+ (net 3 +3V3)
+ (net 4 GPIO_SPI_CS#)
+ (net 5 GPIO_UART1_TXD)
+ (net 6 GPIO_SPI_MISO)
+ (net 7 GPIO_UART1_RXD)
+ (net 8 GPIO_SPI_MOSI)
+ (net 9 GPIO_UART1_CTS)
+ (net 10 GPIO_SPI_CLK)
+ (net 11 GPIO_UART1_RTS)
+ (net 12 GPIO_I2C_SCL)
+ (net 13 GPIO_I2S_CLK)
+ (net 14 GPIO_I2C_SDA)
+ (net 15 GPIO_I2S_FRM)
+ (net 16 GPIO_UART2_TXD)
+ (net 17 GPIO_I2S_DO)
+ (net 18 GPIO_UART2_RXD)
+ (net 19 GPIO_I2S_DI)
+ (net 20 GPIO_S5_0)
+ (net 21 GPIO_PWM0)
+ (net 22 GPIO_S5_1)
+ (net 23 GPIO_PWM1)
+ (net 24 GPIO_S5_2)
+ (net 25 I2SMCLK_GPIO)
+
+ (net_class Default "This is the default net class."
+ (clearance 0.2)
+ (trace_width 0.25)
+ (via_dia 0.6)
+ (via_drill 0.4)
+ (uvia_dia 0.3)
+ (uvia_drill 0.1)
+ (diff_pair_gap 0.25)
+ (diff_pair_width 0.2)
+ (add_net +3V3)
+ (add_net +5V)
+ (add_net GND)
+ (add_net GPIO_I2C_SCL)
+ (add_net GPIO_I2C_SDA)
+ (add_net GPIO_I2S_CLK)
+ (add_net GPIO_I2S_DI)
+ (add_net GPIO_I2S_DO)
+ (add_net GPIO_I2S_FRM)
+ (add_net GPIO_PWM0)
+ (add_net GPIO_PWM1)
+ (add_net GPIO_S5_0)
+ (add_net GPIO_S5_1)
+ (add_net GPIO_S5_2)
+ (add_net GPIO_SPI_CLK)
+ (add_net GPIO_SPI_CS#)
+ (add_net GPIO_SPI_MISO)
+ (add_net GPIO_SPI_MOSI)
+ (add_net GPIO_UART1_CTS)
+ (add_net GPIO_UART1_RTS)
+ (add_net GPIO_UART1_RXD)
+ (add_net GPIO_UART1_TXD)
+ (add_net GPIO_UART2_RXD)
+ (add_net GPIO_UART2_TXD)
+ (add_net I2SMCLK_GPIO)
+ )
+
+ (module Pin_Headers:Pin_Header_Straight_2x13 locked (layer F.Cu) (tedit 577F1E14) (tstamp 57710C62)
+ (at 109.855 142.24 90)
+ (descr "Through hole pin header")
+ (tags "pin header")
+ (path /576C994F)
+ (fp_text reference P1 (at 1.27 -3.175 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value CONN_02X13 (at 5.08 3.175 180) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_line (start -1.75 -1.75) (end -1.75 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 4.3 -1.75) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05))
+ (fp_line (start -1.75 32.25) (end 4.3 32.25) (layer F.CrtYd) (width 0.05))
+ (fp_line (start 3.81 -1.27) (end 3.81 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.27 1.27) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 31.75) (end -1.27 31.75) (layer F.SilkS) (width 0.15))
+ (fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
+ (fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
+ (pad 1 thru_hole rect (at 0 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (pad 2 thru_hole oval (at 2.54 0 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 1 GND))
+ (pad 3 thru_hole oval (at 0 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 2 +5V))
+ (pad 4 thru_hole oval (at 2.54 2.54 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 3 +3V3))
+ (pad 5 thru_hole oval (at 0 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 4 GPIO_SPI_CS#))
+ (pad 6 thru_hole oval (at 2.54 5.08 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 5 GPIO_UART1_TXD))
+ (pad 7 thru_hole oval (at 0 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 6 GPIO_SPI_MISO))
+ (pad 8 thru_hole oval (at 2.54 7.62 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 7 GPIO_UART1_RXD))
+ (pad 9 thru_hole oval (at 0 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 8 GPIO_SPI_MOSI))
+ (pad 10 thru_hole oval (at 2.54 10.16 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 9 GPIO_UART1_CTS))
+ (pad 11 thru_hole oval (at 0 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 10 GPIO_SPI_CLK))
+ (pad 12 thru_hole oval (at 2.54 12.7 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 11 GPIO_UART1_RTS))
+ (pad 13 thru_hole oval (at 0 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 12 GPIO_I2C_SCL))
+ (pad 14 thru_hole oval (at 2.54 15.24 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 13 GPIO_I2S_CLK))
+ (pad 15 thru_hole oval (at 0 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 14 GPIO_I2C_SDA))
+ (pad 16 thru_hole oval (at 2.54 17.78 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 15 GPIO_I2S_FRM))
+ (pad 17 thru_hole oval (at 0 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 16 GPIO_UART2_TXD))
+ (pad 18 thru_hole oval (at 2.54 20.32 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 17 GPIO_I2S_DO))
+ (pad 19 thru_hole oval (at 0 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 18 GPIO_UART2_RXD))
+ (pad 20 thru_hole oval (at 2.54 22.86 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 19 GPIO_I2S_DI))
+ (pad 21 thru_hole oval (at 0 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 20 GPIO_S5_0))
+ (pad 22 thru_hole oval (at 2.54 25.4 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 21 GPIO_PWM0))
+ (pad 23 thru_hole oval (at 0 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 22 GPIO_S5_1))
+ (pad 24 thru_hole oval (at 2.54 27.94 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 23 GPIO_PWM1))
+ (pad 25 thru_hole oval (at 0 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 24 GPIO_S5_2))
+ (pad 26 thru_hole oval (at 2.54 30.48 90) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
+ (net 25 I2SMCLK_GPIO))
+ (model Pin_Headers.3dshapes/Pin_Header_Straight_2x13.wrl
+ (at (xyz 0.05 -0.6 0))
+ (scale (xyz 1 1 1))
+ (rotate (xyz 0 0 90))
+ )
+ )
+
+ (module Mounting_Holes:MountingHole_3-5mm locked (layer F.Cu) (tedit 58633422) (tstamp 577DA462)
+ (at 191.77 140.97)
+ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (path /58633372)
+ (fp_text reference MK2 (at 0 -4.50088) (layer F.SilkS) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Mounting_Hole (at 0 5.00126) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.381))
+ (pad 1 thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers))
+ )
+
+ (module Mounting_Holes:MountingHole_3-5mm locked (layer F.Cu) (tedit 58633418) (tstamp 577F1CAE)
+ (at 100.33 140.97)
+ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (path /58633409)
+ (fp_text reference MK1 (at 0 -4.50088) (layer F.SilkS) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Mounting_Hole (at 0 5.00126) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.381))
+ (pad 1 thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers))
+ )
+
+ (module Mounting_Holes:MountingHole_3-5mm locked (layer F.Cu) (tedit 58633440) (tstamp 577F1CB9)
+ (at 100.33 74.93)
+ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (path /5863348E)
+ (fp_text reference MK4 (at 0 -4.50088) (layer F.SilkS) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Mounting_Hole (at 0 5.00126) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.381))
+ (pad 1 thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers))
+ )
+
+ (module Mounting_Holes:MountingHole_3-5mm locked (layer F.Cu) (tedit 58633432) (tstamp 577F1CC4)
+ (at 191.77 74.93)
+ (descr "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (tags "Mounting hole, Befestigungsbohrung, 3,5mm, No Annular, Kein Restring,")
+ (path /58633454)
+ (fp_text reference MK3 (at 0 -4.50088) (layer F.SilkS) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Mounting_Hole (at 0 5.00126) (layer F.Fab) hide
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_circle (center 0 0) (end 3.5 0) (layer Cmts.User) (width 0.381))
+ (pad 1 thru_hole circle (at 0 0) (size 3.5 3.5) (drill 3.5) (layers))
+ )
+
+ (gr_line (start 96.52 110.15) (end 96.52 144.78) (layer Edge.Cuts) (width 0.2))
+ (gr_line (start 195.58 96.83) (end 195.58 71.12) (angle 90) (layer Edge.Cuts) (width 0.15) (tstamp 586C5EA2))
+ (gr_text "NOTE: NO BOTTOM SIDE OR THROUGH-HOLE\nCOMPONENTS IN THE AREAS DESIGNATED IN THE\nDWGS.USER LAYER TO AVOID COLLISION WITH\nMINNOWBOARD ETHERNET AND USB CONNECTORS." (at 66.421 101.092) (layer Cmts.User)
+ (effects (font (size 1.5 1.5) (thickness 0.3)))
+ )
+ (gr_line (start 178.86 112.02) (end 195.58 96.83) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 178.86 96.83) (end 195.58 112.02) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 114.96 92.05) (end 96.52 110.15) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 96.52 92.05) (end 114.96 110.15) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 96.52 110.15) (end 96.52 92.05) (angle 90) (layer Edge.Cuts) (width 0.2))
+ (gr_line (start 114.96 110.15) (end 96.52 110.15) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 114.96 92.05) (end 114.96 110.15) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 96.52 92.05) (end 114.96 92.05) (angle 90) (layer Dwgs.User) (width 0.2))
+ (gr_line (start 178.86 112.02) (end 178.86 96.83) (angle 90) (layer Dwgs.User) (width 0.15))
+ (gr_line (start 195.58 112.02) (end 178.86 112.02) (angle 90) (layer Dwgs.User) (width 0.15))
+ (gr_line (start 195.58 96.83) (end 195.58 112.02) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 178.86 96.83) (end 195.58 96.83) (angle 90) (layer Dwgs.User) (width 0.15))
+ (target plus (at 96.52 144.78) (size 5) (width 0.15) (layer Edge.Cuts))
+ (gr_line (start 96.52 71.12) (end 96.52 92.05) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 195.58 71.12) (end 96.52 71.12) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 195.58 144.78) (end 195.58 112.02) (angle 90) (layer Edge.Cuts) (width 0.15))
+ (gr_line (start 96.52 144.78) (end 195.58 144.78) (angle 90) (layer Edge.Cuts) (width 0.15))
+
+)
generated by cgit (git 2.34.1) at 2024-12-20 16:49:44 +0000