diff options
Diffstat (limited to 'library/SubcircuitLibrary')
23 files changed, 2310 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74351/3_and-cache.lib b/library/SubcircuitLibrary/SN74351/3_and-cache.lib new file mode 100644 index 00000000..af058641 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir b/library/SubcircuitLibrary/SN74351/3_and.cir new file mode 100644 index 00000000..ba296cf0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and +U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.cir.out b/library/SubcircuitLibrary/SN74351/3_and.cir.out new file mode 100644 index 00000000..d7cf79a0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir + +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/3_and.pro b/library/SubcircuitLibrary/SN74351/3_and.pro new file mode 100644 index 00000000..da3e199e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 20:00:16 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=eSim_Sources +LibName9=eSim_Subckt +LibName10=eSim_User diff --git a/library/SubcircuitLibrary/SN74351/3_and.sch b/library/SubcircuitLibrary/SN74351/3_and.sch new file mode 100644 index 00000000..d6ac89f9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_PSpice +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_User +LIBS:3_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_and U2 +U 1 1 5C9A24D8 +P 4250 2700 +F 0 "U2" H 4250 2700 60 0000 C CNN +F 1 "d_and" H 4300 2800 60 0000 C CNN +F 2 "" H 4250 2700 60 0000 C CNN +F 3 "" H 4250 2700 60 0000 C CNN + 1 4250 2700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2538 +P 5150 2900 +F 0 "U3" H 5150 2900 60 0000 C CNN +F 1 "d_and" H 5200 3000 60 0000 C CNN +F 2 "" H 5150 2900 60 0000 C CNN +F 3 "" H 5150 2900 60 0000 C CNN + 1 5150 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 5C9A259A +P 3050 2600 +F 0 "U1" H 3100 2700 30 0000 C CNN +F 1 "PORT" H 3050 2600 30 0000 C CNN +F 2 "" H 3050 2600 60 0000 C CNN +F 3 "" H 3050 2600 60 0000 C CNN + 1 3050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A25D9 +P 3050 2800 +F 0 "U1" H 3100 2900 30 0000 C CNN +F 1 "PORT" H 3050 2800 30 0000 C CNN +F 2 "" H 3050 2800 60 0000 C CNN +F 3 "" H 3050 2800 60 0000 C CNN + 2 3050 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A260A +P 3050 3100 +F 0 "U1" H 3100 3200 30 0000 C CNN +F 1 "PORT" H 3050 3100 30 0000 C CNN +F 2 "" H 3050 3100 60 0000 C CNN +F 3 "" H 3050 3100 60 0000 C CNN + 3 3050 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A2637 +P 6900 2850 +F 0 "U1" H 6950 2950 30 0000 C CNN +F 1 "PORT" H 6900 2850 30 0000 C CNN +F 2 "" H 6900 2850 60 0000 C CNN +F 3 "" H 6900 2850 60 0000 C CNN + 4 6900 2850 + -1 0 0 1 +$EndComp +Wire Wire Line + 4700 2650 4700 2800 +Wire Wire Line + 5600 2850 6650 2850 +Wire Wire Line + 3800 2600 3300 2600 +Wire Wire Line + 3800 2700 3300 2700 +Wire Wire Line + 3300 2700 3300 2800 +Wire Wire Line + 3300 3100 4700 3100 +Wire Wire Line + 4700 3100 4700 2900 +Text Notes 3500 2600 0 60 ~ 12 +in1 +Text Notes 3450 2800 0 60 ~ 12 +in2\n +Text Notes 3500 3100 0 60 ~ 12 +in3 +Text Notes 6100 2850 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/3_and.sub b/library/SubcircuitLibrary/SN74351/3_and.sub new file mode 100644 index 00000000..3d9120bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and +.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and +* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and +a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2 +a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and-cache.lib b/library/SubcircuitLibrary/SN74351/5_and-cache.lib new file mode 100644 index 00000000..fc177c1f --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and-rescue.lib b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib new file mode 100644 index 00000000..483b8efb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 3_and-RESCUE-5_and +# +DEF 3_and-RESCUE-5_and X 0 40 Y Y 1 F N +F0 "X" 900 300 60 H V C CNN +F1 "3_and-RESCUE-5_and" 950 500 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250 +P 2 0 1 0 650 550 1000 550 N +P 3 0 1 0 650 550 650 250 1000 250 N +X in1 1 450 500 200 R 50 50 1 1 I +X in2 2 450 400 200 R 50 50 1 1 I +X in3 3 450 300 200 R 50 50 1 1 I +X out 4 1300 400 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir b/library/SubcircuitLibrary/SN74351/5_and.cir new file mode 100644 index 00000000..6a05b9b5 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\5_and\5_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:53:13 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U3-Pad1_ 3_and +U2 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U2-Pad3_ d_and +U3 Net-_U3-Pad1_ Net-_U2-Pad3_ Net-_U1-Pad6_ d_and +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ PORT + +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.cir.out b/library/SubcircuitLibrary/SN74351/5_and.cir.out new file mode 100644 index 00000000..6a6b126a --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.cir.out @@ -0,0 +1,22 @@ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir + +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ port +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/5_and.pro b/library/SubcircuitLibrary/SN74351/5_and.pro new file mode 100644 index 00000000..c16a3f85 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.pro @@ -0,0 +1,49 @@ +update=Wed Mar 18 19:59:53 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir=../../../kicadSchematicLibrary +[eeschema/libraries] +LibName1=cypress +LibName2=siliconi +LibName3=opto +LibName4=atmel +LibName5=contrib +LibName6=valves +LibName7=eSim_Analog +LibName8=eSim_Devices +LibName9=eSim_Digital +LibName10=eSim_Hybrid +LibName11=eSim_Miscellaneous +LibName12=eSim_Plot +LibName13=eSim_Power +LibName14=eSim_User +LibName15=eSim_Sources +LibName16=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/5_and.sch b/library/SubcircuitLibrary/SN74351/5_and.sch new file mode 100644 index 00000000..aef3c043 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sch @@ -0,0 +1,171 @@ +EESchema Schematic File Version 2 +LIBS:5_and-rescue +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Plot +LIBS:eSim_Power +LIBS:eSim_User +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:5_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 3_and-RESCUE-5_and X1 +U 1 1 5C9A2741 +P 3800 3350 +F 0 "X1" H 4700 3650 60 0000 C CNN +F 1 "3_and" H 4750 3850 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_and U2 +U 1 1 5C9A2764 +P 4650 3400 +F 0 "U2" H 4650 3400 60 0000 C CNN +F 1 "d_and" H 4700 3500 60 0000 C CNN +F 2 "" H 4650 3400 60 0000 C CNN +F 3 "" H 4650 3400 60 0000 C CNN + 1 4650 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 5C9A2791 +P 5550 3200 +F 0 "U3" H 5550 3200 60 0000 C CNN +F 1 "d_and" H 5600 3300 60 0000 C CNN +F 2 "" H 5550 3200 60 0000 C CNN +F 3 "" H 5550 3200 60 0000 C CNN + 1 5550 3200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5100 3100 5100 2950 +Wire Wire Line + 5100 3200 5100 3350 +Wire Wire Line + 4250 2850 4250 2700 +Wire Wire Line + 4250 2700 3600 2700 +Wire Wire Line + 4250 2950 4150 2950 +Wire Wire Line + 4150 2950 4150 2900 +Wire Wire Line + 4150 2900 3600 2900 +Wire Wire Line + 4200 3300 3600 3300 +Wire Wire Line + 4250 3050 4250 3100 +Wire Wire Line + 4250 3100 3600 3100 +Wire Wire Line + 4200 3400 4200 3500 +Wire Wire Line + 4200 3500 3600 3500 +Wire Wire Line + 6000 3150 6500 3150 +$Comp +L PORT U1 +U 1 1 5C9A2865 +P 3350 2700 +F 0 "U1" H 3400 2800 30 0000 C CNN +F 1 "PORT" H 3350 2700 30 0000 C CNN +F 2 "" H 3350 2700 60 0000 C CNN +F 3 "" H 3350 2700 60 0000 C CNN + 1 3350 2700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 5C9A28B6 +P 3350 2900 +F 0 "U1" H 3400 3000 30 0000 C CNN +F 1 "PORT" H 3350 2900 30 0000 C CNN +F 2 "" H 3350 2900 60 0000 C CNN +F 3 "" H 3350 2900 60 0000 C CNN + 2 3350 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 5C9A28D9 +P 3350 3100 +F 0 "U1" H 3400 3200 30 0000 C CNN +F 1 "PORT" H 3350 3100 30 0000 C CNN +F 2 "" H 3350 3100 60 0000 C CNN +F 3 "" H 3350 3100 60 0000 C CNN + 3 3350 3100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 5C9A28FF +P 3350 3300 +F 0 "U1" H 3400 3400 30 0000 C CNN +F 1 "PORT" H 3350 3300 30 0000 C CNN +F 2 "" H 3350 3300 60 0000 C CNN +F 3 "" H 3350 3300 60 0000 C CNN + 4 3350 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 5C9A2928 +P 3350 3500 +F 0 "U1" H 3400 3600 30 0000 C CNN +F 1 "PORT" H 3350 3500 30 0000 C CNN +F 2 "" H 3350 3500 60 0000 C CNN +F 3 "" H 3350 3500 60 0000 C CNN + 5 3350 3500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 5C9A2958 +P 6750 3150 +F 0 "U1" H 6800 3250 30 0000 C CNN +F 1 "PORT" H 6750 3150 30 0000 C CNN +F 2 "" H 6750 3150 60 0000 C CNN +F 3 "" H 6750 3150 60 0000 C CNN + 6 6750 3150 + -1 0 0 1 +$EndComp +Text Notes 3800 2700 0 60 ~ 12 +in1 +Text Notes 3800 2900 0 60 ~ 12 +in2 +Text Notes 3800 3100 0 60 ~ 12 +in3 +Text Notes 3800 3300 0 60 ~ 12 +in4 +Text Notes 3800 3500 0 60 ~ 12 +in5 +Text Notes 6150 3150 0 60 ~ 12 +out +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/5_and.sub b/library/SubcircuitLibrary/SN74351/5_and.sub new file mode 100644 index 00000000..35b10e17 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and.sub @@ -0,0 +1,16 @@ +* Subcircuit 5_and +.subckt 5_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ +* c:\users\malli\esim\src\subcircuitlibrary\5_and\5_and.cir +.include 3_and.sub +x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u3-pad1_ 3_and +* u2 net-_u1-pad4_ net-_u1-pad5_ net-_u2-pad3_ d_and +* u3 net-_u3-pad1_ net-_u2-pad3_ net-_u1-pad6_ d_and +a1 [net-_u1-pad4_ net-_u1-pad5_ ] net-_u2-pad3_ u2 +a2 [net-_u3-pad1_ net-_u2-pad3_ ] net-_u1-pad6_ u3 +* Schematic Name: d_and, NgSpice Name: d_and +.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends 5_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml new file mode 100644 index 00000000..ae2c08a7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/5_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351-cache.lib b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib new file mode 100644 index 00000000..212e1ab7 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351-cache.lib @@ -0,0 +1,114 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir b/library/SubcircuitLibrary/SN74351/SN74351.cir new file mode 100644 index 00000000..f13d0354 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir @@ -0,0 +1,49 @@ +* C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\SN74351\SN74351.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 02/05/25 22:36:17 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U1-Pad6_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad1_ 5_and +X2 Net-_U1-Pad7_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U6-Pad2_ 5_and +X3 Net-_U1-Pad8_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad1_ 5_and +X4 Net-_U1-Pad9_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U4-Pad2_ Net-_U20-Pad1_ Net-_U7-Pad2_ 5_and +X5 Net-_U1-Pad14_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad1_ 5_and +X6 Net-_U1-Pad13_ Net-_U1-Pad3_ Net-_U3-Pad2_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U9-Pad2_ 5_and +X7 Net-_U1-Pad12_ Net-_U2-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad1_ 5_and +X8 Net-_U1-Pad11_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U20-Pad1_ Net-_U11-Pad2_ 5_and +X9 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad11_ Net-_U8-Pad1_ 5_and +X10 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U2-Pad2_ Net-_U1-Pad12_ Net-_U8-Pad2_ 5_and +X11 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad13_ Net-_U10-Pad1_ 5_and +X12 Net-_U20-Pad1_ Net-_U1-Pad5_ Net-_U3-Pad2_ Net-_U2-Pad2_ Net-_U1-Pad14_ Net-_U10-Pad2_ 5_and +X13 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad3_ Net-_U1-Pad15_ Net-_U12-Pad1_ 5_and +X14 Net-_U20-Pad1_ Net-_U2-Pad2_ Net-_U4-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad16_ Net-_U12-Pad2_ 5_and +X15 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad17_ Net-_U13-Pad1_ 5_and +X16 Net-_U20-Pad1_ Net-_U4-Pad2_ Net-_U2-Pad2_ Net-_U3-Pad2_ Net-_U1-Pad18_ Net-_U13-Pad2_ 5_and +U5 Net-_U1-Pad2_ Net-_U20-Pad1_ d_inverter +U2 Net-_U1-Pad3_ Net-_U2-Pad2_ d_inverter +U3 Net-_U1-Pad4_ Net-_U3-Pad2_ d_inverter +U4 Net-_U1-Pad5_ Net-_U4-Pad2_ d_inverter +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT +U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U1-Pad1_ d_and +U21 Net-_U20-Pad1_ Net-_U21-Pad2_ Net-_U1-Pad19_ d_and +U18 Net-_U14-Pad3_ Net-_U16-Pad3_ Net-_U18-Pad3_ d_or +U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U14-Pad3_ d_or +U16 Net-_U16-Pad1_ Net-_U11-Pad3_ Net-_U16-Pad3_ d_or +U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or +U9 Net-_U9-Pad1_ Net-_U9-Pad2_ Net-_U16-Pad1_ d_or +U7 Net-_U7-Pad1_ Net-_U7-Pad2_ Net-_U14-Pad2_ d_or +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U14-Pad1_ d_or +U19 Net-_U15-Pad3_ Net-_U17-Pad3_ Net-_U19-Pad3_ d_or +U17 Net-_U12-Pad3_ Net-_U13-Pad3_ Net-_U17-Pad3_ d_or +U15 Net-_U15-Pad1_ Net-_U10-Pad3_ Net-_U15-Pad3_ d_or +U8 Net-_U8-Pad1_ Net-_U8-Pad2_ Net-_U15-Pad1_ d_or +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_or +U13 Net-_U13-Pad1_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or +U22 Net-_U18-Pad3_ Net-_U20-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U21-Pad2_ d_inverter + +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.cir.out b/library/SubcircuitLibrary/SN74351/SN74351.cir.out new file mode 100644 index 00000000..07b597bb --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.cir.out @@ -0,0 +1,117 @@ +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir + +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/SN74351/SN74351.pro b/library/SubcircuitLibrary/SN74351/SN74351.pro new file mode 100644 index 00000000..f63b751e --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.pro @@ -0,0 +1,69 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sch b/library/SubcircuitLibrary/SN74351/SN74351.sch new file mode 100644 index 00000000..1d50e5b0 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sch @@ -0,0 +1,1192 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:SN74351-cache +EELAYER 25 0 +EELAYER END +$Descr A2 23386 16535 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" 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+$EndComp +$Comp +L PORT U1 +U 6 1 67970FD6 +P 5150 2750 +F 0 "U1" H 5200 2850 30 0000 C CNN +F 1 "PORT" H 5150 2750 30 0000 C CNN +F 2 "" H 5150 2750 60 0000 C CNN +F 3 "" H 5150 2750 60 0000 C CNN + 6 5150 2750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 679711F9 +P 5150 3450 +F 0 "U1" H 5200 3550 30 0000 C CNN +F 1 "PORT" H 5150 3450 30 0000 C CNN +F 2 "" H 5150 3450 60 0000 C CNN +F 3 "" H 5150 3450 60 0000 C CNN + 7 5150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 679713AA +P 5150 4150 +F 0 "U1" H 5200 4250 30 0000 C CNN +F 1 "PORT" H 5150 4150 30 0000 C CNN +F 2 "" H 5150 4150 60 0000 C CNN +F 3 "" H 5150 4150 60 0000 C CNN + 8 5150 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 679714E7 +P 5200 4850 +F 0 "U1" H 5250 4950 30 0000 C CNN +F 1 "PORT" H 5200 4850 30 0000 C CNN +F 2 "" H 5200 4850 60 0000 C CNN +F 3 "" H 5200 4850 60 0000 C CNN + 9 5200 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67971606 +P 5250 5550 +F 0 "U1" H 5300 5650 30 0000 C CNN +F 1 "PORT" H 5250 5550 30 0000 C CNN +F 2 "" H 5250 5550 60 0000 C CNN +F 3 "" H 5250 5550 60 0000 C CNN + 14 5250 5550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67971753 +P 5200 6250 +F 0 "U1" H 5250 6350 30 0000 C CNN +F 1 "PORT" H 5200 6250 30 0000 C CNN +F 2 "" H 5200 6250 60 0000 C CNN +F 3 "" H 5200 6250 60 0000 C CNN + 13 5200 6250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6797187A +P 5200 6950 +F 0 "U1" H 5250 7050 30 0000 C CNN +F 1 "PORT" H 5200 6950 30 0000 C CNN +F 2 "" H 5200 6950 60 0000 C CNN +F 3 "" H 5200 6950 60 0000 C CNN + 12 5200 6950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 679719A5 +P 5200 7650 +F 0 "U1" H 5250 7750 30 0000 C CNN +F 1 "PORT" H 5200 7650 30 0000 C CNN +F 2 "" H 5200 7650 60 0000 C CNN +F 3 "" H 5200 7650 60 0000 C CNN + 11 5200 7650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67971B42 +P 3450 8550 +F 0 "U1" H 3500 8650 30 0000 C CNN +F 1 "PORT" H 3450 8550 30 0000 C CNN +F 2 "" H 3450 8550 60 0000 C CNN +F 3 "" H 3450 8550 60 0000 C CNN + 3 3450 8550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67971C7F +P 3450 9000 +F 0 "U1" H 3500 9100 30 0000 C CNN +F 1 "PORT" H 3450 9000 30 0000 C CNN +F 2 "" H 3450 9000 60 0000 C CNN +F 3 "" H 3450 9000 60 0000 C CNN + 4 3450 9000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 67971DF1 +P 3450 9450 +F 0 "U1" H 3500 9550 30 0000 C CNN +F 1 "PORT" H 3450 9450 30 0000 C CNN +F 2 "" H 3450 9450 60 0000 C CNN +F 3 "" H 3450 9450 60 0000 C CNN + 5 3450 9450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 6797215C +P 5150 12650 +F 0 "U1" H 5200 12750 30 0000 C CNN +F 1 "PORT" H 5150 12650 30 0000 C CNN +F 2 "" H 5150 12650 60 0000 C CNN +F 3 "" H 5150 12650 60 0000 C CNN + 15 5150 12650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 679721E9 +P 5250 13350 +F 0 "U1" H 5300 13450 30 0000 C CNN +F 1 "PORT" H 5250 13350 30 0000 C CNN +F 2 "" H 5250 13350 60 0000 C CNN +F 3 "" H 5250 13350 60 0000 C CNN + 16 5250 13350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 17 1 679723A6 +P 5150 14050 +F 0 "U1" H 5200 14150 30 0000 C CNN +F 1 "PORT" H 5150 14050 30 0000 C CNN +F 2 "" H 5150 14050 60 0000 C CNN +F 3 "" H 5150 14050 60 0000 C CNN + 17 5150 14050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 18 1 679724FF +P 5050 14750 +F 0 "U1" H 5100 14850 30 0000 C CNN +F 1 "PORT" H 5050 14750 30 0000 C CNN +F 2 "" H 5050 14750 60 0000 C CNN +F 3 "" H 5050 14750 60 0000 C CNN + 18 5050 14750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6797287E +P 19250 7400 +F 0 "U1" H 19300 7500 30 0000 C CNN +F 1 "PORT" H 19250 7400 30 0000 C CNN +F 2 "" H 19250 7400 60 0000 C CNN +F 3 "" H 19250 7400 60 0000 C CNN + 10 19250 7400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 20 1 67972905 +P 19250 7600 +F 0 "U1" H 19300 7700 30 0000 C CNN +F 1 "PORT" H 19250 7600 30 0000 C CNN +F 2 "" H 19250 7600 60 0000 C CNN +F 3 "" H 19250 7600 60 0000 C CNN + 20 19250 7600 + 1 0 0 -1 +$EndComp +NoConn ~ 19500 7400 +NoConn ~ 19500 7600 +Wire Wire Line + 6000 1600 6400 1600 +$Comp +L d_and U20 +U 1 1 67960926 +P 18400 5400 +F 0 "U20" H 18400 5400 60 0000 C CNN +F 1 "d_and" H 18450 5500 60 0000 C CNN +F 2 "" H 18400 5400 60 0000 C CNN +F 3 "" H 18400 5400 60 0000 C CNN + 1 18400 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_and U21 +U 1 1 67961044 +P 18650 12100 +F 0 "U21" H 18650 12100 60 0000 C CNN +F 1 "d_and" H 18700 12200 60 0000 C CNN +F 2 "" H 18650 12100 60 0000 C CNN +F 3 "" H 18650 12100 60 0000 C CNN + 1 18650 12100 + 1 0 0 -1 +$EndComp +$Comp +L d_or U18 +U 1 1 67A37DDA +P 17200 5450 +F 0 "U18" H 17200 5450 60 0000 C CNN +F 1 "d_or" H 17200 5550 60 0000 C CNN +F 2 "" H 17200 5450 60 0000 C CNN +F 3 "" H 17200 5450 60 0000 C CNN + 1 17200 5450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U14 +U 1 1 67A37FBD +P 16050 4050 +F 0 "U14" H 16050 4050 60 0000 C CNN +F 1 "d_or" H 16050 4150 60 0000 C CNN +F 2 "" H 16050 4050 60 0000 C CNN +F 3 "" H 16050 4050 60 0000 C CNN + 1 16050 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U16 +U 1 1 67A380A2 +P 16150 6800 +F 0 "U16" H 16150 6800 60 0000 C CNN +F 1 "d_or" H 16150 6900 60 0000 C CNN +F 2 "" H 16150 6800 60 0000 C CNN +F 3 "" H 16150 6800 60 0000 C CNN + 1 16150 6800 + 1 0 0 -1 +$EndComp +$Comp +L d_or U11 +U 1 1 67A38127 +P 14700 7600 +F 0 "U11" H 14700 7600 60 0000 C CNN +F 1 "d_or" H 14700 7700 60 0000 C CNN +F 2 "" H 14700 7600 60 0000 C CNN +F 3 "" H 14700 7600 60 0000 C CNN + 1 14700 7600 + 1 0 0 -1 +$EndComp +$Comp +L d_or U9 +U 1 1 67A381AE +P 14650 6150 +F 0 "U9" H 14650 6150 60 0000 C CNN +F 1 "d_or" H 14650 6250 60 0000 C CNN +F 2 "" H 14650 6150 60 0000 C CNN +F 3 "" H 14650 6150 60 0000 C CNN + 1 14650 6150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U7 +U 1 1 67A382B3 +P 14600 4750 +F 0 "U7" H 14600 4750 60 0000 C CNN +F 1 "d_or" H 14600 4850 60 0000 C CNN +F 2 "" H 14600 4750 60 0000 C CNN +F 3 "" H 14600 4750 60 0000 C CNN + 1 14600 4750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U6 +U 1 1 67A3833C +P 14550 3350 +F 0 "U6" H 14550 3350 60 0000 C CNN +F 1 "d_or" H 14550 3450 60 0000 C CNN +F 2 "" H 14550 3350 60 0000 C CNN +F 3 "" H 14550 3350 60 0000 C CNN + 1 14550 3350 + 1 0 0 -1 +$EndComp +$Comp +L d_or U19 +U 1 1 67A3867A +P 17250 12150 +F 0 "U19" H 17250 12150 60 0000 C CNN +F 1 "d_or" H 17250 12250 60 0000 C CNN +F 2 "" H 17250 12150 60 0000 C CNN +F 3 "" H 17250 12150 60 0000 C CNN + 1 17250 12150 + 1 0 0 -1 +$EndComp +$Comp +L d_or U17 +U 1 1 67A387A5 +P 16200 13500 +F 0 "U17" H 16200 13500 60 0000 C CNN +F 1 "d_or" H 16200 13600 60 0000 C CNN +F 2 "" H 16200 13500 60 0000 C CNN +F 3 "" H 16200 13500 60 0000 C CNN + 1 16200 13500 + 1 0 0 -1 +$EndComp +$Comp +L d_or U15 +U 1 1 67A38826 +P 16100 10750 +F 0 "U15" H 16100 10750 60 0000 C CNN +F 1 "d_or" H 16100 10850 60 0000 C CNN +F 2 "" H 16100 10750 60 0000 C CNN +F 3 "" H 16100 10750 60 0000 C CNN + 1 16100 10750 + 1 0 0 -1 +$EndComp +$Comp +L d_or U8 +U 1 1 67A38AC4 +P 14600 10050 +F 0 "U8" H 14600 10050 60 0000 C CNN +F 1 "d_or" H 14600 10150 60 0000 C CNN +F 2 "" H 14600 10050 60 0000 C CNN +F 3 "" H 14600 10050 60 0000 C CNN + 1 14600 10050 + 1 0 0 -1 +$EndComp +$Comp +L d_or U10 +U 1 1 67A38B5F +P 14650 11450 +F 0 "U10" H 14650 11450 60 0000 C CNN +F 1 "d_or" H 14650 11550 60 0000 C CNN +F 2 "" H 14650 11450 60 0000 C CNN +F 3 "" H 14650 11450 60 0000 C CNN + 1 14650 11450 + 1 0 0 -1 +$EndComp +$Comp +L d_or U12 +U 1 1 67A38CFC +P 14700 12850 +F 0 "U12" H 14700 12850 60 0000 C CNN +F 1 "d_or" H 14700 12950 60 0000 C CNN +F 2 "" H 14700 12850 60 0000 C CNN +F 3 "" H 14700 12850 60 0000 C CNN + 1 14700 12850 + 1 0 0 -1 +$EndComp +$Comp +L d_or U13 +U 1 1 67A38D7F +P 14750 14300 +F 0 "U13" H 14750 14300 60 0000 C CNN +F 1 "d_or" H 14750 14400 60 0000 C CNN +F 2 "" H 14750 14300 60 0000 C CNN +F 3 "" H 14750 14300 60 0000 C CNN + 1 14750 14300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 67A393F8 +P 17800 5950 +F 0 "U22" H 17800 5850 60 0000 C CNN +F 1 "d_inverter" H 17800 6100 60 0000 C CNN +F 2 "" H 17850 5900 60 0000 C CNN +F 3 "" H 17850 5900 60 0000 C CNN + 1 17800 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 67A39864 +P 17900 12500 +F 0 "U23" H 17900 12400 60 0000 C CNN +F 1 "d_inverter" H 17900 12650 60 0000 C CNN +F 2 "" H 17950 12450 60 0000 C CNN +F 3 "" H 17950 12450 60 0000 C CNN + 1 17900 12500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 17700 12100 17800 12100 +Wire Wire Line + 17800 12100 17800 12250 +Wire Wire Line + 17800 12250 17500 12250 +Wire Wire Line + 17500 12250 17500 12500 +Wire Wire Line + 17500 12500 17600 12500 +Wire Wire Line + 18200 12500 18250 12500 +Wire Wire Line + 18250 12500 18250 12250 +Wire Wire Line + 18250 12250 18150 12250 +Wire Wire Line + 18150 12250 18150 12100 +Wire Wire Line + 18150 12100 18200 12100 +Wire Wire Line + 17650 5400 17700 5400 +Wire Wire Line + 17700 5400 17700 5650 +Wire Wire Line + 17700 5650 17350 5650 +Wire Wire Line + 17350 5650 17350 5950 +Wire Wire Line + 17350 5950 17500 5950 +Wire Wire Line + 18100 5950 18200 5950 +Wire Wire Line + 18200 5950 18200 5650 +Wire Wire Line + 18200 5650 17800 5650 +Wire Wire Line + 17800 5650 17800 5400 +Wire Wire Line + 17800 5400 17950 5400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/SN74351/SN74351.sub b/library/SubcircuitLibrary/SN74351/SN74351.sub new file mode 100644 index 00000000..87054221 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351.sub @@ -0,0 +1,111 @@ +* Subcircuit SN74351 +.subckt SN74351 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? +* c:\fossee_mains\fossee\esim\library\subcircuitlibrary\sn74351\sn74351.cir +.include 5_and.sub +x1 net-_u1-pad6_ net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad1_ 5_and +x2 net-_u1-pad7_ net-_u1-pad3_ net-_u3-pad2_ net-_u4-pad2_ net-_u20-pad1_ net-_u6-pad2_ 5_and +x3 net-_u1-pad8_ net-_u2-pad2_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad1_ 5_and +x4 net-_u1-pad9_ net-_u1-pad3_ net-_u1-pad4_ net-_u4-pad2_ net-_u20-pad1_ net-_u7-pad2_ 5_and +x5 net-_u1-pad14_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad1_ 5_and +x6 net-_u1-pad13_ net-_u1-pad3_ net-_u3-pad2_ net-_u1-pad5_ net-_u20-pad1_ net-_u9-pad2_ 5_and +x7 net-_u1-pad12_ net-_u2-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad1_ 5_and +x8 net-_u1-pad11_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u20-pad1_ net-_u11-pad2_ 5_and +x9 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad11_ net-_u8-pad1_ 5_and +x10 net-_u20-pad1_ net-_u1-pad5_ net-_u1-pad4_ net-_u2-pad2_ net-_u1-pad12_ net-_u8-pad2_ 5_and +x11 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad13_ net-_u10-pad1_ 5_and +x12 net-_u20-pad1_ net-_u1-pad5_ net-_u3-pad2_ net-_u2-pad2_ net-_u1-pad14_ net-_u10-pad2_ 5_and +x13 net-_u20-pad1_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad3_ net-_u1-pad15_ net-_u12-pad1_ 5_and +x14 net-_u20-pad1_ net-_u2-pad2_ net-_u4-pad2_ net-_u1-pad4_ net-_u1-pad16_ net-_u12-pad2_ 5_and +x15 net-_u20-pad1_ net-_u4-pad2_ net-_u3-pad2_ net-_u1-pad3_ net-_u1-pad17_ net-_u13-pad1_ 5_and +x16 net-_u20-pad1_ net-_u4-pad2_ net-_u2-pad2_ net-_u3-pad2_ net-_u1-pad18_ net-_u13-pad2_ 5_and +* u5 net-_u1-pad2_ net-_u20-pad1_ d_inverter +* u2 net-_u1-pad3_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad4_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad5_ net-_u4-pad2_ d_inverter +* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u1-pad1_ d_and +* u21 net-_u20-pad1_ net-_u21-pad2_ net-_u1-pad19_ d_and +* u18 net-_u14-pad3_ net-_u16-pad3_ net-_u18-pad3_ d_or +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u16 net-_u16-pad1_ net-_u11-pad3_ net-_u16-pad3_ d_or +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u9 net-_u9-pad1_ net-_u9-pad2_ net-_u16-pad1_ d_or +* u7 net-_u7-pad1_ net-_u7-pad2_ net-_u14-pad2_ d_or +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u14-pad1_ d_or +* u19 net-_u15-pad3_ net-_u17-pad3_ net-_u19-pad3_ d_or +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_or +* u15 net-_u15-pad1_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u15-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u22 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u21-pad2_ d_inverter +a1 net-_u1-pad2_ net-_u20-pad1_ u5 +a2 net-_u1-pad3_ net-_u2-pad2_ u2 +a3 net-_u1-pad4_ net-_u3-pad2_ u3 +a4 net-_u1-pad5_ net-_u4-pad2_ u4 +a5 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u1-pad1_ u20 +a6 [net-_u20-pad1_ net-_u21-pad2_ ] net-_u1-pad19_ u21 +a7 [net-_u14-pad3_ net-_u16-pad3_ ] net-_u18-pad3_ u18 +a8 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a9 [net-_u16-pad1_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a10 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a11 [net-_u9-pad1_ net-_u9-pad2_ ] net-_u16-pad1_ u9 +a12 [net-_u7-pad1_ net-_u7-pad2_ ] net-_u14-pad2_ u7 +a13 [net-_u6-pad1_ net-_u6-pad2_ ] net-_u14-pad1_ u6 +a14 [net-_u15-pad3_ net-_u17-pad3_ ] net-_u19-pad3_ u19 +a15 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a16 [net-_u15-pad1_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u8-pad1_ net-_u8-pad2_ ] net-_u15-pad1_ u8 +a18 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a19 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a20 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a21 net-_u18-pad3_ net-_u20-pad2_ u22 +a22 net-_u19-pad3_ net-_u21-pad2_ u23 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u18 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u7 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u6 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u19 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u8 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends SN74351
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml new file mode 100644 index 00000000..77e9ef56 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/SN74351_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u8 name="type">d_nor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u8><u10 name="type">d_nor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u10><u12 name="type">d_nor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u13><u15 name="type">d_nor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u15><u17 name="type">d_nor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u17><u19 name="type">d_nor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u19><u5 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u5><u2 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u4><u18 name="type">d_nor<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u18><u16 name="type">d_nor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u16><u14 name="type">d_nor<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u14><u11 name="type">d_nor<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u9 name="type">d_nor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u9><u7 name="type">d_nor<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_nor<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u6><u20 name="type">d_nor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_nor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u20 name="type">d_and<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_and<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_or<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u18><u14 name="type">d_or<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u14><u16 name="type">d_or<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u16><u11 name="type">d_or<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u11><u9 name="type">d_or<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u9><u7 name="type">d_or<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u7><u6 name="type">d_or<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u6><u19 name="type">d_or<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u19><u17 name="type">d_or<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u17><u15 name="type">d_or<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u15><u8 name="type">d_or<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u8><u10 name="type">d_or<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u10><u12 name="type">d_or<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u12><u13 name="type">d_or<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u13><u22 name="type">d_inverter<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22><u23 name="type">d_inverter<field64 name="Enter Fall Delay (default=1.0e-9)" /><field65 name="Enter Input Load (default=1.0e-12)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /></u23></model><devicemodel /><subcircuit><x5><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x5><x1><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x1><x15><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x15><x16><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x16><x6><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x6><x14><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x14><x11><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x11><x12><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x12><x2><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x2><x4><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x4><x9><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x9><x8><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x8><x13><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x13><x7><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x7><x3><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x3><x10><field>C:\FOSSEE_mains\FOSSEE\eSim\library\SubcircuitLibrary\5_and</field></x10></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN74351/analysis b/library/SubcircuitLibrary/SN74351/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN74351/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |