diff options
Diffstat (limited to 'library/SubcircuitLibrary')
8 files changed, 1760 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib new file mode 100644 index 00000000..cca13acf --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_inverter +# +DEF d_inverter U 0 40 Y Y 1 F N +F0 "U" 0 -100 60 H V C CNN +F1 "d_inverter" 0 150 60 H V C CNN +F2 "" 50 -50 60 H V C CNN +F3 "" 50 -50 60 H V C CNN +DRAW +P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N +X ~ 1 -300 0 200 R 50 50 1 1 I +X ~ 2 300 0 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_nand +# +DEF d_nand U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_nand" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir new file mode 100644 index 00000000..dc30556f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir @@ -0,0 +1,57 @@ +* D:\FOSSEE\eSim\library\SubcircuitLibrary\CD4556BMS_IC\CD4556BMS_IC.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/19/24 15:55:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U3 Net-_U2-Pad4_ Net-_U10-Pad1_ d_inverter +U4 Net-_U2-Pad5_ Net-_U4-Pad2_ d_inverter +U5 Net-_U2-Pad6_ Net-_U16-Pad2_ d_inverter +U6 Net-_U10-Pad1_ Net-_U11-Pad1_ d_inverter +U7 Net-_U4-Pad2_ Net-_U10-Pad2_ d_inverter +U8 Net-_U10-Pad1_ Net-_U4-Pad2_ Net-_U12-Pad1_ d_nand +U12 Net-_U12-Pad1_ Net-_U12-Pad1_ Net-_U12-Pad3_ d_nand +U16 Net-_U12-Pad3_ Net-_U16-Pad2_ Net-_U16-Pad3_ d_nand +U9 Net-_U11-Pad1_ Net-_U4-Pad2_ Net-_U13-Pad1_ d_nand +U13 Net-_U13-Pad1_ Net-_U13-Pad1_ Net-_U13-Pad3_ d_nand +U17 Net-_U13-Pad3_ Net-_U16-Pad2_ Net-_U17-Pad3_ d_nand +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nand +U14 Net-_U10-Pad3_ Net-_U10-Pad3_ Net-_U14-Pad3_ d_nand +U18 Net-_U14-Pad3_ Net-_U16-Pad2_ Net-_U18-Pad3_ d_nand +U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nand +U15 Net-_U11-Pad3_ Net-_U11-Pad3_ Net-_U15-Pad3_ d_nand +U19 Net-_U15-Pad3_ Net-_U16-Pad2_ Net-_U19-Pad3_ d_nand +U20 Net-_U16-Pad3_ Net-_U20-Pad2_ d_inverter +U21 Net-_U17-Pad3_ Net-_U21-Pad2_ d_inverter +U22 Net-_U18-Pad3_ Net-_U22-Pad2_ d_inverter +U23 Net-_U19-Pad3_ Net-_U23-Pad2_ d_inverter +U2 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ adc_bridge_3 +U24 Net-_U20-Pad2_ Net-_U21-Pad2_ Net-_U22-Pad2_ Net-_U23-Pad2_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ dac_bridge_4 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ PORT +U26 Net-_U25-Pad4_ Net-_U26-Pad2_ d_inverter +U27 Net-_U25-Pad5_ Net-_U27-Pad2_ d_inverter +U28 Net-_U25-Pad6_ Net-_U28-Pad2_ d_inverter +U29 Net-_U26-Pad2_ Net-_U29-Pad2_ d_inverter +U30 Net-_U27-Pad2_ Net-_U30-Pad2_ d_inverter +U31 Net-_U26-Pad2_ Net-_U27-Pad2_ Net-_U31-Pad3_ d_nand +U35 Net-_U31-Pad3_ Net-_U31-Pad3_ Net-_U35-Pad3_ d_nand +U39 Net-_U35-Pad3_ Net-_U28-Pad2_ Net-_U39-Pad3_ d_nand +U32 Net-_U29-Pad2_ Net-_U27-Pad2_ Net-_U32-Pad3_ d_nand +U36 Net-_U32-Pad3_ Net-_U32-Pad3_ Net-_U36-Pad3_ d_nand +U40 Net-_U36-Pad3_ Net-_U28-Pad2_ Net-_U40-Pad3_ d_nand +U33 Net-_U26-Pad2_ Net-_U30-Pad2_ Net-_U33-Pad3_ d_nand +U37 Net-_U33-Pad3_ Net-_U33-Pad3_ Net-_U37-Pad3_ d_nand +U41 Net-_U37-Pad3_ Net-_U28-Pad2_ Net-_U41-Pad3_ d_nand +U34 Net-_U29-Pad2_ Net-_U30-Pad2_ Net-_U34-Pad3_ d_nand +U38 Net-_U34-Pad3_ Net-_U34-Pad3_ Net-_U38-Pad3_ d_nand +U42 Net-_U38-Pad3_ Net-_U28-Pad2_ Net-_U42-Pad3_ d_nand +U43 Net-_U39-Pad3_ Net-_U43-Pad2_ d_inverter +U44 Net-_U40-Pad3_ Net-_U44-Pad2_ d_inverter +U45 Net-_U41-Pad3_ Net-_U45-Pad2_ d_inverter +U46 Net-_U42-Pad3_ Net-_U46-Pad2_ d_inverter +U25 Net-_U1-Pad13_ Net-_U1-Pad12_ Net-_U1-Pad14_ Net-_U25-Pad4_ Net-_U25-Pad5_ Net-_U25-Pad6_ adc_bridge_3 +U47 Net-_U43-Pad2_ Net-_U44-Pad2_ Net-_U45-Pad2_ Net-_U46-Pad2_ Net-_U1-Pad11_ Net-_U1-Pad10_ Net-_U1-Pad9_ Net-_U1-Pad8_ dac_bridge_4 + +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out new file mode 100644 index 00000000..d1117c7b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.cir.out @@ -0,0 +1,196 @@ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir + +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0.01e-03 100e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch new file mode 100644 index 00000000..7cdf8bf2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sch @@ -0,0 +1,1129 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:CD4556BMS-cache +EELAYER 25 0 +EELAYER END +$Descr User 27559 19685 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_inverter U3 +U 1 1 6672B0FB +P 4050 4000 +F 0 "U3" H 4050 3900 60 0000 C CNN +F 1 "d_inverter" H 4050 4150 60 0000 C CNN +F 2 "" H 4100 3950 60 0000 C CNN +F 3 "" H 4100 3950 60 0000 C CNN + 1 4050 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U4 +U 1 1 6672B0FC +P 4050 4650 +F 0 "U4" H 4050 4550 60 0000 C CNN +F 1 "d_inverter" H 4050 4800 60 0000 C CNN +F 2 "" H 4100 4600 60 0000 C CNN +F 3 "" H 4100 4600 60 0000 C CNN + 1 4050 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U5 +U 1 1 6672B0FD +P 4050 6450 +F 0 "U5" H 4050 6350 60 0000 C CNN +F 1 "d_inverter" H 4050 6600 60 0000 C CNN +F 2 "" H 4100 6400 60 0000 C CNN +F 3 "" H 4100 6400 60 0000 C CNN + 1 4050 6450 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U6 +U 1 1 6672B0FE +P 5000 4000 +F 0 "U6" H 5000 3900 60 0000 C CNN +F 1 "d_inverter" H 5000 4150 60 0000 C CNN +F 2 "" H 5050 3950 60 0000 C CNN +F 3 "" H 5050 3950 60 0000 C CNN + 1 5000 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U7 +U 1 1 6672B0FF +P 5050 4650 +F 0 "U7" H 5050 4550 60 0000 C CNN +F 1 "d_inverter" H 5050 4800 60 0000 C CNN +F 2 "" H 5100 4600 60 0000 C CNN +F 3 "" H 5100 4600 60 0000 C CNN + 1 5050 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4350 4000 4700 4000 +Wire Wire Line + 4350 4650 4750 4650 +$Comp +L d_nand U8 +U 1 1 6672B100 +P 6600 4050 +F 0 "U8" H 6600 4050 60 0000 C CNN +F 1 "d_nand" H 6650 4150 60 0000 C CNN +F 2 "" H 6600 4050 60 0000 C CNN +F 3 "" H 6600 4050 60 0000 C CNN + 1 6600 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U12 +U 1 1 6672B101 +P 7800 4050 +F 0 "U12" H 7800 4050 60 0000 C CNN +F 1 "d_nand" H 7850 4150 60 0000 C CNN +F 2 "" H 7800 4050 60 0000 C CNN +F 3 "" H 7800 4050 60 0000 C CNN + 1 7800 4050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U16 +U 1 1 6672B102 +P 9000 4150 +F 0 "U16" H 9000 4150 60 0000 C CNN +F 1 "d_nand" H 9050 4250 60 0000 C CNN +F 2 "" H 9000 4150 60 0000 C CNN +F 3 "" H 9000 4150 60 0000 C CNN + 1 9000 4150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 4050 8500 4050 +Wire Wire Line + 8500 4050 8500 4000 +Wire Wire Line + 8500 4000 8250 4000 +Wire Wire Line + 7350 3950 7250 3950 +Wire Wire Line + 7250 3950 7250 4050 +Wire Wire Line + 7250 4050 7350 4050 +Wire Wire Line + 7050 4000 7250 4000 +Connection ~ 7250 4000 +$Comp +L d_nand U9 +U 1 1 6672B103 +P 6600 4650 +F 0 "U9" H 6600 4650 60 0000 C CNN +F 1 "d_nand" H 6650 4750 60 0000 C CNN +F 2 "" H 6600 4650 60 0000 C CNN +F 3 "" H 6600 4650 60 0000 C CNN + 1 6600 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U13 +U 1 1 6672B104 +P 7800 4650 +F 0 "U13" H 7800 4650 60 0000 C CNN +F 1 "d_nand" H 7850 4750 60 0000 C CNN +F 2 "" H 7800 4650 60 0000 C CNN +F 3 "" H 7800 4650 60 0000 C CNN + 1 7800 4650 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U17 +U 1 1 6672B105 +P 9000 4750 +F 0 "U17" H 9000 4750 60 0000 C CNN +F 1 "d_nand" H 9050 4850 60 0000 C CNN +F 2 "" H 9000 4750 60 0000 C CNN +F 3 "" H 9000 4750 60 0000 C CNN + 1 9000 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 4650 8500 4650 +Wire Wire Line + 8500 4650 8500 4600 +Wire Wire Line + 8500 4600 8250 4600 +Wire Wire Line + 7350 4550 7250 4550 +Wire Wire Line + 7250 4550 7250 4650 +Wire Wire Line + 7250 4650 7350 4650 +Wire Wire Line + 7050 4600 7250 4600 +Connection ~ 7250 4600 +$Comp +L d_nand U10 +U 1 1 6672B106 +P 6600 5350 +F 0 "U10" H 6600 5350 60 0000 C CNN +F 1 "d_nand" H 6650 5450 60 0000 C CNN +F 2 "" H 6600 5350 60 0000 C CNN +F 3 "" H 6600 5350 60 0000 C CNN + 1 6600 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U14 +U 1 1 6672B107 +P 7800 5350 +F 0 "U14" H 7800 5350 60 0000 C CNN +F 1 "d_nand" H 7850 5450 60 0000 C CNN +F 2 "" H 7800 5350 60 0000 C CNN +F 3 "" H 7800 5350 60 0000 C CNN + 1 7800 5350 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U18 +U 1 1 6672B108 +P 9000 5450 +F 0 "U18" H 9000 5450 60 0000 C CNN +F 1 "d_nand" H 9050 5550 60 0000 C CNN +F 2 "" H 9000 5450 60 0000 C CNN +F 3 "" H 9000 5450 60 0000 C CNN + 1 9000 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 5350 8500 5350 +Wire Wire Line + 8500 5350 8500 5300 +Wire Wire Line + 8500 5300 8250 5300 +Wire Wire Line + 7350 5250 7250 5250 +Wire Wire Line + 7250 5250 7250 5350 +Wire Wire Line + 7250 5350 7350 5350 +Wire Wire Line + 7050 5300 7250 5300 +Connection ~ 7250 5300 +$Comp +L d_nand U11 +U 1 1 6672B109 +P 6600 6050 +F 0 "U11" H 6600 6050 60 0000 C CNN +F 1 "d_nand" H 6650 6150 60 0000 C CNN +F 2 "" H 6600 6050 60 0000 C CNN +F 3 "" H 6600 6050 60 0000 C CNN + 1 6600 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U15 +U 1 1 6672B10A +P 7800 6050 +F 0 "U15" H 7800 6050 60 0000 C CNN +F 1 "d_nand" H 7850 6150 60 0000 C CNN +F 2 "" H 7800 6050 60 0000 C CNN +F 3 "" H 7800 6050 60 0000 C CNN + 1 7800 6050 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U19 +U 1 1 6672B10B +P 9000 6150 +F 0 "U19" H 9000 6150 60 0000 C CNN +F 1 "d_nand" H 9050 6250 60 0000 C CNN +F 2 "" H 9000 6150 60 0000 C CNN +F 3 "" H 9000 6150 60 0000 C CNN + 1 9000 6150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8550 6050 8500 6050 +Wire Wire Line + 8500 6050 8500 6000 +Wire Wire Line + 8500 6000 8250 6000 +Wire Wire Line + 7350 5950 7250 5950 +Wire Wire Line + 7250 5950 7250 6050 +Wire Wire Line + 7250 6050 7350 6050 +Wire Wire Line + 7050 6000 7250 6000 +Connection ~ 7250 6000 +Wire Wire Line + 6150 3950 5900 3950 +Wire Wire Line + 5900 3950 5900 3800 +Wire Wire Line + 5900 3800 4500 3800 +Wire Wire Line + 4500 3800 4500 4000 +Connection ~ 4500 4000 +Wire Wire Line + 5300 4000 5650 4000 +Wire Wire Line + 5650 4000 5650 5950 +Wire Wire Line + 5650 5950 6150 5950 +Wire Wire Line + 5350 4650 5800 4650 +Wire Wire Line + 5800 4650 5800 6050 +Wire Wire Line + 5800 6050 6150 6050 +Wire Wire Line + 8550 6150 8200 6150 +Wire Wire Line + 8200 6150 8200 6450 +Wire Wire Line + 8200 6450 4350 6450 +Wire Wire Line + 8550 4150 6000 4150 +Wire Wire Line + 6000 4150 6000 6450 +Connection ~ 6000 6450 +Wire Wire Line + 8550 5450 6000 5450 +Connection ~ 6000 5450 +Wire Wire Line + 8550 4750 6000 4750 +Connection ~ 6000 4750 +Wire Wire Line + 6150 4650 5900 4650 +Wire Wire Line + 5900 4650 5900 4350 +Wire Wire Line + 5900 4350 4550 4350 +Wire Wire Line + 4550 4350 4550 4650 +Connection ~ 4550 4650 +Wire Wire Line + 6150 4550 5650 4550 +Connection ~ 5650 4550 +Wire Wire Line + 6150 5250 5950 5250 +Wire Wire Line + 5950 5250 5950 3950 +Connection ~ 5950 3950 +Wire Wire Line + 6150 4050 5750 4050 +Wire Wire Line + 5750 4050 5750 4350 +Connection ~ 5750 4350 +Wire Wire Line + 6150 5350 5800 5350 +Connection ~ 5800 5350 +$Comp +L d_inverter U20 +U 1 1 6672B10C +P 10050 4100 +F 0 "U20" H 10050 4000 60 0000 C CNN +F 1 "d_inverter" H 10050 4250 60 0000 C CNN +F 2 "" H 10100 4050 60 0000 C CNN +F 3 "" H 10100 4050 60 0000 C CNN + 1 10050 4100 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U21 +U 1 1 6672B10D +P 10050 4700 +F 0 "U21" H 10050 4600 60 0000 C CNN +F 1 "d_inverter" H 10050 4850 60 0000 C CNN +F 2 "" H 10100 4650 60 0000 C CNN +F 3 "" H 10100 4650 60 0000 C CNN + 1 10050 4700 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U22 +U 1 1 6672B10E +P 10050 5400 +F 0 "U22" H 10050 5300 60 0000 C CNN +F 1 "d_inverter" H 10050 5550 60 0000 C CNN +F 2 "" H 10100 5350 60 0000 C CNN +F 3 "" H 10100 5350 60 0000 C CNN + 1 10050 5400 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U23 +U 1 1 6672B10F +P 10050 6100 +F 0 "U23" H 10050 6000 60 0000 C CNN +F 1 "d_inverter" H 10050 6250 60 0000 C CNN +F 2 "" H 10100 6050 60 0000 C CNN +F 3 "" H 10100 6050 60 0000 C CNN + 1 10050 6100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 4100 9750 4100 +Wire Wire Line + 9450 4700 9750 4700 +Wire Wire Line + 9450 5400 9750 5400 +Wire Wire Line + 9450 6100 9750 6100 +$Comp +L adc_bridge_3 U2 +U 1 1 6672B110 +P 2300 4950 +F 0 "U2" H 2300 4950 60 0000 C CNN +F 1 "adc_bridge_3" H 2300 5100 60 0000 C CNN +F 2 "" H 2300 4950 60 0000 C CNN +F 3 "" H 2300 4950 60 0000 C CNN + 1 2300 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2850 4900 3100 4900 +Wire Wire Line + 3100 4900 3100 4000 +Wire Wire Line + 3100 4000 3750 4000 +Wire Wire Line + 2850 5000 3400 5000 +Wire Wire Line + 3400 5000 3400 4650 +Wire Wire Line + 3400 4650 3750 4650 +Wire Wire Line + 2850 5100 3400 5100 +Wire Wire Line + 3400 5100 3400 6450 +Wire Wire Line + 3400 6450 3750 6450 +$Comp +L dac_bridge_4 U24 +U 1 1 6672B11A +P 11650 5050 +F 0 "U24" H 11650 5050 60 0000 C CNN +F 1 "dac_bridge_4" H 11650 5350 60 0000 C CNN +F 2 "" H 11650 5050 60 0000 C CNN +F 3 "" H 11650 5050 60 0000 C CNN + 1 11650 5050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10350 4100 10900 4100 +Wire Wire Line + 10900 4100 10900 4850 +Wire Wire Line + 10900 4850 11100 4850 +Wire Wire Line + 10350 4700 10800 4700 +Wire Wire Line + 10800 4700 10800 4950 +Wire Wire Line + 10800 4950 11100 4950 +Wire Wire Line + 10350 5400 10800 5400 +Wire Wire Line + 10800 5400 10800 5050 +Wire Wire Line + 10800 5050 11100 5050 +Wire Wire Line + 10350 6100 10950 6100 +Wire Wire Line + 10950 6100 10950 5150 +Wire Wire Line + 10950 5150 11100 5150 +$Comp +L PORT U1 +U 3 1 6672B58A +P 1250 5000 +F 0 "U1" H 1300 5100 30 0000 C CNN +F 1 "PORT" H 1250 5000 30 0000 C CNN +F 2 "" H 1250 5000 60 0000 C CNN +F 3 "" H 1250 5000 60 0000 C CNN + 3 1250 5000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6672B61B +P 1250 5200 +F 0 "U1" H 1300 5300 30 0000 C CNN +F 1 "PORT" H 1250 5200 30 0000 C CNN +F 2 "" H 1250 5200 60 0000 C CNN +F 3 "" H 1250 5200 60 0000 C CNN + 1 1250 5200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6672B6A8 +P 1200 4800 +F 0 "U1" H 1250 4900 30 0000 C CNN +F 1 "PORT" H 1200 4800 30 0000 C CNN +F 2 "" H 1200 4800 60 0000 C CNN +F 3 "" H 1200 4800 60 0000 C CNN + 2 1200 4800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1500 5200 1600 5200 +Wire Wire Line + 1600 5200 1600 5100 +Wire Wire Line + 1600 5100 1700 5100 +Wire Wire Line + 1450 4800 1550 4800 +Wire Wire Line + 1550 4800 1550 4900 +Wire Wire Line + 1550 4900 1700 4900 +Wire Wire Line + 1500 5000 1700 5000 +$Comp +L PORT U1 +U 4 1 6672BC97 +P 12750 4750 +F 0 "U1" H 12800 4850 30 0000 C CNN +F 1 "PORT" H 12750 4750 30 0000 C CNN +F 2 "" H 12750 4750 60 0000 C CNN +F 3 "" H 12750 4750 60 0000 C CNN + 4 12750 4750 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 6672BD04 +P 12800 4950 +F 0 "U1" H 12850 5050 30 0000 C CNN +F 1 "PORT" H 12800 4950 30 0000 C CNN +F 2 "" H 12800 4950 60 0000 C CNN +F 3 "" H 12800 4950 60 0000 C CNN + 5 12800 4950 + -1 0 0 1 +$EndComp +Wire Wire Line + 12500 4750 12300 4750 +Wire Wire Line + 12300 4750 12300 4850 +Wire Wire Line + 12300 4850 12200 4850 +Wire Wire Line + 12550 4950 12200 4950 +$Comp +L PORT U1 +U 6 1 6672BE8F +P 12800 5100 +F 0 "U1" H 12850 5200 30 0000 C CNN +F 1 "PORT" H 12800 5100 30 0000 C CNN +F 2 "" H 12800 5100 60 0000 C CNN +F 3 "" H 12800 5100 60 0000 C CNN + 6 12800 5100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 6672BF35 +P 12850 5350 +F 0 "U1" H 12900 5450 30 0000 C CNN +F 1 "PORT" H 12850 5350 30 0000 C CNN +F 2 "" H 12850 5350 60 0000 C CNN +F 3 "" H 12850 5350 60 0000 C CNN + 7 12850 5350 + -1 0 0 1 +$EndComp +Wire Wire Line + 12550 5100 12200 5100 +Wire Wire Line + 12200 5100 12200 5050 +Wire Wire Line + 12600 5350 12200 5350 +Wire Wire Line + 12200 5350 12200 5150 +$Comp +L d_inverter U26 +U 1 1 6672C760 +P 16150 3900 +F 0 "U26" H 16150 3800 60 0000 C CNN +F 1 "d_inverter" H 16150 4050 60 0000 C CNN +F 2 "" H 16200 3850 60 0000 C CNN +F 3 "" H 16200 3850 60 0000 C CNN + 1 16150 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U27 +U 1 1 6672C766 +P 16150 4550 +F 0 "U27" H 16150 4450 60 0000 C CNN +F 1 "d_inverter" H 16150 4700 60 0000 C CNN +F 2 "" H 16200 4500 60 0000 C CNN +F 3 "" H 16200 4500 60 0000 C CNN + 1 16150 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U28 +U 1 1 6672C76C +P 16150 6350 +F 0 "U28" H 16150 6250 60 0000 C CNN +F 1 "d_inverter" H 16150 6500 60 0000 C CNN +F 2 "" H 16200 6300 60 0000 C CNN +F 3 "" H 16200 6300 60 0000 C CNN + 1 16150 6350 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U29 +U 1 1 6672C772 +P 17100 3900 +F 0 "U29" H 17100 3800 60 0000 C CNN +F 1 "d_inverter" H 17100 4050 60 0000 C CNN +F 2 "" H 17150 3850 60 0000 C CNN +F 3 "" H 17150 3850 60 0000 C CNN + 1 17100 3900 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U30 +U 1 1 6672C778 +P 17150 4550 +F 0 "U30" H 17150 4450 60 0000 C CNN +F 1 "d_inverter" H 17150 4700 60 0000 C CNN +F 2 "" H 17200 4500 60 0000 C CNN +F 3 "" H 17200 4500 60 0000 C CNN + 1 17150 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 16450 3900 16800 3900 +Wire Wire Line + 16450 4550 16850 4550 +$Comp +L d_nand U31 +U 1 1 6672C780 +P 18700 3950 +F 0 "U31" H 18700 3950 60 0000 C CNN +F 1 "d_nand" H 18750 4050 60 0000 C CNN +F 2 "" H 18700 3950 60 0000 C CNN +F 3 "" H 18700 3950 60 0000 C CNN + 1 18700 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U35 +U 1 1 6672C786 +P 19900 3950 +F 0 "U35" H 19900 3950 60 0000 C CNN +F 1 "d_nand" H 19950 4050 60 0000 C CNN +F 2 "" H 19900 3950 60 0000 C CNN +F 3 "" H 19900 3950 60 0000 C CNN + 1 19900 3950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U39 +U 1 1 6672C78C +P 21100 4050 +F 0 "U39" H 21100 4050 60 0000 C CNN +F 1 "d_nand" H 21150 4150 60 0000 C CNN +F 2 "" H 21100 4050 60 0000 C CNN +F 3 "" H 21100 4050 60 0000 C CNN + 1 21100 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 3950 20600 3950 +Wire Wire Line + 20600 3950 20600 3900 +Wire Wire Line + 20600 3900 20350 3900 +Wire Wire Line + 19450 3850 19350 3850 +Wire Wire Line + 19350 3850 19350 3950 +Wire Wire Line + 19350 3950 19450 3950 +Wire Wire Line + 19150 3900 19350 3900 +Connection ~ 19350 3900 +$Comp +L d_nand U32 +U 1 1 6672C79A +P 18700 4550 +F 0 "U32" H 18700 4550 60 0000 C CNN +F 1 "d_nand" H 18750 4650 60 0000 C CNN +F 2 "" H 18700 4550 60 0000 C CNN +F 3 "" H 18700 4550 60 0000 C CNN + 1 18700 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U36 +U 1 1 6672C7A0 +P 19900 4550 +F 0 "U36" H 19900 4550 60 0000 C CNN +F 1 "d_nand" H 19950 4650 60 0000 C CNN +F 2 "" H 19900 4550 60 0000 C CNN +F 3 "" H 19900 4550 60 0000 C CNN + 1 19900 4550 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U40 +U 1 1 6672C7A6 +P 21100 4650 +F 0 "U40" H 21100 4650 60 0000 C CNN +F 1 "d_nand" H 21150 4750 60 0000 C CNN +F 2 "" H 21100 4650 60 0000 C CNN +F 3 "" H 21100 4650 60 0000 C CNN + 1 21100 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 4550 20600 4550 +Wire Wire Line + 20600 4550 20600 4500 +Wire Wire Line + 20600 4500 20350 4500 +Wire Wire Line + 19450 4450 19350 4450 +Wire Wire Line + 19350 4450 19350 4550 +Wire Wire Line + 19350 4550 19450 4550 +Wire Wire Line + 19150 4500 19350 4500 +Connection ~ 19350 4500 +$Comp +L d_nand U33 +U 1 1 6672C7B4 +P 18700 5250 +F 0 "U33" H 18700 5250 60 0000 C CNN +F 1 "d_nand" H 18750 5350 60 0000 C CNN +F 2 "" H 18700 5250 60 0000 C CNN +F 3 "" H 18700 5250 60 0000 C CNN + 1 18700 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U37 +U 1 1 6672C7BA +P 19900 5250 +F 0 "U37" H 19900 5250 60 0000 C CNN +F 1 "d_nand" H 19950 5350 60 0000 C CNN +F 2 "" H 19900 5250 60 0000 C CNN +F 3 "" H 19900 5250 60 0000 C CNN + 1 19900 5250 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U41 +U 1 1 6672C7C0 +P 21100 5350 +F 0 "U41" H 21100 5350 60 0000 C CNN +F 1 "d_nand" H 21150 5450 60 0000 C CNN +F 2 "" H 21100 5350 60 0000 C CNN +F 3 "" H 21100 5350 60 0000 C CNN + 1 21100 5350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 5250 20600 5250 +Wire Wire Line + 20600 5250 20600 5200 +Wire Wire Line + 20600 5200 20350 5200 +Wire Wire Line + 19450 5150 19350 5150 +Wire Wire Line + 19350 5150 19350 5250 +Wire Wire Line + 19350 5250 19450 5250 +Wire Wire Line + 19150 5200 19350 5200 +Connection ~ 19350 5200 +$Comp +L d_nand U34 +U 1 1 6672C7CE +P 18700 5950 +F 0 "U34" H 18700 5950 60 0000 C CNN +F 1 "d_nand" H 18750 6050 60 0000 C CNN +F 2 "" H 18700 5950 60 0000 C CNN +F 3 "" H 18700 5950 60 0000 C CNN + 1 18700 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U38 +U 1 1 6672C7D4 +P 19900 5950 +F 0 "U38" H 19900 5950 60 0000 C CNN +F 1 "d_nand" H 19950 6050 60 0000 C CNN +F 2 "" H 19900 5950 60 0000 C CNN +F 3 "" H 19900 5950 60 0000 C CNN + 1 19900 5950 + 1 0 0 -1 +$EndComp +$Comp +L d_nand U42 +U 1 1 6672C7DA +P 21100 6050 +F 0 "U42" H 21100 6050 60 0000 C CNN +F 1 "d_nand" H 21150 6150 60 0000 C CNN +F 2 "" H 21100 6050 60 0000 C CNN +F 3 "" H 21100 6050 60 0000 C CNN + 1 21100 6050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 20650 5950 20600 5950 +Wire Wire Line + 20600 5950 20600 5900 +Wire Wire Line + 20600 5900 20350 5900 +Wire Wire Line + 19450 5850 19350 5850 +Wire Wire Line + 19350 5850 19350 5950 +Wire Wire Line + 19350 5950 19450 5950 +Wire Wire Line + 19150 5900 19350 5900 +Connection ~ 19350 5900 +Wire Wire Line + 18250 3850 18000 3850 +Wire Wire Line + 18000 3850 18000 3700 +Wire Wire Line + 16600 3700 16600 3900 +Connection ~ 16600 3900 +Wire Wire Line + 17400 3900 17750 3900 +Wire Wire Line + 17750 3900 17750 5850 +Wire Wire Line + 17750 5850 18250 5850 +Wire Wire Line + 17450 4550 17900 4550 +Wire Wire Line + 17900 4550 17900 5950 +Wire Wire Line + 17900 5950 18250 5950 +Wire Wire Line + 20650 6050 20300 6050 +Wire Wire Line + 20300 6050 20300 6350 +Wire Wire Line + 20300 6350 16450 6350 +Wire Wire Line + 20650 4050 18100 4050 +Wire Wire Line + 18100 4050 18100 6350 +Connection ~ 18100 6350 +Wire Wire Line + 20650 5350 18100 5350 +Connection ~ 18100 5350 +Wire Wire Line + 20650 4650 18100 4650 +Connection ~ 18100 4650 +Wire Wire Line + 18250 4550 18000 4550 +Wire Wire Line + 18000 4550 18000 4250 +Wire Wire Line + 18000 4250 16650 4250 +Wire Wire Line + 16650 4250 16650 4550 +Connection ~ 16650 4550 +Wire Wire Line + 18250 4450 17750 4450 +Connection ~ 17750 4450 +Wire Wire Line + 18250 5150 18050 5150 +Wire Wire Line + 18050 5150 18050 3850 +Connection ~ 18050 3850 +Wire Wire Line + 18250 3950 17850 3950 +Wire Wire Line + 17850 3950 17850 4250 +Connection ~ 17850 4250 +Wire Wire Line + 18250 5250 17900 5250 +Connection ~ 17900 5250 +$Comp +L d_inverter U43 +U 1 1 6672C80C +P 22150 4000 +F 0 "U43" H 22150 3900 60 0000 C CNN +F 1 "d_inverter" H 22150 4150 60 0000 C CNN +F 2 "" H 22200 3950 60 0000 C CNN +F 3 "" H 22200 3950 60 0000 C CNN + 1 22150 4000 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U44 +U 1 1 6672C812 +P 22150 4600 +F 0 "U44" H 22150 4500 60 0000 C CNN +F 1 "d_inverter" H 22150 4750 60 0000 C CNN +F 2 "" H 22200 4550 60 0000 C CNN +F 3 "" H 22200 4550 60 0000 C CNN + 1 22150 4600 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U45 +U 1 1 6672C818 +P 22150 5300 +F 0 "U45" H 22150 5200 60 0000 C CNN +F 1 "d_inverter" H 22150 5450 60 0000 C CNN +F 2 "" H 22200 5250 60 0000 C CNN +F 3 "" H 22200 5250 60 0000 C CNN + 1 22150 5300 + 1 0 0 -1 +$EndComp +$Comp +L d_inverter U46 +U 1 1 6672C81E +P 22150 6000 +F 0 "U46" H 22150 5900 60 0000 C CNN +F 1 "d_inverter" H 22150 6150 60 0000 C CNN +F 2 "" H 22200 5950 60 0000 C CNN +F 3 "" H 22200 5950 60 0000 C CNN + 1 22150 6000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 21550 4000 21850 4000 +Wire Wire Line + 21550 4600 21850 4600 +Wire Wire Line + 21550 5300 21850 5300 +Wire Wire Line + 21550 6000 21850 6000 +$Comp +L adc_bridge_3 U25 +U 1 1 6672C828 +P 14400 4850 +F 0 "U25" H 14400 4850 60 0000 C CNN +F 1 "adc_bridge_3" H 14400 5000 60 0000 C CNN +F 2 "" H 14400 4850 60 0000 C CNN +F 3 "" H 14400 4850 60 0000 C CNN + 1 14400 4850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 14950 4800 15200 4800 +Wire Wire Line + 15200 4800 15200 3900 +Wire Wire Line + 15200 3900 15850 3900 +Wire Wire Line + 14950 4900 15500 4900 +Wire Wire Line + 15500 4900 15500 4550 +Wire Wire Line + 15500 4550 15850 4550 +Wire Wire Line + 14950 5000 15500 5000 +Wire Wire Line + 15500 5000 15500 6350 +Wire Wire Line + 15500 6350 15850 6350 +$Comp +L dac_bridge_4 U47 +U 1 1 6672C837 +P 23750 4950 +F 0 "U47" H 23750 4950 60 0000 C CNN +F 1 "dac_bridge_4" H 23750 5250 60 0000 C CNN +F 2 "" H 23750 4950 60 0000 C CNN +F 3 "" H 23750 4950 60 0000 C CNN + 1 23750 4950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 22450 4000 23000 4000 +Wire Wire Line + 23000 4000 23000 4750 +Wire Wire Line + 23000 4750 23200 4750 +Wire Wire Line + 22450 4600 22900 4600 +Wire Wire Line + 22900 4600 22900 4850 +Wire Wire Line + 22900 4850 23200 4850 +Wire Wire Line + 22450 5300 22900 5300 +Wire Wire Line + 22900 5300 22900 4950 +Wire Wire Line + 22900 4950 23200 4950 +Wire Wire Line + 22450 6000 23050 6000 +Wire Wire Line + 23050 6000 23050 5050 +Wire Wire Line + 23050 5050 23200 5050 +Wire Wire Line + 18000 3700 16600 3700 +$Comp +L PORT U1 +U 12 1 6672E56A +P 13400 4900 +F 0 "U1" H 13450 5000 30 0000 C CNN +F 1 "PORT" H 13400 4900 30 0000 C CNN +F 2 "" H 13400 4900 60 0000 C CNN +F 3 "" H 13400 4900 60 0000 C CNN + 12 13400 4900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24550 5050 24300 5050 +$Comp +L PORT U1 +U 14 1 6672E730 +P 13450 5100 +F 0 "U1" H 13500 5200 30 0000 C CNN +F 1 "PORT" H 13450 5100 30 0000 C CNN +F 2 "" H 13450 5100 60 0000 C CNN +F 3 "" H 13450 5100 60 0000 C CNN + 14 13450 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24650 4900 24400 4900 +Wire Wire Line + 24400 4900 24400 4950 +Wire Wire Line + 24400 4950 24300 4950 +$Comp +L PORT U1 +U 13 1 6672E8E7 +P 13450 4650 +F 0 "U1" H 13500 4750 30 0000 C CNN +F 1 "PORT" H 13450 4650 30 0000 C CNN +F 2 "" H 13450 4650 60 0000 C CNN +F 3 "" H 13450 4650 60 0000 C CNN + 13 13450 4650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 24600 4750 24600 4850 +Wire Wire Line + 24600 4850 24300 4850 +$Comp +L PORT U1 +U 11 1 6672EACB +P 24800 4550 +F 0 "U1" H 24850 4650 30 0000 C CNN +F 1 "PORT" H 24800 4550 30 0000 C CNN +F 2 "" H 24800 4550 60 0000 C CNN +F 3 "" H 24800 4550 60 0000 C CNN + 11 24800 4550 + -1 0 0 1 +$EndComp +Wire Wire Line + 24550 4550 24400 4550 +Wire Wire Line + 24400 4550 24400 4750 +Wire Wire Line + 24400 4750 24300 4750 +$Comp +L PORT U1 +U 10 1 6672F27B +P 24850 4750 +F 0 "U1" H 24900 4850 30 0000 C CNN +F 1 "PORT" H 24850 4750 30 0000 C CNN +F 2 "" H 24850 4750 60 0000 C CNN +F 3 "" H 24850 4750 60 0000 C CNN + 10 24850 4750 + -1 0 0 1 +$EndComp +Wire Wire Line + 13650 4900 13800 4900 +$Comp +L PORT U1 +U 9 1 6672FB88 +P 24900 4900 +F 0 "U1" H 24950 5000 30 0000 C CNN +F 1 "PORT" H 24900 4900 30 0000 C CNN +F 2 "" H 24900 4900 60 0000 C CNN +F 3 "" H 24900 4900 60 0000 C CNN + 9 24900 4900 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 4650 13700 4800 +Wire Wire Line + 13700 4800 13800 4800 +$Comp +L PORT U1 +U 8 1 6672FD62 +P 24800 5050 +F 0 "U1" H 24850 5150 30 0000 C CNN +F 1 "PORT" H 24800 5050 30 0000 C CNN +F 2 "" H 24800 5050 60 0000 C CNN +F 3 "" H 24800 5050 60 0000 C CNN + 8 24800 5050 + -1 0 0 1 +$EndComp +Wire Wire Line + 13700 5100 13700 5000 +Wire Wire Line + 13700 5000 13800 5000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub new file mode 100644 index 00000000..fdabce6f --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC.sub @@ -0,0 +1,190 @@ +* Subcircuit CD4556BMS_IC +.subckt CD4556BMS_IC net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* d:\fossee\esim\library\subcircuitlibrary\cd4556bms_ic\cd4556bms_ic.cir +* u3 net-_u2-pad4_ net-_u10-pad1_ d_inverter +* u4 net-_u2-pad5_ net-_u4-pad2_ d_inverter +* u5 net-_u2-pad6_ net-_u16-pad2_ d_inverter +* u6 net-_u10-pad1_ net-_u11-pad1_ d_inverter +* u7 net-_u4-pad2_ net-_u10-pad2_ d_inverter +* u8 net-_u10-pad1_ net-_u4-pad2_ net-_u12-pad1_ d_nand +* u12 net-_u12-pad1_ net-_u12-pad1_ net-_u12-pad3_ d_nand +* u16 net-_u12-pad3_ net-_u16-pad2_ net-_u16-pad3_ d_nand +* u9 net-_u11-pad1_ net-_u4-pad2_ net-_u13-pad1_ d_nand +* u13 net-_u13-pad1_ net-_u13-pad1_ net-_u13-pad3_ d_nand +* u17 net-_u13-pad3_ net-_u16-pad2_ net-_u17-pad3_ d_nand +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nand +* u14 net-_u10-pad3_ net-_u10-pad3_ net-_u14-pad3_ d_nand +* u18 net-_u14-pad3_ net-_u16-pad2_ net-_u18-pad3_ d_nand +* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nand +* u15 net-_u11-pad3_ net-_u11-pad3_ net-_u15-pad3_ d_nand +* u19 net-_u15-pad3_ net-_u16-pad2_ net-_u19-pad3_ d_nand +* u20 net-_u16-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u17-pad3_ net-_u21-pad2_ d_inverter +* u22 net-_u18-pad3_ net-_u22-pad2_ d_inverter +* u23 net-_u19-pad3_ net-_u23-pad2_ d_inverter +* u2 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u24 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ dac_bridge_4 +* u26 net-_u25-pad4_ net-_u26-pad2_ d_inverter +* u27 net-_u25-pad5_ net-_u27-pad2_ d_inverter +* u28 net-_u25-pad6_ net-_u28-pad2_ d_inverter +* u29 net-_u26-pad2_ net-_u29-pad2_ d_inverter +* u30 net-_u27-pad2_ net-_u30-pad2_ d_inverter +* u31 net-_u26-pad2_ net-_u27-pad2_ net-_u31-pad3_ d_nand +* u35 net-_u31-pad3_ net-_u31-pad3_ net-_u35-pad3_ d_nand +* u39 net-_u35-pad3_ net-_u28-pad2_ net-_u39-pad3_ d_nand +* u32 net-_u29-pad2_ net-_u27-pad2_ net-_u32-pad3_ d_nand +* u36 net-_u32-pad3_ net-_u32-pad3_ net-_u36-pad3_ d_nand +* u40 net-_u36-pad3_ net-_u28-pad2_ net-_u40-pad3_ d_nand +* u33 net-_u26-pad2_ net-_u30-pad2_ net-_u33-pad3_ d_nand +* u37 net-_u33-pad3_ net-_u33-pad3_ net-_u37-pad3_ d_nand +* u41 net-_u37-pad3_ net-_u28-pad2_ net-_u41-pad3_ d_nand +* u34 net-_u29-pad2_ net-_u30-pad2_ net-_u34-pad3_ d_nand +* u38 net-_u34-pad3_ net-_u34-pad3_ net-_u38-pad3_ d_nand +* u42 net-_u38-pad3_ net-_u28-pad2_ net-_u42-pad3_ d_nand +* u43 net-_u39-pad3_ net-_u43-pad2_ d_inverter +* u44 net-_u40-pad3_ net-_u44-pad2_ d_inverter +* u45 net-_u41-pad3_ net-_u45-pad2_ d_inverter +* u46 net-_u42-pad3_ net-_u46-pad2_ d_inverter +* u25 net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ adc_bridge_3 +* u47 net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ dac_bridge_4 +a1 net-_u2-pad4_ net-_u10-pad1_ u3 +a2 net-_u2-pad5_ net-_u4-pad2_ u4 +a3 net-_u2-pad6_ net-_u16-pad2_ u5 +a4 net-_u10-pad1_ net-_u11-pad1_ u6 +a5 net-_u4-pad2_ net-_u10-pad2_ u7 +a6 [net-_u10-pad1_ net-_u4-pad2_ ] net-_u12-pad1_ u8 +a7 [net-_u12-pad1_ net-_u12-pad1_ ] net-_u12-pad3_ u12 +a8 [net-_u12-pad3_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a9 [net-_u11-pad1_ net-_u4-pad2_ ] net-_u13-pad1_ u9 +a10 [net-_u13-pad1_ net-_u13-pad1_ ] net-_u13-pad3_ u13 +a11 [net-_u13-pad3_ net-_u16-pad2_ ] net-_u17-pad3_ u17 +a12 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a13 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u16-pad2_ ] net-_u18-pad3_ u18 +a15 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11 +a16 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u15-pad3_ u15 +a17 [net-_u15-pad3_ net-_u16-pad2_ ] net-_u19-pad3_ u19 +a18 net-_u16-pad3_ net-_u20-pad2_ u20 +a19 net-_u17-pad3_ net-_u21-pad2_ u21 +a20 net-_u18-pad3_ net-_u22-pad2_ u22 +a21 net-_u19-pad3_ net-_u23-pad2_ u23 +a22 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a23 [net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ ] [net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ] u24 +a24 net-_u25-pad4_ net-_u26-pad2_ u26 +a25 net-_u25-pad5_ net-_u27-pad2_ u27 +a26 net-_u25-pad6_ net-_u28-pad2_ u28 +a27 net-_u26-pad2_ net-_u29-pad2_ u29 +a28 net-_u27-pad2_ net-_u30-pad2_ u30 +a29 [net-_u26-pad2_ net-_u27-pad2_ ] net-_u31-pad3_ u31 +a30 [net-_u31-pad3_ net-_u31-pad3_ ] net-_u35-pad3_ u35 +a31 [net-_u35-pad3_ net-_u28-pad2_ ] net-_u39-pad3_ u39 +a32 [net-_u29-pad2_ net-_u27-pad2_ ] net-_u32-pad3_ u32 +a33 [net-_u32-pad3_ net-_u32-pad3_ ] net-_u36-pad3_ u36 +a34 [net-_u36-pad3_ net-_u28-pad2_ ] net-_u40-pad3_ u40 +a35 [net-_u26-pad2_ net-_u30-pad2_ ] net-_u33-pad3_ u33 +a36 [net-_u33-pad3_ net-_u33-pad3_ ] net-_u37-pad3_ u37 +a37 [net-_u37-pad3_ net-_u28-pad2_ ] net-_u41-pad3_ u41 +a38 [net-_u29-pad2_ net-_u30-pad2_ ] net-_u34-pad3_ u34 +a39 [net-_u34-pad3_ net-_u34-pad3_ ] net-_u38-pad3_ u38 +a40 [net-_u38-pad3_ net-_u28-pad2_ ] net-_u42-pad3_ u42 +a41 net-_u39-pad3_ net-_u43-pad2_ u43 +a42 net-_u40-pad3_ net-_u44-pad2_ u44 +a43 net-_u41-pad3_ net-_u45-pad2_ u45 +a44 net-_u42-pad3_ net-_u46-pad2_ u46 +a45 [net-_u1-pad13_ net-_u1-pad12_ net-_u1-pad14_ ] [net-_u25-pad4_ net-_u25-pad5_ net-_u25-pad6_ ] u25 +a46 [net-_u43-pad2_ net-_u44-pad2_ net-_u45-pad2_ net-_u46-pad2_ ] [net-_u1-pad11_ net-_u1-pad10_ net-_u1-pad9_ net-_u1-pad8_ ] u47 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u8 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u16 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u9 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u17 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u10 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u14 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u18 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u11 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u15 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u19 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u24 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u31 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u35 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u39 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u32 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u36 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u40 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u33 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u41 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u34 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u38 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u42 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u43 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u44 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u45 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u46 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u25 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u47 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends CD4556BMS_IC
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml new file mode 100644 index 00000000..5d199ade --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/CD4556BMS_IC_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis><source /><model><u3 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u3><u4 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u5><u6 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u7><u8 name="type">d_nand<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u8><u12 name="type">d_nand<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u12><u16 name="type">d_nand<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u16><u9 name="type">d_nand<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u9><u13 name="type">d_nand<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u13><u17 name="type">d_nand<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u17><u10 name="type">d_nand<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u10><u14 name="type">d_nand<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u14><u18 name="type">d_nand<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u18><u11 name="type">d_nand<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u11><u15 name="type">d_nand<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u15><u19 name="type">d_nand<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u21><u22 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u22><u23 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u23><u2 name="type">adc_bridge<field64 name="Enter value for in_low (default=1.0)" /><field65 name="Enter value for in_high (default=2.0)" /><field66 name="Enter Rise Delay (default=1.0e-9)" /><field67 name="Enter Fall Delay (default=1.0e-9)" /></u2><u24 name="type">dac_bridge<field68 name="Enter value for out_low (default=0.0)" /><field69 name="Enter value for out_high (default=5.0)" /><field70 name="Enter value for out_undef (default=0.5)" /><field71 name="Enter value for input load (default=1.0e-12)" /><field72 name="Enter the Rise Time (default=1.0e-9)" /><field73 name="Enter the Fall Time (default=1.0e-9)" /></u24><u26 name="type">d_inverter<field74 name="Enter Rise Delay (default=1.0e-9)" /><field75 name="Enter Fall Delay (default=1.0e-9)" /><field76 name="Enter Input Load (default=1.0e-12)" /></u26><u27 name="type">d_inverter<field77 name="Enter Rise Delay (default=1.0e-9)" /><field78 name="Enter Fall Delay (default=1.0e-9)" /><field79 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_inverter<field80 name="Enter Rise Delay (default=1.0e-9)" /><field81 name="Enter Fall Delay (default=1.0e-9)" /><field82 name="Enter Input Load (default=1.0e-12)" /></u28><u29 name="type">d_inverter<field83 name="Enter Rise Delay (default=1.0e-9)" /><field84 name="Enter Fall Delay (default=1.0e-9)" /><field85 name="Enter Input Load (default=1.0e-12)" /></u29><u30 name="type">d_inverter<field86 name="Enter Rise Delay (default=1.0e-9)" /><field87 name="Enter Fall Delay (default=1.0e-9)" /><field88 name="Enter Input Load (default=1.0e-12)" /></u30><u31 name="type">d_nand<field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /><field91 name="Enter Input Load (default=1.0e-12)" /></u31><u35 name="type">d_nand<field92 name="Enter Rise Delay (default=1.0e-9)" /><field93 name="Enter Fall Delay (default=1.0e-9)" /><field94 name="Enter Input Load (default=1.0e-12)" /></u35><u39 name="type">d_nand<field95 name="Enter Rise Delay (default=1.0e-9)" /><field96 name="Enter Fall Delay (default=1.0e-9)" /><field97 name="Enter Input Load (default=1.0e-12)" /></u39><u32 name="type">d_nand<field98 name="Enter Rise Delay (default=1.0e-9)" /><field99 name="Enter Fall Delay (default=1.0e-9)" /><field100 name="Enter Input Load (default=1.0e-12)" /></u32><u36 name="type">d_nand<field101 name="Enter Rise Delay (default=1.0e-9)" /><field102 name="Enter Fall Delay (default=1.0e-9)" /><field103 name="Enter Input Load (default=1.0e-12)" /></u36><u40 name="type">d_nand<field104 name="Enter Rise Delay (default=1.0e-9)" /><field105 name="Enter Fall Delay (default=1.0e-9)" /><field106 name="Enter Input Load (default=1.0e-12)" /></u40><u33 name="type">d_nand<field107 name="Enter Rise Delay (default=1.0e-9)" /><field108 name="Enter Fall Delay (default=1.0e-9)" /><field109 name="Enter Input Load (default=1.0e-12)" /></u33><u37 name="type">d_nand<field110 name="Enter Rise Delay (default=1.0e-9)" /><field111 name="Enter Fall Delay (default=1.0e-9)" /><field112 name="Enter Input Load (default=1.0e-12)" /></u37><u41 name="type">d_nand<field113 name="Enter Rise Delay (default=1.0e-9)" /><field114 name="Enter Fall Delay (default=1.0e-9)" /><field115 name="Enter Input Load (default=1.0e-12)" /></u41><u34 name="type">d_nand<field116 name="Enter Rise Delay (default=1.0e-9)" /><field117 name="Enter Fall Delay (default=1.0e-9)" /><field118 name="Enter Input Load (default=1.0e-12)" /></u34><u38 name="type">d_nand<field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /><field121 name="Enter Input Load (default=1.0e-12)" /></u38><u42 name="type">d_nand<field122 name="Enter Rise Delay (default=1.0e-9)" /><field123 name="Enter Fall Delay (default=1.0e-9)" /><field124 name="Enter Input Load (default=1.0e-12)" /></u42><u43 name="type">d_inverter<field125 name="Enter Rise Delay (default=1.0e-9)" /><field126 name="Enter Fall Delay (default=1.0e-9)" /><field127 name="Enter Input Load (default=1.0e-12)" /></u43><u44 name="type">d_inverter<field128 name="Enter Rise Delay (default=1.0e-9)" /><field129 name="Enter Fall Delay (default=1.0e-9)" /><field130 name="Enter Input Load (default=1.0e-12)" /></u44><u45 name="type">d_inverter<field131 name="Enter Rise Delay (default=1.0e-9)" /><field132 name="Enter Fall Delay (default=1.0e-9)" /><field133 name="Enter Input Load (default=1.0e-12)" /></u45><u46 name="type">d_inverter<field134 name="Enter Rise Delay (default=1.0e-9)" /><field135 name="Enter Fall Delay (default=1.0e-9)" /><field136 name="Enter Input Load (default=1.0e-12)" /></u46><u25 name="type">adc_bridge<field137 name="Enter value for in_low (default=1.0)" /><field138 name="Enter value for in_high (default=2.0)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /></u25><u47 name="type">dac_bridge<field141 name="Enter value for out_low (default=0.0)" /><field142 name="Enter value for out_high (default=5.0)" /><field143 name="Enter value for out_undef (default=0.5)" /><field144 name="Enter value for input load (default=1.0e-12)" /><field145 name="Enter the Rise Time (default=1.0e-9)" /><field146 name="Enter the Fall Time (default=1.0e-9)" /></u47></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4556BMS_sub/analysis b/library/SubcircuitLibrary/CD4556BMS_sub/analysis new file mode 100644 index 00000000..db9906e6 --- /dev/null +++ b/library/SubcircuitLibrary/CD4556BMS_sub/analysis @@ -0,0 +1 @@ +.tran 0.01e-03 100e-03 0e-00
\ No newline at end of file |