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-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib170
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir48
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out160
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro73
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch896
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub154
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC688_sub/analysis1
8 files changed, 1503 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib
new file mode 100644
index 00000000..4c0d3858
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub-cache.lib
@@ -0,0 +1,170 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_3
+#
+DEF adc_bridge_3 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_3" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -200 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X OUT1 4 550 50 200 L 50 50 1 1 O
+X OUT2 5 550 -50 200 L 50 50 1 1 O
+X OUT3 6 550 -150 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_7
+#
+DEF adc_bridge_7 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_7" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -600 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X OUT1 8 550 50 200 L 50 50 1 1 O
+X OUT2 9 550 -50 200 L 50 50 1 1 O
+X OUT3 10 550 -150 200 L 50 50 1 1 O
+X OUT4 11 550 -250 200 L 50 50 1 1 O
+X OUT5 12 550 -350 200 L 50 50 1 1 O
+X OUT6 13 550 -450 200 L 50 50 1 1 O
+X OUT7 14 550 -550 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nand
+#
+DEF d_nand U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nand" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_1
+#
+DEF dac_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir
new file mode 100644
index 00000000..32fe40e6
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir
@@ -0,0 +1,48 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\74HC688_sub\74HC688_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 12/06/2024 12:19:51 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U5 Net-_U2-Pad8_ Net-_U22-Pad1_ d_inverter
+U6 Net-_U2-Pad9_ Net-_U22-Pad2_ d_inverter
+U7 Net-_U2-Pad10_ Net-_U23-Pad1_ d_inverter
+U8 Net-_U2-Pad11_ Net-_U23-Pad2_ d_inverter
+U9 Net-_U2-Pad12_ Net-_U24-Pad1_ d_inverter
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ d_inverter
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U13-Pad1_ Net-_U13-Pad2_ d_inverter
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ d_inverter
+U15 Net-_U15-Pad1_ Net-_U15-Pad2_ d_inverter
+U16 Net-_U16-Pad1_ Net-_U16-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ d_inverter
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ d_inverter
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_xnor
+U23 Net-_U23-Pad1_ Net-_U23-Pad2_ Net-_U23-Pad3_ d_xnor
+U24 Net-_U24-Pad1_ Net-_U10-Pad2_ Net-_U24-Pad3_ d_xnor
+U25 Net-_U11-Pad2_ Net-_U12-Pad2_ Net-_U25-Pad3_ d_xnor
+U26 Net-_U13-Pad2_ Net-_U14-Pad2_ Net-_U26-Pad3_ d_xnor
+U27 Net-_U15-Pad2_ Net-_U16-Pad2_ Net-_U27-Pad3_ d_xnor
+U28 Net-_U17-Pad2_ Net-_U18-Pad2_ Net-_U28-Pad3_ d_xnor
+U29 Net-_U19-Pad2_ Net-_U20-Pad2_ Net-_U29-Pad3_ d_xnor
+U30 Net-_U22-Pad3_ Net-_U23-Pad3_ Net-_U30-Pad3_ d_and
+U31 Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U31-Pad3_ d_and
+U32 Net-_U26-Pad3_ Net-_U27-Pad3_ Net-_U32-Pad3_ d_and
+U33 Net-_U28-Pad3_ Net-_U29-Pad3_ Net-_U33-Pad3_ d_and
+U34 Net-_U30-Pad3_ Net-_U31-Pad3_ Net-_U34-Pad3_ d_and
+U35 Net-_U32-Pad3_ Net-_U33-Pad3_ Net-_U35-Pad3_ d_and
+U37 Net-_U36-Pad3_ Net-_U21-Pad2_ Net-_U37-Pad3_ d_nand
+U36 Net-_U34-Pad3_ Net-_U35-Pad3_ Net-_U36-Pad3_ d_and
+U38 Net-_U37-Pad3_ Net-_U1-Pad18_ dac_bridge_1
+U2 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad10_ Net-_U2-Pad8_ Net-_U2-Pad9_ Net-_U2-Pad10_ Net-_U2-Pad11_ Net-_U2-Pad12_ Net-_U10-Pad1_ Net-_U11-Pad1_ adc_bridge_7
+U3 Net-_U1-Pad11_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U12-Pad1_ Net-_U13-Pad1_ Net-_U14-Pad1_ Net-_U15-Pad1_ Net-_U16-Pad1_ Net-_U17-Pad1_ Net-_U18-Pad1_ adc_bridge_7
+U4 Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad1_ Net-_U19-Pad1_ Net-_U20-Pad1_ Net-_U21-Pad1_ adc_bridge_3
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out
new file mode 100644
index 00000000..b0a3d406
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.cir.out
@@ -0,0 +1,160 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc688_sub\74hc688_sub.cir
+
+* u5 net-_u2-pad8_ net-_u22-pad1_ d_inverter
+* u6 net-_u2-pad9_ net-_u22-pad2_ d_inverter
+* u7 net-_u2-pad10_ net-_u23-pad1_ d_inverter
+* u8 net-_u2-pad11_ net-_u23-pad2_ d_inverter
+* u9 net-_u2-pad12_ net-_u24-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_xnor
+* u24 net-_u24-pad1_ net-_u10-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u11-pad2_ net-_u12-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u13-pad2_ net-_u14-pad2_ net-_u26-pad3_ d_xnor
+* u27 net-_u15-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_xnor
+* u28 net-_u17-pad2_ net-_u18-pad2_ net-_u28-pad3_ d_xnor
+* u29 net-_u19-pad2_ net-_u20-pad2_ net-_u29-pad3_ d_xnor
+* u30 net-_u22-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_and
+* u31 net-_u24-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_and
+* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_and
+* u33 net-_u28-pad3_ net-_u29-pad3_ net-_u33-pad3_ d_and
+* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_and
+* u35 net-_u32-pad3_ net-_u33-pad3_ net-_u35-pad3_ d_and
+* u37 net-_u36-pad3_ net-_u21-pad2_ net-_u37-pad3_ d_nand
+* u36 net-_u34-pad3_ net-_u35-pad3_ net-_u36-pad3_ d_and
+* u38 net-_u37-pad3_ net-_u1-pad18_ dac_bridge_1
+* u2 net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ adc_bridge_7
+* u3 net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ adc_bridge_7
+* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ adc_bridge_3
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ port
+a1 net-_u2-pad8_ net-_u22-pad1_ u5
+a2 net-_u2-pad9_ net-_u22-pad2_ u6
+a3 net-_u2-pad10_ net-_u23-pad1_ u7
+a4 net-_u2-pad11_ net-_u23-pad2_ u8
+a5 net-_u2-pad12_ net-_u24-pad1_ u9
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad1_ net-_u11-pad2_ u11
+a8 net-_u12-pad1_ net-_u12-pad2_ u12
+a9 net-_u13-pad1_ net-_u13-pad2_ u13
+a10 net-_u14-pad1_ net-_u14-pad2_ u14
+a11 net-_u15-pad1_ net-_u15-pad2_ u15
+a12 net-_u16-pad1_ net-_u16-pad2_ u16
+a13 net-_u17-pad1_ net-_u17-pad2_ u17
+a14 net-_u18-pad1_ net-_u18-pad2_ u18
+a15 net-_u19-pad1_ net-_u19-pad2_ u19
+a16 net-_u20-pad1_ net-_u20-pad2_ u20
+a17 net-_u21-pad1_ net-_u21-pad2_ u21
+a18 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u24-pad1_ net-_u10-pad2_ ] net-_u24-pad3_ u24
+a21 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u26-pad3_ u26
+a23 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27
+a24 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u28-pad3_ u28
+a25 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u29-pad3_ u29
+a26 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32
+a29 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u33-pad3_ u33
+a30 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a31 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u35-pad3_ u35
+a32 [net-_u36-pad3_ net-_u21-pad2_ ] net-_u37-pad3_ u37
+a33 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u36-pad3_ u36
+a34 [net-_u37-pad3_ ] [net-_u1-pad18_ ] u38
+a35 [net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ ] [net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ ] u2
+a36 [net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ ] u3
+a37 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u28 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch
new file mode 100644
index 00000000..c2d69973
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sch
@@ -0,0 +1,896 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:74HC688-cache
+EELAYER 25 0
+EELAYER END
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+L PORT U1
+U 17 1 66695A66
+P 6650 6550
+F 0 "U1" H 6700 6650 30 0000 C CNN
+F 1 "PORT" H 6650 6550 30 0000 C CNN
+F 2 "" H 6650 6550 60 0000 C CNN
+F 3 "" H 6650 6550 60 0000 C CNN
+ 17 6650 6550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 66695D9F
+P 6650 6750
+F 0 "U1" H 6700 6850 30 0000 C CNN
+F 1 "PORT" H 6650 6750 30 0000 C CNN
+F 2 "" H 6650 6750 60 0000 C CNN
+F 3 "" H 6650 6750 60 0000 C CNN
+ 15 6650 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 66695EA8
+P 6650 6450
+F 0 "U1" H 6700 6550 30 0000 C CNN
+F 1 "PORT" H 6650 6450 30 0000 C CNN
+F 2 "" H 6650 6450 60 0000 C CNN
+F 3 "" H 6650 6450 60 0000 C CNN
+ 16 6650 6450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 66695F3D
+P 6650 6950
+F 0 "U1" H 6700 7050 30 0000 C CNN
+F 1 "PORT" H 6650 6950 30 0000 C CNN
+F 2 "" H 6650 6950 60 0000 C CNN
+F 3 "" H 6650 6950 60 0000 C CNN
+ 13 6650 6950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 66695FB6
+P 6650 6650
+F 0 "U1" H 6700 6750 30 0000 C CNN
+F 1 "PORT" H 6650 6650 30 0000 C CNN
+F 2 "" H 6650 6650 60 0000 C CNN
+F 3 "" H 6650 6650 60 0000 C CNN
+ 14 6650 6650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 66696035
+P 6650 9350
+F 0 "U1" H 6700 9450 30 0000 C CNN
+F 1 "PORT" H 6650 9350 30 0000 C CNN
+F 2 "" H 6650 9350 60 0000 C CNN
+F 3 "" H 6650 9350 60 0000 C CNN
+ 11 6650 9350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 666960E8
+P 6650 6850
+F 0 "U1" H 6700 6950 30 0000 C CNN
+F 1 "PORT" H 6650 6850 30 0000 C CNN
+F 2 "" H 6650 6850 60 0000 C CNN
+F 3 "" H 6650 6850 60 0000 C CNN
+ 12 6650 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 66696199
+P 6650 9550
+F 0 "U1" H 6700 9650 30 0000 C CNN
+F 1 "PORT" H 6650 9550 30 0000 C CNN
+F 2 "" H 6650 9550 60 0000 C CNN
+F 3 "" H 6650 9550 60 0000 C CNN
+ 9 6650 9550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6669622C
+P 6650 7050
+F 0 "U1" H 6700 7150 30 0000 C CNN
+F 1 "PORT" H 6650 7050 30 0000 C CNN
+F 2 "" H 6650 7050 60 0000 C CNN
+F 3 "" H 6650 7050 60 0000 C CNN
+ 10 6650 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6669631D
+P 6650 9750
+F 0 "U1" H 6700 9850 30 0000 C CNN
+F 1 "PORT" H 6650 9750 30 0000 C CNN
+F 2 "" H 6650 9750 60 0000 C CNN
+F 3 "" H 6650 9750 60 0000 C CNN
+ 7 6650 9750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 66698A02
+P 6650 9450
+F 0 "U1" H 6700 9550 30 0000 C CNN
+F 1 "PORT" H 6650 9450 30 0000 C CNN
+F 2 "" H 6650 9450 60 0000 C CNN
+F 3 "" H 6650 9450 60 0000 C CNN
+ 8 6650 9450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 66699935
+P 6650 9950
+F 0 "U1" H 6700 10050 30 0000 C CNN
+F 1 "PORT" H 6650 9950 30 0000 C CNN
+F 2 "" H 6650 9950 60 0000 C CNN
+F 3 "" H 6650 9950 60 0000 C CNN
+ 5 6650 9950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 666999CC
+P 6650 9650
+F 0 "U1" H 6700 9750 30 0000 C CNN
+F 1 "PORT" H 6650 9650 30 0000 C CNN
+F 2 "" H 6650 9650 60 0000 C CNN
+F 3 "" H 6650 9650 60 0000 C CNN
+ 6 6650 9650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 66699A5B
+P 6650 11700
+F 0 "U1" H 6700 11800 30 0000 C CNN
+F 1 "PORT" H 6650 11700 30 0000 C CNN
+F 2 "" H 6650 11700 60 0000 C CNN
+F 3 "" H 6650 11700 60 0000 C CNN
+ 3 6650 11700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 66699AFA
+P 6650 9850
+F 0 "U1" H 6700 9950 30 0000 C CNN
+F 1 "PORT" H 6650 9850 30 0000 C CNN
+F 2 "" H 6650 9850 60 0000 C CNN
+F 3 "" H 6650 9850 60 0000 C CNN
+ 4 6650 9850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 66699B9B
+P 6650 11800
+F 0 "U1" H 6700 11900 30 0000 C CNN
+F 1 "PORT" H 6650 11800 30 0000 C CNN
+F 2 "" H 6650 11800 60 0000 C CNN
+F 3 "" H 6650 11800 60 0000 C CNN
+ 1 6650 11800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 66699C3E
+P 6650 11600
+F 0 "U1" H 6700 11700 30 0000 C CNN
+F 1 "PORT" H 6650 11600 30 0000 C CNN
+F 2 "" H 6650 11600 60 0000 C CNN
+F 3 "" H 6650 11600 60 0000 C CNN
+ 2 6650 11600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 6669AAF7
+P 17300 9900
+F 0 "U1" H 17350 10000 30 0000 C CNN
+F 1 "PORT" H 17300 9900 30 0000 C CNN
+F 2 "" H 17300 9900 60 0000 C CNN
+F 3 "" H 17300 9900 60 0000 C CNN
+ 18 17300 9900
+ -1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
new file mode 100644
index 00000000..68303a9d
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub.sub
@@ -0,0 +1,154 @@
+* Subcircuit 74HC688_sub
+.subckt 74HC688_sub net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_
+* c:\fossee\esim\library\subcircuitlibrary\74hc688_sub\74hc688_sub.cir
+* u5 net-_u2-pad8_ net-_u22-pad1_ d_inverter
+* u6 net-_u2-pad9_ net-_u22-pad2_ d_inverter
+* u7 net-_u2-pad10_ net-_u23-pad1_ d_inverter
+* u8 net-_u2-pad11_ net-_u23-pad2_ d_inverter
+* u9 net-_u2-pad12_ net-_u24-pad1_ d_inverter
+* u10 net-_u10-pad1_ net-_u10-pad2_ d_inverter
+* u11 net-_u11-pad1_ net-_u11-pad2_ d_inverter
+* u12 net-_u12-pad1_ net-_u12-pad2_ d_inverter
+* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter
+* u14 net-_u14-pad1_ net-_u14-pad2_ d_inverter
+* u15 net-_u15-pad1_ net-_u15-pad2_ d_inverter
+* u16 net-_u16-pad1_ net-_u16-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u17-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u19 net-_u19-pad1_ net-_u19-pad2_ d_inverter
+* u20 net-_u20-pad1_ net-_u20-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u23 net-_u23-pad1_ net-_u23-pad2_ net-_u23-pad3_ d_xnor
+* u24 net-_u24-pad1_ net-_u10-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u11-pad2_ net-_u12-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u13-pad2_ net-_u14-pad2_ net-_u26-pad3_ d_xnor
+* u27 net-_u15-pad2_ net-_u16-pad2_ net-_u27-pad3_ d_xnor
+* u28 net-_u17-pad2_ net-_u18-pad2_ net-_u28-pad3_ d_xnor
+* u29 net-_u19-pad2_ net-_u20-pad2_ net-_u29-pad3_ d_xnor
+* u30 net-_u22-pad3_ net-_u23-pad3_ net-_u30-pad3_ d_and
+* u31 net-_u24-pad3_ net-_u25-pad3_ net-_u31-pad3_ d_and
+* u32 net-_u26-pad3_ net-_u27-pad3_ net-_u32-pad3_ d_and
+* u33 net-_u28-pad3_ net-_u29-pad3_ net-_u33-pad3_ d_and
+* u34 net-_u30-pad3_ net-_u31-pad3_ net-_u34-pad3_ d_and
+* u35 net-_u32-pad3_ net-_u33-pad3_ net-_u35-pad3_ d_and
+* u37 net-_u36-pad3_ net-_u21-pad2_ net-_u37-pad3_ d_nand
+* u36 net-_u34-pad3_ net-_u35-pad3_ net-_u36-pad3_ d_and
+* u38 net-_u37-pad3_ net-_u1-pad18_ dac_bridge_1
+* u2 net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ adc_bridge_7
+* u3 net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ adc_bridge_7
+* u4 net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ adc_bridge_3
+a1 net-_u2-pad8_ net-_u22-pad1_ u5
+a2 net-_u2-pad9_ net-_u22-pad2_ u6
+a3 net-_u2-pad10_ net-_u23-pad1_ u7
+a4 net-_u2-pad11_ net-_u23-pad2_ u8
+a5 net-_u2-pad12_ net-_u24-pad1_ u9
+a6 net-_u10-pad1_ net-_u10-pad2_ u10
+a7 net-_u11-pad1_ net-_u11-pad2_ u11
+a8 net-_u12-pad1_ net-_u12-pad2_ u12
+a9 net-_u13-pad1_ net-_u13-pad2_ u13
+a10 net-_u14-pad1_ net-_u14-pad2_ u14
+a11 net-_u15-pad1_ net-_u15-pad2_ u15
+a12 net-_u16-pad1_ net-_u16-pad2_ u16
+a13 net-_u17-pad1_ net-_u17-pad2_ u17
+a14 net-_u18-pad1_ net-_u18-pad2_ u18
+a15 net-_u19-pad1_ net-_u19-pad2_ u19
+a16 net-_u20-pad1_ net-_u20-pad2_ u20
+a17 net-_u21-pad1_ net-_u21-pad2_ u21
+a18 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a19 [net-_u23-pad1_ net-_u23-pad2_ ] net-_u23-pad3_ u23
+a20 [net-_u24-pad1_ net-_u10-pad2_ ] net-_u24-pad3_ u24
+a21 [net-_u11-pad2_ net-_u12-pad2_ ] net-_u25-pad3_ u25
+a22 [net-_u13-pad2_ net-_u14-pad2_ ] net-_u26-pad3_ u26
+a23 [net-_u15-pad2_ net-_u16-pad2_ ] net-_u27-pad3_ u27
+a24 [net-_u17-pad2_ net-_u18-pad2_ ] net-_u28-pad3_ u28
+a25 [net-_u19-pad2_ net-_u20-pad2_ ] net-_u29-pad3_ u29
+a26 [net-_u22-pad3_ net-_u23-pad3_ ] net-_u30-pad3_ u30
+a27 [net-_u24-pad3_ net-_u25-pad3_ ] net-_u31-pad3_ u31
+a28 [net-_u26-pad3_ net-_u27-pad3_ ] net-_u32-pad3_ u32
+a29 [net-_u28-pad3_ net-_u29-pad3_ ] net-_u33-pad3_ u33
+a30 [net-_u30-pad3_ net-_u31-pad3_ ] net-_u34-pad3_ u34
+a31 [net-_u32-pad3_ net-_u33-pad3_ ] net-_u35-pad3_ u35
+a32 [net-_u36-pad3_ net-_u21-pad2_ ] net-_u37-pad3_ u37
+a33 [net-_u34-pad3_ net-_u35-pad3_ ] net-_u36-pad3_ u36
+a34 [net-_u37-pad3_ ] [net-_u1-pad18_ ] u38
+a35 [net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad10_ ] [net-_u2-pad8_ net-_u2-pad9_ net-_u2-pad10_ net-_u2-pad11_ net-_u2-pad12_ net-_u10-pad1_ net-_u11-pad1_ ] u2
+a36 [net-_u1-pad11_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad4_ net-_u1-pad5_ ] [net-_u12-pad1_ net-_u13-pad1_ net-_u14-pad1_ net-_u15-pad1_ net-_u16-pad1_ net-_u17-pad1_ net-_u18-pad1_ ] u3
+a37 [net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad1_ ] [net-_u19-pad1_ net-_u20-pad1_ net-_u21-pad1_ ] u4
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u19 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u27 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u28 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u29 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u31 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u34 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u35 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nand, NgSpice Name: d_nand
+.model u37 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u36 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge
+.model u38 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_7, NgSpice Name: adc_bridge
+.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge
+.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 74HC688_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml
new file mode 100644
index 00000000..8781d549
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/74HC688_sub_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u5 name="type">d_inverter<field1 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field1><field2 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field2><field3 name="Enter Input Load (default=1.0e-12)">1.0e-12</field3></u5><u6 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field4><field5 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field5><field6 name="Enter Input Load (default=1.0e-12)">1.0e-12</field6></u6><u7 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field7><field8 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field8><field9 name="Enter Input Load (default=1.0e-12)">1.0e-12</field9></u7><u8 name="type">d_inverter<field10 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field10><field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field11><field12 name="Enter Input Load (default=1.0e-12)">1.0e-12</field12></u8><u9 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field13><field14 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field14><field15 name="Enter Input Load (default=1.0e-12)">1.0e-12</field15></u9><u10 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field16><field17 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field17><field18 name="Enter Input Load (default=1.0e-12)">1.0e-12</field18></u10><u11 name="type">d_inverter<field19 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field19><field20 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field20><field21 name="Enter Input Load (default=1.0e-12)">1.0e-12</field21></u11><u12 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field22><field23 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field23><field24 name="Enter Input Load (default=1.0e-12)">1.0e-12</field24></u12><u13 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field25><field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field26><field27 name="Enter Input Load (default=1.0e-12)">1.0e-12</field27></u13><u14 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field28><field29 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field29><field30 name="Enter Input Load (default=1.0e-12)">1.0e-12</field30></u14><u15 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field31><field32 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field32><field33 name="Enter Input Load (default=1.0e-12)">1.0e-12</field33></u15><u16 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field34><field35 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field35><field36 name="Enter Input Load (default=1.0e-12)">1.0e-12</field36></u16><u17 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field37><field38 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field38><field39 name="Enter Input Load (default=1.0e-12)">1.0e-12</field39></u17><u18 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field40><field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field41><field42 name="Enter Input Load (default=1.0e-12)">1.0e-12</field42></u18><u19 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field43><field44 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field44><field45 name="Enter Input Load (default=1.0e-12)">1.0e-12</field45></u19><u20 name="type">d_inverter<field46 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field46><field47 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field47><field48 name="Enter Input Load (default=1.0e-12)">1.0e-12</field48></u20><u21 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field49><field50 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field50><field51 name="Enter Input Load (default=1.0e-12)">1.0e-12</field51></u21><u22 name="type">d_xnor<field52 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field52><field53 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field53><field54 name="Enter Input Load (default=1.0e-12)">1.0e-12</field54></u22><u23 name="type">d_xnor<field55 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field55><field56 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field56><field57 name="Enter Input Load (default=1.0e-12)">1.0e-12</field57></u23><u24 name="type">d_xnor<field58 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field58><field59 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field59><field60 name="Enter Input Load (default=1.0e-12)">1.0e-12</field60></u24><u25 name="type">d_xnor<field61 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field61><field62 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field62><field63 name="Enter Input Load (default=1.0e-12)">1.0e-12</field63></u25><u26 name="type">d_xnor<field64 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field64><field65 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field65><field66 name="Enter Input Load (default=1.0e-12)">1.0e-12</field66></u26><u27 name="type">d_xnor<field67 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field67><field68 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field68><field69 name="Enter Input Load (default=1.0e-12)">1.0e-12</field69></u27><u28 name="type">d_xnor<field70 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field70><field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field71><field72 name="Enter Input Load (default=1.0e-12)">1.0e-12</field72></u28><u29 name="type">d_xnor<field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field73><field74 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field74><field75 name="Enter Input Load (default=1.0e-12)">1.0e-12</field75></u29><u30 name="type">d_and<field76 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field76><field77 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field77><field78 name="Enter Input Load (default=1.0e-12)">1.0e-12</field78></u30><u31 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field79><field80 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field80><field81 name="Enter Input Load (default=1.0e-12)">1.0e-12</field81></u31><u32 name="type">d_and<field82 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field82><field83 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field83><field84 name="Enter Input Load (default=1.0e-12)">1.0e-12</field84></u32><u33 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field85><field86 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field86><field87 name="Enter Input Load (default=1.0e-12)">1.0e-12</field87></u33><u34 name="type">d_and<field88 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field88><field89 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field89><field90 name="Enter Input Load (default=1.0e-12)">1.0e-12</field90></u34><u35 name="type">d_and<field91 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field91><field92 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field92><field93 name="Enter Input Load (default=1.0e-12)">1.0e-12</field93></u35><u37 name="type">d_nand<field94 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field94><field95 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field95><field96 name="Enter Input Load (default=1.0e-12)">1.0e-12</field96></u37><u36 name="type">d_and<field97 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field97><field98 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field98><field99 name="Enter Input Load (default=1.0e-12)">1.0e-12</field99></u36><u38 name="type">dac_bridge<field100 name="Enter value for out_low (default=0.0)">0.0</field100><field101 name="Enter value for out_high (default=5.0)">5.0</field101><field102 name="Enter value for out_undef (default=0.5)">0.5</field102><field103 name="Enter value for input load (default=1.0e-12)">1.0e-12</field103><field104 name="Enter the Rise Time (default=1.0e-9)">1.0e-9</field104><field105 name="Enter the Fall Time (default=1.0e-9)">1.0e-9</field105></u38><u2 name="type">adc_bridge<field106 name="Enter value for in_low (default=1.0)">1.0</field106><field107 name="Enter value for in_high (default=2.0)">2.0</field107><field108 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field108><field109 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field109></u2><u3 name="type">adc_bridge<field110 name="Enter value for in_low (default=1.0)">1.0</field110><field111 name="Enter value for in_high (default=2.0)">2.0</field111><field112 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field112><field113 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field113></u3><u4 name="type">adc_bridge<field114 name="Enter value for in_low (default=1.0)">1.0</field114><field115 name="Enter value for in_high (default=2.0)">2.0</field115><field116 name="Enter Rise Delay (default=1.0e-9)">1.0e-9</field116><field117 name="Enter Fall Delay (default=1.0e-9)">1.0e-9</field117></u4></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC688_sub/analysis b/library/SubcircuitLibrary/74HC688_sub/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC688_sub/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-20 16:00:06 +0000