summaryrefslogtreecommitdiff
path: root/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub
diff options
context:
space:
mode:
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub')
-rw-r--r--library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub22
1 files changed, 22 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub
new file mode 100644
index 00000000..2ebb644d
--- /dev/null
+++ b/library/SubcircuitLibrary/esim_ic_files/sn74ls375/375.sub
@@ -0,0 +1,22 @@
+* Subcircuit 375
+.subckt 375 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_
+* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\375\375.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ d_dlatch
+* u3 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ d_dlatch
+* u4 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ d_dlatch
+* u5 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ d_dlatch
+a1 net-_u1-pad1_ net-_u1-pad2_ ? ? net-_u1-pad3_ net-_u1-pad10_ u2
+a2 net-_u1-pad4_ net-_u1-pad2_ ? ? net-_u1-pad5_ net-_u1-pad11_ u3
+a3 net-_u1-pad6_ net-_u1-pad2_ ? ? net-_u1-pad7_ net-_u1-pad12_ u4
+a4 net-_u1-pad8_ net-_u1-pad2_ ? ? net-_u1-pad9_ net-_u1-pad13_ u5
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u2 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u3 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u4 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_dlatch, NgSpice Name: d_dlatch
+.model u5 d_dlatch(data_delay=1.0e-9 enable_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0e-9 ic=0 data_load=1.0e-12 enable_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends 375 \ No newline at end of file