diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/sn54ls90')
15 files changed, 1525 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib new file mode 100644 index 00000000..268e1bb1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90-cache.lib @@ -0,0 +1,99 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_jkff +# +DEF d_jkff U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_jkff" 50 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 600 550 -600 -600 0 1 0 N +X J 1 -800 400 200 R 50 50 1 1 I +X K 2 -800 -450 200 R 50 50 1 1 I +X Clk 3 -800 0 200 R 50 50 1 1 I C +X Set 4 0 750 200 D 50 50 1 1 I +X Reset 5 0 -800 200 U 50 50 1 1 I +X Out 6 800 400 200 L 50 50 1 1 O +X Nout 7 800 -450 200 L 50 50 1 1 O I +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir new file mode 100644 index 00000000..78ecb37d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir @@ -0,0 +1,21 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls90\74ls90.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/15/25 15:54:08 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 /JK /JK /CLK /R01 /R91 /QA ? d_jkff +U4 Net-_U3-Pad3_ Net-_U3-Pad3_ /CLK /R01 /R91 /QB ? d_jkff +U8 Net-_U5-Pad3_ Net-_U5-Pad3_ /CLK /R01 /R91 /QC ? d_jkff +U11 Net-_U10-Pad3_ Net-_U10-Pad3_ /CLK /R01 /R91 /QD Net-_U11-Pad7_ d_jkff +U3 Net-_U11-Pad7_ /QA Net-_U3-Pad3_ d_and +U5 /QA /QB Net-_U5-Pad3_ d_and +U7 /QA /QD Net-_U10-Pad2_ d_and +U6 /QA /QB Net-_U6-Pad3_ d_and +U9 Net-_U6-Pad3_ /QC Net-_U10-Pad1_ d_and +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_or +U1 /R91 /CLK /R01 /JK ? ? ? ? /QA /QB /QC /QD PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out new file mode 100644 index 00000000..b942ea4d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.cir.out @@ -0,0 +1,52 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir + +* u2 /jk /jk /clk /r01 /r91 /qa ? d_jkff +* u4 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? d_jkff +* u8 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? d_jkff +* u11 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ d_jkff +* u3 net-_u11-pad7_ /qa net-_u3-pad3_ d_and +* u5 /qa /qb net-_u5-pad3_ d_and +* u7 /qa /qd net-_u10-pad2_ d_and +* u6 /qa /qb net-_u6-pad3_ d_and +* u9 net-_u6-pad3_ /qc net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u1 /r91 /clk /r01 /jk ? ? ? ? /qa /qb /qc /qd port +a1 /jk /jk /clk /r01 /r91 /qa ? u2 +a2 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? u4 +a3 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? u8 +a4 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ u11 +a5 [net-_u11-pad7_ /qa ] net-_u3-pad3_ u3 +a6 [/qa /qb ] net-_u5-pad3_ u5 +a7 [/qa /qd ] net-_u10-pad2_ u7 +a8 [/qa /qb ] net-_u6-pad3_ u6 +a9 [net-_u6-pad3_ /qc ] net-_u10-pad1_ u9 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u4 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u8 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u11 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch new file mode 100644 index 00000000..b8a1d6e2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sch @@ -0,0 +1,494 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_jkff U2 +U 1 1 6825B2FF +P 2800 3400 +F 0 "U2" H 2800 3400 60 0000 C CNN +F 1 "d_jkff" H 2850 3550 60 0000 C CNN +F 2 "" H 2800 3400 60 0000 C CNN +F 3 "" H 2800 3400 60 0000 C CNN + 1 2800 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U4 +U 1 1 6825B328 +P 5000 3400 +F 0 "U4" H 5000 3400 60 0000 C CNN +F 1 "d_jkff" H 5050 3550 60 0000 C CNN +F 2 "" H 5000 3400 60 0000 C CNN +F 3 "" H 5000 3400 60 0000 C CNN + 1 5000 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U8 +U 1 1 6825B407 +P 7250 3400 +F 0 "U8" H 7250 3400 60 0000 C CNN +F 1 "d_jkff" H 7300 3550 60 0000 C CNN +F 2 "" H 7250 3400 60 0000 C CNN +F 3 "" H 7250 3400 60 0000 C CNN + 1 7250 3400 + 1 0 0 -1 +$EndComp +$Comp +L d_jkff U11 +U 1 1 6825B40D +P 9450 3400 +F 0 "U11" H 9450 3400 60 0000 C CNN +F 1 "d_jkff" H 9500 3550 60 0000 C CNN +F 2 "" H 9450 3400 60 0000 C CNN +F 3 "" H 9450 3400 60 0000 C CNN + 1 9450 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 2650 9450 2650 +Connection ~ 5000 2650 +Connection ~ 7250 2650 +Wire Wire Line + 2800 4200 9450 4200 +Connection ~ 7250 4200 +Connection ~ 5000 4200 +Wire Wire Line + 3550 800 3550 2650 +Wire Wire Line + 1850 800 3550 800 +Connection ~ 3550 2650 +Wire Wire Line + 2000 3850 1850 3850 +Wire Wire Line + 1850 3850 1850 1100 +Wire Wire Line + 2000 3000 1850 3000 +Connection ~ 1850 3000 +Wire Wire Line + 2000 3400 1750 3400 +Wire Wire Line + 1750 1400 1750 4600 +Wire Wire Line + 1750 4600 8350 4600 +Wire Wire Line + 3950 4600 3950 3400 +Wire Wire Line + 3950 3400 4200 3400 +Connection ~ 1750 3400 +Wire Wire Line + 6150 4600 6150 3400 +Wire Wire Line + 6150 3400 6450 3400 +Connection ~ 3950 4600 +Wire Wire Line + 8350 4600 8350 3400 +Wire Wire Line + 8350 3400 8650 3400 +Connection ~ 6150 4600 +$Comp +L d_and U3 +U 1 1 6825B512 +P 4200 1600 +F 0 "U3" H 4200 1600 60 0000 C CNN +F 1 "d_and" H 4250 1700 60 0000 C CNN +F 2 "" H 4200 1600 60 0000 C CNN +F 3 "" H 4200 1600 60 0000 C CNN + 1 4200 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3750 1600 3750 5850 +Wire Wire Line + 3750 3000 3600 3000 +Connection ~ 3750 3000 +NoConn ~ 3600 3850 +NoConn ~ 5800 3850 +NoConn ~ 8050 3850 +Wire Wire Line + 4200 3000 4200 2000 +Wire Wire Line + 4200 2000 4650 2000 +Wire Wire Line + 4650 2000 4650 1550 +Wire Wire Line + 4200 3850 4050 3850 +Wire Wire Line + 4050 3850 4050 2950 +Wire Wire Line + 4050 2950 4200 2950 +Connection ~ 4200 2950 +$Comp +L d_and U5 +U 1 1 6825B774 +P 6150 1700 +F 0 "U5" H 6150 1700 60 0000 C CNN +F 1 "d_and" H 6200 1800 60 0000 C CNN +F 2 "" H 6150 1700 60 0000 C CNN +F 3 "" H 6150 1700 60 0000 C CNN + 1 6150 1700 + 1 0 0 -1 +$EndComp +$Comp +L d_and U7 +U 1 1 6825B7B9 +P 6600 1400 +F 0 "U7" H 6600 1400 60 0000 C CNN +F 1 "d_and" H 6650 1500 60 0000 C CNN +F 2 "" H 6600 1400 60 0000 C CNN +F 3 "" H 6600 1400 60 0000 C CNN + 1 6600 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1600 1100 +F 0 "U1" H 1650 1200 30 0000 C CNN +F 1 "PORT" H 1600 1100 30 0000 C CNN +F 2 "" H 1600 1100 60 0000 C CNN +F 3 "" H 1600 1100 60 0000 C CNN + 4 1600 1100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 6825C422 +P 1500 1400 +F 0 "U1" H 1550 1500 30 0000 C CNN +F 1 "PORT" H 1500 1400 30 0000 C CNN +F 2 "" H 1500 1400 60 0000 C CNN +F 3 "" H 1500 1400 60 0000 C CNN + 2 1500 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6825C479 +P 1400 1750 +F 0 "U1" H 1450 1850 30 0000 C CNN +F 1 "PORT" H 1400 1750 30 0000 C CNN +F 2 "" H 1400 1750 60 0000 C CNN +F 3 "" H 1400 1750 60 0000 C CNN + 1 1400 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 6825C4DE +P 3500 5850 +F 0 "U1" H 3550 5950 30 0000 C CNN +F 1 "PORT" H 3500 5850 30 0000 C CNN +F 2 "" H 3500 5850 60 0000 C CNN +F 3 "" H 3500 5850 60 0000 C CNN + 9 3500 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 6825C543 +P 5550 5850 +F 0 "U1" H 5600 5950 30 0000 C CNN +F 1 "PORT" H 5550 5850 30 0000 C CNN +F 2 "" H 5550 5850 60 0000 C CNN +F 3 "" H 5550 5850 60 0000 C CNN + 10 5550 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 6825C5B8 +P 8000 5850 +F 0 "U1" H 8050 5950 30 0000 C CNN +F 1 "PORT" H 8000 5850 30 0000 C CNN +F 2 "" H 8000 5850 60 0000 C CNN +F 3 "" H 8000 5850 60 0000 C CNN + 11 8000 5850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 6825C637 +P 10200 5850 +F 0 "U1" H 10250 5950 30 0000 C CNN +F 1 "PORT" H 10200 5850 30 0000 C CNN +F 2 "" H 10200 5850 60 0000 C CNN +F 3 "" H 10200 5850 60 0000 C CNN + 12 10200 5850 + 1 0 0 -1 +$EndComp +Text Label 2650 800 0 60 ~ 0 +R01 +$Comp +L PORT U1 +U 5 1 6825C6D3 +P 1750 5100 +F 0 "U1" H 1800 5200 30 0000 C CNN +F 1 "PORT" H 1750 5100 30 0000 C CNN +F 2 "" H 1750 5100 60 0000 C CNN +F 3 "" H 1750 5100 60 0000 C CNN + 5 1750 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 5100 2600 5100 +NoConn ~ 2600 5100 +Text Label 2250 5100 0 60 ~ 0 +R02 +Text Label 1850 1200 0 60 ~ 0 +JK +Text Label 1750 1600 0 60 ~ 0 +CLK +Text Label 1650 2200 0 60 ~ 0 +R91 +$Comp +L PORT U1 +U 6 1 6825C88D +P 1750 5450 +F 0 "U1" H 1800 5550 30 0000 C CNN +F 1 "PORT" H 1750 5450 30 0000 C CNN +F 2 "" H 1750 5450 60 0000 C CNN +F 3 "" H 1750 5450 60 0000 C CNN + 6 1750 5450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2000 5450 2600 5450 +NoConn ~ 2600 5450 +Text Label 2300 5450 0 60 ~ 0 +R92 +Text Label 3750 5050 0 60 ~ 0 +QA +Text Label 5800 4950 0 60 ~ 0 +QB +Text Label 8250 4900 0 60 ~ 0 +QC +Text Label 10450 4800 0 60 ~ 0 +QD +$Comp +L PORT U1 +U 7 1 6825CE65 +P 1750 5800 +F 0 "U1" H 1800 5900 30 0000 C CNN +F 1 "PORT" H 1750 5800 30 0000 C CNN +F 2 "" H 1750 5800 60 0000 C CNN +F 3 "" H 1750 5800 60 0000 C CNN + 7 1750 5800 + 1 0 0 -1 +$EndComp +NoConn ~ 2000 5800 +$Comp +L PORT U1 +U 8 1 6825CEDB +P 1750 6000 +F 0 "U1" H 1800 6100 30 0000 C CNN +F 1 "PORT" H 1750 6000 30 0000 C CNN +F 2 "" H 1750 6000 60 0000 C CNN +F 3 "" H 1750 6000 60 0000 C CNN + 8 1750 6000 + 1 0 0 -1 +$EndComp +NoConn ~ 2000 6000 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub new file mode 100644 index 00000000..1830a145 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90.sub @@ -0,0 +1,46 @@ +* Subcircuit 74ls90 +.subckt 74ls90 /r91 /clk /r01 /jk ? ? ? ? /qa /qb /qc /qd +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ls90\74ls90.cir +* u2 /jk /jk /clk /r01 /r91 /qa ? d_jkff +* u4 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? d_jkff +* u8 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? d_jkff +* u11 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ d_jkff +* u3 net-_u11-pad7_ /qa net-_u3-pad3_ d_and +* u5 /qa /qb net-_u5-pad3_ d_and +* u7 /qa /qd net-_u10-pad2_ d_and +* u6 /qa /qb net-_u6-pad3_ d_and +* u9 net-_u6-pad3_ /qc net-_u10-pad1_ d_and +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +a1 /jk /jk /clk /r01 /r91 /qa ? u2 +a2 net-_u3-pad3_ net-_u3-pad3_ /clk /r01 /r91 /qb ? u4 +a3 net-_u5-pad3_ net-_u5-pad3_ /clk /r01 /r91 /qc ? u8 +a4 net-_u10-pad3_ net-_u10-pad3_ /clk /r01 /r91 /qd net-_u11-pad7_ u11 +a5 [net-_u11-pad7_ /qa ] net-_u3-pad3_ u3 +a6 [/qa /qb ] net-_u5-pad3_ u5 +a7 [/qa /qd ] net-_u10-pad2_ u7 +a8 [/qa /qb ] net-_u6-pad3_ u6 +a9 [net-_u6-pad3_ /qc ] net-_u10-pad1_ u9 +a10 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u2 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u4 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u8 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_jkff, NgSpice Name: d_jkff +.model u11 d_jkff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 jk_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74ls90
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml new file mode 100644 index 00000000..05fccb1a --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/74ls90_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_jkff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for JK Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u2><u4 name="type">d_jkff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for JK Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u4><u8 name="type">d_jkff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for JK Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u8><u11 name="type">d_jkff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for JK Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u11><u3 name="type">d_and<field41 name="Enter Rise Delay (default=1.0e-9)" /><field42 name="Enter Fall Delay (default=1.0e-9)" /><field43 name="Enter Input Load (default=1.0e-12)" /></u3><u5 name="type">d_and<field44 name="Enter Rise Delay (default=1.0e-9)" /><field45 name="Enter Fall Delay (default=1.0e-9)" /><field46 name="Enter Input Load (default=1.0e-12)" /></u5><u7 name="type">d_and<field47 name="Enter Rise Delay (default=1.0e-9)" /><field48 name="Enter Fall Delay (default=1.0e-9)" /><field49 name="Enter Input Load (default=1.0e-12)" /></u7><u6 name="type">d_and<field50 name="Enter Rise Delay (default=1.0e-9)" /><field51 name="Enter Fall Delay (default=1.0e-9)" /><field52 name="Enter Input Load (default=1.0e-12)" /></u6><u9 name="type">d_and<field53 name="Enter Rise Delay (default=1.0e-9)" /><field54 name="Enter Fall Delay (default=1.0e-9)" /><field55 name="Enter Input Load (default=1.0e-12)" /></u9><u10 name="type">d_or<field56 name="Enter Rise Delay (default=1.0e-9)" /><field57 name="Enter Fall Delay (default=1.0e-9)" /><field58 name="Enter Input Load (default=1.0e-12)" /></u10></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis new file mode 100644 index 00000000..af548eb1 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/analysis @@ -0,0 +1 @@ +.tran 0.1e-06 100e-06 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib new file mode 100644 index 00000000..6ac291da --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90-cache.lib @@ -0,0 +1,147 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 54LS90 +# +DEF 54LS90 X 0 40 Y Y 1 F N +F0 "X" -100 -550 60 H V C CNN +F1 "54LS90" 50 1100 60 H V C CNN +F2 "" 50 1100 60 H I C CNN +F3 "" 50 1100 60 H I C CNN +DRAW +S 300 1000 -400 -400 0 1 0 N +X R91 1 -600 100 200 R 50 50 1 1 I +X CLK 2 -600 300 200 R 50 50 1 1 I +X R01 3 -600 900 200 R 50 50 1 1 I +X JK 4 -600 500 200 R 50 50 1 1 I +X R02 5 -600 700 200 R 50 50 1 1 I +X R92 6 -600 -100 200 R 50 50 1 1 I +X VCC 7 -600 -300 200 R 50 50 1 1 I +X GND 8 500 900 200 L 50 50 1 1 O +X QA 9 500 700 200 L 50 50 1 1 O +X QB 10 500 500 200 L 50 50 1 1 O +X QC 11 500 300 200 L 50 50 1 1 O +X QD 12 500 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_4 +# +DEF dac_bridge_4 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_4" 0 300 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 350 350 -200 0 1 0 N +X IN1 1 -550 200 200 R 50 50 1 1 I +X IN2 2 -550 100 200 R 50 50 1 1 I +X IN3 3 -550 0 200 R 50 50 1 1 I +X IN4 4 -550 -100 200 R 50 50 1 1 I +X OUT1 5 550 200 200 L 50 50 1 1 O +X OUT2 6 550 100 200 L 50 50 1 1 O +X OUT3 7 550 0 200 L 50 50 1 1 O +X OUT4 8 550 -100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir new file mode 100644 index 00000000..1374b669 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir @@ -0,0 +1,29 @@ +* C:\Users\Shanthipriya\eSim-Workspace\sn74ls90\sn74ls90.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 05/15/25 17:30:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U4-Pad2_ clock Net-_U3-Pad2_ Net-_U1-Pad2_ ? ? ? ? Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ 54LS90 +v3 Net-_U2-Pad1_ GND pulse +U2 Net-_U2-Pad1_ clock adc_bridge_1 +U5 clock plot_v1 +v1 Net-_U1-Pad1_ GND DC +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ adc_bridge_1 +v2 Net-_U3-Pad1_ GND DC +U3 Net-_U3-Pad1_ Net-_U3-Pad2_ adc_bridge_1 +v4 Net-_U4-Pad1_ GND DC +U4 Net-_U4-Pad1_ Net-_U4-Pad2_ adc_bridge_1 +U6 QA plot_v1 +U7 QB plot_v1 +U8 QC plot_v1 +U9 QD plot_v1 +R4 QD GND 10K +R3 QC GND 10K +R2 QB GND 10K +R1 QA GND 10K +U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ QA QB QC QD dac_bridge_4 + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out new file mode 100644 index 00000000..61732f8b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.cir.out @@ -0,0 +1,47 @@ +* c:\users\shanthipriya\esim-workspace\sn74ls90\sn74ls90.cir + +.include 74ls90.sub +x1 net-_u4-pad2_ clock net-_u3-pad2_ net-_u1-pad2_ ? ? ? ? net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ 74ls90 +v3 net-_u2-pad1_ gnd pulse(0 5 0 1n 1n 5u 10u) +* u2 net-_u2-pad1_ clock adc_bridge_1 +* u5 clock plot_v1 +v1 net-_u1-pad1_ gnd dc 5 +* u1 net-_u1-pad1_ net-_u1-pad2_ adc_bridge_1 +v2 net-_u3-pad1_ gnd dc 1 +* u3 net-_u3-pad1_ net-_u3-pad2_ adc_bridge_1 +v4 net-_u4-pad1_ gnd dc 1 +* u4 net-_u4-pad1_ net-_u4-pad2_ adc_bridge_1 +* u6 qa plot_v1 +* u7 qb plot_v1 +* u8 qc plot_v1 +* u9 qd plot_v1 +r4 qd gnd 10k +r3 qc gnd 10k +r2 qb gnd 10k +r1 qa gnd 10k +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ qa qb qc qd dac_bridge_4 +a1 [net-_u2-pad1_ ] [clock ] u2 +a2 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +a3 [net-_u3-pad1_ ] [net-_u3-pad2_ ] u3 +a4 [net-_u4-pad1_ ] [net-_u4-pad2_ ] u4 +a5 [net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ ] [qa qb qc qd ] u10 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_4, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0.1e-06 100e-06 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(qd)+6 v(qc)+12 v(qb)+18v(qa)+24 v(clock) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj new file mode 100644 index 00000000..015ebc9c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.proj @@ -0,0 +1 @@ +schematicFile sn74ls90.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch new file mode 100644 index 00000000..3cd9bdbf --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90.sch @@ -0,0 +1,440 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L 54LS90 X1 +U 1 1 6825C471 +P 5500 3450 +F 0 "X1" H 5400 2900 60 0000 C CNN +F 1 "54LS90" H 5550 4550 60 0000 C CNN +F 2 "" H 5550 4550 60 0001 C CNN +F 3 "" H 5550 4550 60 0001 C CNN + 1 5500 3450 + 1 0 0 -1 +$EndComp +$Comp +L pulse v3 +U 1 1 6825C505 +P 1050 3450 +F 0 "v3" H 850 3550 60 0000 C CNN +F 1 "pulse" H 850 3400 60 0000 C CNN +F 2 "R1" H 750 3450 60 0000 C CNN +F 3 "" H 1050 3450 60 0000 C CNN + 1 1050 3450 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 6825C540 +P 1050 4200 +F 0 "#PWR01" H 1050 3950 50 0001 C CNN +F 1 "GND" H 1050 4050 50 0000 C CNN +F 2 "" H 1050 4200 50 0001 C CNN +F 3 "" H 1050 4200 50 0001 C CNN + 1 1050 4200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1050 4200 1050 3900 +$Comp +L adc_bridge_1 U2 +U 1 1 6825C55C +P 1950 3050 +F 0 "U2" H 1950 3050 60 0000 C CNN +F 1 "adc_bridge_1" H 1950 3200 60 0000 C CNN +F 2 "" H 1950 3050 60 0000 C CNN +F 3 "" H 1950 3050 60 0000 C CNN + 1 1950 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 3000 1050 3000 +Wire Wire Line + 2500 3000 2850 3000 +Wire Wire Line + 2850 3000 2850 3150 +Wire Wire Line + 2850 3150 4900 3150 +$Comp +L plot_v1 U5 +U 1 1 6825C5C6 +P 2850 3200 +F 0 "U5" H 2850 3700 60 0000 C CNN +F 1 "plot_v1" H 3050 3550 60 0000 C CNN +F 2 "" H 2850 3200 60 0000 C CNN +F 3 "" H 2850 3200 60 0000 C CNN + 1 2850 3200 + 1 0 0 -1 +$EndComp +Text GLabel 2500 2750 0 60 Input ~ 0 +clock +Wire Wire Line + 2500 2750 2600 2750 +Wire Wire Line + 2600 2750 2600 3000 +Connection ~ 2600 3000 +$Comp +L DC v1 +U 1 1 6825C612 +P 900 2350 +F 0 "v1" H 700 2450 60 0000 C CNN +F 1 "DC" H 700 2300 60 0000 C CNN +F 2 "R1" H 600 2350 60 0000 C CNN +F 3 "" H 900 2350 60 0000 C CNN + 1 900 2350 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 6825C703 +P 900 3000 +F 0 "#PWR02" H 900 2750 50 0001 C CNN +F 1 "GND" H 900 2850 50 0000 C CNN +F 2 "" H 900 3000 50 0001 C CNN +F 3 "" H 900 3000 50 0001 C CNN + 1 900 3000 + 1 0 0 -1 +$EndComp +Wire Wire Line + 900 3000 900 2800 +Wire Wire Line + 3300 2950 4900 2950 +$Comp +L adc_bridge_1 U1 +U 1 1 6825CB17 +P 1900 1950 +F 0 "U1" H 1900 1950 60 0000 C CNN +F 1 "adc_bridge_1" H 1900 2100 60 0000 C CNN +F 2 "" H 1900 1950 60 0000 C CNN +F 3 "" H 1900 1950 60 0000 C CNN + 1 1900 1950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2450 1900 3300 1900 +Wire Wire Line + 3300 1900 3300 2950 +Wire Wire Line + 1300 1900 900 1900 +$Comp +L DC v2 +U 1 1 6825CCA7 +P 1000 1150 +F 0 "v2" H 800 1250 60 0000 C CNN +F 1 "DC" H 800 1100 60 0000 C CNN +F 2 "R1" H 700 1150 60 0000 C CNN +F 3 "" H 1000 1150 60 0000 C CNN + 1 1000 1150 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U3 +U 1 1 6825CCAD +P 2000 750 +F 0 "U3" H 2000 750 60 0000 C CNN +F 1 "adc_bridge_1" H 2000 900 60 0000 C CNN +F 2 "" H 2000 750 60 0000 C CNN +F 3 "" H 2000 750 60 0000 C CNN + 1 2000 750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 700 3400 700 +Wire Wire Line + 1400 700 1000 700 +$Comp +L GND #PWR03 +U 1 1 6825CCD8 +P 1000 1600 +F 0 "#PWR03" H 1000 1350 50 0001 C CNN +F 1 "GND" H 1000 1450 50 0000 C CNN +F 2 "" H 1000 1600 50 0001 C CNN +F 3 "" H 1000 1600 50 0001 C CNN + 1 1000 1600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3400 700 3400 2550 +Wire Wire Line + 3400 2550 4900 2550 +$Comp +L DC v4 +U 1 1 6825CE12 +P 1550 4100 +F 0 "v4" H 1350 4200 60 0000 C CNN +F 1 "DC" H 1350 4050 60 0000 C CNN +F 2 "R1" H 1250 4100 60 0000 C CNN +F 3 "" H 1550 4100 60 0000 C CNN + 1 1550 4100 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_1 U4 +U 1 1 6825CE18 +P 2550 3700 +F 0 "U4" H 2550 3700 60 0000 C CNN +F 1 "adc_bridge_1" H 2550 3850 60 0000 C CNN +F 2 "" H 2550 3700 60 0000 C CNN +F 3 "" H 2550 3700 60 0000 C CNN + 1 2550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 3650 3950 3650 +Wire Wire Line + 1950 3650 1550 3650 +$Comp +L GND #PWR04 +U 1 1 6825CE20 +P 1550 4550 +F 0 "#PWR04" H 1550 4300 50 0001 C CNN +F 1 "GND" H 1550 4400 50 0000 C CNN +F 2 "" H 1550 4550 50 0001 C CNN +F 3 "" H 1550 4550 50 0001 C CNN + 1 1550 4550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3950 3650 3950 3350 +Wire Wire Line + 3950 3350 4900 3350 +$Comp +L plot_v1 U6 +U 1 1 6825CE66 +P 8400 2900 +F 0 "U6" H 8400 3400 60 0000 C CNN +F 1 "plot_v1" H 8600 3250 60 0000 C CNN +F 2 "" H 8400 2900 60 0000 C CNN +F 3 "" H 8400 2900 60 0000 C CNN + 1 8400 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 6825CEA5 +P 8900 2900 +F 0 "U7" H 8900 3400 60 0000 C CNN +F 1 "plot_v1" H 9100 3250 60 0000 C CNN +F 2 "" H 8900 2900 60 0000 C CNN +F 3 "" H 8900 2900 60 0000 C CNN + 1 8900 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 6825CF44 +P 9350 2900 +F 0 "U8" H 9350 3400 60 0000 C CNN +F 1 "plot_v1" H 9550 3250 60 0000 C CNN +F 2 "" H 9350 2900 60 0000 C CNN +F 3 "" H 9350 2900 60 0000 C CNN + 1 9350 2900 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 6825CF4A +P 9850 2900 +F 0 "U9" H 9850 3400 60 0000 C CNN +F 1 "plot_v1" H 10050 3250 60 0000 C CNN +F 2 "" H 9850 2900 60 0000 C CNN +F 3 "" H 9850 2900 60 0000 C CNN + 1 9850 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7500 2700 8400 2700 +Wire Wire Line + 8900 2700 8900 2900 +Wire Wire Line + 8900 2900 7750 2900 +Wire Wire Line + 9350 2700 9350 3100 +Wire Wire Line + 9350 3100 7750 3100 +Wire Wire Line + 7500 3300 9850 3300 +Wire Wire Line + 9850 3300 9850 2700 +Text GLabel 8050 3600 0 60 Input ~ 0 +QA +Wire Wire Line + 8050 3600 8050 2700 +Connection ~ 8050 2700 +Text GLabel 8250 3800 0 60 Input ~ 0 +QB +Wire Wire Line + 8250 3800 8250 2900 +Connection ~ 8250 2900 +Text GLabel 8500 4000 0 60 Input ~ 0 +QC +Text GLabel 8700 4200 0 60 Input ~ 0 +QD +Wire Wire Line + 8550 4000 8500 4000 +Wire Wire Line + 8550 3100 8550 4000 +Connection ~ 8550 3100 +Wire Wire Line + 8700 4200 8800 4200 +Wire Wire Line + 8800 4200 8800 3300 +Connection ~ 8800 3300 +$Comp +L resistor R4 +U 1 1 6825D1F5 +P 9950 3350 +F 0 "R4" H 10000 3480 50 0000 C CNN +F 1 "10K" H 10000 3300 50 0000 C CNN +F 2 "" H 10000 3330 30 0000 C CNN +F 3 "" V 10000 3400 30 0000 C CNN + 1 9950 3350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R3 +U 1 1 6825D252 +P 9450 3150 +F 0 "R3" H 9500 3280 50 0000 C CNN +F 1 "10K" H 9500 3100 50 0000 C CNN +F 2 "" H 9500 3130 30 0000 C CNN +F 3 "" V 9500 3200 30 0000 C CNN + 1 9450 3150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R2 +U 1 1 6825D2B5 +P 9000 2950 +F 0 "R2" H 9050 3080 50 0000 C CNN +F 1 "10K" H 9050 2900 50 0000 C CNN +F 2 "" H 9050 2930 30 0000 C CNN +F 3 "" V 9050 3000 30 0000 C CNN + 1 9000 2950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 6825D326 +P 8500 2750 +F 0 "R1" H 8550 2880 50 0000 C CNN +F 1 "10K" H 8550 2700 50 0000 C CNN +F 2 "" H 8550 2730 30 0000 C CNN +F 3 "" V 8550 2800 30 0000 C CNN + 1 8500 2750 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR05 +U 1 1 6825D38D +P 10900 3350 +F 0 "#PWR05" H 10900 3100 50 0001 C CNN +F 1 "GND" H 10900 3200 50 0000 C CNN +F 2 "" H 10900 3350 50 0001 C CNN +F 3 "" H 10900 3350 50 0001 C CNN + 1 10900 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8700 2700 10900 2700 +Wire Wire Line + 10900 2700 10900 3350 +Wire Wire Line + 10150 3300 10900 3300 +Connection ~ 10900 3300 +Wire Wire Line + 9650 3100 10900 3100 +Connection ~ 10900 3100 +Wire Wire Line + 9200 2900 10900 2900 +Connection ~ 10900 2900 +$Comp +L dac_bridge_4 U10 +U 1 1 6825D8D1 +P 6950 3050 +F 0 "U10" H 6950 3050 60 0000 C CNN +F 1 "dac_bridge_4" H 6950 3350 60 0000 C CNN +F 2 "" H 6950 3050 60 0000 C CNN +F 3 "" H 6950 3050 60 0000 C CNN + 1 6950 3050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6400 2850 6400 2750 +Wire Wire Line + 6400 2750 6000 2750 +Wire Wire Line + 6400 2950 6000 2950 +Wire Wire Line + 6400 3050 6000 3050 +Wire Wire Line + 6000 3050 6000 3150 +Wire Wire Line + 6400 3150 6400 3350 +Wire Wire Line + 6400 3350 6000 3350 +Wire Wire Line + 7500 2850 7500 2700 +Wire Wire Line + 7500 2950 7750 2950 +Wire Wire Line + 7750 2950 7750 2900 +Wire Wire Line + 7500 3050 7750 3050 +Wire Wire Line + 7750 3050 7750 3100 +Wire Wire Line + 7500 3150 7500 3300 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml new file mode 100644 index 00000000..36b30476 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls90/sn54ls90_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">5u</field5><field5 name="Period">10u</field5></v3><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v2 name="Source type">dc<field1 name="Value">1</field1></v2><v4 name="Source type">dc<field1 name="Value">1</field1></v4></source><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u1 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u1><u3 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u4><u10 name="type">dac_bridge<field17 name="Enter value for out_low (default=0.0)" /><field18 name="Enter value for out_high (default=5.0)" /><field19 name="Enter value for out_undef (default=0.5)" /><field20 name="Enter value for input load (default=1.0e-12)" /><field21 name="Enter the Rise Time (default=1.0e-9)" /><field22 name="Enter the Fall Time (default=1.0e-9)" /></u10></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74ls90</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.1</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">us</field6></tran></analysis></KicadtoNgspice>
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