1 files changed, 40 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out
new file mode 100644
index 00000000..ec11a6c2
--- /dev/null
+++ b/library/SubcircuitLibrary/esim_ic_files/sn54ls72/internalsn54ls72.cir.out
@@ -0,0 +1,40 @@
+* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\internal72\internal72.cir
+
+* u3  net-_u3-pad1_ net-_u1-pad1_ net-_u3-pad3_ d_nand
+* u4  net-_u2-pad2_ net-_u4-pad2_ net-_u4-pad3_ d_nand
+* u5  net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_nand
+* u2  net-_u1-pad3_ net-_u2-pad2_ d_inverter
+* u7  net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ d_dff
+* u8  net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ d_dff
+* u6  net-_u1-pad2_ net-_u6-pad2_ d_inverter
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ? ? net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ port
+a1 [net-_u3-pad1_ net-_u1-pad1_ ] net-_u3-pad3_ u3
+a2 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5
+a4 net-_u1-pad3_ net-_u2-pad2_ u2
+a5 net-_u5-pad3_ net-_u1-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad2_ net-_u3-pad1_ u7
+a6 net-_u4-pad2_ net-_u6-pad2_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ u8
+a7 net-_u1-pad2_ net-_u6-pad2_ u6
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u7 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u8 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end