diff options
Diffstat (limited to 'library/SubcircuitLibrary/esim_ic_files/cdx4ac283')
30 files changed, 2221 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib new file mode 100644 index 00000000..007a4e66 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283-cache.lib @@ -0,0 +1,117 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# adc_bridge_2 +# +DEF adc_bridge_2 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_2" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -100 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X OUT1 3 550 50 200 L 50 50 1 1 O +X OUT2 4 550 -50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# adc_bridge_3 +# +DEF adc_bridge_3 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_3" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -200 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X OUT1 4 550 50 200 L 50 50 1 1 O +X OUT2 5 550 -50 200 L 50 50 1 1 O +X OUT3 6 550 -150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_5 +# +DEF dac_bridge_5 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_5" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -400 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X IN2 2 -600 -50 200 R 50 50 1 1 I +X IN3 3 -600 -150 200 R 50 50 1 1 I +X IN4 4 -600 -250 200 R 50 50 1 1 I +X IN5 5 -600 -350 200 R 50 50 1 1 I +X OUT1 6 550 50 200 L 50 50 1 1 O +X OUT2 7 550 -50 200 L 50 50 1 1 O +X OUT3 8 550 -150 200 L 50 50 1 1 O +X OUT4 9 550 -250 200 L 50 50 1 1 O +X OUT5 10 550 -350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# full_adder +# +DEF full_adder X 0 40 Y Y 1 F N +F0 "X" 1400 700 60 H V C CNN +F1 "full_adder" 1400 600 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 800 1150 1950 0 0 1 0 N +X IN1 1 600 950 200 R 50 50 1 1 I +X IN2 2 600 550 200 R 50 50 1 1 I +X CIN 3 600 150 200 R 50 50 1 1 I +X SUM 4 2150 950 200 L 50 50 1 1 O +X COUT 5 2150 150 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir new file mode 100644 index 00000000..61d06ffa --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir @@ -0,0 +1,20 @@ +* C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74AC283\74AC283.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/07/25 22:10:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X1 Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ Net-_U6-Pad1_ Net-_X1-Pad5_ full_adder +X2 Net-_U3-Pad3_ Net-_U3-Pad4_ Net-_X1-Pad5_ Net-_U6-Pad2_ Net-_X2-Pad5_ full_adder +X3 Net-_U4-Pad3_ Net-_U4-Pad4_ Net-_X2-Pad5_ Net-_U6-Pad3_ Net-_X3-Pad5_ full_adder +X4 Net-_U5-Pad3_ Net-_U5-Pad4_ Net-_X3-Pad5_ Net-_U6-Pad4_ Net-_U6-Pad5_ full_adder +U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad4_ Net-_U2-Pad5_ Net-_U2-Pad6_ adc_bridge_3 +U3 Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U3-Pad3_ Net-_U3-Pad4_ adc_bridge_2 +U4 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U4-Pad3_ Net-_U4-Pad4_ adc_bridge_2 +U5 Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U5-Pad3_ Net-_U5-Pad4_ adc_bridge_2 +U6 Net-_U6-Pad1_ Net-_U6-Pad2_ Net-_U6-Pad3_ Net-_U6-Pad4_ Net-_U6-Pad5_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ dac_bridge_5 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ ? ? PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out new file mode 100644 index 00000000..c177727e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.cir.out @@ -0,0 +1,37 @@ +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ac283\74ac283.cir + +.include full_adder.sub +x1 net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u6-pad1_ net-_x1-pad5_ full_adder +x2 net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ net-_u6-pad2_ net-_x2-pad5_ full_adder +x3 net-_u4-pad3_ net-_u4-pad4_ net-_x2-pad5_ net-_u6-pad3_ net-_x3-pad5_ full_adder +x4 net-_u5-pad3_ net-_u5-pad4_ net-_x3-pad5_ net-_u6-pad4_ net-_u6-pad5_ full_adder +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ net-_u3-pad4_ adc_bridge_2 +* u4 net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2 +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_5 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? port +a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] [net-_u3-pad3_ net-_u3-pad4_ ] u3 +a3 [net-_u1-pad6_ net-_u1-pad7_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +a4 [net-_u1-pad8_ net-_u1-pad9_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5 +a5 [net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ ] [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u6 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro new file mode 100644 index 00000000..e27a398b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.pro @@ -0,0 +1,73 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +LibName39=eSim_SKY130 +LibName40=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch new file mode 100644 index 00000000..d10df53c --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sch @@ -0,0 +1,449 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L full_adder X1 +U 1 1 67F3F735 +P 3500 2250 +F 0 "X1" H 4900 2950 60 0000 C CNN +F 1 "full_adder" H 4900 2850 60 0000 C CNN +F 2 "" H 3500 2250 60 0000 C CNN +F 3 "" H 3500 2250 60 0000 C CNN + 1 3500 2250 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X2 +U 1 1 67F3F786 +P 3550 3700 +F 0 "X2" H 4950 4400 60 0000 C CNN +F 1 "full_adder" H 4950 4300 60 0000 C CNN +F 2 "" H 3550 3700 60 0000 C CNN +F 3 "" H 3550 3700 60 0000 C CNN + 1 3550 3700 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X3 +U 1 1 67F3F7B7 +P 3550 5050 +F 0 "X3" H 4950 5750 60 0000 C CNN +F 1 "full_adder" H 4950 5650 60 0000 C CNN +F 2 "" H 3550 5050 60 0000 C CNN +F 3 "" H 3550 5050 60 0000 C CNN + 1 3550 5050 + 1 0 0 -1 +$EndComp +$Comp +L full_adder X4 +U 1 1 67F3F822 +P 3600 6550 +F 0 "X4" H 5000 7250 60 0000 C CNN +F 1 "full_adder" H 5000 7150 60 0000 C CNN +F 2 "" H 3600 6550 60 0000 C CNN +F 3 "" H 3600 6550 60 0000 C CNN + 1 3600 6550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5650 2100 5650 2450 +Wire Wire Line + 5650 2450 4000 2450 +Wire Wire Line + 4000 2450 4000 3550 +Wire Wire Line + 4000 3550 4150 3550 +Wire Wire Line + 5700 3550 5700 3800 +Wire Wire Line + 5700 3800 4000 3800 +Wire Wire Line + 4000 3800 4000 4900 +Wire Wire Line + 4000 4900 4150 4900 +Wire Wire Line + 5700 4900 5700 5300 +Wire Wire Line + 5700 5300 4000 5300 +Wire Wire Line + 4000 5300 4000 6400 +Wire Wire Line + 4000 6400 4200 6400 +$Comp +L adc_bridge_3 U2 +U 1 1 67F3F897 +P 3250 1600 +F 0 "U2" H 3250 1600 60 0000 C CNN +F 1 "adc_bridge_3" H 3250 1750 60 0000 C CNN +F 2 "" H 3250 1600 60 0000 C CNN +F 3 "" H 3250 1600 60 0000 C CNN + 1 3250 1600 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U3 +U 1 1 67F3F8CA +P 3350 2850 +F 0 "U3" H 3350 2850 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 3000 60 0000 C CNN +F 2 "" H 3350 2850 60 0000 C CNN +F 3 "" H 3350 2850 60 0000 C CNN + 1 3350 2850 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U4 +U 1 1 67F3F91B +P 3350 4250 +F 0 "U4" H 3350 4250 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 4400 60 0000 C CNN +F 2 "" H 3350 4250 60 0000 C CNN +F 3 "" H 3350 4250 60 0000 C CNN + 1 3350 4250 + 1 0 0 -1 +$EndComp +$Comp +L adc_bridge_2 U5 +U 1 1 67F3F95C +P 3350 5750 +F 0 "U5" H 3350 5750 60 0000 C CNN +F 1 "adc_bridge_2" H 3350 5900 60 0000 C CNN +F 2 "" H 3350 5750 60 0000 C CNN +F 3 "" H 3350 5750 60 0000 C CNN + 1 3350 5750 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_5 U6 +U 1 1 67F3F998 +P 7100 3350 +F 0 "U6" H 7100 3350 60 0000 C CNN +F 1 "dac_bridge_5" H 7100 3500 60 0000 C CNN +F 2 "" H 7100 3350 60 0000 C CNN +F 3 "" H 7100 3350 60 0000 C CNN + 1 7100 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 1550 3800 1300 +Wire Wire Line + 3800 1300 4100 1300 +Wire Wire Line + 3800 1650 4100 1650 +Wire Wire Line + 4100 1650 4100 1700 +Wire Wire Line + 3800 1750 3800 2100 +Wire Wire Line + 3800 2100 4100 2100 +Wire Wire Line + 3900 2800 4150 2800 +Wire Wire Line + 4150 2800 4150 2750 +Wire Wire Line + 3900 2900 4150 2900 +Wire Wire Line + 4150 2900 4150 3150 +Wire Wire Line + 3900 4200 4150 4200 +Wire Wire Line + 4150 4200 4150 4100 +Wire Wire Line + 3900 4300 4150 4300 +Wire Wire Line + 4150 4300 4150 4500 +Wire Wire Line + 3900 5700 4200 5700 +Wire Wire Line + 4200 5700 4200 5600 +Wire Wire Line + 3900 5800 4200 5800 +Wire Wire Line + 4200 5800 4200 6000 +Wire Wire Line + 5650 1300 6500 1300 +Wire Wire Line + 6500 1300 6500 3300 +Wire Wire Line + 5700 2750 6150 2750 +Wire Wire Line + 6150 2750 6150 3400 +Wire Wire Line + 6150 3400 6500 3400 +Wire Wire Line + 5700 4100 5800 4100 +Wire Wire Line + 5800 4100 5800 3500 +Wire Wire Line + 5800 3500 6500 3500 +Wire Wire Line + 5750 5600 5900 5600 +Wire Wire Line + 5900 5600 5900 3600 +Wire Wire Line + 5900 3600 6500 3600 +Wire Wire Line + 5750 6400 6000 6400 +Wire Wire Line + 6000 6400 6000 3700 +Wire Wire Line + 6000 3700 6500 3700 +$Comp +L PORT U1 +U 5 1 67F3FBD8 +P 1750 2900 +F 0 "U1" H 1800 3000 30 0000 C CNN +F 1 "PORT" H 1750 2900 30 0000 C CNN +F 2 "" H 1750 2900 60 0000 C CNN +F 3 "" H 1750 2900 60 0000 C CNN + 5 1750 2900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 67F3FC33 +P 1750 4200 +F 0 "U1" H 1800 4300 30 0000 C CNN +F 1 "PORT" H 1750 4200 30 0000 C CNN +F 2 "" H 1750 4200 60 0000 C CNN +F 3 "" H 1750 4200 60 0000 C CNN + 6 1750 4200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 67F3FC80 +P 1750 4300 +F 0 "U1" H 1800 4400 30 0000 C CNN +F 1 "PORT" H 1750 4300 30 0000 C CNN +F 2 "" H 1750 4300 60 0000 C CNN +F 3 "" H 1750 4300 60 0000 C CNN + 7 1750 4300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2050 1550 2650 1550 +Wire Wire Line + 2050 1650 2650 1650 +Wire Wire Line + 2000 1750 2650 1750 +$Comp +L PORT U1 +U 1 1 67F3FD74 +P 1800 1550 +F 0 "U1" H 1850 1650 30 0000 C CNN +F 1 "PORT" H 1800 1550 30 0000 C CNN +F 2 "" H 1800 1550 60 0000 C CNN +F 3 "" H 1800 1550 60 0000 C CNN + 1 1800 1550 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 67F3FDD5 +P 1800 1650 +F 0 "U1" H 1850 1750 30 0000 C CNN +F 1 "PORT" H 1800 1650 30 0000 C CNN +F 2 "" H 1800 1650 60 0000 C CNN +F 3 "" H 1800 1650 60 0000 C CNN + 2 1800 1650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 67F3FE38 +P 1750 1750 +F 0 "U1" H 1800 1850 30 0000 C CNN +F 1 "PORT" H 1750 1750 30 0000 C CNN +F 2 "" H 1750 1750 60 0000 C CNN +F 3 "" H 1750 1750 60 0000 C CNN + 3 1750 1750 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 67F3FEA1 +P 1750 2800 +F 0 "U1" H 1800 2900 30 0000 C CNN +F 1 "PORT" H 1750 2800 30 0000 C CNN +F 2 "" H 1750 2800 60 0000 C CNN +F 3 "" H 1750 2800 60 0000 C CNN + 4 1750 2800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 67F3FEEE +P 1850 5700 +F 0 "U1" H 1900 5800 30 0000 C CNN +F 1 "PORT" H 1850 5700 30 0000 C CNN +F 2 "" H 1850 5700 60 0000 C CNN +F 3 "" H 1850 5700 60 0000 C CNN + 8 1850 5700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 9 1 67F3FF3B +P 1850 5800 +F 0 "U1" H 1900 5900 30 0000 C CNN +F 1 "PORT" H 1850 5800 30 0000 C CNN +F 2 "" H 1850 5800 60 0000 C CNN +F 3 "" H 1850 5800 60 0000 C CNN + 9 1850 5800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 67F3FF88 +P 8100 3300 +F 0 "U1" H 8150 3400 30 0000 C CNN +F 1 "PORT" H 8100 3300 30 0000 C CNN +F 2 "" H 8100 3300 60 0000 C CNN +F 3 "" H 8100 3300 60 0000 C CNN + 10 8100 3300 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 67F3FFED +P 8100 3400 +F 0 "U1" H 8150 3500 30 0000 C CNN +F 1 "PORT" H 8100 3400 30 0000 C CNN +F 2 "" H 8100 3400 60 0000 C CNN +F 3 "" H 8100 3400 60 0000 C CNN + 11 8100 3400 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 67F40040 +P 8100 3500 +F 0 "U1" H 8150 3600 30 0000 C CNN +F 1 "PORT" H 8100 3500 30 0000 C CNN +F 2 "" H 8100 3500 60 0000 C CNN +F 3 "" H 8100 3500 60 0000 C CNN + 12 8100 3500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 67F40089 +P 8100 3600 +F 0 "U1" H 8150 3700 30 0000 C CNN +F 1 "PORT" H 8100 3600 30 0000 C CNN +F 2 "" H 8100 3600 60 0000 C CNN +F 3 "" H 8100 3600 60 0000 C CNN + 13 8100 3600 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 67F40102 +P 8100 3700 +F 0 "U1" H 8150 3800 30 0000 C CNN +F 1 "PORT" H 8100 3700 30 0000 C CNN +F 2 "" H 8100 3700 60 0000 C CNN +F 3 "" H 8100 3700 60 0000 C CNN + 14 8100 3700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2000 2800 2750 2800 +Wire Wire Line + 2000 2900 2750 2900 +Wire Wire Line + 2000 4200 2750 4200 +Wire Wire Line + 2000 4300 2750 4300 +Wire Wire Line + 2100 5700 2750 5700 +Wire Wire Line + 2100 5800 2750 5800 +Wire Wire Line + 7650 3300 7850 3300 +Wire Wire Line + 7650 3400 7850 3400 +Wire Wire Line + 7650 3500 7850 3500 +Wire Wire Line + 7650 3600 7850 3600 +Wire Wire Line + 7650 3700 7850 3700 +$Comp +L PORT U1 +U 15 1 67F40B32 +P 8400 4150 +F 0 "U1" H 8450 4250 30 0000 C CNN +F 1 "PORT" H 8400 4150 30 0000 C CNN +F 2 "" H 8400 4150 60 0000 C CNN +F 3 "" H 8400 4150 60 0000 C CNN + 15 8400 4150 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 67F40B8B +P 8400 4350 +F 0 "U1" H 8450 4450 30 0000 C CNN +F 1 "PORT" H 8400 4350 30 0000 C CNN +F 2 "" H 8400 4350 60 0000 C CNN +F 3 "" H 8400 4350 60 0000 C CNN + 16 8400 4350 + 1 0 0 -1 +$EndComp +NoConn ~ 8650 4150 +NoConn ~ 8650 4350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub new file mode 100644 index 00000000..368d89c9 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283.sub @@ -0,0 +1,31 @@ +* Subcircuit 74AC283 +.subckt 74AC283 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ? ? +* c:\users\shanthipriya\desktop\madeeasy\fossee\esim\library\subcircuitlibrary\74ac283\74ac283.cir +.include full_adder.sub +x1 net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ net-_u6-pad1_ net-_x1-pad5_ full_adder +x2 net-_u3-pad3_ net-_u3-pad4_ net-_x1-pad5_ net-_u6-pad2_ net-_x2-pad5_ full_adder +x3 net-_u4-pad3_ net-_u4-pad4_ net-_x2-pad5_ net-_u6-pad3_ net-_x3-pad5_ full_adder +x4 net-_u5-pad3_ net-_u5-pad4_ net-_x3-pad5_ net-_u6-pad4_ net-_u6-pad5_ full_adder +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ adc_bridge_3 +* u3 net-_u1-pad4_ net-_u1-pad5_ net-_u3-pad3_ net-_u3-pad4_ adc_bridge_2 +* u4 net-_u1-pad6_ net-_u1-pad7_ net-_u4-pad3_ net-_u4-pad4_ adc_bridge_2 +* u5 net-_u1-pad8_ net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad4_ adc_bridge_2 +* u6 net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ dac_bridge_5 +a1 [net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ ] [net-_u2-pad4_ net-_u2-pad5_ net-_u2-pad6_ ] u2 +a2 [net-_u1-pad4_ net-_u1-pad5_ ] [net-_u3-pad3_ net-_u3-pad4_ ] u3 +a3 [net-_u1-pad6_ net-_u1-pad7_ ] [net-_u4-pad3_ net-_u4-pad4_ ] u4 +a4 [net-_u1-pad8_ net-_u1-pad9_ ] [net-_u5-pad3_ net-_u5-pad4_ ] u5 +a5 [net-_u6-pad1_ net-_u6-pad2_ net-_u6-pad3_ net-_u6-pad4_ net-_u6-pad5_ ] [net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ ] u6 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u3 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u4 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u5 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_5, NgSpice Name: dac_bridge +.model u6 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Control Statements + +.ends 74AC283
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml new file mode 100644 index 00000000..e0fa4837 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/74AC283_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">adc_bridge<field1 name="Enter value for in_low (default=1.0)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter Fall Delay (default=1.0e-9)" /></u2><u3 name="type">adc_bridge<field5 name="Enter value for in_low (default=1.0)" /><field6 name="Enter value for in_high (default=2.0)" /><field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /></u3><u4 name="type">adc_bridge<field9 name="Enter value for in_low (default=1.0)" /><field10 name="Enter value for in_high (default=2.0)" /><field11 name="Enter Rise Delay (default=1.0e-9)" /><field12 name="Enter Fall Delay (default=1.0e-9)" /></u4><u5 name="type">adc_bridge<field13 name="Enter value for in_low (default=1.0)" /><field14 name="Enter value for in_high (default=2.0)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /><field16 name="Enter Fall Delay (default=1.0e-9)" /></u5><u6 name="type">dac_bridge<field17 name="Enter value for out_low (default=0.0)" /><field18 name="Enter value for out_high (default=5.0)" /><field19 name="Enter value for out_undef (default=0.5)" /><field20 name="Enter value for input load (default=1.0e-12)" /><field21 name="Enter the Rise Time (default=1.0e-9)" /><field22 name="Enter the Fall Time (default=1.0e-9)" /></u6></model><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x1><x2><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x2><x3><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x3><x4><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\full_adder</field></x4></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis new file mode 100644 index 00000000..1ff7c211 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/analysis @@ -0,0 +1 @@ +.tran 0.01e-06 2e-03 0e-00
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib new file mode 100644 index 00000000..0e92eab0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-cache.lib @@ -0,0 +1,81 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 283 +# +DEF 283 X 0 40 Y Y 1 F N +F0 "X" -400 100 60 H V C CNN +F1 "283" -350 1500 60 H V C CNN +F2 "" -350 1500 60 H I C CNN +F3 "" -350 1500 60 H I C CNN +DRAW +S 0 1400 -800 200 0 1 0 N +X A1 1 -1000 1200 200 R 50 50 1 1 I +X B1 2 -1000 750 200 R 50 50 1 1 I +X C0 3 -1000 1300 200 R 50 50 1 1 I +X A2 4 -1000 1100 200 R 50 50 1 1 I +X B2 5 -1000 650 200 R 50 50 1 1 I +X A3 6 -1000 1000 200 R 50 50 1 1 I +X B3 7 -1000 550 200 R 50 50 1 1 I +X A4 8 -1000 900 200 R 50 50 1 1 I +X B4 9 -1000 450 200 R 50 50 1 1 I +X S1 10 200 1050 200 L 50 50 1 1 O +X S2 11 200 950 200 L 50 50 1 1 O +X S3 12 200 850 200 L 50 50 1 1 O +X S4 13 200 750 200 L 50 50 1 1 O +X C_out 14 200 600 200 L 50 50 1 1 O +X GND 15 -1000 300 200 R 50 50 1 1 N +X vcc 16 200 1300 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib new file mode 100644 index 00000000..09091d02 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283-rescue.lib @@ -0,0 +1,32 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 283-RESCUE-4_bit_FA +# +DEF 283-RESCUE-4_bit_FA X 0 40 Y Y 1 F N +F0 "X" -400 100 60 H V C CNN +F1 "283-RESCUE-4_bit_FA" -350 1500 60 H V C CNN +F2 "" -350 1500 60 H I C CNN +F3 "" -350 1500 60 H I C CNN +DRAW +S 0 1400 -800 200 0 1 0 N +X A1 1 -1000 1200 200 R 50 50 1 1 I +X B1 2 -1000 750 200 R 50 50 1 1 I +X C0 3 -1000 1300 200 R 50 50 1 1 I +X A2 4 -1000 1100 200 R 50 50 1 1 I +X B2 5 -1000 650 200 R 50 50 1 1 I +X A3 6 -1000 1000 200 R 50 50 1 1 I +X B3 6 -1000 550 200 R 50 50 1 1 I +X A4 8 -1000 900 200 R 50 50 1 1 I +X B4 9 -1000 450 200 R 50 50 1 1 I +X S1 10 200 1050 200 L 50 50 1 1 O +X S2 11 200 950 200 L 50 50 1 1 O +X S3 12 200 850 200 L 50 50 1 1 O +X S4 13 200 750 200 L 50 50 1 1 O +X C_out 14 200 600 200 L 50 50 1 1 O +X GND 15 -1000 300 200 R 50 50 1 1 N +X vcc 16 200 1300 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir new file mode 100644 index 00000000..083e3772 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir @@ -0,0 +1,34 @@ +* C:\Users\Shanthipriya\eSim-Workspace\4_bit_FA\4_bit_FA.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 04/08/25 10:08:09 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 C0 plot_v1 +U3 A1 plot_v1 +U4 A2 plot_v1 +U5 A3 plot_v1 +U7 A4 plot_v1 +U1 B1 plot_v1 +U6 B4 plot_v1 +U8 B3 plot_v1 +U9 B2 plot_v1 +U10 S1 plot_v1 +U11 S2 plot_v1 +U12 S3 plot_v1 +U13 S4 plot_v1 +U14 C_out plot_v1 +X1 A1 B1 C0 A2 B2 A3 B3 A4 B4 S1 S2 S3 S4 C_out ? ? 283 +v1 C0 GND pulse +v2 A1 GND pulse +v3 A2 GND pulse +v4 A3 GND pulse +v5 A4 GND pulse +v6 B1 GND pulse +v7 B2 GND pulse +v8 B3 GND pulse +v9 B4 GND pulse + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out new file mode 100644 index 00000000..db240b25 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.cir.out @@ -0,0 +1,37 @@ +* c:\users\shanthipriya\esim-workspace\4_bit_fa\4_bit_fa.cir + +.include 74AC283.sub +* u2 c0 plot_v1 +* u3 a1 plot_v1 +* u4 a2 plot_v1 +* u5 a3 plot_v1 +* u7 a4 plot_v1 +* u1 b1 plot_v1 +* u6 b4 plot_v1 +* u8 b3 plot_v1 +* u9 b2 plot_v1 +* u10 s1 plot_v1 +* u11 s2 plot_v1 +* u12 s3 plot_v1 +* u13 s4 plot_v1 +* u14 c_out plot_v1 +x1 a1 b1 c0 a2 b2 a3 b3 a4 b4 s1 s2 s3 s4 c_out ? ? 74AC283 +v1 c0 gnd pulse(0 5 0 1n 1n 250u 5120u) +v2 a1 gnd pulse(0 5 0 1n 1n 10u 20u) +v3 a2 gnd pulse(0 5 0 1n 1n 20u 40u) +v4 a3 gnd pulse(0 5 0 1n 1n 40u 80u) +v5 a4 gnd pulse(0 5 0 1n 1n 80u 160u) +v6 b1 gnd pulse(0 5 0 1n 1n 160u 320u) +v7 b2 gnd pulse(0 5 0 1n 1n 320u 640u) +v8 b3 gnd pulse(0 5 0 1n 1n 640u 1280u) +v9 b4 gnd pulse(0 5 0 1n 1n 1280u 2560u) +.tran 0.01e-06 2e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(c0)+6v(a1)+12 v(a2)+18v(a3)+24 v(a4)+30 v(b1)+36 v(b2)+42 v(b3)+48v(b4)+54 v(s1)+60 v(s2)+66 v(s3)+72v(s4)+78v(c_out) +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro new file mode 100644 index 00000000..6dffef6e --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.pro @@ -0,0 +1,74 @@ +update=04/07/25 22:12:09 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=4_bit_FA-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri +LibName40=eSim_SKY130 +LibName41=eSim_SKY130_Subckts diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj new file mode 100644 index 00000000..74da6851 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.proj @@ -0,0 +1 @@ +schematicFile 4_bit_FA.sch diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch new file mode 100644 index 00000000..89d7e29d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283.sch @@ -0,0 +1,572 @@ +EESchema Schematic File Version 2 +LIBS:4_bit_FA-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:eSim_SKY130 +LIBS:eSim_SKY130_Subckts +LIBS:4_bit_FA-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3500 2050 5100 2050 +Wire Wire Line + 5100 2050 5100 2800 +Wire Wire Line + 3500 2350 5000 2350 +Wire Wire Line + 5000 2350 5000 2900 +Wire Wire Line + 5000 2900 5100 2900 +Wire Wire Line + 3500 2650 4900 2650 +Wire Wire Line + 4900 2650 4900 3000 +Wire Wire Line + 4900 3000 5100 3000 +Wire Wire Line + 3500 2950 4800 2950 +Wire Wire Line + 4800 2950 4800 3100 +Wire Wire Line + 4800 3100 5100 3100 +Wire Wire Line + 3500 3250 5100 3250 +Wire Wire Line + 5100 3250 5100 3200 +Wire Wire Line + 3500 3550 3850 3550 +Wire Wire Line + 3850 3550 3850 3350 +Wire Wire Line + 3850 3350 5100 3350 +Wire Wire Line + 3500 3850 3900 3850 +Wire Wire Line + 3900 3850 3900 3450 +Wire Wire Line + 3900 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+Connection ~ 1800 3850 +Wire Wire Line + 1800 4450 2600 4450 +Connection ~ 1800 4150 +$Comp +L plot_v1 U2 +U 1 1 67F401B5 +P 3650 2100 +F 0 "U2" H 3650 2600 60 0000 C CNN +F 1 "plot_v1" H 3850 2450 60 0000 C CNN +F 2 "" H 3650 2100 60 0000 C CNN +F 3 "" H 3650 2100 60 0000 C CNN + 1 3650 2100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3650 1900 3650 2050 +Connection ~ 3650 2050 +$Comp +L plot_v1 U3 +U 1 1 67F403E7 +P 3850 2400 +F 0 "U3" H 3850 2900 60 0000 C CNN +F 1 "plot_v1" H 4050 2750 60 0000 C CNN +F 2 "" H 3850 2400 60 0000 C CNN +F 3 "" H 3850 2400 60 0000 C CNN + 1 3850 2400 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 67F40422 +P 4100 2650 +F 0 "U4" H 4100 3150 60 0000 C CNN +F 1 "plot_v1" H 4300 3000 60 0000 C CNN +F 2 "" H 4100 2650 60 0000 C CNN +F 3 "" H 4100 2650 60 0000 C CNN + 1 4100 2650 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 67F4046B +P 4300 3000 +F 0 "U5" H 4300 3500 60 0000 C CNN +F 1 "plot_v1" H 4500 3350 60 0000 C CNN +F 2 "" H 4300 3000 60 0000 C CNN +F 3 "" H 4300 3000 60 0000 C CNN + 1 4300 3000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 67F404AA +P 4550 3350 +F 0 "U7" H 4550 3850 60 0000 C CNN +F 1 "plot_v1" H 4750 3700 60 0000 C CNN +F 2 "" H 4550 3350 60 0000 C CNN +F 3 "" H 4550 3350 60 0000 C CNN + 1 4550 3350 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 67F404E7 +P 3600 3550 +F 0 "U1" H 3600 4050 60 0000 C CNN +F 1 "plot_v1" H 3800 3900 60 0000 C CNN +F 2 "" H 3600 3550 60 0000 C CNN +F 3 "" H 3600 3550 60 0000 C CNN + 1 3600 3550 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 67F405AC +P 4400 4600 +F 0 "U6" H 4400 5100 60 0000 C CNN +F 1 "plot_v1" H 4600 4950 60 0000 C CNN +F 2 "" H 4400 4600 60 0000 C CNN +F 3 "" H 4400 4600 60 0000 C CNN + 1 4400 4600 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U8 +U 1 1 67F405F7 +P 4850 4700 +F 0 "U8" H 4850 5200 60 0000 C CNN +F 1 "plot_v1" H 5050 5050 60 0000 C CNN +F 2 "" H 4850 4700 60 0000 C CNN +F 3 "" H 4850 4700 60 0000 C CNN + 1 4850 4700 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U9 +U 1 1 67F4064A +P 5400 4750 +F 0 "U9" H 5400 5250 60 0000 C CNN +F 1 "plot_v1" H 5600 5100 60 0000 C CNN +F 2 "" H 5400 4750 60 0000 C CNN +F 3 "" H 5400 4750 60 0000 C CNN + 1 5400 4750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3850 2200 3850 2350 +Connection ~ 3850 2350 +Wire Wire Line + 4100 2450 4100 2650 +Connection ~ 4100 2650 +Wire Wire Line + 4300 2800 4300 2950 +Connection ~ 4300 2950 +Wire Wire Line + 4550 3150 4550 3250 +Connection ~ 4550 3250 +Wire Wire Line + 3600 3350 3600 3550 +Connection ~ 3600 3550 +Wire Wire Line + 4400 4400 4000 4400 +Connection ~ 4000 4400 +Wire Wire Line + 4850 4500 3850 4500 +Wire Wire Line + 3850 4500 3850 4150 +Connection ~ 3850 4150 +Wire Wire Line + 5400 4550 5400 4650 +Wire Wire Line + 5400 4650 3700 4650 +Wire Wire Line + 3700 4650 3700 3850 +Connection ~ 3700 3850 +Text GLabel 3450 1800 0 60 Input ~ 0 +C0 +Wire Wire Line + 3450 1800 3550 1800 +Wire Wire Line + 3550 1800 3550 2000 +Wire Wire Line + 3550 2000 3650 2000 +Connection ~ 3650 2000 +Text GLabel 3650 2200 0 60 Input ~ 0 +A1 +Wire Wire Line + 3650 2200 3800 2200 +Wire Wire Line + 3800 2200 3800 2300 +Wire Wire Line + 3800 2300 3850 2300 +Connection ~ 3850 2300 +Text GLabel 3850 2500 0 60 Input ~ 0 +A2 +Wire Wire Line + 3850 2500 3950 2500 +Wire Wire Line + 3950 2500 3950 2600 +Wire Wire Line + 3950 2600 4100 2600 +Connection ~ 4100 2600 +Text GLabel 3900 2800 0 60 Input ~ 0 +A3 +Wire Wire Line + 3900 2800 4100 2800 +Wire Wire Line + 4100 2800 4100 2900 +Wire Wire Line + 4100 2900 4300 2900 +Connection ~ 4300 2900 +Text GLabel 4150 3100 0 60 Input ~ 0 +A4 +Wire Wire Line + 4150 3100 4350 3100 +Wire Wire Line + 4350 3100 4350 3200 +Wire Wire Line + 4350 3200 4550 3200 +Connection ~ 4550 3200 +Text GLabel 3450 3400 0 60 Input ~ 0 +B1 +Wire Wire Line + 3450 3400 3450 3500 +Wire Wire Line + 3450 3500 3600 3500 +Connection ~ 3600 3500 +Text GLabel 4300 4850 0 60 Input ~ 0 +B2 +Wire Wire Line + 4300 4850 4400 4850 +Wire Wire Line + 4400 4850 4400 4650 +Connection ~ 4400 4650 +Text GLabel 3900 4800 0 60 Input ~ 0 +B3 +Wire Wire Line + 3900 4800 4050 4800 +Wire Wire Line + 4050 4800 4050 4500 +Connection ~ 4050 4500 +Text GLabel 4100 4150 0 60 Input ~ 0 +B4 +Wire Wire Line + 4100 4150 4150 4150 +Wire Wire Line + 4150 4150 4150 4400 +Connection ~ 4150 4400 +$Comp +L plot_v1 U10 +U 1 1 67F40F19 +P 6800 3250 +F 0 "U10" H 6800 3750 60 0000 C CNN +F 1 "plot_v1" H 7000 3600 60 0000 C CNN +F 2 "" H 6800 3250 60 0000 C CNN +F 3 "" H 6800 3250 60 0000 C CNN + 1 6800 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U11 +U 1 1 67F40F66 +P 7250 3250 +F 0 "U11" H 7250 3750 60 0000 C CNN +F 1 "plot_v1" H 7450 3600 60 0000 C CNN +F 2 "" H 7250 3250 60 0000 C CNN +F 3 "" H 7250 3250 60 0000 C CNN + 1 7250 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U12 +U 1 1 67F40FB3 +P 7700 3250 +F 0 "U12" H 7700 3750 60 0000 C CNN +F 1 "plot_v1" H 7900 3600 60 0000 C CNN +F 2 "" H 7700 3250 60 0000 C CNN +F 3 "" H 7700 3250 60 0000 C CNN + 1 7700 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U13 +U 1 1 67F41000 +P 8100 3250 +F 0 "U13" H 8100 3750 60 0000 C CNN +F 1 "plot_v1" H 8300 3600 60 0000 C CNN +F 2 "" H 8100 3250 60 0000 C CNN +F 3 "" H 8100 3250 60 0000 C CNN + 1 8100 3250 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U14 +U 1 1 67F4104F +P 8500 3250 +F 0 "U14" H 8500 3750 60 0000 C CNN +F 1 "plot_v1" H 8700 3600 60 0000 C CNN +F 2 "" H 8500 3250 60 0000 C CNN +F 3 "" H 8500 3250 60 0000 C CNN + 1 8500 3250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6800 3050 6300 3050 +Wire Wire Line + 7250 3050 7250 3150 +Wire Wire Line + 7250 3150 6300 3150 +Wire Wire Line + 7700 3050 7700 3250 +Wire Wire Line + 7700 3250 6300 3250 +Wire Wire Line + 8100 3050 8100 3350 +Wire Wire Line + 8100 3350 6300 3350 +Wire Wire Line + 8500 3050 8500 3500 +Wire Wire Line + 8500 3500 6300 3500 +Text GLabel 6500 2950 0 60 Input ~ 0 +S1 +Wire Wire Line + 6500 2950 6550 2950 +Wire Wire Line + 6550 2950 6550 3050 +Connection ~ 6550 3050 +Text GLabel 6400 2600 0 60 Input ~ 0 +S2 +Wire Wire Line + 6400 2600 6600 2600 +Wire Wire Line + 6600 2600 6600 3150 +Connection ~ 6600 3150 +Text GLabel 6400 2350 0 60 Input ~ 0 +S3 +Wire Wire Line + 6400 2350 6650 2350 +Wire Wire Line + 6650 2350 6650 3250 +Connection ~ 6650 3250 +Text GLabel 6400 2100 0 60 Input ~ 0 +S4 +Wire Wire Line + 6400 2100 6700 2100 +Wire Wire Line + 6700 2100 6700 3350 +Connection ~ 6700 3350 +Text GLabel 6850 3600 0 60 Input ~ 0 +C_out +Wire Wire Line + 6850 3600 7000 3600 +Wire Wire Line + 7000 3600 7000 3500 +Connection ~ 7000 3500 +$Comp +L 283 X1 +U 1 1 67F4018C +P 6100 4100 +F 0 "X1" H 5700 4200 60 0000 C CNN +F 1 "283" H 5750 5600 60 0000 C CNN +F 2 "" H 5750 5600 60 0001 C CNN +F 3 "" H 5750 5600 60 0001 C CNN + 1 6100 4100 + 1 0 0 -1 +$EndComp +$Comp +L pulse v1 +U 1 1 67F4A87C +P 3050 2050 +F 0 "v1" H 2850 2150 60 0000 C CNN +F 1 "pulse" H 2850 2000 60 0000 C CNN +F 2 "R1" H 2750 2050 60 0000 C CNN +F 3 "" H 3050 2050 60 0000 C CNN + 1 3050 2050 + 0 1 1 0 +$EndComp +$Comp +L pulse v2 +U 1 1 67F4A8DB +P 3050 2350 +F 0 "v2" H 2850 2450 60 0000 C CNN +F 1 "pulse" H 2850 2300 60 0000 C CNN +F 2 "R1" H 2750 2350 60 0000 C CNN +F 3 "" H 3050 2350 60 0000 C CNN + 1 3050 2350 + 0 1 1 0 +$EndComp +$Comp +L pulse v3 +U 1 1 67F4A950 +P 3050 2650 +F 0 "v3" H 2850 2750 60 0000 C CNN +F 1 "pulse" H 2850 2600 60 0000 C CNN +F 2 "R1" H 2750 2650 60 0000 C CNN +F 3 "" H 3050 2650 60 0000 C CNN + 1 3050 2650 + 0 1 1 0 +$EndComp +$Comp +L pulse v4 +U 1 1 67F4A956 +P 3050 2950 +F 0 "v4" H 2850 3050 60 0000 C CNN +F 1 "pulse" H 2850 2900 60 0000 C CNN +F 2 "R1" H 2750 2950 60 0000 C CNN +F 3 "" H 3050 2950 60 0000 C CNN + 1 3050 2950 + 0 1 1 0 +$EndComp +$Comp +L pulse v5 +U 1 1 67F4A9E6 +P 3050 3250 +F 0 "v5" H 2850 3350 60 0000 C CNN +F 1 "pulse" H 2850 3200 60 0000 C CNN +F 2 "R1" H 2750 3250 60 0000 C CNN +F 3 "" H 3050 3250 60 0000 C CNN + 1 3050 3250 + 0 1 1 0 +$EndComp +$Comp +L pulse v6 +U 1 1 67F4A9EC +P 3050 3550 +F 0 "v6" H 2850 3650 60 0000 C CNN +F 1 "pulse" H 2850 3500 60 0000 C CNN +F 2 "R1" H 2750 3550 60 0000 C CNN +F 3 "" H 3050 3550 60 0000 C CNN + 1 3050 3550 + 0 1 1 0 +$EndComp +$Comp +L pulse v7 +U 1 1 67F4A9F2 +P 3050 3850 +F 0 "v7" H 2850 3950 60 0000 C CNN +F 1 "pulse" H 2850 3800 60 0000 C CNN +F 2 "R1" H 2750 3850 60 0000 C CNN +F 3 "" H 3050 3850 60 0000 C CNN + 1 3050 3850 + 0 1 1 0 +$EndComp +$Comp +L pulse v8 +U 1 1 67F4A9F8 +P 3050 4150 +F 0 "v8" H 2850 4250 60 0000 C CNN +F 1 "pulse" H 2850 4100 60 0000 C CNN +F 2 "R1" H 2750 4150 60 0000 C CNN +F 3 "" H 3050 4150 60 0000 C CNN + 1 3050 4150 + 0 1 1 0 +$EndComp +$Comp +L pulse v9 +U 1 1 67F4AA2C +P 3050 4450 +F 0 "v9" H 2850 4550 60 0000 C CNN +F 1 "pulse" H 2850 4400 60 0000 C CNN +F 2 "R1" H 2750 4450 60 0000 C CNN +F 3 "" H 3050 4450 60 0000 C CNN + 1 3050 4450 + 0 1 1 0 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml new file mode 100644 index 00000000..27d2915b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/cdx4ac283_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v3 name="Source type">dc<field1 name="Value">5</field1></v3><v4 name="Source type">dc<field1 name="Value">5</field1></v4><v5 name="Source type">dc<field1 name="Value">5</field1></v5><v6 name="Source type">dc<field1 name="Value">0</field1></v6><v7 name="Source type">dc<field1 name="Value">0</field1></v7><v8 name="Source type">dc<field1 name="Value">0</field1></v8><v9 name="Source type">dc<field1 name="Value">5</field1></v9><v1 name="Source type">dc<field1 name="Value">5</field1></v1><v1 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">250u</field5><field5 name="Period">5120u</field5></v1><v2 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">10u</field5><field5 name="Period">20u</field5></v2><v3 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">20u</field5><field5 name="Period">40u</field5></v3><v4 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">40u</field5><field5 name="Period">80u</field5></v4><v5 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">80u</field5><field5 name="Period">160u</field5></v5><v6 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">160u</field5><field5 name="Period">320u</field5></v6><v7 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">320u</field5><field5 name="Period">640u</field5></v7><v8 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">640u</field5><field5 name="Period">1280u</field5></v8><v9 name="Source type">pulse<field1 name="Initial Value">0</field1><field2 name="Pulse Value">5</field2><field3 name="Delay Time">0</field3><field4 name="Rise Time">1n</field4><field5 name="Fall Time">1n</field5><field5 name="Pulse width">1280u</field5><field5 name="Period">2560u</field5></v9></source><model /><devicemodel /><subcircuit><x1><field>C:\Users\Shanthipriya\Desktop\madeeasy\FOSSEE\eSim\library\SubcircuitLibrary\74AC283</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">2</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">us</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib new file mode 100644 index 00000000..623a7f41 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_or +# +DEF d_or U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_or" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 -250 -50 150 -50 N +P 2 0 1 0 -250 150 150 150 N +X IN1 1 -450 100 215 R 50 50 1 1 I +X IN2 2 -450 0 215 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# half_adder +# +DEF half_adder X 0 40 Y Y 1 F N +F0 "X" 900 500 60 H V C CNN +F1 "half_adder" 900 400 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S 500 800 1250 0 0 1 0 N +X IN1 1 300 700 200 R 50 50 1 1 I +X IN2 2 300 100 200 R 50 50 1 1 I +X SUM 3 1450 700 200 L 50 50 1 1 O +X COUT 4 1450 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir new file mode 100644 index 00000000..6461b5b6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir @@ -0,0 +1,12 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +X1 8 7 6 2 half_adder +X2 5 6 4 3 half_adder +U1 8 7 5 4 1 PORT +U2 3 2 1 d_or + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out new file mode 100644 index 00000000..b90ce70d --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.cir.out @@ -0,0 +1,19 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 + +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u1 8 7 5 4 1 port +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro new file mode 100644 index 00000000..ad45a0b3 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.pro @@ -0,0 +1,44 @@ +update=Wed Jun 24 12:19:16 2015 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=eSim_Analog +LibName2=eSim_Devices +LibName3=eSim_Digital +LibName4=eSim_Hybrid +LibName5=eSim_Miscellaneous +LibName6=eSim_Plot +LibName7=eSim_Power +LibName8=power +LibName9=eSim_Sources +LibName10=eSim_Subckt +LibName11=eSim_User diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch new file mode 100644 index 00000000..8bd400f2 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sch @@ -0,0 +1,180 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L half_adder X1 +U 1 1 558AA064 +P 3800 3350 +F 0 "X1" H 4700 3850 60 0000 C CNN +F 1 "half_adder" H 4700 3750 60 0000 C CNN +F 2 "" H 3800 3350 60 0000 C CNN +F 3 "" H 3800 3350 60 0000 C CNN + 1 3800 3350 + 1 0 0 -1 +$EndComp +$Comp +L half_adder X2 +U 1 1 558AA0C1 +P 5700 3350 +F 0 "X2" H 6600 3850 60 0000 C CNN +F 1 "half_adder" H 6600 3750 60 0000 C CNN +F 2 "" H 5700 3350 60 0000 C CNN +F 3 "" H 5700 3350 60 0000 C CNN + 1 5700 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558AA277 +P 3450 2650 +F 0 "U1" H 3500 2750 30 0000 C CNN +F 1 "PORT" H 3450 2650 30 0000 C CNN +F 2 "" H 3450 2650 60 0000 C CNN +F 3 "" H 3450 2650 60 0000 C CNN + 1 3450 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558AA29E +P 3450 3250 +F 0 "U1" H 3500 3350 30 0000 C CNN +F 1 "PORT" H 3450 3250 30 0000 C CNN +F 2 "" H 3450 3250 60 0000 C CNN +F 3 "" H 3450 3250 60 0000 C CNN + 2 3450 3250 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558AA2D8 +P 5650 2300 +F 0 "U1" H 5700 2400 30 0000 C CNN +F 1 "PORT" H 5650 2300 30 0000 C CNN +F 2 "" H 5650 2300 60 0000 C CNN +F 3 "" H 5650 2300 60 0000 C CNN + 3 5650 2300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 558AA378 +P 7900 2650 +F 0 "U1" H 7950 2750 30 0000 C CNN +F 1 "PORT" H 7900 2650 30 0000 C CNN +F 2 "" H 7900 2650 60 0000 C CNN +F 3 "" H 7900 2650 60 0000 C CNN + 4 7900 2650 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 558AA3E0 +P 8700 3400 +F 0 "U1" H 8750 3500 30 0000 C CNN +F 1 "PORT" H 8700 3400 30 0000 C CNN +F 2 "" H 8700 3400 60 0000 C CNN +F 3 "" H 8700 3400 60 0000 C CNN + 5 8700 3400 + -1 0 0 1 +$EndComp +$Comp +L d_or U2 +U 1 1 558AA43B +P 7900 3450 +F 0 "U2" H 7900 3450 60 0000 C CNN +F 1 "d_or" H 7900 3550 60 0000 C CNN +F 2 "" H 7900 3450 60 0000 C CNN +F 3 "" H 7900 3450 60 0000 C CNN + 1 7900 3450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3700 2650 4100 2650 +Wire Wire Line + 3700 3250 4100 3250 +Wire Wire Line + 5250 2650 5650 2650 +Wire Wire Line + 5650 2650 5650 3250 +Wire Wire Line + 5650 3250 6000 3250 +Wire Wire Line + 5900 2300 5900 2650 +Wire Wire Line + 5900 2650 6000 2650 +Wire Wire Line + 7150 2650 7650 2650 +Wire Wire Line + 7150 3250 7350 3250 +Wire Wire Line + 7350 3250 7350 3350 +Wire Wire Line + 7350 3350 7450 3350 +Wire Wire Line + 5250 3250 5400 3250 +Wire Wire Line + 5400 3250 5400 3450 +Wire Wire Line + 5400 3450 7450 3450 +Wire Wire Line + 8350 3400 8450 3400 +Text Notes 3850 2500 0 60 ~ 0 +IN1 +Text Notes 3850 3150 0 60 ~ 0 +IN2 +Text Notes 6000 2350 0 60 ~ 0 +CIN +Text Notes 7350 2550 0 60 ~ 0 +SUM +Text Notes 8300 3200 0 60 ~ 0 +COUT +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub new file mode 100644 index 00000000..5f261f78 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder.sub @@ -0,0 +1,13 @@ +* Subcircuit full_adder +.subckt full_adder 8 7 5 4 1 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015 +.include half_adder.sub +x1 8 7 6 2 half_adder +x2 5 6 4 3 half_adder +* u2 3 2 1 d_or +a1 [3 2 ] 1 u2 +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends full_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml new file mode 100644 index 00000000..b63184d6 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/full_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib new file mode 100644 index 00000000..68785220 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 8 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +ENDDRAW +ENDDEF +# +# d_and +# +DEF d_and U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_and" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 149 50 100 -894 0 0 1 0 N 150 -50 250 50 +A 150 49 100 6 900 0 1 0 N 250 50 150 150 +P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N +X IN1 1 -450 100 200 R 50 50 1 1 I +X IN2 2 -450 0 200 R 50 50 1 1 I +X OUT 3 450 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# d_xor +# +DEF d_xor U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "d_xor" 50 100 47 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50 +A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150 +A -25 -124 325 574 323 0 1 0 N 150 150 250 50 +A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50 +P 2 0 1 0 150 -50 -200 -50 N +P 2 0 1 0 150 150 -200 150 N +X IN1 1 -450 100 215 R 50 43 1 1 I +X IN2 2 -450 0 215 R 50 43 1 1 I +X OUT 3 450 50 200 L 50 39 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir new file mode 100644 index 00000000..8b2e7e06 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir @@ -0,0 +1,11 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +U2 1 4 3 d_xor +U3 1 4 2 d_and +U1 1 4 3 2 PORT + +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out new file mode 100644 index 00000000..b1b6b1e7 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.cir.out @@ -0,0 +1,20 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 + +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +* u1 1 4 3 2 port +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +.ac lin 0 0Hz 0Hz + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro new file mode 100644 index 00000000..582cec8b --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.pro @@ -0,0 +1,69 @@ +update=Wed Mar 18 20:13:43 2020 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=transistors +LibName3=conn +LibName4=74xx +LibName5=cmos4000 +LibName6=adc-dac +LibName7=memory +LibName8=xilinx +LibName9=microcontrollers +LibName10=dsp +LibName11=microchip +LibName12=analog_switches +LibName13=motorola +LibName14=texas +LibName15=intel +LibName16=audio +LibName17=interface +LibName18=digital-audio +LibName19=philips +LibName20=display +LibName21=cypress +LibName22=siliconi +LibName23=opto +LibName24=atmel +LibName25=contrib +LibName26=valves +LibName27=eSim_Analog +LibName28=eSim_Devices +LibName29=eSim_Digital +LibName30=eSim_Hybrid +LibName31=eSim_Miscellaneous +LibName32=eSim_Plot +LibName33=eSim_Power +LibName34=eSim_Sources +LibName35=eSim_Subckt +LibName36=eSim_User diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch new file mode 100644 index 00000000..bf9bcbf0 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sch @@ -0,0 +1,152 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Sources +LIBS:eSim_Subckt +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L d_xor U2 +U 1 1 558A946A +P 5650 3050 +F 0 "U2" H 5650 3050 60 0000 C CNN +F 1 "d_xor" H 5700 3150 47 0000 C CNN +F 2 "" H 5650 3050 60 0000 C CNN +F 3 "" H 5650 3050 60 0000 C CNN + 1 5650 3050 + 1 0 0 -1 +$EndComp +$Comp +L d_and U3 +U 1 1 558A94D5 +P 5700 3800 +F 0 "U3" H 5700 3800 60 0000 C CNN +F 1 "d_and" H 5750 3900 60 0000 C CNN +F 2 "" H 5700 3800 60 0000 C CNN +F 3 "" H 5700 3800 60 0000 C CNN + 1 5700 3800 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 558A94F6 +P 4150 3000 +F 0 "U1" H 4200 3100 30 0000 C CNN +F 1 "PORT" H 4150 3000 30 0000 C CNN +F 2 "" H 4150 3000 60 0000 C CNN +F 3 "" H 4150 3000 60 0000 C CNN + 1 4150 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 558A9543 +P 4150 3450 +F 0 "U1" H 4200 3550 30 0000 C CNN +F 1 "PORT" H 4150 3450 30 0000 C CNN +F 2 "" H 4150 3450 60 0000 C CNN +F 3 "" H 4150 3450 60 0000 C CNN + 2 4150 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 558A9573 +P 6650 3000 +F 0 "U1" H 6700 3100 30 0000 C CNN +F 1 "PORT" H 6650 3000 30 0000 C CNN +F 2 "" H 6650 3000 60 0000 C CNN +F 3 "" H 6650 3000 60 0000 C CNN + 3 6650 3000 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 558A9606 +P 6700 3750 +F 0 "U1" H 6750 3850 30 0000 C CNN +F 1 "PORT" H 6700 3750 30 0000 C CNN +F 2 "" H 6700 3750 60 0000 C CNN +F 3 "" H 6700 3750 60 0000 C CNN + 4 6700 3750 + -1 0 0 1 +$EndComp +Wire Wire Line + 5200 2950 4450 2950 +Wire Wire Line + 4450 2950 4450 3000 +Wire Wire Line + 4450 3000 4400 3000 +Wire Wire Line + 4400 3450 4550 3450 +Wire Wire Line + 4550 3450 4550 3050 +Wire Wire Line + 4550 3050 5200 3050 +Wire Wire Line + 5250 3700 5000 3700 +Wire Wire Line + 5000 3700 5000 2950 +Connection ~ 5000 2950 +Wire Wire Line + 5250 3800 4850 3800 +Wire Wire Line + 4850 3800 4850 3050 +Connection ~ 4850 3050 +Wire Wire Line + 6100 3000 6400 3000 +Wire Wire Line + 6150 3750 6450 3750 +Text Notes 4550 2950 0 60 ~ 0 +IN1\n\n +Text Notes 4600 3150 0 60 ~ 0 +IN2 +Text Notes 6200 2950 0 60 ~ 0 +SUM\n +Text Notes 6200 3650 0 60 ~ 0 +COUT\n +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub new file mode 100644 index 00000000..e9f92223 --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder.sub @@ -0,0 +1,14 @@ +* Subcircuit half_adder +.subckt half_adder 1 4 3 2 +* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015 +* u2 1 4 3 d_xor +* u3 1 4 2 d_and +a1 [1 4 ] 3 u2 +a2 [1 4 ] 2 u3 +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) +* Control Statements + +.ends half_adder
\ No newline at end of file diff --git a/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml new file mode 100644 index 00000000..b915f0da --- /dev/null +++ b/library/SubcircuitLibrary/esim_ic_files/cdx4ac283/half_adder_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file |