1 files changed, 50 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/TLC271/TLC271.cir.out b/library/SubcircuitLibrary/TLC271/TLC271.cir.out
new file mode 100644
index 00000000..4d4fe33a
--- /dev/null
+++ b/library/SubcircuitLibrary/TLC271/TLC271.cir.out
@@ -0,0 +1,50 @@
+* c:\users\hp\onedrive\documents\fossee\esim\library\subcircuitlibrary\tlc271\tlc271.cir
+
+.include D.lib
+.include PMOS-180nm.lib
+.include NMOS-180nm.lib
+m1 net-_m1-pad1_ /inv net-_d1-pad2_ /vdd CMOSP W=100u L=100u M=1
+m5 net-_m1-pad1_ /non_inv net-_d2-pad2_ /vdd CMOSP W=100u L=100u M=1
+m2 net-_d1-pad2_ net-_d1-pad2_ /offset_null1 /vss CMOSN W=100u L=100u M=1
+m4 net-_d2-pad2_ net-_d1-pad2_ /offset_null2 /vss CMOSN W=100u L=100u M=1
+r1  /offset_null1 /vss 3k
+r2  /offset_null2 /vss 3k
+d1 /vss net-_d1-pad2_ 1N4148
+m3 /vdd net-_m10-pad2_ net-_m1-pad1_ /vdd CMOSP W=100u L=100u M=1
+m7 /vdd net-_m10-pad2_ net-_m6-pad1_ /vdd CMOSP W=100u L=100u M=1
+m6 net-_m6-pad1_ net-_d2-pad2_ /vss /vss CMOSN W=100u L=100u M=1
+r3  net-_d2-pad2_ net-_c1-pad1_ 10k
+c1  net-_c1-pad1_ /out 30p
+m8 net-_m8-pad1_ net-_m6-pad1_ /out /vss CMOSN W=100u L=100u M=1
+m9 /out net-_d2-pad2_ /vss /vss CMOSN W=100u L=100u M=1
+d2 /vss net-_d2-pad2_ 1N4148
+r4  /vdd net-_m8-pad1_ 39k
+m10 /vdd net-_m10-pad2_ net-_m10-pad2_ /vdd CMOSP W=100u L=100u M=1
+m11 net-_m11-pad1_ net-_m10-pad2_ net-_m10-pad2_ /vdd CMOSP W=100u L=100u M=1
+m13 net-_m13-pad1_ net-_m10-pad2_ net-_m10-pad2_ /vdd CMOSP W=100u L=100u M=1
+m15 net-_m13-pad1_ net-_m10-pad2_ net-_m12-pad2_ /vdd CMOSP W=100u L=100u M=1
+m14 /vdd net-_m14-pad2_ net-_m13-pad1_ /vdd CMOSP W=100u L=100u M=1
+m17 net-_m11-pad1_ net-_m10-pad2_ net-_m12-pad2_ /vdd CMOSP W=100u L=100u M=1
+m16 /vdd net-_m16-pad2_ net-_m11-pad1_ /vdd CMOSP W=100u L=100u M=1
+m19 /vdd net-_m10-pad2_ net-_m12-pad2_ /vdd CMOSP W=100u L=100u M=1
+m21 /vdd /bias_select net-_m14-pad2_ /vdd CMOSP W=100u L=100u M=1
+m23 /vdd net-_m10-pad2_ net-_m16-pad2_ /vdd CMOSP W=100u L=100u M=1
+m27 /vdd net-_m10-pad2_ /bias_select /vdd CMOSP W=100u L=100u M=1
+m12 net-_m10-pad2_ net-_m12-pad2_ net-_m12-pad3_ /vss CMOSN W=100u L=100u M=1
+m18 net-_m12-pad2_ net-_m12-pad2_ /vss /vss CMOSN W=100u L=100u M=1
+r5  net-_m12-pad3_ /vss 100k
+m24 /bias_select /bias_select net-_m24-pad3_ /vss CMOSN W=100u L=100u M=1
+m25 net-_m24-pad3_ net-_m24-pad3_ net-_m25-pad3_ /vss CMOSN W=100u L=100u M=1
+m26 net-_m25-pad3_ net-_m12-pad2_ /vss /vss CMOSN W=100u L=100u M=1
+m22 net-_m16-pad2_ /bias_select /vss /vss CMOSN W=100u L=100u M=1
+m20 net-_m14-pad2_ net-_m12-pad2_ /vss /vss CMOSN W=100u L=100u M=1
+* u1  /vdd /inv /non_inv /offset_null1 /offset_null2 /out /vss /bias_select port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end