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diff --git a/library/SubcircuitLibrary/SRAM/SRAM.cir.out b/library/SubcircuitLibrary/SRAM/SRAM.cir.out
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+* c:\users\aditya\esim-workspace\sram\sram.cir
+
+.include SRAM_Cell.sub
+v1 wl gnd pulse(0 1.8 0 25p 25p 10n 20n)
+v2 bl gnd pulse(0 1.8 0 25p 25p 15n 30n)
+v3 net-_x1-pad1_ gnd dc 1.8
+* u1 wl plot_v1
+* u2 bl plot_v1
+* u5 not_bl plot_v1
+* u4 q plot_v1
+* u3 not_q plot_v1
+r1 not_q gnd 1000k
+r2 q gnd 1000k
+v4 not_bl gnd pulse(1.8 0 0 25p 25p 15n 30n)
+x1 net-_x1-pad1_ wl bl not_bl gnd q not_q SRAM_Cell
+.tran 0.01e-09 80e-09 0e-09
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(wl)
+plot v(bl)
+plot v(not_bl)
+plot v(q)
+plot v(not_q)
+.endc
+.end