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diff --git a/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir.out b/library/SubcircuitLibrary/SN74LS76/SN74LS76.cir.out
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+* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn74ls76\sn74ls76.cir
+
+.include 3_and.sub
+.include 4_and.sub
+x2 net-_u1-pad6_ net-_u3-pad2_ net-_u1-pad5_ net-_u2-pad2_ 3_and
+x3 net-_u1-pad5_ net-_u1-pad4_ net-_u1-pad6_ net-_u2-pad1_ 3_and
+x4 net-_u1-pad1_ net-_u4-pad2_ net-_u1-pad2_ net-_u5-pad1_ 3_and
+x5 net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad1_ net-_u5-pad2_ 3_and
+x1 net-_u1-pad5_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad1_ 4_and
+* u3 net-_u3-pad1_ net-_u3-pad2_ d_inverter
+x6 net-_u1-pad4_ net-_u1-pad7_ net-_u1-pad6_ net-_u1-pad1_ net-_u4-pad1_ 4_and
+* u4 net-_u4-pad1_ net-_u4-pad2_ d_inverter
+* u5 net-_u5-pad1_ net-_u5-pad2_ net-_u1-pad5_ d_nor
+* u2 net-_u2-pad1_ net-_u2-pad2_ net-_u1-pad1_ d_nor
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ port
+a1 net-_u3-pad1_ net-_u3-pad2_ u3
+a2 net-_u4-pad1_ net-_u4-pad2_ u4
+a3 [net-_u5-pad1_ net-_u5-pad2_ ] net-_u1-pad5_ u5
+a4 [net-_u2-pad1_ net-_u2-pad2_ ] net-_u1-pad1_ u2
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u5 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u2 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end