diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS151/74151.sub')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LS151/74151.sub | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS151/74151.sub b/library/SubcircuitLibrary/SN74LS151/74151.sub new file mode 100644 index 00000000..c53f323b --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS151/74151.sub @@ -0,0 +1,79 @@ +* Subcircuit 74151 +.subckt 74151 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74151\74151.cir +.include 4_and.sub +* u5 net-_u1-pad4_ net-_u16-pad1_ d_inverter +x1 net-_u2-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad5_ net-_u11-pad1_ 4_and +x2 net-_u6-pad2_ net-_u3-pad2_ net-_u4-pad2_ net-_u1-pad6_ net-_u11-pad2_ 4_and +x3 net-_u2-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad7_ net-_u13-pad2_ 4_and +x4 net-_u6-pad2_ net-_u7-pad2_ net-_u4-pad2_ net-_u1-pad8_ net-_u14-pad2_ 4_and +x5 net-_u2-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad9_ net-_u12-pad1_ 4_and +x6 net-_u6-pad2_ net-_u3-pad2_ net-_u8-pad2_ net-_u1-pad10_ net-_u12-pad2_ 4_and +x7 net-_u2-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad11_ net-_u9-pad2_ 4_and +x8 net-_u6-pad2_ net-_u7-pad2_ net-_u8-pad2_ net-_u1-pad12_ net-_u10-pad2_ 4_and +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_or +* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u13-pad3_ d_or +* u14 net-_u13-pad3_ net-_u14-pad2_ net-_u14-pad3_ d_or +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_or +* u9 net-_u12-pad3_ net-_u9-pad2_ net-_u10-pad1_ d_or +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_or +* u15 net-_u14-pad3_ net-_u10-pad3_ net-_u15-pad3_ d_or +* u16 net-_u16-pad1_ net-_u15-pad3_ net-_u1-pad13_ d_and +* u17 net-_u1-pad13_ net-_u1-pad14_ d_inverter +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u6 net-_u2-pad2_ net-_u6-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u7 net-_u3-pad2_ net-_u7-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u8 net-_u4-pad2_ net-_u8-pad2_ d_inverter +a1 net-_u1-pad4_ net-_u16-pad1_ u5 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a4 [net-_u13-pad3_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a5 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a6 [net-_u12-pad3_ net-_u9-pad2_ ] net-_u10-pad1_ u9 +a7 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a8 [net-_u14-pad3_ net-_u10-pad3_ ] net-_u15-pad3_ u15 +a9 [net-_u16-pad1_ net-_u15-pad3_ ] net-_u1-pad13_ u16 +a10 net-_u1-pad13_ net-_u1-pad14_ u17 +a11 net-_u1-pad1_ net-_u2-pad2_ u2 +a12 net-_u2-pad2_ net-_u6-pad2_ u6 +a13 net-_u1-pad2_ net-_u3-pad2_ u3 +a14 net-_u3-pad2_ net-_u7-pad2_ u7 +a15 net-_u1-pad3_ net-_u4-pad2_ u4 +a16 net-_u4-pad2_ net-_u8-pad2_ u8 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u14 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u12 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u10 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74151
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