diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN74LS148/74148.sub')
| -rw-r--r-- | library/SubcircuitLibrary/SN74LS148/74148.sub | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN74LS148/74148.sub b/library/SubcircuitLibrary/SN74LS148/74148.sub new file mode 100644 index 00000000..a4dc5a51 --- /dev/null +++ b/library/SubcircuitLibrary/SN74LS148/74148.sub @@ -0,0 +1,164 @@ +* Subcircuit 74148 +.subckt 74148 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ +* c:\fossee\esim\library\subcircuitlibrary\74148\74148.cir +.include 4_and.sub +.include 3_and.sub +.include 5_and.sub +* u2 net-_u2-pad1_ net-_u2-pad2_ d_inverter +* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ d_nor +* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_nor +* u17 net-_u10-pad3_ net-_u10-pad3_ net-_u17-pad3_ d_nor +* u18 net-_u11-pad3_ net-_u11-pad3_ net-_u18-pad3_ d_nor +* u25 net-_u17-pad3_ net-_u18-pad3_ net-_u1-pad12_ d_nor +* u13 net-_u13-pad1_ net-_u13-pad2_ net-_u13-pad3_ d_nor +* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_nor +* u19 net-_u12-pad3_ net-_u12-pad3_ net-_u19-pad3_ d_nor +* u20 net-_u13-pad3_ net-_u13-pad3_ net-_u20-pad3_ d_nor +* u26 net-_u19-pad3_ net-_u20-pad3_ net-_u1-pad13_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u21 net-_u14-pad3_ net-_u14-pad3_ net-_u21-pad3_ d_nor +* u22 net-_u15-pad3_ net-_u15-pad3_ net-_u22-pad3_ d_nor +* u27 net-_u21-pad3_ net-_u22-pad3_ net-_u1-pad14_ d_nor +* u24 net-_u1-pad10_ net-_u24-pad2_ net-_u1-pad11_ d_nand +x7 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u16-pad1_ 5_and +* u16 net-_u16-pad1_ net-_u16-pad2_ net-_u16-pad3_ d_and +* u23 net-_u16-pad3_ net-_u1-pad10_ d_inverter +x5 net-_u37-pad2_ net-_u2-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad1_ 5_and +x2 net-_u32-pad2_ net-_u30-pad2_ net-_u29-pad2_ net-_u24-pad2_ net-_u10-pad2_ 4_and +x1 net-_u28-pad1_ net-_u29-pad2_ net-_u24-pad2_ net-_u11-pad1_ 3_and +* u3 net-_u3-pad1_ net-_u24-pad2_ net-_u11-pad2_ d_and +x3 net-_u2-pad1_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad1_ 4_and +x4 net-_u32-pad2_ net-_u30-pad2_ net-_u28-pad2_ net-_u24-pad2_ net-_u12-pad2_ 4_and +* u4 net-_u29-pad1_ net-_u24-pad2_ net-_u13-pad1_ d_and +* u5 net-_u3-pad1_ net-_u24-pad2_ net-_u13-pad2_ d_and +* u6 net-_u30-pad1_ net-_u24-pad2_ net-_u14-pad1_ d_and +* u7 net-_u28-pad1_ net-_u24-pad2_ net-_u14-pad2_ d_and +* u8 net-_u29-pad1_ net-_u24-pad2_ net-_u15-pad1_ d_and +* u9 net-_u3-pad1_ net-_u24-pad2_ net-_u15-pad2_ d_and +* u30 net-_u30-pad1_ net-_u30-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +x6 net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u24-pad2_ net-_u16-pad2_ 4_and +* u37 net-_u1-pad2_ net-_u37-pad2_ d_inverter +* u35 net-_u1-pad3_ net-_u2-pad1_ d_inverter +* u32 net-_u1-pad4_ net-_u32-pad2_ d_inverter +* u31 net-_u1-pad5_ net-_u30-pad1_ d_inverter +* u34 net-_u1-pad6_ net-_u28-pad1_ d_inverter +* u36 net-_u1-pad7_ net-_u29-pad1_ d_inverter +* u33 net-_u1-pad8_ net-_u3-pad1_ d_inverter +* u38 net-_u1-pad9_ net-_u24-pad2_ d_inverter +a1 net-_u2-pad1_ net-_u2-pad2_ u2 +a2 [net-_u11-pad1_ net-_u11-pad2_ ] net-_u11-pad3_ u11 +a3 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a4 [net-_u10-pad3_ net-_u10-pad3_ ] net-_u17-pad3_ u17 +a5 [net-_u11-pad3_ net-_u11-pad3_ ] net-_u18-pad3_ u18 +a6 [net-_u17-pad3_ net-_u18-pad3_ ] net-_u1-pad12_ u25 +a7 [net-_u13-pad1_ net-_u13-pad2_ ] net-_u13-pad3_ u13 +a8 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a9 [net-_u12-pad3_ net-_u12-pad3_ ] net-_u19-pad3_ u19 +a10 [net-_u13-pad3_ net-_u13-pad3_ ] net-_u20-pad3_ u20 +a11 [net-_u19-pad3_ net-_u20-pad3_ ] net-_u1-pad13_ u26 +a12 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a13 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a14 [net-_u14-pad3_ net-_u14-pad3_ ] net-_u21-pad3_ u21 +a15 [net-_u15-pad3_ net-_u15-pad3_ ] net-_u22-pad3_ u22 +a16 [net-_u21-pad3_ net-_u22-pad3_ ] net-_u1-pad14_ u27 +a17 [net-_u1-pad10_ net-_u24-pad2_ ] net-_u1-pad11_ u24 +a18 [net-_u16-pad1_ net-_u16-pad2_ ] net-_u16-pad3_ u16 +a19 net-_u16-pad3_ net-_u1-pad10_ u23 +a20 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u11-pad2_ u3 +a21 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u13-pad1_ u4 +a22 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u13-pad2_ u5 +a23 [net-_u30-pad1_ net-_u24-pad2_ ] net-_u14-pad1_ u6 +a24 [net-_u28-pad1_ net-_u24-pad2_ ] net-_u14-pad2_ u7 +a25 [net-_u29-pad1_ net-_u24-pad2_ ] net-_u15-pad1_ u8 +a26 [net-_u3-pad1_ net-_u24-pad2_ ] net-_u15-pad2_ u9 +a27 net-_u30-pad1_ net-_u30-pad2_ u30 +a28 net-_u28-pad1_ net-_u28-pad2_ u28 +a29 net-_u29-pad1_ net-_u29-pad2_ u29 +a30 net-_u1-pad2_ net-_u37-pad2_ u37 +a31 net-_u1-pad3_ net-_u2-pad1_ u35 +a32 net-_u1-pad4_ net-_u32-pad2_ u32 +a33 net-_u1-pad5_ net-_u30-pad1_ u31 +a34 net-_u1-pad6_ net-_u28-pad1_ u34 +a35 net-_u1-pad7_ net-_u29-pad1_ u36 +a36 net-_u1-pad8_ net-_u3-pad1_ u33 +a37 net-_u1-pad9_ net-_u24-pad2_ u38 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u11 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u10 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u18 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u25 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u13 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u12 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u20 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u26 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u21 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u22 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u27 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u24 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u16 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u5 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u37 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u35 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u34 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u36 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u33 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u38 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74148
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