diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN54F521')
26 files changed, 2506 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN54F521/3_and-cache.lib b/library/SubcircuitLibrary/SN54F521/3_and-cache.lib new file mode 100644 index 00000000..0a3ccf7f --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and-cache.lib @@ -0,0 +1,61 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54F521/3_and.cir b/library/SubcircuitLibrary/SN54F521/3_and.cir new file mode 100644 index 00000000..15f8954d --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54F521/3_and.cir.out b/library/SubcircuitLibrary/SN54F521/3_and.cir.out new file mode 100644 index 00000000..e3c96645 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and.cir.out @@ -0,0 +1,20 @@ +* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54F521/3_and.pro b/library/SubcircuitLibrary/SN54F521/3_and.pro new file mode 100644 index 00000000..36e29799 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and.pro @@ -0,0 +1,43 @@ +update=Wed Mar 18 19:54:53 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/library/SubcircuitLibrary/SN54F521/3_and.sch b/library/SubcircuitLibrary/SN54F521/3_and.sch new file mode 100644 index 00000000..c853bf49 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and.sch @@ -0,0 +1,130 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54F521/3_and.sub b/library/SubcircuitLibrary/SN54F521/3_and.sub new file mode 100644 index 00000000..b949ae4f --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and.sub @@ -0,0 +1,14 @@ +* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/3_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54F521/3_and_Previous_Values.xml new file mode 100644 index 00000000..abc5faaa --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/3_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/4_and-cache.lib b/library/SubcircuitLibrary/SN54F521/4_and-cache.lib new file mode 100644 index 00000000..cb84d8f2 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and-cache.lib @@ -0,0 +1,79 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54F521/4_and-rescue.lib b/library/SubcircuitLibrary/SN54F521/4_and-rescue.lib new file mode 100644 index 00000000..6b2c17f7 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and-rescue.lib @@ -0,0 +1,22 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54F521/4_and.cir b/library/SubcircuitLibrary/SN54F521/4_and.cir new file mode 100644 index 00000000..35e46097 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and.cir @@ -0,0 +1,13 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/SN54F521/4_and.cir.out b/library/SubcircuitLibrary/SN54F521/4_and.cir.out new file mode 100644 index 00000000..6e35b18a --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and.cir.out @@ -0,0 +1,18 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/SN54F521/4_and.pro b/library/SubcircuitLibrary/SN54F521/4_and.pro new file mode 100644 index 00000000..673ae0ac --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and.pro @@ -0,0 +1,57 @@ +update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/SN54F521/4_and.sch b/library/SubcircuitLibrary/SN54F521/4_and.sch new file mode 100644 index 00000000..2d8296d4 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and.sch @@ -0,0 +1,151 @@ +EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
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+$EndComp
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diff --git a/library/SubcircuitLibrary/SN54F521/4_and.sub b/library/SubcircuitLibrary/SN54F521/4_and.sub new file mode 100644 index 00000000..bf20b628 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and.sub @@ -0,0 +1,12 @@ +* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/4_and_Previous_Values.xml b/library/SubcircuitLibrary/SN54F521/4_and_Previous_Values.xml new file mode 100644 index 00000000..f2ba0130 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/4_and_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521-cache.lib b/library/SubcircuitLibrary/SN54F521/SN54F521-cache.lib new file mode 100644 index 00000000..c7d8a722 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521-cache.lib @@ -0,0 +1,128 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521.bak b/library/SubcircuitLibrary/SN54F521/SN54F521.bak new file mode 100644 index 00000000..3090d8a3 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521.bak @@ -0,0 +1,684 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54F521-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
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+Wire Wire Line
+ 6000 7300 6000 4600
+Wire Wire Line
+ 6000 4600 8850 4600
+Wire Wire Line
+ 8850 4600 8850 3100
+Wire Wire Line
+ 8850 3100 8950 3100
+Wire Wire Line
+ 5050 6800 5400 6800
+Wire Wire Line
+ 5400 6800 5400 3850
+Wire Wire Line
+ 5400 3850 6250 3850
+Wire Wire Line
+ 5000 6050 5200 6050
+Wire Wire Line
+ 5200 6050 5200 3750
+Wire Wire Line
+ 5200 3750 6250 3750
+Wire Wire Line
+ 5000 5300 5100 5300
+Wire Wire Line
+ 5100 5300 5100 3650
+Wire Wire Line
+ 5100 3650 6250 3650
+Wire Wire Line
+ 4950 4550 4950 3550
+Wire Wire Line
+ 4950 3550 6250 3550
+Wire Wire Line
+ 5000 3750 5000 2650
+Wire Wire Line
+ 5000 2650 6300 2650
+Wire Wire Line
+ 4950 3000 4950 2550
+Wire Wire Line
+ 4950 2550 6300 2550
+Wire Wire Line
+ 4950 2250 6200 2250
+Wire Wire Line
+ 6200 2250 6200 2450
+Wire Wire Line
+ 6200 2450 6300 2450
+Wire Wire Line
+ 4900 1500 6300 1500
+Wire Wire Line
+ 6300 1500 6300 2350
+$Comp
+L PORT U1
+U 4 1 681D28CC
+P 3250 6000
+F 0 "U1" H 3300 6100 30 0000 C CNN
+F 1 "PORT" H 3250 6000 30 0000 C CNN
+F 2 "" H 3250 6000 60 0000 C CNN
+F 3 "" H 3250 6000 60 0000 C CNN
+ 4 3250 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 681D2D2D
+P 3300 6750
+F 0 "U1" H 3350 6850 30 0000 C CNN
+F 1 "PORT" H 3300 6750 30 0000 C CNN
+F 2 "" H 3300 6750 60 0000 C CNN
+F 3 "" H 3300 6750 60 0000 C CNN
+ 2 3300 6750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681D2DB5
+P 3300 6850
+F 0 "U1" H 3350 6950 30 0000 C CNN
+F 1 "PORT" H 3300 6850 30 0000 C CNN
+F 2 "" H 3300 6850 60 0000 C CNN
+F 3 "" H 3300 6850 60 0000 C CNN
+ 3 3300 6850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 681D2E22
+P 10450 3300
+F 0 "U1" H 10500 3400 30 0000 C CNN
+F 1 "PORT" H 10450 3300 30 0000 C CNN
+F 2 "" H 10450 3300 60 0000 C CNN
+F 3 "" H 10450 3300 60 0000 C CNN
+ 19 10450 3300
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 20 1 681D2E89
+P 1650 5000
+F 0 "U1" H 1700 5100 30 0000 C CNN
+F 1 "PORT" H 1650 5000 30 0000 C CNN
+F 2 "" H 1650 5000 60 0000 C CNN
+F 3 "" H 1650 5000 60 0000 C CNN
+ 20 1650 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 681D2F36
+P 3150 1450
+F 0 "U1" H 3200 1550 30 0000 C CNN
+F 1 "PORT" H 3150 1450 30 0000 C CNN
+F 2 "" H 3150 1450 60 0000 C CNN
+F 3 "" H 3150 1450 60 0000 C CNN
+ 17 3150 1450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 681D2F9B
+P 3150 1550
+F 0 "U1" H 3200 1650 30 0000 C CNN
+F 1 "PORT" H 3150 1550 30 0000 C CNN
+F 2 "" H 3150 1550 60 0000 C CNN
+F 3 "" H 3150 1550 60 0000 C CNN
+ 18 3150 1550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 681D3004
+P 3200 2950
+F 0 "U1" H 3250 3050 30 0000 C CNN
+F 1 "PORT" H 3200 2950 30 0000 C CNN
+F 2 "" H 3200 2950 60 0000 C CNN
+F 3 "" H 3200 2950 60 0000 C CNN
+ 13 3200 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 681D3071
+P 3200 3050
+F 0 "U1" H 3250 3150 30 0000 C CNN
+F 1 "PORT" H 3200 3050 30 0000 C CNN
+F 2 "" H 3200 3050 60 0000 C CNN
+F 3 "" H 3200 3050 60 0000 C CNN
+ 14 3200 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 681D30EC
+P 3300 7300
+F 0 "U1" H 3350 7400 30 0000 C CNN
+F 1 "PORT" H 3300 7300 30 0000 C CNN
+F 2 "" H 3300 7300 60 0000 C CNN
+F 3 "" H 3300 7300 60 0000 C CNN
+ 1 3300 7300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 681D3167
+P 3200 2200
+F 0 "U1" H 3250 2300 30 0000 C CNN
+F 1 "PORT" H 3200 2200 30 0000 C CNN
+F 2 "" H 3200 2200 60 0000 C CNN
+F 3 "" H 3200 2200 60 0000 C CNN
+ 15 3200 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 681D3254
+P 3200 2300
+F 0 "U1" H 3250 2400 30 0000 C CNN
+F 1 "PORT" H 3200 2300 30 0000 C CNN
+F 2 "" H 3200 2300 60 0000 C CNN
+F 3 "" H 3200 2300 60 0000 C CNN
+ 16 3200 2300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 681D36BF
+P 3250 3700
+F 0 "U1" H 3300 3800 30 0000 C CNN
+F 1 "PORT" H 3250 3700 30 0000 C CNN
+F 2 "" H 3250 3700 60 0000 C CNN
+F 3 "" H 3250 3700 60 0000 C CNN
+ 11 3250 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 681D37BC
+P 3250 3800
+F 0 "U1" H 3300 3900 30 0000 C CNN
+F 1 "PORT" H 3250 3800 30 0000 C CNN
+F 2 "" H 3250 3800 60 0000 C CNN
+F 3 "" H 3250 3800 60 0000 C CNN
+ 12 3250 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 681D3835
+P 3200 4600
+F 0 "U1" H 3250 4700 30 0000 C CNN
+F 1 "PORT" H 3200 4600 30 0000 C CNN
+F 2 "" H 3200 4600 60 0000 C CNN
+F 3 "" H 3200 4600 60 0000 C CNN
+ 9 3200 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 681D38BA
+P 1600 4650
+F 0 "U1" H 1650 4750 30 0000 C CNN
+F 1 "PORT" H 1600 4650 30 0000 C CNN
+F 2 "" H 1600 4650 60 0000 C CNN
+F 3 "" H 1600 4650 60 0000 C CNN
+ 10 1600 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 681D393B
+P 3250 5350
+F 0 "U1" H 3300 5450 30 0000 C CNN
+F 1 "PORT" H 3250 5350 30 0000 C CNN
+F 2 "" H 3250 5350 60 0000 C CNN
+F 3 "" H 3250 5350 60 0000 C CNN
+ 7 3250 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 681D39C0
+P 3200 4500
+F 0 "U1" H 3250 4600 30 0000 C CNN
+F 1 "PORT" H 3200 4500 30 0000 C CNN
+F 2 "" H 3200 4500 60 0000 C CNN
+F 3 "" H 3200 4500 60 0000 C CNN
+ 8 3200 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 681D3C91
+P 3250 5250
+F 0 "U1" H 3300 5350 30 0000 C CNN
+F 1 "PORT" H 3250 5250 30 0000 C CNN
+F 2 "" H 3250 5250 60 0000 C CNN
+F 3 "" H 3250 5250 60 0000 C CNN
+ 6 3250 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 681D3D12
+P 3250 6100
+F 0 "U1" H 3300 6200 30 0000 C CNN
+F 1 "PORT" H 3250 6100 30 0000 C CNN
+F 2 "" H 3250 6100 60 0000 C CNN
+F 3 "" H 3250 6100 60 0000 C CNN
+ 5 3250 6100
+ 1 0 0 -1
+$EndComp
+NoConn ~ 2350 4650
+NoConn ~ 2350 5000
+Wire Wire Line
+ 1900 5000 2350 5000
+Wire Wire Line
+ 1850 4650 2350 4650
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521.cir b/library/SubcircuitLibrary/SN54F521/SN54F521.cir new file mode 100644 index 00000000..23472622 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521.cir @@ -0,0 +1,42 @@ +* C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\SN54F521\SN54F521.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/10/25 04:05:21
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X2 Net-_U19-Pad3_ Net-_U20-Pad3_ Net-_U21-Pad3_ Net-_U23-Pad3_ Net-_U28-Pad1_ 4_and
+X1 Net-_U22-Pad3_ Net-_U24-Pad3_ Net-_U25-Pad3_ Net-_U26-Pad3_ Net-_U28-Pad2_ 4_and
+U2 Net-_U1-Pad17_ Net-_U19-Pad1_ d_inverter
+U3 Net-_U1-Pad18_ Net-_U19-Pad2_ d_inverter
+U4 Net-_U1-Pad15_ Net-_U20-Pad1_ d_inverter
+U5 Net-_U1-Pad16_ Net-_U20-Pad2_ d_inverter
+U6 Net-_U1-Pad13_ Net-_U21-Pad1_ d_inverter
+U7 Net-_U1-Pad14_ Net-_U21-Pad2_ d_inverter
+U10 Net-_U1-Pad11_ Net-_U10-Pad2_ d_inverter
+U11 Net-_U1-Pad12_ Net-_U11-Pad2_ d_inverter
+U8 Net-_U1-Pad8_ Net-_U22-Pad1_ d_inverter
+U9 Net-_U1-Pad9_ Net-_U22-Pad2_ d_inverter
+U12 Net-_U1-Pad6_ Net-_U12-Pad2_ d_inverter
+U13 Net-_U1-Pad7_ Net-_U13-Pad2_ d_inverter
+U14 Net-_U1-Pad4_ Net-_U14-Pad2_ d_inverter
+U15 Net-_U1-Pad5_ Net-_U15-Pad2_ d_inverter
+U16 Net-_U1-Pad2_ Net-_U16-Pad2_ d_inverter
+U17 Net-_U1-Pad3_ Net-_U17-Pad2_ d_inverter
+U18 Net-_U1-Pad1_ Net-_U18-Pad2_ d_inverter
+U27 Net-_U18-Pad2_ Net-_U27-Pad2_ d_buffer
+U28 Net-_U28-Pad1_ Net-_U28-Pad2_ Net-_U28-Pad3_ d_and
+U30 Net-_U29-Pad3_ Net-_U1-Pad19_ d_inverter
+U29 Net-_U28-Pad3_ Net-_U27-Pad2_ Net-_U29-Pad3_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ ? Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ ? PORT
+U19 Net-_U19-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_xnor
+U20 Net-_U20-Pad1_ Net-_U20-Pad2_ Net-_U20-Pad3_ d_xnor
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ Net-_U21-Pad3_ d_xnor
+U23 Net-_U10-Pad2_ Net-_U11-Pad2_ Net-_U23-Pad3_ d_xnor
+U22 Net-_U22-Pad1_ Net-_U22-Pad2_ Net-_U22-Pad3_ d_xnor
+U24 Net-_U12-Pad2_ Net-_U13-Pad2_ Net-_U24-Pad3_ d_xnor
+U25 Net-_U14-Pad2_ Net-_U15-Pad2_ Net-_U25-Pad3_ d_xnor
+U26 Net-_U16-Pad2_ Net-_U17-Pad2_ Net-_U26-Pad3_ d_xnor
+
+.end
diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521.cir.out b/library/SubcircuitLibrary/SN54F521/SN54F521.cir.out new file mode 100644 index 00000000..8ccd912f --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521.cir.out @@ -0,0 +1,131 @@ +* c:\users\public\music\fossee\esim\library\subcircuitlibrary\sn54f521\sn54f521.cir
+
+.include 4_and.sub
+x2 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u23-pad3_ net-_u28-pad1_ 4_and
+x1 net-_u22-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u28-pad2_ 4_and
+* u2 net-_u1-pad17_ net-_u19-pad1_ d_inverter
+* u3 net-_u1-pad18_ net-_u19-pad2_ d_inverter
+* u4 net-_u1-pad15_ net-_u20-pad1_ d_inverter
+* u5 net-_u1-pad16_ net-_u20-pad2_ d_inverter
+* u6 net-_u1-pad13_ net-_u21-pad1_ d_inverter
+* u7 net-_u1-pad14_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad11_ net-_u10-pad2_ d_inverter
+* u11 net-_u1-pad12_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad8_ net-_u22-pad1_ d_inverter
+* u9 net-_u1-pad9_ net-_u22-pad2_ d_inverter
+* u12 net-_u1-pad6_ net-_u12-pad2_ d_inverter
+* u13 net-_u1-pad7_ net-_u13-pad2_ d_inverter
+* u14 net-_u1-pad4_ net-_u14-pad2_ d_inverter
+* u15 net-_u1-pad5_ net-_u15-pad2_ d_inverter
+* u16 net-_u1-pad2_ net-_u16-pad2_ d_inverter
+* u17 net-_u1-pad3_ net-_u17-pad2_ d_inverter
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u27 net-_u18-pad2_ net-_u27-pad2_ d_buffer
+* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and
+* u30 net-_u29-pad3_ net-_u1-pad19_ d_inverter
+* u29 net-_u28-pad3_ net-_u27-pad2_ net-_u29-pad3_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ? port
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_xnor
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_xnor
+* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_xnor
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_xnor
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u14-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u16-pad2_ net-_u17-pad2_ net-_u26-pad3_ d_xnor
+a1 net-_u1-pad17_ net-_u19-pad1_ u2
+a2 net-_u1-pad18_ net-_u19-pad2_ u3
+a3 net-_u1-pad15_ net-_u20-pad1_ u4
+a4 net-_u1-pad16_ net-_u20-pad2_ u5
+a5 net-_u1-pad13_ net-_u21-pad1_ u6
+a6 net-_u1-pad14_ net-_u21-pad2_ u7
+a7 net-_u1-pad11_ net-_u10-pad2_ u10
+a8 net-_u1-pad12_ net-_u11-pad2_ u11
+a9 net-_u1-pad8_ net-_u22-pad1_ u8
+a10 net-_u1-pad9_ net-_u22-pad2_ u9
+a11 net-_u1-pad6_ net-_u12-pad2_ u12
+a12 net-_u1-pad7_ net-_u13-pad2_ u13
+a13 net-_u1-pad4_ net-_u14-pad2_ u14
+a14 net-_u1-pad5_ net-_u15-pad2_ u15
+a15 net-_u1-pad2_ net-_u16-pad2_ u16
+a16 net-_u1-pad3_ net-_u17-pad2_ u17
+a17 net-_u1-pad1_ net-_u18-pad2_ u18
+a18 net-_u18-pad2_ net-_u27-pad2_ u27
+a19 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a20 net-_u29-pad3_ net-_u1-pad19_ u30
+a21 [net-_u28-pad3_ net-_u27-pad2_ ] net-_u29-pad3_ u29
+a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a23 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a24 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a26 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a27 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a28 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a29 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u26-pad3_ u26
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:SN54F521-cache
+EELAYER 25 0
+EELAYER END
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+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521.sub b/library/SubcircuitLibrary/SN54F521/SN54F521.sub new file mode 100644 index 00000000..035b073b --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521.sub @@ -0,0 +1,125 @@ +* Subcircuit SN54F521
+.subckt SN54F521 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ ? net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ ?
+* c:\users\public\music\fossee\esim\library\subcircuitlibrary\sn54f521\sn54f521.cir
+.include 4_and.sub
+x2 net-_u19-pad3_ net-_u20-pad3_ net-_u21-pad3_ net-_u23-pad3_ net-_u28-pad1_ 4_and
+x1 net-_u22-pad3_ net-_u24-pad3_ net-_u25-pad3_ net-_u26-pad3_ net-_u28-pad2_ 4_and
+* u2 net-_u1-pad17_ net-_u19-pad1_ d_inverter
+* u3 net-_u1-pad18_ net-_u19-pad2_ d_inverter
+* u4 net-_u1-pad15_ net-_u20-pad1_ d_inverter
+* u5 net-_u1-pad16_ net-_u20-pad2_ d_inverter
+* u6 net-_u1-pad13_ net-_u21-pad1_ d_inverter
+* u7 net-_u1-pad14_ net-_u21-pad2_ d_inverter
+* u10 net-_u1-pad11_ net-_u10-pad2_ d_inverter
+* u11 net-_u1-pad12_ net-_u11-pad2_ d_inverter
+* u8 net-_u1-pad8_ net-_u22-pad1_ d_inverter
+* u9 net-_u1-pad9_ net-_u22-pad2_ d_inverter
+* u12 net-_u1-pad6_ net-_u12-pad2_ d_inverter
+* u13 net-_u1-pad7_ net-_u13-pad2_ d_inverter
+* u14 net-_u1-pad4_ net-_u14-pad2_ d_inverter
+* u15 net-_u1-pad5_ net-_u15-pad2_ d_inverter
+* u16 net-_u1-pad2_ net-_u16-pad2_ d_inverter
+* u17 net-_u1-pad3_ net-_u17-pad2_ d_inverter
+* u18 net-_u1-pad1_ net-_u18-pad2_ d_inverter
+* u27 net-_u18-pad2_ net-_u27-pad2_ d_buffer
+* u28 net-_u28-pad1_ net-_u28-pad2_ net-_u28-pad3_ d_and
+* u30 net-_u29-pad3_ net-_u1-pad19_ d_inverter
+* u29 net-_u28-pad3_ net-_u27-pad2_ net-_u29-pad3_ d_and
+* u19 net-_u19-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_xnor
+* u20 net-_u20-pad1_ net-_u20-pad2_ net-_u20-pad3_ d_xnor
+* u21 net-_u21-pad1_ net-_u21-pad2_ net-_u21-pad3_ d_xnor
+* u23 net-_u10-pad2_ net-_u11-pad2_ net-_u23-pad3_ d_xnor
+* u22 net-_u22-pad1_ net-_u22-pad2_ net-_u22-pad3_ d_xnor
+* u24 net-_u12-pad2_ net-_u13-pad2_ net-_u24-pad3_ d_xnor
+* u25 net-_u14-pad2_ net-_u15-pad2_ net-_u25-pad3_ d_xnor
+* u26 net-_u16-pad2_ net-_u17-pad2_ net-_u26-pad3_ d_xnor
+a1 net-_u1-pad17_ net-_u19-pad1_ u2
+a2 net-_u1-pad18_ net-_u19-pad2_ u3
+a3 net-_u1-pad15_ net-_u20-pad1_ u4
+a4 net-_u1-pad16_ net-_u20-pad2_ u5
+a5 net-_u1-pad13_ net-_u21-pad1_ u6
+a6 net-_u1-pad14_ net-_u21-pad2_ u7
+a7 net-_u1-pad11_ net-_u10-pad2_ u10
+a8 net-_u1-pad12_ net-_u11-pad2_ u11
+a9 net-_u1-pad8_ net-_u22-pad1_ u8
+a10 net-_u1-pad9_ net-_u22-pad2_ u9
+a11 net-_u1-pad6_ net-_u12-pad2_ u12
+a12 net-_u1-pad7_ net-_u13-pad2_ u13
+a13 net-_u1-pad4_ net-_u14-pad2_ u14
+a14 net-_u1-pad5_ net-_u15-pad2_ u15
+a15 net-_u1-pad2_ net-_u16-pad2_ u16
+a16 net-_u1-pad3_ net-_u17-pad2_ u17
+a17 net-_u1-pad1_ net-_u18-pad2_ u18
+a18 net-_u18-pad2_ net-_u27-pad2_ u27
+a19 [net-_u28-pad1_ net-_u28-pad2_ ] net-_u28-pad3_ u28
+a20 net-_u29-pad3_ net-_u1-pad19_ u30
+a21 [net-_u28-pad3_ net-_u27-pad2_ ] net-_u29-pad3_ u29
+a22 [net-_u19-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a23 [net-_u20-pad1_ net-_u20-pad2_ ] net-_u20-pad3_ u20
+a24 [net-_u21-pad1_ net-_u21-pad2_ ] net-_u21-pad3_ u21
+a25 [net-_u10-pad2_ net-_u11-pad2_ ] net-_u23-pad3_ u23
+a26 [net-_u22-pad1_ net-_u22-pad2_ ] net-_u22-pad3_ u22
+a27 [net-_u12-pad2_ net-_u13-pad2_ ] net-_u24-pad3_ u24
+a28 [net-_u14-pad2_ net-_u15-pad2_ ] net-_u25-pad3_ u25
+a29 [net-_u16-pad2_ net-_u17-pad2_ ] net-_u26-pad3_ u26
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u7 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u10 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u11 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u8 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u9 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u12 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u14 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u15 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u16 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u17 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u27 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u28 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u29 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u19 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u20 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u21 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u23 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u22 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u24 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u25 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u26 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends SN54F521
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/SN54F521_Previous_Values.xml b/library/SubcircuitLibrary/SN54F521/SN54F521_Previous_Values.xml new file mode 100644 index 00000000..755befb6 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SN54F521_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u19 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u19><u2 name="type">d_inverter<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u20 name="type">d_xor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u20><u4 name="type">d_inverter<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u5><u21 name="type">d_xor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u21><u6 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u7><u23 name="type">d_xor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u23><u10 name="type">d_inverter<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_inverter<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u11><u22 name="type">d_xor<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u22><u8 name="type">d_inverter<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_inverter<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u9><u24 name="type">d_xor<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u24><u12 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u12><u13 name="type">d_inverter<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u13><u25 name="type">d_xor<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u25><u14 name="type">d_inverter<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u14><u15 name="type">d_inverter<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u15><u26 name="type">d_xor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u26><u16 name="type">d_inverter<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u16><u17 name="type">d_inverter<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u17><u18 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u18><u27 name="type">d_buffer<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_and<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u28><u30 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u30><u29 name="type">d_and<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u29><u19 name="type">d_xnor<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u19><u20 name="type">d_xnor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u20><u21 name="type">d_xnor<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u21><u23 name="type">d_xnor<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u23><u22 name="type">d_xnor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u22><u24 name="type">d_xnor<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u24><u25 name="type">d_xnor<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u25><u26 name="type">d_xnor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u26></model><devicemodel /><subcircuit><x2><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x1><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/SN54F521/SUB file b/library/SubcircuitLibrary/SN54F521/SUB file new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/SUB file @@ -0,0 +1 @@ + diff --git a/library/SubcircuitLibrary/SN54F521/analysis b/library/SubcircuitLibrary/SN54F521/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/SN54F521/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |