diff options
Diffstat (limited to 'library/SubcircuitLibrary/SN5485/SN5485.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/SN5485/SN5485.cir.out | 156 |
1 files changed, 156 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/SN5485/SN5485.cir.out b/library/SubcircuitLibrary/SN5485/SN5485.cir.out new file mode 100644 index 00000000..37ae8fb4 --- /dev/null +++ b/library/SubcircuitLibrary/SN5485/SN5485.cir.out @@ -0,0 +1,156 @@ +* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\sn5485\sn5485.cir + +.include 3_and.sub +.include 4_and.sub +.include 5_and.sub +* u19 net-_u18-pad2_ net-_u1-pad1_ net-_u19-pad3_ d_and +x2 net-_u14-pad3_ net-_u3-pad3_ net-_u1-pad3_ net-_u29-pad1_ 3_and +x4 net-_u15-pad3_ net-_u14-pad3_ net-_u10-pad2_ net-_u1-pad8_ net-_u28-pad1_ 4_and +x10 net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u12-pad2_ net-_u1-pad10_ net-_u27-pad1_ 5_and +x9 net-_u1-pad7_ net-_u17-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u14-pad3_ net-_u26-pad1_ 5_and +x8 net-_u1-pad6_ net-_u17-pad3_ net-_u16-pad3_ net-_u15-pad3_ net-_u14-pad3_ net-_u25-pad1_ 5_and +x7 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad6_ net-_u31-pad1_ 5_and +x6 net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad5_ net-_u24-pad1_ 5_and +x5 net-_u1-pad11_ net-_u12-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u16-pad3_ net-_u23-pad1_ 5_and +x3 net-_u1-pad9_ net-_u10-pad2_ net-_u14-pad3_ net-_u15-pad3_ net-_u22-pad1_ 4_and +x1 net-_u1-pad4_ net-_u3-pad3_ net-_u14-pad3_ net-_u21-pad1_ 3_and +* u18 net-_u1-pad2_ net-_u18-pad2_ net-_u18-pad3_ d_and +x12 net-_u20-pad2_ net-_u21-pad2_ net-_u22-pad2_ net-_u23-pad2_ net-_u24-pad2_ net-_u33-pad1_ 5_and +* u33 net-_u33-pad1_ net-_u31-pad2_ net-_u1-pad12_ d_and +* u20 net-_u18-pad3_ net-_u20-pad2_ d_inverter +* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter +* u22 net-_u22-pad1_ net-_u22-pad2_ d_inverter +* u23 net-_u23-pad1_ net-_u23-pad2_ d_inverter +* u24 net-_u24-pad1_ net-_u24-pad2_ d_inverter +* u31 net-_u31-pad1_ net-_u31-pad2_ d_inverter +x13 net-_u25-pad2_ net-_u26-pad2_ net-_u27-pad2_ net-_u28-pad2_ net-_u29-pad2_ net-_u32-pad1_ 5_and +* u32 net-_u32-pad1_ net-_u30-pad2_ net-_u1-pad14_ d_and +* u25 net-_u25-pad1_ net-_u25-pad2_ d_inverter +* u26 net-_u26-pad1_ net-_u26-pad2_ d_inverter +* u27 net-_u27-pad1_ net-_u27-pad2_ d_inverter +* u28 net-_u28-pad1_ net-_u28-pad2_ d_inverter +* u29 net-_u29-pad1_ net-_u29-pad2_ d_inverter +* u30 net-_u19-pad3_ net-_u30-pad2_ d_inverter +* u6 net-_u1-pad1_ net-_u18-pad2_ net-_u14-pad1_ d_and +* u7 net-_u18-pad2_ net-_u1-pad2_ net-_u14-pad2_ d_and +* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u14-pad3_ d_nor +* u15 net-_u15-pad1_ net-_u15-pad2_ net-_u15-pad3_ d_nor +* u8 net-_u1-pad3_ net-_u3-pad3_ net-_u15-pad1_ d_and +* u9 net-_u3-pad3_ net-_u1-pad4_ net-_u15-pad2_ d_and +* u16 net-_u10-pad3_ net-_u11-pad3_ net-_u16-pad3_ d_nor +* u10 net-_u1-pad8_ net-_u10-pad2_ net-_u10-pad3_ d_and +* u11 net-_u10-pad2_ net-_u1-pad9_ net-_u11-pad3_ d_and +* u12 net-_u1-pad10_ net-_u12-pad2_ net-_u12-pad3_ d_and +* u13 net-_u12-pad2_ net-_u1-pad11_ net-_u13-pad3_ d_and +* u17 net-_u12-pad3_ net-_u13-pad3_ net-_u17-pad3_ d_nor +* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u18-pad2_ d_nand +* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_nand +* u4 net-_u1-pad8_ net-_u1-pad9_ net-_u10-pad2_ d_nand +* u5 net-_u1-pad10_ net-_u1-pad11_ net-_u12-pad2_ d_nand +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ port +x11 net-_u14-pad3_ net-_u15-pad3_ net-_u1-pad6_ net-_u16-pad3_ net-_u17-pad3_ net-_u1-pad13_ 5_and +a1 [net-_u18-pad2_ net-_u1-pad1_ ] net-_u19-pad3_ u19 +a2 [net-_u1-pad2_ net-_u18-pad2_ ] net-_u18-pad3_ u18 +a3 [net-_u33-pad1_ net-_u31-pad2_ ] net-_u1-pad12_ u33 +a4 net-_u18-pad3_ net-_u20-pad2_ u20 +a5 net-_u21-pad1_ net-_u21-pad2_ u21 +a6 net-_u22-pad1_ net-_u22-pad2_ u22 +a7 net-_u23-pad1_ net-_u23-pad2_ u23 +a8 net-_u24-pad1_ net-_u24-pad2_ u24 +a9 net-_u31-pad1_ net-_u31-pad2_ u31 +a10 [net-_u32-pad1_ net-_u30-pad2_ ] net-_u1-pad14_ u32 +a11 net-_u25-pad1_ net-_u25-pad2_ u25 +a12 net-_u26-pad1_ net-_u26-pad2_ u26 +a13 net-_u27-pad1_ net-_u27-pad2_ u27 +a14 net-_u28-pad1_ net-_u28-pad2_ u28 +a15 net-_u29-pad1_ net-_u29-pad2_ u29 +a16 net-_u19-pad3_ net-_u30-pad2_ u30 +a17 [net-_u1-pad1_ net-_u18-pad2_ ] net-_u14-pad1_ u6 +a18 [net-_u18-pad2_ net-_u1-pad2_ ] net-_u14-pad2_ u7 +a19 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u14-pad3_ u14 +a20 [net-_u15-pad1_ net-_u15-pad2_ ] net-_u15-pad3_ u15 +a21 [net-_u1-pad3_ net-_u3-pad3_ ] net-_u15-pad1_ u8 +a22 [net-_u3-pad3_ net-_u1-pad4_ ] net-_u15-pad2_ u9 +a23 [net-_u10-pad3_ net-_u11-pad3_ ] net-_u16-pad3_ u16 +a24 [net-_u1-pad8_ net-_u10-pad2_ ] net-_u10-pad3_ u10 +a25 [net-_u10-pad2_ net-_u1-pad9_ ] net-_u11-pad3_ u11 +a26 [net-_u1-pad10_ net-_u12-pad2_ ] net-_u12-pad3_ u12 +a27 [net-_u12-pad2_ net-_u1-pad11_ ] net-_u13-pad3_ u13 +a28 [net-_u12-pad3_ net-_u13-pad3_ ] net-_u17-pad3_ u17 +a29 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u18-pad2_ u2 +a30 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3 +a31 [net-_u1-pad8_ net-_u1-pad9_ ] net-_u10-pad2_ u4 +a32 [net-_u1-pad10_ net-_u1-pad11_ ] net-_u12-pad2_ u5 +* Schematic Name: d_and, NgSpice Name: d_and +.model u19 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u18 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u33 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u20 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u22 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u24 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u31 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u32 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u27 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u28 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u30 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u14 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u15 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u16 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u11 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u13 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nor, NgSpice Name: d_nor +.model u17 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u2 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u3 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u4 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_nand, NgSpice Name: d_nand +.model u5 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |