summaryrefslogtreecommitdiff
path: root/library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net
diff options
context:
space:
mode:
Diffstat (limited to 'library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net')
-rw-r--r--library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net294
1 files changed, 294 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net b/library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net
new file mode 100644
index 00000000..90136df9
--- /dev/null
+++ b/library/SubcircuitLibrary/MC1496_IC1/MC1496_IC1.net
@@ -0,0 +1,294 @@
+(export (version D)
+ (design
+ (source C:/Users/Aditya/eSim-Workspace/MC1496_IC1/MC1496_IC1.sch)
+ (date "06/12/24 15:21:33")
+ (tool "Eeschema 4.0.7")
+ (sheet (number 1) (name /) (tstamps /)
+ (title_block
+ (title)
+ (company)
+ (rev)
+ (date)
+ (source MC1496_IC1.sch)
+ (comment (number 1) (value ""))
+ (comment (number 2) (value ""))
+ (comment (number 3) (value ""))
+ (comment (number 4) (value "")))))
+ (components
+ (comp (ref X1)
+ (value MC1496)
+ (libsource (lib eSim_Subckt) (part MC1496))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668C05F))
+ (comp (ref R7)
+ (value 1k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668C0C6))
+ (comp (ref R9)
+ (value 51)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668C413))
+ (comp (ref R10)
+ (value 1k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668C5EA))
+ (comp (ref R11)
+ (value 1k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668C93C))
+ (comp (ref R2)
+ (value 10k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668CAC4))
+ (comp (ref R1)
+ (value 10k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668CB1C))
+ (comp (ref R3)
+ (value 51)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668CB75))
+ (comp (ref R6)
+ (value 51)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 6668CBE1))
+ (comp (ref R8)
+ (value 6.8k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66694A7B))
+ (comp (ref R4)
+ (value 3.9k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66695AE8))
+ (comp (ref R5)
+ (value 3.9k)
+ (libsource (lib eSim_Devices) (part resistor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66695F1B))
+ (comp (ref v3)
+ (value DC)
+ (footprint R1)
+ (libsource (lib eSim_Sources) (part DC))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66696605))
+ (comp (ref v2)
+ (value DC)
+ (footprint R1)
+ (libsource (lib eSim_Sources) (part DC))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 666969AA))
+ (comp (ref v1)
+ (value sine)
+ (footprint R1)
+ (libsource (lib eSim_Sources) (part sine))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66696F5A))
+ (comp (ref v4)
+ (value sine)
+ (footprint R1)
+ (libsource (lib eSim_Sources) (part sine))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66697195))
+ (comp (ref U4)
+ (value plot_v1)
+ (libsource (lib eSim_Plot) (part plot_v1))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 666986F6))
+ (comp (ref U1)
+ (value plot_v1)
+ (libsource (lib eSim_Plot) (part plot_v1))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66698947))
+ (comp (ref U2)
+ (value plot_v1)
+ (libsource (lib eSim_Plot) (part plot_v1))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66698C09))
+ (comp (ref U3)
+ (value plot_v1)
+ (libsource (lib eSim_Plot) (part plot_v1))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66698EAE))
+ (comp (ref C1)
+ (value 0.47u)
+ (libsource (lib eSim_Devices) (part capacitor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66697216))
+ (comp (ref C2)
+ (value 0.1u)
+ (libsource (lib eSim_Devices) (part capacitor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 666972F9))
+ (comp (ref C3)
+ (value 0.1u)
+ (libsource (lib eSim_Devices) (part capacitor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66697427))
+ (comp (ref C4)
+ (value 2.47u)
+ (libsource (lib eSim_Devices) (part capacitor))
+ (sheetpath (names /) (tstamps /))
+ (tstamp 66697B54)))
+ (libparts
+ (libpart (lib eSim_Sources) (part DC)
+ (footprints
+ (fp 1_pin))
+ (fields
+ (field (name Reference) v)
+ (field (name Value) DC)
+ (field (name Footprint) R1))
+ (pins
+ (pin (num 1) (name +) (type power_out))
+ (pin (num 2) (name -) (type power_out))))
+ (libpart (lib eSim_Subckt) (part MC1496)
+ (fields
+ (field (name Reference) X)
+ (field (name Value) MC1496))
+ (pins
+ (pin (num 1) (name Signal_IN+) (type input))
+ (pin (num 2) (name Gain_Adj1) (type input))
+ (pin (num 3) (name Gain_Adj2) (type input))
+ (pin (num 4) (name Sig_IN-) (type input))
+ (pin (num 5) (name Bias) (type input))
+ (pin (num 6) (name OUT+) (type output))
+ (pin (num 7) (name NC) (type NotConnected))
+ (pin (num 8) (name Carrier_IN+) (type input))
+ (pin (num 9) (name NC) (type NotConnected))
+ (pin (num 10) (name Carrier_IN-) (type input))
+ (pin (num 11) (name NC) (type NotConnected))
+ (pin (num 12) (name OUT-) (type output))
+ (pin (num 13) (name NC) (type NotConnected))
+ (pin (num 14) (name VEE) (type input))))
+ (libpart (lib eSim_Devices) (part eSim_C)
+ (aliases
+ (alias capacitor))
+ (footprints
+ (fp C_*))
+ (fields
+ (field (name Reference) C)
+ (field (name Value) eSim_C))
+ (pins
+ (pin (num 1) (name ~) (type passive))
+ (pin (num 2) (name ~) (type passive))))
+ (libpart (lib eSim_Devices) (part eSim_R)
+ (aliases
+ (alias resistor))
+ (footprints
+ (fp R_*)
+ (fp Resistor_*))
+ (fields
+ (field (name Reference) R)
+ (field (name Value) eSim_R))
+ (pins
+ (pin (num 1) (name ~) (type passive))
+ (pin (num 2) (name ~) (type passive))))
+ (libpart (lib eSim_Plot) (part plot_v1)
+ (fields
+ (field (name Reference) U)
+ (field (name Value) plot_v1))
+ (pins
+ (pin (num ~) (name ~) (type input))))
+ (libpart (lib eSim_Sources) (part sine)
+ (footprints
+ (fp 1_pin))
+ (fields
+ (field (name Reference) v)
+ (field (name Value) sine)
+ (field (name Footprint) R1))
+ (pins
+ (pin (num 1) (name +) (type input))
+ (pin (num 2) (name -) (type input)))))
+ (libraries
+ (library (logical eSim_Devices)
+ (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Devices.lib))
+ (library (logical eSim_Plot)
+ (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Plot.lib))
+ (library (logical eSim_Sources)
+ (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Sources.lib))
+ (library (logical eSim_Subckt)
+ (uri C:\FOSSEE\KiCad\share\kicad\library\eSim_Subckt.lib)))
+ (nets
+ (net (code 1) (name GND)
+ (node (ref C3) (pin 1))
+ (node (ref R10) (pin 2))
+ (node (ref C1) (pin 2))
+ (node (ref C4) (pin 1))
+ (node (ref R8) (pin 2))
+ (node (ref R6) (pin 2))
+ (node (ref v3) (pin 2))
+ (node (ref R3) (pin 2))
+ (node (ref v2) (pin 2))
+ (node (ref v1) (pin 2))
+ (node (ref v4) (pin 2)))
+ (net (code 2) (name "Net-(R8-Pad1)")
+ (node (ref X1) (pin 5))
+ (node (ref R8) (pin 1)))
+ (net (code 3) (name "Net-(C3-Pad2)")
+ (node (ref R10) (pin 1))
+ (node (ref R9) (pin 2))
+ (node (ref X1) (pin 8))
+ (node (ref R11) (pin 2))
+ (node (ref C3) (pin 2)))
+ (net (code 4) (name OUT_n)
+ (node (ref U3) (pin ~))
+ (node (ref X1) (pin 12))
+ (node (ref R5) (pin 2)))
+ (net (code 5) (name CAR)
+ (node (ref C2) (pin 1))
+ (node (ref U4) (pin ~))
+ (node (ref v4) (pin 1)))
+ (net (code 6) (name OUT_p)
+ (node (ref X1) (pin 6))
+ (node (ref R4) (pin 1))
+ (node (ref U2) (pin ~)))
+ (net (code 7) (name "Net-(R7-Pad2)")
+ (node (ref X1) (pin 3))
+ (node (ref R7) (pin 2)))
+ (net (code 8) (name "Net-(C2-Pad2)")
+ (node (ref X1) (pin 10))
+ (node (ref C2) (pin 2))
+ (node (ref R9) (pin 1)))
+ (net (code 9) (name "Net-(X1-Pad11)")
+ (node (ref X1) (pin 11)))
+ (net (code 10) (name "Net-(R7-Pad1)")
+ (node (ref R7) (pin 1))
+ (node (ref X1) (pin 2)))
+ (net (code 11) (name "Net-(X1-Pad7)")
+ (node (ref X1) (pin 7)))
+ (net (code 12) (name "Net-(X1-Pad9)")
+ (node (ref X1) (pin 9)))
+ (net (code 13) (name "Net-(X1-Pad13)")
+ (node (ref X1) (pin 13)))
+ (net (code 14) (name "Net-(X1-Pad14)")
+ (node (ref v2) (pin 1))
+ (node (ref X1) (pin 14)))
+ (net (code 15) (name "Net-(C1-Pad1)")
+ (node (ref R2) (pin 2))
+ (node (ref C1) (pin 1))
+ (node (ref R1) (pin 2)))
+ (net (code 16) (name SIG)
+ (node (ref v1) (pin 1))
+ (node (ref R1) (pin 1))
+ (node (ref X1) (pin 1))
+ (node (ref R3) (pin 1))
+ (node (ref U1) (pin ~)))
+ (net (code 17) (name "Net-(C4-Pad2)")
+ (node (ref C4) (pin 2))
+ (node (ref R5) (pin 1))
+ (node (ref R11) (pin 1))
+ (node (ref v3) (pin 1))
+ (node (ref R4) (pin 2)))
+ (net (code 18) (name "Net-(R2-Pad1)")
+ (node (ref R6) (pin 1))
+ (node (ref R2) (pin 1))
+ (node (ref X1) (pin 4))))) \ No newline at end of file
generated by cgit (git 2.34.1) at 2024-12-20 14:18:50 +0000