diff options
Diffstat (limited to 'library/SubcircuitLibrary/MC10H166')
18 files changed, 2629 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR-cache.lib b/library/SubcircuitLibrary/MC10H166/4_OR-cache.lib new file mode 100644 index 00000000..a3c1c972 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR-cache.lib @@ -0,0 +1,63 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR.cir b/library/SubcircuitLibrary/MC10H166/4_OR.cir new file mode 100644 index 00000000..7adbf177 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR.cir @@ -0,0 +1,14 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4_OR\4_OR.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/28/19 22:47:12
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_or
+U3 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U3-Pad3_ d_or
+U4 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U1-Pad5_ d_or
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR.cir.out b/library/SubcircuitLibrary/MC10H166/4_OR.cir.out new file mode 100644 index 00000000..4388b975 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR.cir.out @@ -0,0 +1,24 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR.pro b/library/SubcircuitLibrary/MC10H166/4_OR.pro new file mode 100644 index 00000000..a19bf425 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR.pro @@ -0,0 +1,44 @@ +update=06/01/19 12:36:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR.sch b/library/SubcircuitLibrary/MC10H166/4_OR.sch new file mode 100644 index 00000000..2f28896c --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR.sch @@ -0,0 +1,150 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_or U2
+U 1 1 5C9D00E1
+P 4300 2950
+F 0 "U2" H 4300 2950 60 0000 C CNN
+F 1 "d_or" H 4300 3050 60 0000 C CNN
+F 2 "" H 4300 2950 60 0000 C CNN
+F 3 "" H 4300 2950 60 0000 C CNN
+ 1 4300 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U3
+U 1 1 5C9D011F
+P 4300 3350
+F 0 "U3" H 4300 3350 60 0000 C CNN
+F 1 "d_or" H 4300 3450 60 0000 C CNN
+F 2 "" H 4300 3350 60 0000 C CNN
+F 3 "" H 4300 3350 60 0000 C CNN
+ 1 4300 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U4
+U 1 1 5C9D0141
+P 5250 3150
+F 0 "U4" H 5250 3150 60 0000 C CNN
+F 1 "d_or" H 5250 3250 60 0000 C CNN
+F 2 "" H 5250 3150 60 0000 C CNN
+F 3 "" H 5250 3150 60 0000 C CNN
+ 1 5250 3150
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4800 3050 4800 2900
+Wire Wire Line
+ 4800 2900 4750 2900
+Wire Wire Line
+ 4800 3150 4800 3300
+Wire Wire Line
+ 4800 3300 4750 3300
+Wire Wire Line
+ 3350 2850 3850 2850
+Wire Wire Line
+ 3850 2950 3600 2950
+Wire Wire Line
+ 3850 3250 3350 3250
+Wire Wire Line
+ 3600 2950 3600 3000
+Wire Wire Line
+ 3600 3000 3350 3000
+Wire Wire Line
+ 3850 3350 3850 3400
+Wire Wire Line
+ 3850 3400 3350 3400
+Wire Wire Line
+ 5700 3100 6200 3100
+$Comp
+L PORT U1
+U 1 1 5C9D01F4
+P 3100 2850
+F 0 "U1" H 3150 2950 30 0000 C CNN
+F 1 "PORT" H 3100 2850 30 0000 C CNN
+F 2 "" H 3100 2850 60 0000 C CNN
+F 3 "" H 3100 2850 60 0000 C CNN
+ 1 3100 2850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9D022F
+P 3100 3000
+F 0 "U1" H 3150 3100 30 0000 C CNN
+F 1 "PORT" H 3100 3000 30 0000 C CNN
+F 2 "" H 3100 3000 60 0000 C CNN
+F 3 "" H 3100 3000 60 0000 C CNN
+ 2 3100 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9D0271
+P 3100 3250
+F 0 "U1" H 3150 3350 30 0000 C CNN
+F 1 "PORT" H 3100 3250 30 0000 C CNN
+F 2 "" H 3100 3250 60 0000 C CNN
+F 3 "" H 3100 3250 60 0000 C CNN
+ 3 3100 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9D0299
+P 3100 3400
+F 0 "U1" H 3150 3500 30 0000 C CNN
+F 1 "PORT" H 3100 3400 30 0000 C CNN
+F 2 "" H 3100 3400 60 0000 C CNN
+F 3 "" H 3100 3400 60 0000 C CNN
+ 4 3100 3400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9D02C2
+P 6450 3100
+F 0 "U1" H 6500 3200 30 0000 C CNN
+F 1 "PORT" H 6450 3100 30 0000 C CNN
+F 2 "" H 6450 3100 60 0000 C CNN
+F 3 "" H 6450 3100 60 0000 C CNN
+ 5 6450 3100
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2850 0 60 ~ 12
+in1
+Text Notes 3450 3000 0 60 ~ 12
+in2
+Text Notes 3450 3250 0 60 ~ 12
+in3
+Text Notes 3450 3400 0 60 ~ 12
+in4
+Text Notes 5800 3100 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC10H166/4_OR.sub b/library/SubcircuitLibrary/MC10H166/4_OR.sub new file mode 100644 index 00000000..53fc8b33 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR.sub @@ -0,0 +1,18 @@ +* Subcircuit 4_OR
+.subckt 4_OR net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_or\4_or.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_or
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u1-pad5_ d_or
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u1-pad5_ u4
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u3 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u4 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_OR
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H166/4_OR_Previous_Values.xml b/library/SubcircuitLibrary/MC10H166/4_OR_Previous_Values.xml new file mode 100644 index 00000000..0683d9eb --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/4_OR_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_or<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_or<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u4></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166-cache.lib b/library/SubcircuitLibrary/MC10H166/MC10H166-cache.lib new file mode 100644 index 00000000..727ea0a3 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166-cache.lib @@ -0,0 +1,154 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4_OR
+#
+DEF 4_OR X 0 40 Y Y 1 F N
+F0 "X" 150 -100 60 H V C CNN
+F1 "4_OR" 150 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250
+A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0
+A -30 -99 393 627 146 0 1 0 N 150 250 350 0
+P 2 0 1 0 -200 -250 150 -250 N
+P 2 0 1 0 -200 250 150 250 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X in4 4 -350 -150 200 R 50 50 1 1 I
+X out 5 550 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.bak b/library/SubcircuitLibrary/MC10H166/MC10H166.bak new file mode 100644 index 00000000..b9ef4775 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.bak @@ -0,0 +1,874 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC10H166-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U10
+U 1 1 681518A6
+P 2650 4450
+F 0 "U10" H 2650 4450 60 0000 C CNN
+F 1 "d_xor" H 2700 4550 47 0000 C CNN
+F 2 "" H 2650 4450 60 0000 C CNN
+F 3 "" H 2650 4450 60 0000 C CNN
+ 1 2650 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U9
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+F 1 "d_or" H 2650 4100 60 0000 C CNN
+F 2 "" H 2650 4000 60 0000 C CNN
+F 3 "" H 2650 4000 60 0000 C CNN
+ 1 2650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 681518B2
+P 1900 4200
+F 0 "U3" H 1900 4100 60 0000 C CNN
+F 1 "d_inverter" H 1900 4350 60 0000 C CNN
+F 2 "" H 1950 4150 60 0000 C CNN
+F 3 "" H 1950 4150 60 0000 C CNN
+ 1 1900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U19
+U 1 1 68151AAF
+P 5600 3800
+F 0 "U19" H 5600 3800 60 0000 C CNN
+F 1 "d_nor" H 5650 3900 60 0000 C CNN
+F 2 "" H 5600 3800 60 0000 C CNN
+F 3 "" H 5600 3800 60 0000 C CNN
+ 1 5600 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X3
+U 1 1 68151B0E
+P 5500 3050
+F 0 "X3" H 5650 2950 60 0000 C CNN
+F 1 "4_OR" H 5650 3150 60 0000 C CNN
+F 2 "" H 5500 3050 60 0000 C CNN
+F 3 "" H 5500 3050 60 0000 C CNN
+ 1 5500 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X2
+U 1 1 68151BD0
+P 5400 1750
+F 0 "X2" H 5550 1650 60 0000 C CNN
+F 1 "4_OR" H 5550 1850 60 0000 C CNN
+F 2 "" H 5400 1750 60 0000 C CNN
+F 3 "" H 5400 1750 60 0000 C CNN
+ 1 5400 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U24
+U 1 1 68151C14
+P 6500 2200
+F 0 "U24" H 6500 2200 60 0000 C CNN
+F 1 "d_or" H 6500 2300 60 0000 C CNN
+F 2 "" H 6500 2200 60 0000 C CNN
+F 3 "" H 6500 2200 60 0000 C CNN
+ 1 6500 2200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5950 1750 6050 1750
+Wire Wire Line
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+$Comp
+L d_inverter U26
+U 1 1 68151DBD
+P 7250 2150
+F 0 "U26" H 7250 2050 60 0000 C CNN
+F 1 "d_inverter" H 7250 2300 60 0000 C CNN
+F 2 "" H 7300 2100 60 0000 C CNN
+F 3 "" H 7300 2100 60 0000 C CNN
+ 1 7250 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X1
+U 1 1 681521BE
+P 5250 4950
+F 0 "X1" H 5400 4850 60 0000 C CNN
+F 1 "4_OR" H 5400 5050 60 0000 C CNN
+F 2 "" H 5250 4950 60 0000 C CNN
+F 3 "" H 5250 4950 60 0000 C CNN
+ 1 5250 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U22
+U 1 1 681521C4
+P 6350 5400
+F 0 "U22" H 6350 5400 60 0000 C CNN
+F 1 "d_or" H 6350 5500 60 0000 C CNN
+F 2 "" H 6350 5400 60 0000 C CNN
+F 3 "" H 6350 5400 60 0000 C CNN
+ 1 6350 5400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5800 4950 5900 4950
+Wire Wire Line
+ 5900 4950 5900 5300
+$Comp
+L d_inverter U25
+U 1 1 681521CC
+P 7100 5350
+F 0 "U25" H 7100 5250 60 0000 C CNN
+F 1 "d_inverter" H 7100 5500 60 0000 C CNN
+F 2 "" H 7150 5300 60 0000 C CNN
+F 3 "" H 7150 5300 60 0000 C CNN
+ 1 7100 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 681522D1
+P 6350 3050
+F 0 "U21" H 6350 2950 60 0000 C CNN
+F 1 "d_inverter" H 6350 3200 60 0000 C CNN
+F 2 "" H 6400 3000 60 0000 C CNN
+F 3 "" H 6400 3000 60 0000 C CNN
+ 1 6350 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 68152332
+P 5500 2500
+F 0 "U18" H 5500 2400 60 0000 C CNN
+F 1 "d_inverter" H 5500 2650 60 0000 C CNN
+F 2 "" H 5550 2450 60 0000 C CNN
+F 3 "" H 5550 2450 60 0000 C CNN
+ 1 5500 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U17
+U 1 1 681523E1
+P 4700 4350
+F 0 "U17" H 4700 4350 60 0000 C CNN
+F 1 "d_or" H 4700 4450 60 0000 C CNN
+F 2 "" H 4700 4350 60 0000 C CNN
+F 3 "" H 4700 4350 60 0000 C CNN
+ 1 4700 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U20
+U 1 1 68152548
+P 5700 4400
+F 0 "U20" H 5700 4400 60 0000 C CNN
+F 1 "d_or" H 5700 4500 60 0000 C CNN
+F 2 "" H 5700 4400 60 0000 C CNN
+F 3 "" H 5700 4400 60 0000 C CNN
+ 1 5700 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5250 4300 5150 4300
+$Comp
+L d_inverter U23
+U 1 1 681528D0
+P 6450 4350
+F 0 "U23" H 6450 4250 60 0000 C CNN
+F 1 "d_inverter" H 6450 4500 60 0000 C CNN
+F 2 "" H 6500 4300 60 0000 C CNN
+F 3 "" H 6500 4300 60 0000 C CNN
+ 1 6450 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X4
+U 1 1 681535BF
+P 7600 3450
+F 0 "X4" H 7750 3350 60 0000 C CNN
+F 1 "4_OR" H 7750 3550 60 0000 C CNN
+F 2 "" H 7600 3450 60 0000 C CNN
+F 3 "" H 7600 3450 60 0000 C CNN
+ 1 7600 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U27
+U 1 1 681535C5
+P 8700 3900
+F 0 "U27" H 8700 3900 60 0000 C CNN
+F 1 "d_or" H 8700 4000 60 0000 C CNN
+F 2 "" H 8700 3900 60 0000 C CNN
+F 3 "" H 8700 3900 60 0000 C CNN
+ 1 8700 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L d_or U28
+U 1 1 68154B3E
+P 9250 3050
+F 0 "U28" H 9250 3050 60 0000 C CNN
+F 1 "d_or" H 9250 3150 60 0000 C CNN
+F 2 "" H 9250 3050 60 0000 C CNN
+F 3 "" H 9250 3050 60 0000 C CNN
+ 1 9250 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U31
+U 1 1 68154B44
+P 10250 3100
+F 0 "U31" H 10250 3100 60 0000 C CNN
+F 1 "d_or" H 10250 3200 60 0000 C CNN
+F 2 "" H 10250 3100 60 0000 C CNN
+F 3 "" H 10250 3100 60 0000 C CNN
+ 1 10250 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9800 3000 9700 3000
+$Comp
+L d_inverter U32
+U 1 1 68154B4B
+P 11000 3050
+F 0 "U32" H 11000 2950 60 0000 C CNN
+F 1 "d_inverter" H 11000 3200 60 0000 C CNN
+F 2 "" H 11050 3000 60 0000 C CNN
+F 3 "" H 11050 3000 60 0000 C CNN
+ 1 11000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 68154B74
+P 10200 4350
+F 0 "U30" H 10200 4350 60 0000 C CNN
+F 1 "d_and" H 10250 4450 60 0000 C CNN
+F 2 "" H 10200 4350 60 0000 C CNN
+F 3 "" H 10200 4350 60 0000 C CNN
+ 1 10200 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 68154C6B
+P 9450 4350
+F 0 "U29" H 9450 4250 60 0000 C CNN
+F 1 "d_inverter" H 9450 4500 60 0000 C CNN
+F 2 "" H 9500 4300 60 0000 C CNN
+F 3 "" H 9500 4300 60 0000 C CNN
+ 1 9450 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1200 4350 2200 4350
+Wire Wire Line
+ 1600 4350 1600 4200
+Wire Wire Line
+ 2200 4000 2200 4200
+Wire Wire Line
+ 2200 3900 1550 3900
+Wire Wire Line
+ 1550 3900 1550 4450
+Wire Wire Line
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+Connection ~ 1550 4450
+Connection ~ 1600 4350
+$Comp
+L d_xor U14
+U 1 1 681554DE
+P 2700 3200
+F 0 "U14" H 2700 3200 60 0000 C CNN
+F 1 "d_xor" H 2750 3300 47 0000 C CNN
+F 2 "" H 2700 3200 60 0000 C CNN
+F 3 "" H 2700 3200 60 0000 C CNN
+ 1 2700 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U13
+U 1 1 681554E4
+P 2700 2750
+F 0 "U13" H 2700 2750 60 0000 C CNN
+F 1 "d_or" H 2700 2850 60 0000 C CNN
+F 2 "" H 2700 2750 60 0000 C CNN
+F 3 "" H 2700 2750 60 0000 C CNN
+ 1 2700 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 681554EA
+P 1950 2950
+F 0 "U5" H 1950 2850 60 0000 C CNN
+F 1 "d_inverter" H 1950 3100 60 0000 C CNN
+F 2 "" H 2000 2900 60 0000 C CNN
+F 3 "" H 2000 2900 60 0000 C CNN
+ 1 1950 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1250 3100 2250 3100
+Wire Wire Line
+ 1650 3100 1650 2950
+Wire Wire Line
+ 2250 2750 2250 2950
+Wire Wire Line
+ 2250 2650 1600 2650
+Wire Wire Line
+ 1600 2650 1600 3200
+Wire Wire Line
+ 1150 3200 2250 3200
+Connection ~ 1600 3200
+Connection ~ 1650 3100
+$Comp
+L d_xor U12
+U 1 1 68155848
+P 2650 7050
+F 0 "U12" H 2650 7050 60 0000 C CNN
+F 1 "d_xor" H 2700 7150 47 0000 C CNN
+F 2 "" H 2650 7050 60 0000 C CNN
+F 3 "" H 2650 7050 60 0000 C CNN
+ 1 2650 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U11
+U 1 1 6815584E
+P 2650 6600
+F 0 "U11" H 2650 6600 60 0000 C CNN
+F 1 "d_or" H 2650 6700 60 0000 C CNN
+F 2 "" H 2650 6600 60 0000 C CNN
+F 3 "" H 2650 6600 60 0000 C CNN
+ 1 2650 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68155854
+P 1900 6800
+F 0 "U4" H 1900 6700 60 0000 C CNN
+F 1 "d_inverter" H 1900 6950 60 0000 C CNN
+F 2 "" H 1950 6750 60 0000 C CNN
+F 3 "" H 1950 6750 60 0000 C CNN
+ 1 1900 6800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
+ 1600 6950 1600 6800
+Wire Wire Line
+ 2200 6600 2200 6800
+Wire Wire Line
+ 2200 6500 1550 6500
+Wire Wire Line
+ 1550 6500 1550 7050
+Wire Wire Line
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+Connection ~ 1550 7050
+Connection ~ 1600 6950
+$Comp
+L d_xor U16
+U 1 1 68155862
+P 2700 5800
+F 0 "U16" H 2700 5800 60 0000 C CNN
+F 1 "d_xor" H 2750 5900 47 0000 C CNN
+F 2 "" H 2700 5800 60 0000 C CNN
+F 3 "" H 2700 5800 60 0000 C CNN
+ 1 2700 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U15
+U 1 1 68155868
+P 2700 5350
+F 0 "U15" H 2700 5350 60 0000 C CNN
+F 1 "d_or" H 2700 5450 60 0000 C CNN
+F 2 "" H 2700 5350 60 0000 C CNN
+F 3 "" H 2700 5350 60 0000 C CNN
+ 1 2700 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 6815586E
+P 1950 5550
+F 0 "U6" H 1950 5450 60 0000 C CNN
+F 1 "d_inverter" H 1950 5700 60 0000 C CNN
+F 2 "" H 2000 5500 60 0000 C CNN
+F 3 "" H 2000 5500 60 0000 C CNN
+ 1 1950 5550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1250 5700 2250 5700
+Wire Wire Line
+ 1650 5700 1650 5550
+Wire Wire Line
+ 2250 5350 2250 5550
+Wire Wire Line
+ 2250 5250 1600 5250
+Wire Wire Line
+ 1600 5250 1600 5800
+Wire Wire Line
+ 1200 5800 2250 5800
+Connection ~ 1600 5800
+Connection ~ 1650 5700
+$Comp
+L d_xor U8
+U 1 1 681559C2
+P 2600 1850
+F 0 "U8" H 2600 1850 60 0000 C CNN
+F 1 "d_xor" H 2650 1950 47 0000 C CNN
+F 2 "" H 2600 1850 60 0000 C CNN
+F 3 "" H 2600 1850 60 0000 C CNN
+ 1 2600 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U7
+U 1 1 681559C8
+P 2600 1400
+F 0 "U7" H 2600 1400 60 0000 C CNN
+F 1 "d_or" H 2600 1500 60 0000 C CNN
+F 2 "" H 2600 1400 60 0000 C CNN
+F 3 "" H 2600 1400 60 0000 C CNN
+ 1 2600 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 681559CE
+P 1850 1600
+F 0 "U2" H 1850 1500 60 0000 C CNN
+F 1 "d_inverter" H 1850 1750 60 0000 C CNN
+F 2 "" H 1900 1550 60 0000 C CNN
+F 3 "" H 1900 1550 60 0000 C CNN
+ 1 1850 1600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 2150 1400 2150 1600
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4750 3700
+Wire Wire Line
+ 4250 4250 4000 4250
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 4150 5100
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+$Comp
+L PORT U1
+U 1 1 68169E45
+P 1500 850
+F 0 "U1" H 1550 950 30 0000 C CNN
+F 1 "PORT" H 1500 850 30 0000 C CNN
+F 2 "" H 1500 850 60 0000 C CNN
+F 3 "" H 1500 850 60 0000 C CNN
+ 1 1500 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68169EEE
+P 11150 3350
+F 0 "U1" H 11200 3450 30 0000 C CNN
+F 1 "PORT" H 11150 3350 30 0000 C CNN
+F 2 "" H 11150 3350 60 0000 C CNN
+F 3 "" H 11150 3350 60 0000 C CNN
+ 2 11150 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68169F71
+P 950 7050
+F 0 "U1" H 1000 7150 30 0000 C CNN
+F 1 "PORT" H 950 7050 30 0000 C CNN
+F 2 "" H 950 7050 60 0000 C CNN
+F 3 "" H 950 7050 60 0000 C CNN
+ 4 950 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68169FDC
+P 10750 4500
+F 0 "U1" H 10800 4600 30 0000 C CNN
+F 1 "PORT" H 10750 4500 30 0000 C CNN
+F 2 "" H 10750 4500 60 0000 C CNN
+F 3 "" H 10750 4500 60 0000 C CNN
+ 3 10750 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6816A05B
+P 900 6800
+F 0 "U1" H 950 6900 30 0000 C CNN
+F 1 "PORT" H 900 6800 30 0000 C CNN
+F 2 "" H 900 6800 60 0000 C CNN
+F 3 "" H 900 6800 60 0000 C CNN
+ 5 900 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6816A0CA
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+F 0 "U1" H 1050 5800 30 0000 C CNN
+F 1 "PORT" H 1000 5700 30 0000 C CNN
+F 2 "" H 1000 5700 60 0000 C CNN
+F 3 "" H 1000 5700 60 0000 C CNN
+ 6 1000 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6816A151
+P 950 5950
+F 0 "U1" H 1000 6050 30 0000 C CNN
+F 1 "PORT" H 950 5950 30 0000 C CNN
+F 2 "" H 950 5950 60 0000 C CNN
+F 3 "" H 950 5950 60 0000 C CNN
+ 7 950 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6816A1CE
+P 3950 1150
+F 0 "U1" H 4000 1250 30 0000 C CNN
+F 1 "PORT" H 3950 1150 30 0000 C CNN
+F 2 "" H 3950 1150 60 0000 C CNN
+F 3 "" H 3950 1150 60 0000 C CNN
+ 8 3950 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6816A24F
+P 900 1750
+F 0 "U1" H 950 1850 30 0000 C CNN
+F 1 "PORT" H 900 1750 30 0000 C CNN
+F 2 "" H 900 1750 60 0000 C CNN
+F 3 "" H 900 1750 60 0000 C CNN
+ 9 900 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6816A615
+P 800 2050
+F 0 "U1" H 850 2150 30 0000 C CNN
+F 1 "PORT" H 800 2050 30 0000 C CNN
+F 2 "" H 800 2050 60 0000 C CNN
+F 3 "" H 800 2050 60 0000 C CNN
+ 10 800 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6816A798
+P 900 3450
+F 0 "U1" H 950 3550 30 0000 C CNN
+F 1 "PORT" H 900 3450 30 0000 C CNN
+F 2 "" H 900 3450 60 0000 C CNN
+F 3 "" H 900 3450 60 0000 C CNN
+ 11 900 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6816A829
+P 1000 3100
+F 0 "U1" H 1050 3200 30 0000 C CNN
+F 1 "PORT" H 1000 3100 30 0000 C CNN
+F 2 "" H 1000 3100 60 0000 C CNN
+F 3 "" H 1000 3100 60 0000 C CNN
+ 12 1000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6816A8AE
+P 900 4700
+F 0 "U1" H 950 4800 30 0000 C CNN
+F 1 "PORT" H 900 4700 30 0000 C CNN
+F 2 "" H 900 4700 60 0000 C CNN
+F 3 "" H 900 4700 60 0000 C CNN
+ 14 900 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6816A927
+P 950 4350
+F 0 "U1" H 1000 4450 30 0000 C CNN
+F 1 "PORT" H 950 4350 30 0000 C CNN
+F 2 "" H 950 4350 60 0000 C CNN
+F 3 "" H 950 4350 60 0000 C CNN
+ 13 950 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6816A9A0
+P 6150 850
+F 0 "U1" H 6200 950 30 0000 C CNN
+F 1 "PORT" H 6150 850 30 0000 C CNN
+F 2 "" H 6150 850 60 0000 C CNN
+F 3 "" H 6150 850 60 0000 C CNN
+ 16 6150 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6816AA21
+P 7050 5950
+F 0 "U1" H 7100 6050 30 0000 C CNN
+F 1 "PORT" H 7050 5950 30 0000 C CNN
+F 2 "" H 7050 5950 60 0000 C CNN
+F 3 "" H 7050 5950 60 0000 C CNN
+ 15 7050 5950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1050 2050 1050 1850
+Wire Wire Line
+ 1150 3450 1150 3200
+Wire Wire Line
+ 1200 4450 1200 4700
+Wire Wire Line
+ 1200 4700 1150 4700
+Wire Wire Line
+ 1200 5950 1200 5800
+Wire Wire Line
+ 1150 6800 1200 6800
+Wire Wire Line
+ 1200 6800 1200 6950
+Wire Wire Line
+ 11400 3350 11400 3050
+Wire Wire Line
+ 11400 3050 11300 3050
+Wire Wire Line
+ 10650 4300 11000 4300
+Wire Wire Line
+ 11000 4300 11000 4500
+NoConn ~ 2050 900
+NoConn ~ 4600 1150
+NoConn ~ 6650 850
+Wire Wire Line
+ 1750 850 2050 850
+Wire Wire Line
+ 2050 850 2050 900
+Wire Wire Line
+ 4200 1150 4600 1150
+Wire Wire Line
+ 6400 850 6650 850
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.cir b/library/SubcircuitLibrary/MC10H166/MC10H166.cir new file mode 100644 index 00000000..4dcd3308 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.cir @@ -0,0 +1,46 @@ +* C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\MC10H166\MC10H166.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/04/25 07:39:05
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U10 Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U10-Pad3_ d_xor
+U9 Net-_U1-Pad14_ Net-_U3-Pad2_ Net-_U19-Pad2_ d_or
+U3 Net-_U1-Pad13_ Net-_U3-Pad2_ d_inverter
+U19 Net-_U17-Pad1_ Net-_U19-Pad2_ Net-_U19-Pad3_ d_nor
+X3 Net-_U17-Pad1_ Net-_U13-Pad3_ Net-_U14-Pad3_ Net-_U10-Pad3_ Net-_U21-Pad1_ 4_OR
+X2 Net-_U12-Pad3_ Net-_U14-Pad3_ Net-_U17-Pad1_ Net-_U10-Pad3_ Net-_U24-Pad1_ 4_OR
+U24 Net-_U24-Pad1_ Net-_U16-Pad3_ Net-_U24-Pad3_ d_or
+U26 Net-_U24-Pad3_ Net-_U26-Pad2_ d_inverter
+X1 Net-_U17-Pad1_ Net-_U14-Pad3_ Net-_U10-Pad3_ Net-_U16-Pad3_ Net-_U22-Pad1_ 4_OR
+U22 Net-_U22-Pad1_ Net-_U11-Pad3_ Net-_U22-Pad3_ d_or
+U25 Net-_U22-Pad3_ Net-_U25-Pad2_ d_inverter
+U21 Net-_U21-Pad1_ Net-_U21-Pad2_ d_inverter
+U18 Net-_U18-Pad1_ Net-_U18-Pad2_ d_inverter
+U17 Net-_U17-Pad1_ Net-_U15-Pad3_ Net-_U17-Pad3_ d_or
+U20 Net-_U17-Pad3_ Net-_U14-Pad3_ Net-_U20-Pad3_ d_or
+U23 Net-_U20-Pad3_ Net-_U23-Pad2_ d_inverter
+X4 Net-_U18-Pad2_ Net-_U21-Pad2_ Net-_U19-Pad3_ Net-_U23-Pad2_ Net-_U27-Pad1_ 4_OR
+U27 Net-_U27-Pad1_ Net-_U25-Pad2_ Net-_U27-Pad3_ d_or
+U28 Net-_U26-Pad2_ Net-_U1-Pad15_ Net-_U28-Pad3_ d_or
+U31 Net-_U28-Pad3_ Net-_U27-Pad3_ Net-_U31-Pad3_ d_or
+U32 Net-_U31-Pad3_ Net-_U1-Pad2_ d_inverter
+U30 Net-_U27-Pad3_ Net-_U29-Pad2_ Net-_U1-Pad3_ d_and
+U29 Net-_U1-Pad15_ Net-_U29-Pad2_ d_inverter
+U14 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U14-Pad3_ d_xor
+U13 Net-_U1-Pad11_ Net-_U13-Pad2_ Net-_U13-Pad3_ d_or
+U5 Net-_U1-Pad12_ Net-_U13-Pad2_ d_inverter
+U12 Net-_U1-Pad5_ Net-_U1-Pad4_ Net-_U12-Pad3_ d_xor
+U11 Net-_U1-Pad4_ Net-_U11-Pad2_ Net-_U11-Pad3_ d_or
+U4 Net-_U1-Pad5_ Net-_U11-Pad2_ d_inverter
+U16 Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U16-Pad3_ d_xor
+U15 Net-_U1-Pad7_ Net-_U15-Pad2_ Net-_U15-Pad3_ d_or
+U6 Net-_U1-Pad6_ Net-_U15-Pad2_ d_inverter
+U8 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U17-Pad1_ d_xor
+U7 Net-_U1-Pad10_ Net-_U2-Pad2_ Net-_U18-Pad1_ d_or
+U2 Net-_U1-Pad9_ Net-_U2-Pad2_ d_inverter
+U1 ? Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.cir.out b/library/SubcircuitLibrary/MC10H166/MC10H166.cir.out new file mode 100644 index 00000000..c74a3149 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.cir.out @@ -0,0 +1,141 @@ +* c:\users\public\music\fossee\esim\library\subcircuitlibrary\mc10h166\mc10h166.cir
+
+.include 4_OR.sub
+* u10 net-_u1-pad13_ net-_u1-pad14_ net-_u10-pad3_ d_xor
+* u9 net-_u1-pad14_ net-_u3-pad2_ net-_u19-pad2_ d_or
+* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter
+* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_nor
+x3 net-_u17-pad1_ net-_u13-pad3_ net-_u14-pad3_ net-_u10-pad3_ net-_u21-pad1_ 4_OR
+x2 net-_u12-pad3_ net-_u14-pad3_ net-_u17-pad1_ net-_u10-pad3_ net-_u24-pad1_ 4_OR
+* u24 net-_u24-pad1_ net-_u16-pad3_ net-_u24-pad3_ d_or
+* u26 net-_u24-pad3_ net-_u26-pad2_ d_inverter
+x1 net-_u17-pad1_ net-_u14-pad3_ net-_u10-pad3_ net-_u16-pad3_ net-_u22-pad1_ 4_OR
+* u22 net-_u22-pad1_ net-_u11-pad3_ net-_u22-pad3_ d_or
+* u25 net-_u22-pad3_ net-_u25-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u15-pad3_ net-_u17-pad3_ d_or
+* u20 net-_u17-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u23 net-_u20-pad3_ net-_u23-pad2_ d_inverter
+x4 net-_u18-pad2_ net-_u21-pad2_ net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad1_ 4_OR
+* u27 net-_u27-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_or
+* u28 net-_u26-pad2_ net-_u1-pad15_ net-_u28-pad3_ d_or
+* u31 net-_u28-pad3_ net-_u27-pad3_ net-_u31-pad3_ d_or
+* u32 net-_u31-pad3_ net-_u1-pad2_ d_inverter
+* u30 net-_u27-pad3_ net-_u29-pad2_ net-_u1-pad3_ d_and
+* u29 net-_u1-pad15_ net-_u29-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u1-pad11_ net-_u14-pad3_ d_xor
+* u13 net-_u1-pad11_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u5 net-_u1-pad12_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad5_ net-_u1-pad4_ net-_u12-pad3_ d_xor
+* u11 net-_u1-pad4_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u4 net-_u1-pad5_ net-_u11-pad2_ d_inverter
+* u16 net-_u1-pad6_ net-_u1-pad7_ net-_u16-pad3_ d_xor
+* u15 net-_u1-pad7_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u6 net-_u1-pad6_ net-_u15-pad2_ d_inverter
+* u8 net-_u1-pad9_ net-_u1-pad10_ net-_u17-pad1_ d_xor
+* u7 net-_u1-pad10_ net-_u2-pad2_ net-_u18-pad1_ d_or
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+* u1 ? net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+a1 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u10-pad3_ u10
+a2 [net-_u1-pad14_ net-_u3-pad2_ ] net-_u19-pad2_ u9
+a3 net-_u1-pad13_ net-_u3-pad2_ u3
+a4 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a5 [net-_u24-pad1_ net-_u16-pad3_ ] net-_u24-pad3_ u24
+a6 net-_u24-pad3_ net-_u26-pad2_ u26
+a7 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u22-pad3_ u22
+a8 net-_u22-pad3_ net-_u25-pad2_ u25
+a9 net-_u21-pad1_ net-_u21-pad2_ u21
+a10 net-_u18-pad1_ net-_u18-pad2_ u18
+a11 [net-_u17-pad1_ net-_u15-pad3_ ] net-_u17-pad3_ u17
+a12 [net-_u17-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a13 net-_u20-pad3_ net-_u23-pad2_ u23
+a14 [net-_u27-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27
+a15 [net-_u26-pad2_ net-_u1-pad15_ ] net-_u28-pad3_ u28
+a16 [net-_u28-pad3_ net-_u27-pad3_ ] net-_u31-pad3_ u31
+a17 net-_u31-pad3_ net-_u1-pad2_ u32
+a18 [net-_u27-pad3_ net-_u29-pad2_ ] net-_u1-pad3_ u30
+a19 net-_u1-pad15_ net-_u29-pad2_ u29
+a20 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u14-pad3_ u14
+a21 [net-_u1-pad11_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a22 net-_u1-pad12_ net-_u13-pad2_ u5
+a23 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u12-pad3_ u12
+a24 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a25 net-_u1-pad5_ net-_u11-pad2_ u4
+a26 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u16-pad3_ u16
+a27 [net-_u1-pad7_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a28 net-_u1-pad6_ net-_u15-pad2_ u6
+a29 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u17-pad1_ u8
+a30 [net-_u1-pad10_ net-_u2-pad2_ ] net-_u18-pad1_ u7
+a31 net-_u1-pad9_ net-_u2-pad2_ u2
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u16 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.pro b/library/SubcircuitLibrary/MC10H166/MC10H166.pro new file mode 100644 index 00000000..85c572ea --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.pro @@ -0,0 +1,83 @@ +update=05/05/25 03:16:05
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
+[schematic_editor]
+version=1
+PageLayoutDescrFile=
+PlotDirectoryName=
+SubpartIdSeparator=0
+SubpartFirstId=65
+NetFmtName=
+SpiceForceRefPrefix=0
+SpiceUseNetNumbers=0
+LabSize=60
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.proj b/library/SubcircuitLibrary/MC10H166/MC10H166.proj new file mode 100644 index 00000000..2674fad6 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.proj @@ -0,0 +1 @@ +schematicFile MC10H166.sch diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.sch b/library/SubcircuitLibrary/MC10H166/MC10H166.sch new file mode 100644 index 00000000..bf649638 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.sch @@ -0,0 +1,878 @@ +EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:MC10H166-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U10
+U 1 1 681518A6
+P 2650 4450
+F 0 "U10" H 2650 4450 60 0000 C CNN
+F 1 "d_xor" H 2700 4550 47 0000 C CNN
+F 2 "" H 2650 4450 60 0000 C CNN
+F 3 "" H 2650 4450 60 0000 C CNN
+ 1 2650 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U9
+U 1 1 681518AC
+P 2650 4000
+F 0 "U9" H 2650 4000 60 0000 C CNN
+F 1 "d_or" H 2650 4100 60 0000 C CNN
+F 2 "" H 2650 4000 60 0000 C CNN
+F 3 "" H 2650 4000 60 0000 C CNN
+ 1 2650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 681518B2
+P 1900 4200
+F 0 "U3" H 1900 4100 60 0000 C CNN
+F 1 "d_inverter" H 1900 4350 60 0000 C CNN
+F 2 "" H 1950 4150 60 0000 C CNN
+F 3 "" H 1950 4150 60 0000 C CNN
+ 1 1900 4200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U19
+U 1 1 68151AAF
+P 5600 3800
+F 0 "U19" H 5600 3800 60 0000 C CNN
+F 1 "d_nor" H 5650 3900 60 0000 C CNN
+F 2 "" H 5600 3800 60 0000 C CNN
+F 3 "" H 5600 3800 60 0000 C CNN
+ 1 5600 3800
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X3
+U 1 1 68151B0E
+P 5500 3050
+F 0 "X3" H 5650 2950 60 0000 C CNN
+F 1 "4_OR" H 5650 3150 60 0000 C CNN
+F 2 "" H 5500 3050 60 0000 C CNN
+F 3 "" H 5500 3050 60 0000 C CNN
+ 1 5500 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X2
+U 1 1 68151BD0
+P 5400 1750
+F 0 "X2" H 5550 1650 60 0000 C CNN
+F 1 "4_OR" H 5550 1850 60 0000 C CNN
+F 2 "" H 5400 1750 60 0000 C CNN
+F 3 "" H 5400 1750 60 0000 C CNN
+ 1 5400 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U24
+U 1 1 68151C14
+P 6500 2200
+F 0 "U24" H 6500 2200 60 0000 C CNN
+F 1 "d_or" H 6500 2300 60 0000 C CNN
+F 2 "" H 6500 2200 60 0000 C CNN
+F 3 "" H 6500 2200 60 0000 C CNN
+ 1 6500 2200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5950 1750 6050 1750
+Wire Wire Line
+ 6050 1750 6050 2100
+$Comp
+L d_inverter U26
+U 1 1 68151DBD
+P 7250 2150
+F 0 "U26" H 7250 2050 60 0000 C CNN
+F 1 "d_inverter" H 7250 2300 60 0000 C CNN
+F 2 "" H 7300 2100 60 0000 C CNN
+F 3 "" H 7300 2100 60 0000 C CNN
+ 1 7250 2150
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X1
+U 1 1 681521BE
+P 5250 4950
+F 0 "X1" H 5400 4850 60 0000 C CNN
+F 1 "4_OR" H 5400 5050 60 0000 C CNN
+F 2 "" H 5250 4950 60 0000 C CNN
+F 3 "" H 5250 4950 60 0000 C CNN
+ 1 5250 4950
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U22
+U 1 1 681521C4
+P 6350 5400
+F 0 "U22" H 6350 5400 60 0000 C CNN
+F 1 "d_or" H 6350 5500 60 0000 C CNN
+F 2 "" H 6350 5400 60 0000 C CNN
+F 3 "" H 6350 5400 60 0000 C CNN
+ 1 6350 5400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5800 4950 5900 4950
+Wire Wire Line
+ 5900 4950 5900 5300
+$Comp
+L d_inverter U25
+U 1 1 681521CC
+P 7100 5350
+F 0 "U25" H 7100 5250 60 0000 C CNN
+F 1 "d_inverter" H 7100 5500 60 0000 C CNN
+F 2 "" H 7150 5300 60 0000 C CNN
+F 3 "" H 7150 5300 60 0000 C CNN
+ 1 7100 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U21
+U 1 1 681522D1
+P 6350 3050
+F 0 "U21" H 6350 2950 60 0000 C CNN
+F 1 "d_inverter" H 6350 3200 60 0000 C CNN
+F 2 "" H 6400 3000 60 0000 C CNN
+F 3 "" H 6400 3000 60 0000 C CNN
+ 1 6350 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U18
+U 1 1 68152332
+P 5500 2500
+F 0 "U18" H 5500 2400 60 0000 C CNN
+F 1 "d_inverter" H 5500 2650 60 0000 C CNN
+F 2 "" H 5550 2450 60 0000 C CNN
+F 3 "" H 5550 2450 60 0000 C CNN
+ 1 5500 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U17
+U 1 1 681523E1
+P 4700 4350
+F 0 "U17" H 4700 4350 60 0000 C CNN
+F 1 "d_or" H 4700 4450 60 0000 C CNN
+F 2 "" H 4700 4350 60 0000 C CNN
+F 3 "" H 4700 4350 60 0000 C CNN
+ 1 4700 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U20
+U 1 1 68152548
+P 5700 4400
+F 0 "U20" H 5700 4400 60 0000 C CNN
+F 1 "d_or" H 5700 4500 60 0000 C CNN
+F 2 "" H 5700 4400 60 0000 C CNN
+F 3 "" H 5700 4400 60 0000 C CNN
+ 1 5700 4400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5250 4300 5150 4300
+$Comp
+L d_inverter U23
+U 1 1 681528D0
+P 6450 4350
+F 0 "U23" H 6450 4250 60 0000 C CNN
+F 1 "d_inverter" H 6450 4500 60 0000 C CNN
+F 2 "" H 6500 4300 60 0000 C CNN
+F 3 "" H 6500 4300 60 0000 C CNN
+ 1 6450 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_OR X4
+U 1 1 681535BF
+P 7600 3450
+F 0 "X4" H 7750 3350 60 0000 C CNN
+F 1 "4_OR" H 7750 3550 60 0000 C CNN
+F 2 "" H 7600 3450 60 0000 C CNN
+F 3 "" H 7600 3450 60 0000 C CNN
+ 1 7600 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U27
+U 1 1 681535C5
+P 8700 3900
+F 0 "U27" H 8700 3900 60 0000 C CNN
+F 1 "d_or" H 8700 4000 60 0000 C CNN
+F 2 "" H 8700 3900 60 0000 C CNN
+F 3 "" H 8700 3900 60 0000 C CNN
+ 1 8700 3900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8150 3450 8250 3450
+Wire Wire Line
+ 8250 3450 8250 3800
+$Comp
+L d_or U28
+U 1 1 68154B3E
+P 9250 3050
+F 0 "U28" H 9250 3050 60 0000 C CNN
+F 1 "d_or" H 9250 3150 60 0000 C CNN
+F 2 "" H 9250 3050 60 0000 C CNN
+F 3 "" H 9250 3050 60 0000 C CNN
+ 1 9250 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U31
+U 1 1 68154B44
+P 10250 3100
+F 0 "U31" H 10250 3100 60 0000 C CNN
+F 1 "d_or" H 10250 3200 60 0000 C CNN
+F 2 "" H 10250 3100 60 0000 C CNN
+F 3 "" H 10250 3100 60 0000 C CNN
+ 1 10250 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9800 3000 9700 3000
+$Comp
+L d_inverter U32
+U 1 1 68154B4B
+P 11000 3050
+F 0 "U32" H 11000 2950 60 0000 C CNN
+F 1 "d_inverter" H 11000 3200 60 0000 C CNN
+F 2 "" H 11050 3000 60 0000 C CNN
+F 3 "" H 11050 3000 60 0000 C CNN
+ 1 11000 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U30
+U 1 1 68154B74
+P 10200 4350
+F 0 "U30" H 10200 4350 60 0000 C CNN
+F 1 "d_and" H 10250 4450 60 0000 C CNN
+F 2 "" H 10200 4350 60 0000 C CNN
+F 3 "" H 10200 4350 60 0000 C CNN
+ 1 10200 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U29
+U 1 1 68154C6B
+P 9450 4350
+F 0 "U29" H 9450 4250 60 0000 C CNN
+F 1 "d_inverter" H 9450 4500 60 0000 C CNN
+F 2 "" H 9500 4300 60 0000 C CNN
+F 3 "" H 9500 4300 60 0000 C CNN
+ 1 9450 4350
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1200 4350 2200 4350
+Wire Wire Line
+ 1600 4350 1600 4200
+Wire Wire Line
+ 2200 4000 2200 4200
+Wire Wire Line
+ 2200 3900 1550 3900
+Wire Wire Line
+ 1550 3900 1550 4450
+Wire Wire Line
+ 1200 4450 2200 4450
+Connection ~ 1550 4450
+Connection ~ 1600 4350
+$Comp
+L d_xor U14
+U 1 1 681554DE
+P 2700 3200
+F 0 "U14" H 2700 3200 60 0000 C CNN
+F 1 "d_xor" H 2750 3300 47 0000 C CNN
+F 2 "" H 2700 3200 60 0000 C CNN
+F 3 "" H 2700 3200 60 0000 C CNN
+ 1 2700 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U13
+U 1 1 681554E4
+P 2700 2750
+F 0 "U13" H 2700 2750 60 0000 C CNN
+F 1 "d_or" H 2700 2850 60 0000 C CNN
+F 2 "" H 2700 2750 60 0000 C CNN
+F 3 "" H 2700 2750 60 0000 C CNN
+ 1 2700 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 681554EA
+P 1950 2950
+F 0 "U5" H 1950 2850 60 0000 C CNN
+F 1 "d_inverter" H 1950 3100 60 0000 C CNN
+F 2 "" H 2000 2900 60 0000 C CNN
+F 3 "" H 2000 2900 60 0000 C CNN
+ 1 1950 2950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1250 3100 2250 3100
+Wire Wire Line
+ 1650 3100 1650 2950
+Wire Wire Line
+ 2250 2750 2250 2950
+Wire Wire Line
+ 2250 2650 1600 2650
+Wire Wire Line
+ 1600 2650 1600 3200
+Wire Wire Line
+ 1150 3200 2250 3200
+Connection ~ 1600 3200
+Connection ~ 1650 3100
+$Comp
+L d_xor U12
+U 1 1 68155848
+P 2650 7050
+F 0 "U12" H 2650 7050 60 0000 C CNN
+F 1 "d_xor" H 2700 7150 47 0000 C CNN
+F 2 "" H 2650 7050 60 0000 C CNN
+F 3 "" H 2650 7050 60 0000 C CNN
+ 1 2650 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U11
+U 1 1 6815584E
+P 2650 6600
+F 0 "U11" H 2650 6600 60 0000 C CNN
+F 1 "d_or" H 2650 6700 60 0000 C CNN
+F 2 "" H 2650 6600 60 0000 C CNN
+F 3 "" H 2650 6600 60 0000 C CNN
+ 1 2650 6600
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 68155854
+P 1900 6800
+F 0 "U4" H 1900 6700 60 0000 C CNN
+F 1 "d_inverter" H 1900 6950 60 0000 C CNN
+F 2 "" H 1950 6750 60 0000 C CNN
+F 3 "" H 1950 6750 60 0000 C CNN
+ 1 1900 6800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1200 6950 2200 6950
+Wire Wire Line
+ 1600 6950 1600 6800
+Wire Wire Line
+ 2200 6600 2200 6800
+Wire Wire Line
+ 2200 6500 1550 6500
+Wire Wire Line
+ 1550 6500 1550 7050
+Wire Wire Line
+ 1200 7050 2200 7050
+Connection ~ 1550 7050
+Connection ~ 1600 6950
+$Comp
+L d_xor U16
+U 1 1 68155862
+P 2700 5800
+F 0 "U16" H 2700 5800 60 0000 C CNN
+F 1 "d_xor" H 2750 5900 47 0000 C CNN
+F 2 "" H 2700 5800 60 0000 C CNN
+F 3 "" H 2700 5800 60 0000 C CNN
+ 1 2700 5800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U15
+U 1 1 68155868
+P 2700 5350
+F 0 "U15" H 2700 5350 60 0000 C CNN
+F 1 "d_or" H 2700 5450 60 0000 C CNN
+F 2 "" H 2700 5350 60 0000 C CNN
+F 3 "" H 2700 5350 60 0000 C CNN
+ 1 2700 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U6
+U 1 1 6815586E
+P 1950 5550
+F 0 "U6" H 1950 5450 60 0000 C CNN
+F 1 "d_inverter" H 1950 5700 60 0000 C CNN
+F 2 "" H 2000 5500 60 0000 C CNN
+F 3 "" H 2000 5500 60 0000 C CNN
+ 1 1950 5550
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1250 5700 2250 5700
+Wire Wire Line
+ 1650 5700 1650 5550
+Wire Wire Line
+ 2250 5350 2250 5550
+Wire Wire Line
+ 2250 5250 1600 5250
+Wire Wire Line
+ 1600 5250 1600 5800
+Wire Wire Line
+ 1200 5800 2250 5800
+Connection ~ 1600 5800
+Connection ~ 1650 5700
+$Comp
+L d_xor U8
+U 1 1 681559C2
+P 2600 1850
+F 0 "U8" H 2600 1850 60 0000 C CNN
+F 1 "d_xor" H 2650 1950 47 0000 C CNN
+F 2 "" H 2600 1850 60 0000 C CNN
+F 3 "" H 2600 1850 60 0000 C CNN
+ 1 2600 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_or U7
+U 1 1 681559C8
+P 2600 1400
+F 0 "U7" H 2600 1400 60 0000 C CNN
+F 1 "d_or" H 2600 1500 60 0000 C CNN
+F 2 "" H 2600 1400 60 0000 C CNN
+F 3 "" H 2600 1400 60 0000 C CNN
+ 1 2600 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 681559CE
+P 1850 1600
+F 0 "U2" H 1850 1500 60 0000 C CNN
+F 1 "d_inverter" H 1850 1750 60 0000 C CNN
+F 2 "" H 1900 1550 60 0000 C CNN
+F 3 "" H 1900 1550 60 0000 C CNN
+ 1 1850 1600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1150 1750 2150 1750
+Wire Wire Line
+ 1550 1750 1550 1600
+Wire Wire Line
+ 2150 1400 2150 1600
+Wire Wire Line
+ 2150 1300 1500 1300
+Wire Wire Line
+ 1500 1300 1500 1850
+Wire Wire Line
+ 1050 1850 2150 1850
+Connection ~ 1500 1850
+Connection ~ 1550 1750
+Wire Wire Line
+ 3050 1350 4900 1350
+Wire Wire Line
+ 4900 1350 4900 2500
+Wire Wire Line
+ 4900 2500 5200 2500
+Wire Wire Line
+ 3050 1800 5050 1800
+Wire Wire Line
+ 4750 1800 4750 3700
+Wire Wire Line
+ 4750 2900 5150 2900
+Connection ~ 4750 1800
+Wire Wire Line
+ 4250 3700 5150 3700
+Connection ~ 4750 2900
+Wire Wire Line
+ 4250 3700 4250 4250
+Connection ~ 4750 3700
+Wire Wire Line
+ 4250 4250 4000 4250
+Wire Wire Line
+ 4000 4250 4000 4800
+Wire Wire Line
+ 4000 4800 4900 4800
+Wire Wire Line
+ 4600 3800 5150 3800
+Wire Wire Line
+ 4600 3950 4600 3800
+Wire Wire Line
+ 3150 2700 4300 2700
+Wire Wire Line
+ 4300 2700 4300 3000
+Wire Wire Line
+ 4300 3000 5150 3000
+Wire Wire Line
+ 3150 5300 3750 5300
+Wire Wire Line
+ 3750 5300 3750 4350
+Wire Wire Line
+ 3750 4350 4250 4350
+Wire Wire Line
+ 3100 6550 5900 6550
+Wire Wire Line
+ 5900 6550 5900 5400
+Wire Wire Line
+ 5050 1700 3550 1700
+Wire Wire Line
+ 3550 1700 3550 4900
+Wire Wire Line
+ 3550 3150 3150 3150
+Wire Wire Line
+ 5150 3100 3550 3100
+Connection ~ 3550 3100
+Wire Wire Line
+ 5250 4600 5250 4400
+Wire Wire Line
+ 3550 4600 5250 4600
+Connection ~ 3550 3150
+Wire Wire Line
+ 3100 3950 4600 3950
+Wire Wire Line
+ 3550 4900 4900 4900
+Connection ~ 3550 4600
+Wire Wire Line
+ 3100 4400 3900 4400
+Wire Wire Line
+ 3900 1900 3900 5000
+Wire Wire Line
+ 3900 1900 5050 1900
+Wire Wire Line
+ 5150 3200 3900 3200
+Connection ~ 3900 3200
+Wire Wire Line
+ 3900 5000 4900 5000
+Connection ~ 3900 4400
+Wire Wire Line
+ 6050 2200 4150 2200
+Wire Wire Line
+ 4150 2200 4150 5750
+Wire Wire Line
+ 4150 5750 3150 5750
+Wire Wire Line
+ 4900 5100 4150 5100
+Connection ~ 4150 5100
+Wire Wire Line
+ 5050 1600 3350 1600
+Wire Wire Line
+ 3350 1600 3350 7000
+Wire Wire Line
+ 3350 7000 3100 7000
+Wire Wire Line
+ 5800 2500 7250 2500
+Wire Wire Line
+ 7250 2500 7250 3300
+Wire Wire Line
+ 6650 3050 7100 3050
+Wire Wire Line
+ 7100 3050 7100 3400
+Wire Wire Line
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+Wire Wire Line
+ 7400 5350 7400 3900
+Wire Wire Line
+ 7400 3900 8250 3900
+Wire Wire Line
+ 6050 3750 6050 3500
+Wire Wire Line
+ 6050 3500 7250 3500
+Wire Wire Line
+ 6750 4350 7250 4350
+Wire Wire Line
+ 7250 4350 7250 3600
+Wire Wire Line
+ 9750 4250 9750 3100
+Wire Wire Line
+ 9750 3100 9800 3100
+Wire Wire Line
+ 9150 3850 9750 3850
+Connection ~ 9750 3850
+Wire Wire Line
+ 7550 2150 8800 2150
+Wire Wire Line
+ 8800 2150 8800 2950
+Wire Wire Line
+ 8800 3050 8800 3500
+Wire Wire Line
+ 8800 3500 9200 3500
+Wire Wire Line
+ 9150 3600 9150 5950
+Wire Wire Line
+ 9150 3600 9200 3600
+Wire Wire Line
+ 9200 3600 9200 3500
+Wire Wire Line
+ 9150 5950 7300 5950
+Connection ~ 9150 4350
+$Comp
+L PORT U1
+U 1 1 68169E45
+P 1500 850
+F 0 "U1" H 1550 950 30 0000 C CNN
+F 1 "PORT" H 1500 850 30 0000 C CNN
+F 2 "" H 1500 850 60 0000 C CNN
+F 3 "" H 1500 850 60 0000 C CNN
+ 1 1500 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 68169EEE
+P 11300 3550
+F 0 "U1" H 11350 3650 30 0000 C CNN
+F 1 "PORT" H 11300 3550 30 0000 C CNN
+F 2 "" H 11300 3550 60 0000 C CNN
+F 3 "" H 11300 3550 60 0000 C CNN
+ 2 11300 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 68169F71
+P 950 7050
+F 0 "U1" H 1000 7150 30 0000 C CNN
+F 1 "PORT" H 950 7050 30 0000 C CNN
+F 2 "" H 950 7050 60 0000 C CNN
+F 3 "" H 950 7050 60 0000 C CNN
+ 4 950 7050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 68169FDC
+P 10750 4500
+F 0 "U1" H 10800 4600 30 0000 C CNN
+F 1 "PORT" H 10750 4500 30 0000 C CNN
+F 2 "" H 10750 4500 60 0000 C CNN
+F 3 "" H 10750 4500 60 0000 C CNN
+ 3 10750 4500
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6816A05B
+P 900 6800
+F 0 "U1" H 950 6900 30 0000 C CNN
+F 1 "PORT" H 900 6800 30 0000 C CNN
+F 2 "" H 900 6800 60 0000 C CNN
+F 3 "" H 900 6800 60 0000 C CNN
+ 5 900 6800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6816A0CA
+P 1000 5700
+F 0 "U1" H 1050 5800 30 0000 C CNN
+F 1 "PORT" H 1000 5700 30 0000 C CNN
+F 2 "" H 1000 5700 60 0000 C CNN
+F 3 "" H 1000 5700 60 0000 C CNN
+ 6 1000 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6816A151
+P 950 5950
+F 0 "U1" H 1000 6050 30 0000 C CNN
+F 1 "PORT" H 950 5950 30 0000 C CNN
+F 2 "" H 950 5950 60 0000 C CNN
+F 3 "" H 950 5950 60 0000 C CNN
+ 7 950 5950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6816A1CE
+P 3950 1150
+F 0 "U1" H 4000 1250 30 0000 C CNN
+F 1 "PORT" H 3950 1150 30 0000 C CNN
+F 2 "" H 3950 1150 60 0000 C CNN
+F 3 "" H 3950 1150 60 0000 C CNN
+ 8 3950 1150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 6816A24F
+P 900 1750
+F 0 "U1" H 950 1850 30 0000 C CNN
+F 1 "PORT" H 900 1750 30 0000 C CNN
+F 2 "" H 900 1750 60 0000 C CNN
+F 3 "" H 900 1750 60 0000 C CNN
+ 9 900 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 6816A615
+P 800 2050
+F 0 "U1" H 850 2150 30 0000 C CNN
+F 1 "PORT" H 800 2050 30 0000 C CNN
+F 2 "" H 800 2050 60 0000 C CNN
+F 3 "" H 800 2050 60 0000 C CNN
+ 10 800 2050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 6816A798
+P 900 3450
+F 0 "U1" H 950 3550 30 0000 C CNN
+F 1 "PORT" H 900 3450 30 0000 C CNN
+F 2 "" H 900 3450 60 0000 C CNN
+F 3 "" H 900 3450 60 0000 C CNN
+ 11 900 3450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 6816A829
+P 1000 3100
+F 0 "U1" H 1050 3200 30 0000 C CNN
+F 1 "PORT" H 1000 3100 30 0000 C CNN
+F 2 "" H 1000 3100 60 0000 C CNN
+F 3 "" H 1000 3100 60 0000 C CNN
+ 12 1000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 6816A8AE
+P 900 4700
+F 0 "U1" H 950 4800 30 0000 C CNN
+F 1 "PORT" H 900 4700 30 0000 C CNN
+F 2 "" H 900 4700 60 0000 C CNN
+F 3 "" H 900 4700 60 0000 C CNN
+ 14 900 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 6816A927
+P 950 4350
+F 0 "U1" H 1000 4450 30 0000 C CNN
+F 1 "PORT" H 950 4350 30 0000 C CNN
+F 2 "" H 950 4350 60 0000 C CNN
+F 3 "" H 950 4350 60 0000 C CNN
+ 13 950 4350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 6816A9A0
+P 6150 850
+F 0 "U1" H 6200 950 30 0000 C CNN
+F 1 "PORT" H 6150 850 30 0000 C CNN
+F 2 "" H 6150 850 60 0000 C CNN
+F 3 "" H 6150 850 60 0000 C CNN
+ 16 6150 850
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 6816AA21
+P 7050 5950
+F 0 "U1" H 7100 6050 30 0000 C CNN
+F 1 "PORT" H 7050 5950 30 0000 C CNN
+F 2 "" H 7050 5950 60 0000 C CNN
+F 3 "" H 7050 5950 60 0000 C CNN
+ 15 7050 5950
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1050 2050 1050 1850
+Wire Wire Line
+ 1150 3450 1150 3200
+Wire Wire Line
+ 1200 4450 1200 4700
+Wire Wire Line
+ 1200 4700 1150 4700
+Wire Wire Line
+ 1200 5950 1200 5800
+Wire Wire Line
+ 1150 6800 1200 6800
+Wire Wire Line
+ 1200 6800 1200 6950
+Wire Wire Line
+ 11400 3350 11400 3050
+Wire Wire Line
+ 11400 3050 11300 3050
+Wire Wire Line
+ 10650 4300 11000 4300
+Wire Wire Line
+ 11000 4300 11000 4500
+NoConn ~ 2050 900
+NoConn ~ 4600 1150
+NoConn ~ 6650 850
+Wire Wire Line
+ 1750 850 2050 850
+Wire Wire Line
+ 2050 850 2050 900
+Wire Wire Line
+ 4200 1150 4600 1150
+Wire Wire Line
+ 6400 850 6650 850
+Wire Wire Line
+ 11400 3350 11550 3350
+Wire Wire Line
+ 11550 3350 11550 3550
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166.sub b/library/SubcircuitLibrary/MC10H166/MC10H166.sub new file mode 100644 index 00000000..b7459092 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166.sub @@ -0,0 +1,135 @@ +* Subcircuit MC10H166
+.subckt MC10H166 ? net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\users\public\music\fossee\esim\library\subcircuitlibrary\mc10h166\mc10h166.cir
+.include 4_OR.sub
+* u10 net-_u1-pad13_ net-_u1-pad14_ net-_u10-pad3_ d_xor
+* u9 net-_u1-pad14_ net-_u3-pad2_ net-_u19-pad2_ d_or
+* u3 net-_u1-pad13_ net-_u3-pad2_ d_inverter
+* u19 net-_u17-pad1_ net-_u19-pad2_ net-_u19-pad3_ d_nor
+x3 net-_u17-pad1_ net-_u13-pad3_ net-_u14-pad3_ net-_u10-pad3_ net-_u21-pad1_ 4_OR
+x2 net-_u12-pad3_ net-_u14-pad3_ net-_u17-pad1_ net-_u10-pad3_ net-_u24-pad1_ 4_OR
+* u24 net-_u24-pad1_ net-_u16-pad3_ net-_u24-pad3_ d_or
+* u26 net-_u24-pad3_ net-_u26-pad2_ d_inverter
+x1 net-_u17-pad1_ net-_u14-pad3_ net-_u10-pad3_ net-_u16-pad3_ net-_u22-pad1_ 4_OR
+* u22 net-_u22-pad1_ net-_u11-pad3_ net-_u22-pad3_ d_or
+* u25 net-_u22-pad3_ net-_u25-pad2_ d_inverter
+* u21 net-_u21-pad1_ net-_u21-pad2_ d_inverter
+* u18 net-_u18-pad1_ net-_u18-pad2_ d_inverter
+* u17 net-_u17-pad1_ net-_u15-pad3_ net-_u17-pad3_ d_or
+* u20 net-_u17-pad3_ net-_u14-pad3_ net-_u20-pad3_ d_or
+* u23 net-_u20-pad3_ net-_u23-pad2_ d_inverter
+x4 net-_u18-pad2_ net-_u21-pad2_ net-_u19-pad3_ net-_u23-pad2_ net-_u27-pad1_ 4_OR
+* u27 net-_u27-pad1_ net-_u25-pad2_ net-_u27-pad3_ d_or
+* u28 net-_u26-pad2_ net-_u1-pad15_ net-_u28-pad3_ d_or
+* u31 net-_u28-pad3_ net-_u27-pad3_ net-_u31-pad3_ d_or
+* u32 net-_u31-pad3_ net-_u1-pad2_ d_inverter
+* u30 net-_u27-pad3_ net-_u29-pad2_ net-_u1-pad3_ d_and
+* u29 net-_u1-pad15_ net-_u29-pad2_ d_inverter
+* u14 net-_u1-pad12_ net-_u1-pad11_ net-_u14-pad3_ d_xor
+* u13 net-_u1-pad11_ net-_u13-pad2_ net-_u13-pad3_ d_or
+* u5 net-_u1-pad12_ net-_u13-pad2_ d_inverter
+* u12 net-_u1-pad5_ net-_u1-pad4_ net-_u12-pad3_ d_xor
+* u11 net-_u1-pad4_ net-_u11-pad2_ net-_u11-pad3_ d_or
+* u4 net-_u1-pad5_ net-_u11-pad2_ d_inverter
+* u16 net-_u1-pad6_ net-_u1-pad7_ net-_u16-pad3_ d_xor
+* u15 net-_u1-pad7_ net-_u15-pad2_ net-_u15-pad3_ d_or
+* u6 net-_u1-pad6_ net-_u15-pad2_ d_inverter
+* u8 net-_u1-pad9_ net-_u1-pad10_ net-_u17-pad1_ d_xor
+* u7 net-_u1-pad10_ net-_u2-pad2_ net-_u18-pad1_ d_or
+* u2 net-_u1-pad9_ net-_u2-pad2_ d_inverter
+a1 [net-_u1-pad13_ net-_u1-pad14_ ] net-_u10-pad3_ u10
+a2 [net-_u1-pad14_ net-_u3-pad2_ ] net-_u19-pad2_ u9
+a3 net-_u1-pad13_ net-_u3-pad2_ u3
+a4 [net-_u17-pad1_ net-_u19-pad2_ ] net-_u19-pad3_ u19
+a5 [net-_u24-pad1_ net-_u16-pad3_ ] net-_u24-pad3_ u24
+a6 net-_u24-pad3_ net-_u26-pad2_ u26
+a7 [net-_u22-pad1_ net-_u11-pad3_ ] net-_u22-pad3_ u22
+a8 net-_u22-pad3_ net-_u25-pad2_ u25
+a9 net-_u21-pad1_ net-_u21-pad2_ u21
+a10 net-_u18-pad1_ net-_u18-pad2_ u18
+a11 [net-_u17-pad1_ net-_u15-pad3_ ] net-_u17-pad3_ u17
+a12 [net-_u17-pad3_ net-_u14-pad3_ ] net-_u20-pad3_ u20
+a13 net-_u20-pad3_ net-_u23-pad2_ u23
+a14 [net-_u27-pad1_ net-_u25-pad2_ ] net-_u27-pad3_ u27
+a15 [net-_u26-pad2_ net-_u1-pad15_ ] net-_u28-pad3_ u28
+a16 [net-_u28-pad3_ net-_u27-pad3_ ] net-_u31-pad3_ u31
+a17 net-_u31-pad3_ net-_u1-pad2_ u32
+a18 [net-_u27-pad3_ net-_u29-pad2_ ] net-_u1-pad3_ u30
+a19 net-_u1-pad15_ net-_u29-pad2_ u29
+a20 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u14-pad3_ u14
+a21 [net-_u1-pad11_ net-_u13-pad2_ ] net-_u13-pad3_ u13
+a22 net-_u1-pad12_ net-_u13-pad2_ u5
+a23 [net-_u1-pad5_ net-_u1-pad4_ ] net-_u12-pad3_ u12
+a24 [net-_u1-pad4_ net-_u11-pad2_ ] net-_u11-pad3_ u11
+a25 net-_u1-pad5_ net-_u11-pad2_ u4
+a26 [net-_u1-pad6_ net-_u1-pad7_ ] net-_u16-pad3_ u16
+a27 [net-_u1-pad7_ net-_u15-pad2_ ] net-_u15-pad3_ u15
+a28 net-_u1-pad6_ net-_u15-pad2_ u6
+a29 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u17-pad1_ u8
+a30 [net-_u1-pad10_ net-_u2-pad2_ ] net-_u18-pad1_ u7
+a31 net-_u1-pad9_ net-_u2-pad2_ u2
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u10 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u19 d_nor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u24 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u26 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u22 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u25 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u21 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u18 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u20 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u23 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u27 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u28 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u31 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u32 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u30 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u29 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u13 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u12 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u16 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u15 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u7 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends MC10H166
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H166/MC10H166_Previous_Values.xml b/library/SubcircuitLibrary/MC10H166/MC10H166_Previous_Values.xml new file mode 100644 index 00000000..bfb45706 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/MC10H166_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model><u10 name="type">d_xor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u10><u9 name="type">d_or<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u9><u3 name="type">d_inverter<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u3><u19 name="type">d_nor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u19><u24 name="type">d_or<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u24><u26 name="type">d_inverter<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u26><u22 name="type">d_or<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u22><u25 name="type">d_inverter<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u25><u21 name="type">d_inverter<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u21><u18 name="type">d_inverter<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u18><u17 name="type">d_or<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u17><u20 name="type">d_or<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u20><u23 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u23><u27 name="type">d_or<field40 name="Enter Rise Delay (default=1.0e-9)" /><field41 name="Enter Fall Delay (default=1.0e-9)" /><field42 name="Enter Input Load (default=1.0e-12)" /></u27><u28 name="type">d_or<field43 name="Enter Rise Delay (default=1.0e-9)" /><field44 name="Enter Fall Delay (default=1.0e-9)" /><field45 name="Enter Input Load (default=1.0e-12)" /></u28><u31 name="type">d_or<field46 name="Enter Rise Delay (default=1.0e-9)" /><field47 name="Enter Fall Delay (default=1.0e-9)" /><field48 name="Enter Input Load (default=1.0e-12)" /></u31><u32 name="type">d_inverter<field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /><field51 name="Enter Input Load (default=1.0e-12)" /></u32><u30 name="type">d_and<field52 name="Enter Rise Delay (default=1.0e-9)" /><field53 name="Enter Fall Delay (default=1.0e-9)" /><field54 name="Enter Input Load (default=1.0e-12)" /></u30><u29 name="type">d_inverter<field55 name="Enter Rise Delay (default=1.0e-9)" /><field56 name="Enter Fall Delay (default=1.0e-9)" /><field57 name="Enter Input Load (default=1.0e-12)" /></u29><u14 name="type">d_xor<field58 name="Enter Rise Delay (default=1.0e-9)" /><field59 name="Enter Fall Delay (default=1.0e-9)" /><field60 name="Enter Input Load (default=1.0e-12)" /></u14><u13 name="type">d_or<field61 name="Enter Rise Delay (default=1.0e-9)" /><field62 name="Enter Fall Delay (default=1.0e-9)" /><field63 name="Enter Input Load (default=1.0e-12)" /></u13><u5 name="type">d_inverter<field64 name="Enter Rise Delay (default=1.0e-9)" /><field65 name="Enter Fall Delay (default=1.0e-9)" /><field66 name="Enter Input Load (default=1.0e-12)" /></u5><u12 name="type">d_xor<field67 name="Enter Rise Delay (default=1.0e-9)" /><field68 name="Enter Fall Delay (default=1.0e-9)" /><field69 name="Enter Input Load (default=1.0e-12)" /></u12><u11 name="type">d_or<field70 name="Enter Rise Delay (default=1.0e-9)" /><field71 name="Enter Fall Delay (default=1.0e-9)" /><field72 name="Enter Input Load (default=1.0e-12)" /></u11><u4 name="type">d_inverter<field73 name="Enter Rise Delay (default=1.0e-9)" /><field74 name="Enter Fall Delay (default=1.0e-9)" /><field75 name="Enter Input Load (default=1.0e-12)" /></u4><u16 name="type">d_xor<field76 name="Enter Rise Delay (default=1.0e-9)" /><field77 name="Enter Fall Delay (default=1.0e-9)" /><field78 name="Enter Input Load (default=1.0e-12)" /></u16><u15 name="type">d_or<field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /><field81 name="Enter Input Load (default=1.0e-12)" /></u15><u6 name="type">d_inverter<field82 name="Enter Rise Delay (default=1.0e-9)" /><field83 name="Enter Fall Delay (default=1.0e-9)" /><field84 name="Enter Input Load (default=1.0e-12)" /></u6><u8 name="type">d_xor<field85 name="Enter Rise Delay (default=1.0e-9)" /><field86 name="Enter Fall Delay (default=1.0e-9)" /><field87 name="Enter Input Load (default=1.0e-12)" /></u8><u7 name="type">d_or<field88 name="Enter Rise Delay (default=1.0e-9)" /><field89 name="Enter Fall Delay (default=1.0e-9)" /><field90 name="Enter Input Load (default=1.0e-12)" /></u7><u2 name="type">d_inverter<field91 name="Enter Rise Delay (default=1.0e-9)" /><field92 name="Enter Fall Delay (default=1.0e-9)" /><field93 name="Enter Input Load (default=1.0e-12)" /></u2></model><devicemodel /><subcircuit><x3><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x3><x2><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x2><x1><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x1><x4><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_OR</field></x4></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/MC10H166/SUB file b/library/SubcircuitLibrary/MC10H166/SUB file new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/SUB file @@ -0,0 +1 @@ + diff --git a/library/SubcircuitLibrary/MC10H166/analysis b/library/SubcircuitLibrary/MC10H166/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/MC10H166/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |