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-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413-cache.lib143
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413.cir44
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413.cir.out47
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413.pro71
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413.sch1012
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413.sub41
-rw-r--r--library/SubcircuitLibrary/MAX7413/MAX7413_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/MAX7413/NMOS-180nm.lib13
-rw-r--r--library/SubcircuitLibrary/MAX7413/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/MAX7413/PNP.lib4
-rw-r--r--library/SubcircuitLibrary/MAX7413/analysis1
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741-cache.lib119
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741.cir43
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741.cir.out46
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741.pro44
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741.sch697
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741.sub40
-rw-r--r--library/SubcircuitLibrary/MAX7413/lm_741_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/MAX7413/npn_1.lib29
-rw-r--r--library/SubcircuitLibrary/MAX7413/pnp_1.lib29
20 files changed, 2429 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413-cache.lib b/library/SubcircuitLibrary/MAX7413/MAX7413-cache.lib
new file mode 100644
index 00000000..c7f00121
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413-cache.lib
@@ -0,0 +1,143 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS capacitor
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_MOS_N
+#
+DEF eSim_MOS_N M 0 0 Y N 1 F N
+F0 "M" 0 -150 50 H V R CNN
+F1 "eSim_MOS_N" 100 -50 50 H V R CNN
+F2 "" 300 -300 29 H V C CNN
+F3 "" 100 -200 60 H V C CNN
+ALIAS mosfet_n
+DRAW
+C 150 -200 111 0 1 10 N
+P 2 0 1 10 130 -290 130 -250 N
+P 2 0 1 0 130 -270 200 -270 N
+P 2 0 1 10 130 -220 130 -180 N
+P 2 0 1 0 130 -200 200 -200 N
+P 2 0 1 10 130 -150 130 -110 N
+P 2 0 1 0 130 -130 200 -130 N
+P 2 0 1 0 200 -300 200 -270 N
+P 2 0 1 0 200 -130 200 -100 N
+P 3 0 1 10 110 -275 110 -125 110 -125 N
+P 3 0 1 0 200 -200 300 -200 300 -250 N
+P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F
+X D 1 200 0 100 D 50 50 1 1 P
+X G 2 -100 -200 210 R 50 50 1 1 P
+X S 3 200 -400 100 U 50 50 1 1 P
+X B 4 300 -350 98 U 47 47 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# lm_741
+#
+DEF lm_741 X 0 40 Y Y 1 F N
+F0 "X" -200 0 60 H V C CNN
+F1 "lm_741" -100 -250 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -350 350 350 0 -350 -350 -350 350 N
+X off_null 1 -50 400 200 D 50 38 1 1 I
+X inv 2 -550 150 200 R 50 38 1 1 I
+X non_inv 3 -550 -100 200 R 50 38 1 1 I
+X v_neg 4 -150 -450 200 U 50 38 1 1 I
+X off_null 5 50 350 200 D 50 38 1 1 I
+X out 6 550 0 200 L 50 38 1 1 O
+X v_pos 7 -150 450 200 D 50 38 1 1 I
+X NC 8 150 -300 200 U 50 38 1 1 N
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413.cir b/library/SubcircuitLibrary/MAX7413/MAX7413.cir
new file mode 100644
index 00000000..ceabfc14
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413.cir
@@ -0,0 +1,44 @@
+* E:\ESIM\FOSSEE\eSim\library\SubcircuitLibrary\MAX7413\MAX7413.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/30/25 20:59:23
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X2 ? Net-_C3-Pad1_ Net-_C4-Pad1_ Net-_U1-Pad4_ ? Net-_C5-Pad1_ Net-_U1-Pad3_ ? lm_741
+R7 Net-_C3-Pad1_ Net-_C5-Pad1_ 9.089k
+R6 Net-_C3-Pad1_ GND 10k
+C4 Net-_C4-Pad1_ GND 0.05n
+C3 Net-_C3-Pad1_ GND 0.0099u
+C5 Net-_C5-Pad1_ Net-_C5-Pad2_ 0.05n
+X3 ? Net-_C6-Pad1_ Net-_C7-Pad1_ Net-_U1-Pad4_ ? Net-_C8-Pad1_ Net-_U1-Pad3_ ? lm_741
+R11 Net-_C6-Pad1_ Net-_C8-Pad1_ 2.254k
+R10 Net-_C6-Pad1_ GND 10k
+C7 Net-_C7-Pad1_ GND 0.05n
+C6 Net-_C6-Pad1_ GND 0.0199u
+C8 Net-_C8-Pad1_ Net-_C8-Pad2_ 0.05n
+X1 ? Net-_C1-Pad1_ Net-_C2-Pad1_ Net-_U1-Pad4_ ? Net-_M7-Pad2_ Net-_U1-Pad3_ ? lm_741
+R1 Net-_M2-Pad1_ Net-_C2-Pad1_ 3.4k
+R3 Net-_C1-Pad1_ Net-_M7-Pad2_ 10k
+R2 Net-_C1-Pad1_ GND 10k
+C2 Net-_C2-Pad1_ GND 0.05n
+C1 Net-_C1-Pad1_ GND 0.001u
+M1 Net-_C9-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad2_ Net-_M1-Pad2_ eSim_MOS_N
+M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C9-Pad1_ Net-_M1-Pad2_ eSim_MOS_N
+C9 Net-_C9-Pad1_ GND 0.05n
+M7 Net-_C12-Pad1_ Net-_M7-Pad2_ Net-_M7-Pad2_ Net-_M7-Pad2_ eSim_MOS_N
+M8 Net-_C5-Pad2_ Net-_M7-Pad2_ Net-_C12-Pad1_ Net-_M7-Pad2_ eSim_MOS_N
+C12 Net-_C12-Pad1_ GND 0.005n
+M9 Net-_C13-Pad1_ Net-_C5-Pad2_ Net-_C5-Pad2_ Net-_C5-Pad2_ eSim_MOS_N
+M10 Net-_C4-Pad1_ Net-_C5-Pad2_ Net-_C13-Pad1_ Net-_C5-Pad2_ eSim_MOS_N
+C13 Net-_C13-Pad1_ GND 0.005n
+M3 Net-_C10-Pad1_ Net-_C5-Pad1_ Net-_C5-Pad1_ Net-_C5-Pad1_ eSim_MOS_N
+M4 Net-_C8-Pad2_ Net-_C5-Pad1_ Net-_C10-Pad1_ Net-_C5-Pad1_ eSim_MOS_N
+C10 Net-_C10-Pad1_ GND 0.05n
+M5 Net-_C11-Pad1_ Net-_C8-Pad2_ Net-_C8-Pad2_ Net-_C8-Pad2_ eSim_MOS_N
+M6 Net-_C7-Pad1_ Net-_C8-Pad2_ Net-_C11-Pad1_ Net-_C8-Pad2_ eSim_MOS_N
+C11 Net-_C11-Pad1_ GND 0.05n
+U1 ? Net-_M1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_C8-Pad1_ ? GND GND PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413.cir.out b/library/SubcircuitLibrary/MAX7413/MAX7413.cir.out
new file mode 100644
index 00000000..546940e5
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413.cir.out
@@ -0,0 +1,47 @@
+* e:\esim\fossee\esim\library\subcircuitlibrary\max7413\max7413.cir
+
+.include lm_741.sub
+.include NMOS-180nm.lib
+x2 ? net-_c3-pad1_ net-_c4-pad1_ net-_u1-pad4_ ? net-_c5-pad1_ net-_u1-pad3_ ? lm_741
+r7 net-_c3-pad1_ net-_c5-pad1_ 9.089k
+r6 net-_c3-pad1_ gnd 10k
+c4 net-_c4-pad1_ gnd 0.05n
+c3 net-_c3-pad1_ gnd 0.0099u
+c5 net-_c5-pad1_ net-_c5-pad2_ 0.05n
+x3 ? net-_c6-pad1_ net-_c7-pad1_ net-_u1-pad4_ ? net-_c8-pad1_ net-_u1-pad3_ ? lm_741
+r11 net-_c6-pad1_ net-_c8-pad1_ 2.254k
+r10 net-_c6-pad1_ gnd 10k
+c7 net-_c7-pad1_ gnd 0.05n
+c6 net-_c6-pad1_ gnd 0.0199u
+c8 net-_c8-pad1_ net-_c8-pad2_ 0.05n
+x1 ? net-_c1-pad1_ net-_c2-pad1_ net-_u1-pad4_ ? net-_m7-pad2_ net-_u1-pad3_ ? lm_741
+r1 net-_m2-pad1_ net-_c2-pad1_ 3.4k
+r3 net-_c1-pad1_ net-_m7-pad2_ 10k
+r2 net-_c1-pad1_ gnd 10k
+c2 net-_c2-pad1_ gnd 0.05n
+c1 net-_c1-pad1_ gnd 0.001u
+m1 net-_c9-pad1_ net-_m1-pad2_ net-_m1-pad2_ net-_m1-pad2_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c9-pad1_ net-_m1-pad2_ CMOSN W=100u L=100u M=1
+c9 net-_c9-pad1_ gnd 0.05n
+m7 net-_c12-pad1_ net-_m7-pad2_ net-_m7-pad2_ net-_m7-pad2_ CMOSN W=100u L=100u M=1
+m8 net-_c5-pad2_ net-_m7-pad2_ net-_c12-pad1_ net-_m7-pad2_ CMOSN W=100u L=100u M=1
+c12 net-_c12-pad1_ gnd 0.005n
+m9 net-_c13-pad1_ net-_c5-pad2_ net-_c5-pad2_ net-_c5-pad2_ CMOSN W=100u L=100u M=1
+m10 net-_c4-pad1_ net-_c5-pad2_ net-_c13-pad1_ net-_c5-pad2_ CMOSN W=100u L=100u M=1
+c13 net-_c13-pad1_ gnd 0.005n
+m3 net-_c10-pad1_ net-_c5-pad1_ net-_c5-pad1_ net-_c5-pad1_ CMOSN W=100u L=100u M=1
+m4 net-_c8-pad2_ net-_c5-pad1_ net-_c10-pad1_ net-_c5-pad1_ CMOSN W=100u L=100u M=1
+c10 net-_c10-pad1_ gnd 0.05n
+m5 net-_c11-pad1_ net-_c8-pad2_ net-_c8-pad2_ net-_c8-pad2_ CMOSN W=100u L=100u M=1
+m6 net-_c7-pad1_ net-_c8-pad2_ net-_c11-pad1_ net-_c8-pad2_ CMOSN W=100u L=100u M=1
+c11 net-_c11-pad1_ gnd 0.05n
+* u1 ? net-_m1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_c8-pad1_ ? gnd gnd port
+.ac lin 0 0Hz 0Hz
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413.pro b/library/SubcircuitLibrary/MAX7413/MAX7413.pro
new file mode 100644
index 00000000..d7f78c3b
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413.pro
@@ -0,0 +1,71 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413.sch b/library/SubcircuitLibrary/MAX7413/MAX7413.sch
new file mode 100644
index 00000000..59223f4c
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413.sch
@@ -0,0 +1,1012 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:MAX7413-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L lm_741 X2
+U 1 1 68319B36
+P 9750 2400
+F 0 "X2" H 9550 2400 60 0000 C CNN
+F 1 "lm_741" H 9650 2150 60 0000 C CNN
+F 2 "" H 9750 2400 60 0000 C CNN
+F 3 "" H 9750 2400 60 0000 C CNN
+ 1 9750 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R7
+U 1 1 68319B39
+P 9650 1300
+F 0 "R7" H 9700 1430 50 0000 C CNN
+F 1 "9.089k" H 9700 1250 50 0000 C CNN
+F 2 "" H 9700 1280 30 0000 C CNN
+F 3 "" V 9700 1350 30 0000 C CNN
+ 1 9650 1300
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R6
+U 1 1 68319B3A
+P 8800 1350
+F 0 "R6" H 8850 1480 50 0000 C CNN
+F 1 "10k" H 8850 1300 50 0000 C CNN
+F 2 "" H 8850 1330 30 0000 C CNN
+F 3 "" V 8850 1400 30 0000 C CNN
+ 1 8800 1350
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C4
+U 1 1 68319B3B
+P 9050 3050
+F 0 "C4" H 9075 3150 50 0000 L CNN
+F 1 "0.05n" H 9075 2950 50 0000 L CNN
+F 2 "" H 9088 2900 30 0000 C CNN
+F 3 "" H 9050 3050 60 0000 C CNN
+ 1 9050 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor C3
+U 1 1 68319B3C
+P 8450 1400
+F 0 "C3" H 8475 1500 50 0000 L CNN
+F 1 "0.0099u" H 8475 1300 50 0000 L CNN
+F 2 "" H 8488 1250 30 0000 C CNN
+F 3 "" H 8450 1400 60 0000 C CNN
+ 1 8450 1400
+ 1 0 0 -1
+$EndComp
+$Comp
+L capacitor C5
+U 1 1 68319B3D
+P 8850 4250
+F 0 "C5" H 8875 4350 50 0000 L CNN
+F 1 "0.05n" H 8875 4150 50 0000 L CNN
+F 2 "" H 8888 4100 30 0000 C CNN
+F 3 "" H 8850 4250 60 0000 C CNN
+ 1 8850 4250
+ 0 1 1 0
+$EndComp
+$Comp
+L GND #PWR01
+U 1 1 68319B3E
+P 9050 3350
+F 0 "#PWR01" H 9050 3100 50 0001 C CNN
+F 1 "GND" H 9050 3200 50 0000 C CNN
+F 2 "" H 9050 3350 50 0001 C CNN
+F 3 "" H 9050 3350 50 0001 C CNN
+ 1 9050 3350
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR02
+U 1 1 68319B3F
+P 8850 1750
+F 0 "#PWR02" H 8850 1500 50 0001 C CNN
+F 1 "GND" H 8850 1600 50 0000 C CNN
+F 2 "" H 8850 1750 50 0001 C CNN
+F 3 "" H 8850 1750 50 0001 C CNN
+ 1 8850 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR03
+U 1 1 68319B40
+P 8450 1750
+F 0 "#PWR03" H 8450 1500 50 0001 C CNN
+F 1 "GND" H 8450 1600 50 0000 C CNN
+F 2 "" H 8450 1750 50 0001 C CNN
+F 3 "" H 8450 1750 50 0001 C CNN
+ 1 8450 1750
+ 1 0 0 -1
+$EndComp
+NoConn ~ 9700 2000
+NoConn ~ 9800 2050
+NoConn ~ 9900 2700
+$Comp
+L lm_741 X3
+U 1 1 68319B45
+P 5400 5750
+F 0 "X3" H 5200 5750 60 0000 C CNN
+F 1 "lm_741" H 5300 5500 60 0000 C CNN
+F 2 "" H 5400 5750 60 0000 C CNN
+F 3 "" H 5400 5750 60 0000 C CNN
+ 1 5400 5750
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R11
+U 1 1 68319B48
+P 5300 4650
+F 0 "R11" H 5350 4780 50 0000 C CNN
+F 1 "2.254k" H 5350 4600 50 0000 C CNN
+F 2 "" H 5350 4630 30 0000 C CNN
+F 3 "" V 5350 4700 30 0000 C CNN
+ 1 5300 4650
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R10
+U 1 1 68319B49
+P 4450 4700
+F 0 "R10" H 4500 4830 50 0000 C CNN
+F 1 "10k" H 4500 4650 50 0000 C CNN
+F 2 "" H 4500 4680 30 0000 C CNN
+F 3 "" V 4500 4750 30 0000 C CNN
+ 1 4450 4700
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C7
+U 1 1 68319B4A
+P 4700 6400
+F 0 "C7" H 4725 6500 50 0000 L CNN
+F 1 "0.05n" H 4725 6300 50 0000 L CNN
+F 2 "" H 4738 6250 30 0000 C CNN
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+U 1 1 68319B59
+P 2550 1300
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+U 1 1 68319B5A
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+U 1 1 68319B5B
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+F 0 "#PWR08" H 2950 1400 50 0001 C CNN
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+U 1 1 68319B5C
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+F 3 "" H 2550 1650 50 0001 C CNN
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+ 1 0 0 -1
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+NoConn ~ 3800 1900
+NoConn ~ 3900 1950
+NoConn ~ 4000 2600
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+L eSim_MOS_N M1
+U 1 1 6839CDFE
+P 1400 2800
+F 0 "M1" H 1400 2650 50 0000 R CNN
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+ 0 1 1 0
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+U 1 1 6839CE89
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+F 0 "M2" H 2050 2650 50 0000 R CNN
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+F 2 "" H 2350 2500 29 0000 C CNN
+F 3 "" H 2150 2600 60 0000 C CNN
+ 1 2050 2800
+ 0 1 1 0
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+$Comp
+L capacitor C9
+U 1 1 6839CFA7
+P 1500 3750
+F 0 "C9" H 1525 3850 50 0000 L CNN
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+L GND #PWR010
+U 1 1 6839CFAD
+P 1500 4050
+F 0 "#PWR010" H 1500 3800 50 0001 C CNN
+F 1 "GND" H 1500 3900 50 0000 C CNN
+F 2 "" H 1500 4050 50 0001 C CNN
+F 3 "" H 1500 4050 50 0001 C CNN
+ 1 1500 4050
+ 1 0 0 -1
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+L eSim_MOS_N M7
+U 1 1 6839D4E3
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+F 0 "M7" H 6300 2500 50 0000 R CNN
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+F 2 "" H 6600 2350 29 0000 C CNN
+F 3 "" H 6400 2450 60 0000 C CNN
+ 1 6300 2650
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+L eSim_MOS_N M8
+U 1 1 6839D4E9
+P 6950 2650
+F 0 "M8" H 6950 2500 50 0000 R CNN
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+F 2 "" H 7250 2350 29 0000 C CNN
+F 3 "" H 7050 2450 60 0000 C CNN
+ 1 6950 2650
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C12
+U 1 1 6839D4EF
+P 6400 3600
+F 0 "C12" H 6425 3700 50 0000 L CNN
+F 1 "0.005n" H 6425 3500 50 0000 L CNN
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+L GND #PWR011
+U 1 1 6839D4F5
+P 6400 3900
+F 0 "#PWR011" H 6400 3650 50 0001 C CNN
+F 1 "GND" H 6400 3750 50 0000 C CNN
+F 2 "" H 6400 3900 50 0001 C CNN
+F 3 "" H 6400 3900 50 0001 C CNN
+ 1 6400 3900
+ 1 0 0 -1
+$EndComp
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+L eSim_MOS_N M9
+U 1 1 6839D72F
+P 7750 2650
+F 0 "M9" H 7750 2500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 7850 2600 50 0000 R CNN
+F 2 "" H 8050 2350 29 0000 C CNN
+F 3 "" H 7850 2450 60 0000 C CNN
+ 1 7750 2650
+ 0 1 1 0
+$EndComp
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+L eSim_MOS_N M10
+U 1 1 6839D735
+P 8400 2650
+F 0 "M10" H 8400 2500 50 0000 R CNN
+F 1 "eSim_MOS_N" H 8500 2600 50 0000 R CNN
+F 2 "" H 8700 2350 29 0000 C CNN
+F 3 "" H 8500 2450 60 0000 C CNN
+ 1 8400 2650
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C13
+U 1 1 6839D73B
+P 7850 3600
+F 0 "C13" H 7875 3700 50 0000 L CNN
+F 1 "0.005n" H 7875 3500 50 0000 L CNN
+F 2 "" H 7888 3450 30 0000 C CNN
+F 3 "" H 7850 3600 60 0000 C CNN
+ 1 7850 3600
+ 1 0 0 -1
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+L GND #PWR012
+U 1 1 6839D741
+P 7850 3900
+F 0 "#PWR012" H 7850 3650 50 0001 C CNN
+F 1 "GND" H 7850 3750 50 0000 C CNN
+F 2 "" H 7850 3900 50 0001 C CNN
+F 3 "" H 7850 3900 50 0001 C CNN
+ 1 7850 3900
+ 1 0 0 -1
+$EndComp
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+L eSim_MOS_N M3
+U 1 1 6839DAA8
+P 2050 5950
+F 0 "M3" H 2050 5800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 2150 5900 50 0000 R CNN
+F 2 "" H 2350 5650 29 0000 C CNN
+F 3 "" H 2150 5750 60 0000 C CNN
+ 1 2050 5950
+ 0 1 1 0
+$EndComp
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+L eSim_MOS_N M4
+U 1 1 6839DAAE
+P 2700 5950
+F 0 "M4" H 2700 5800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 2800 5900 50 0000 R CNN
+F 2 "" H 3000 5650 29 0000 C CNN
+F 3 "" H 2800 5750 60 0000 C CNN
+ 1 2700 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C10
+U 1 1 6839DAB4
+P 2150 6900
+F 0 "C10" H 2175 7000 50 0000 L CNN
+F 1 "0.05n" H 2175 6800 50 0000 L CNN
+F 2 "" H 2188 6750 30 0000 C CNN
+F 3 "" H 2150 6900 60 0000 C CNN
+ 1 2150 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR013
+U 1 1 6839DABA
+P 2150 7200
+F 0 "#PWR013" H 2150 6950 50 0001 C CNN
+F 1 "GND" H 2150 7050 50 0000 C CNN
+F 2 "" H 2150 7200 50 0001 C CNN
+F 3 "" H 2150 7200 50 0001 C CNN
+ 1 2150 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_MOS_N M5
+U 1 1 6839DAD1
+P 3500 5950
+F 0 "M5" H 3500 5800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 3600 5900 50 0000 R CNN
+F 2 "" H 3800 5650 29 0000 C CNN
+F 3 "" H 3600 5750 60 0000 C CNN
+ 1 3500 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L eSim_MOS_N M6
+U 1 1 6839DAD7
+P 4150 5950
+F 0 "M6" H 4150 5800 50 0000 R CNN
+F 1 "eSim_MOS_N" H 4250 5900 50 0000 R CNN
+F 2 "" H 4450 5650 29 0000 C CNN
+F 3 "" H 4250 5750 60 0000 C CNN
+ 1 4150 5950
+ 0 1 1 0
+$EndComp
+$Comp
+L capacitor C11
+U 1 1 6839DADD
+P 3600 6900
+F 0 "C11" H 3625 7000 50 0000 L CNN
+F 1 "0.05n" H 3625 6800 50 0000 L CNN
+F 2 "" H 3638 6750 30 0000 C CNN
+F 3 "" H 3600 6900 60 0000 C CNN
+ 1 3600 6900
+ 1 0 0 -1
+$EndComp
+$Comp
+L GND #PWR014
+U 1 1 6839DAE3
+P 3600 7200
+F 0 "#PWR014" H 3600 6950 50 0001 C CNN
+F 1 "GND" H 3600 7050 50 0000 C CNN
+F 2 "" H 3600 7200 50 0001 C CNN
+F 3 "" H 3600 7200 50 0001 C CNN
+ 1 3600 7200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 6839E4AE
+P 400 1750
+F 0 "U1" H 450 1850 30 0000 C CNN
+F 1 "PORT" H 400 1750 30 0000 C CNN
+F 2 "" H 400 1750 60 0000 C CNN
+F 3 "" H 400 1750 60 0000 C CNN
+ 1 400 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 6839E5AF
+P 400 3000
+F 0 "U1" H 450 3100 30 0000 C CNN
+F 1 "PORT" H 400 3000 30 0000 C CNN
+F 2 "" H 400 3000 60 0000 C CNN
+F 3 "" H 400 3000 60 0000 C CNN
+ 2 400 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 6839E682
+P 600 3950
+F 0 "U1" H 650 4050 30 0000 C CNN
+F 1 "PORT" H 600 3950 30 0000 C CNN
+F 2 "" H 600 3950 60 0000 C CNN
+F 3 "" H 600 3950 60 0000 C CNN
+ 3 600 3950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 6839E7FF
+P 600 4300
+F 0 "U1" H 650 4400 30 0000 C CNN
+F 1 "PORT" H 600 4300 30 0000 C CNN
+F 2 "" H 600 4300 60 0000 C CNN
+F 3 "" H 600 4300 60 0000 C CNN
+ 4 600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 6839E8D8
+P 7350 6750
+F 0 "U1" H 7400 6850 30 0000 C CNN
+F 1 "PORT" H 7350 6750 30 0000 C CNN
+F 2 "" H 7350 6750 60 0000 C CNN
+F 3 "" H 7350 6750 60 0000 C CNN
+ 8 7350 6750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 6839E997
+P 7350 5800
+F 0 "U1" H 7400 5900 30 0000 C CNN
+F 1 "PORT" H 7350 5800 30 0000 C CNN
+F 2 "" H 7350 5800 60 0000 C CNN
+F 3 "" H 7350 5800 60 0000 C CNN
+ 5 7350 5800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 6839EA34
+P 7350 6200
+F 0 "U1" H 7400 6300 30 0000 C CNN
+F 1 "PORT" H 7350 6200 30 0000 C CNN
+F 2 "" H 7350 6200 60 0000 C CNN
+F 3 "" H 7350 6200 60 0000 C CNN
+ 6 7350 6200
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 6839EAC1
+P 7350 6450
+F 0 "U1" H 7400 6550 30 0000 C CNN
+F 1 "PORT" H 7350 6450 30 0000 C CNN
+F 2 "" H 7350 6450 60 0000 C CNN
+F 3 "" H 7350 6450 60 0000 C CNN
+ 7 7350 6450
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 3050 2400 3300 2400
+Wire Wire Line
+ 2950 1150 3650 1150
+Wire Wire Line
+ 3200 650 3200 2150
+Wire Wire Line
+ 4600 5850 4850 5850
+Wire Wire Line
+ 6350 4600 6350 7400
+Wire Wire Line
+ 4500 4600 5200 4600
+Wire Wire Line
+ 4750 4100 4750 5600
+Connection ~ 10700 2400
+Wire Wire Line
+ 10700 4250 9000 4250
+Wire Wire Line
+ 9050 3200 9050 3350
+Connection ~ 9050 2500
+Wire Wire Line
+ 9050 2500 9050 2900
+Wire Wire Line
+ 8950 2500 9200 2500
+Wire Wire Line
+ 8450 750 9100 750
+Wire Wire Line
+ 8450 1250 8450 750
+Wire Wire Line
+ 8450 1550 8450 1750
+Wire Wire Line
+ 8850 1550 8850 1750
+Connection ~ 9100 1250
+Wire Wire Line
+ 10300 2400 11150 2400
+Wire Wire Line
+ 10700 1250 10700 4250
+Wire Wire Line
+ 9850 1250 10700 1250
+Wire Wire Line
+ 8850 1250 9550 1250
+Wire Wire Line
+ 9100 750 9100 2250
+Wire Wire Line
+ 9100 2250 9200 2250
+Wire Wire Line
+ 10250 2850 9600 2850
+Wire Wire Line
+ 10950 1500 9600 1500
+Wire Wire Line
+ 9600 1500 9600 1950
+Wire Wire Line
+ 5250 5300 5250 4850
+Wire Wire Line
+ 5250 4850 6600 4850
+Wire Wire Line
+ 5250 6200 6050 6200
+Wire Wire Line
+ 4750 5600 4850 5600
+Wire Wire Line
+ 5500 4600 6350 4600
+Connection ~ 4750 4600
+Wire Wire Line
+ 4500 4900 4500 5100
+Wire Wire Line
+ 4100 4900 4100 5100
+Wire Wire Line
+ 4100 4600 4100 4100
+Wire Wire Line
+ 4100 4100 4750 4100
+Wire Wire Line
+ 4700 5850 4700 6250
+Connection ~ 4700 5850
+Wire Wire Line
+ 4700 6550 4700 6700
+Wire Wire Line
+ 6350 7400 5450 7400
+Connection ~ 6350 5750
+Wire Wire Line
+ 3700 1850 3700 1400
+Wire Wire Line
+ 3700 1400 5050 1400
+Wire Wire Line
+ 3700 2750 4350 2750
+Wire Wire Line
+ 3200 2150 3300 2150
+Wire Wire Line
+ 3950 1150 4800 1150
+Wire Wire Line
+ 4800 1150 4800 2400
+Wire Wire Line
+ 4800 2300 4400 2300
+Connection ~ 3200 1150
+Wire Wire Line
+ 2950 1450 2950 1650
+Wire Wire Line
+ 2550 1450 2550 1650
+Wire Wire Line
+ 2550 1150 2550 650
+Wire Wire Line
+ 2550 650 3200 650
+Wire Wire Line
+ 3150 2400 3150 2800
+Connection ~ 3150 2400
+Wire Wire Line
+ 3150 3100 3150 3250
+Connection ~ 4800 2300
+Wire Wire Line
+ 4800 2400 5150 2400
+Wire Wire Line
+ 11150 2400 11150 4450
+Wire Wire Line
+ 2350 2400 2750 2400
+Wire Wire Line
+ 1500 3000 1500 3600
+Wire Wire Line
+ 1500 3900 1500 4050
+Wire Wire Line
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+Connection ~ 1500 3000
+Wire Wire Line
+ 1200 2700 1200 2300
+Wire Wire Line
+ 1200 2300 1850 2300
+Wire Wire Line
+ 1850 2300 1850 2700
+Wire Wire Line
+ 800 3100 1050 3100
+Wire Wire Line
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+Wire Wire Line
+ 650 3000 1000 3000
+Wire Wire Line
+ 1650 3100 1650 3300
+Wire Wire Line
+ 1650 3300 800 3300
+Connection ~ 800 3100
+Wire Wire Line
+ 1500 2300 1500 2100
+Wire Wire Line
+ 1500 2100 800 2100
+Connection ~ 800 3000
+Connection ~ 1500 2300
+Wire Wire Line
+ 6400 2850 6400 3450
+Wire Wire Line
+ 6400 3750 6400 3900
+Wire Wire Line
+ 6300 2850 6550 2850
+Connection ~ 6400 2850
+Wire Wire Line
+ 6100 2550 6100 2150
+Wire Wire Line
+ 6100 2150 6750 2150
+Wire Wire Line
+ 6750 2150 6750 2550
+Wire Wire Line
+ 5700 2950 5950 2950
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6550 2950 6550 3150
+Wire Wire Line
+ 6550 3150 5700 3150
+Connection ~ 5700 2950
+Wire Wire Line
+ 6400 2150 6400 1950
+Wire Wire Line
+ 6400 1950 5700 1950
+Connection ~ 5700 2850
+Connection ~ 6400 2150
+Wire Wire Line
+ 7850 2850 7850 3450
+Wire Wire Line
+ 7850 3750 7850 3900
+Wire Wire Line
+ 7750 2850 8000 2850
+Connection ~ 7850 2850
+Wire Wire Line
+ 7550 2550 7550 2150
+Wire Wire Line
+ 7550 2150 8200 2150
+Wire Wire Line
+ 8200 2150 8200 2550
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 6950 2850 7350 2850
+Wire Wire Line
+ 8000 2950 8000 3150
+Wire Wire Line
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+Connection ~ 7150 2950
+Wire Wire Line
+ 7850 2150 7850 1950
+Wire Wire Line
+ 7850 1950 7150 1950
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+Connection ~ 7850 2150
+Wire Wire Line
+ 2150 6150 2150 6750
+Wire Wire Line
+ 2150 7050 2150 7200
+Wire Wire Line
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+Connection ~ 2150 6150
+Wire Wire Line
+ 1850 5850 1850 5450
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 2300 6450 1450 6450
+Connection ~ 1450 6250
+Wire Wire Line
+ 2150 5450 2150 5250
+Wire Wire Line
+ 2150 5250 1450 5250
+Connection ~ 1450 6150
+Connection ~ 2150 5450
+Wire Wire Line
+ 3600 6150 3600 6750
+Wire Wire Line
+ 3600 7050 3600 7200
+Wire Wire Line
+ 3500 6150 3750 6150
+Connection ~ 3600 6150
+Wire Wire Line
+ 3300 5850 3300 5450
+Wire Wire Line
+ 3300 5450 3950 5450
+Wire Wire Line
+ 3950 5450 3950 5850
+Wire Wire Line
+ 2900 6250 3150 6250
+Wire Wire Line
+ 2900 5250 2900 6450
+Wire Wire Line
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+Wire Wire Line
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+Wire Wire Line
+ 3750 6450 2900 6450
+Connection ~ 2900 6250
+Wire Wire Line
+ 3600 5450 3600 5250
+Wire Wire Line
+ 3600 5250 2900 5250
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+Connection ~ 3600 5450
+Wire Wire Line
+ 2050 3000 2350 3000
+Wire Wire Line
+ 2350 3000 2350 2400
+Wire Wire Line
+ 5150 2400 5150 2850
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 7050 2850
+Wire Wire Line
+ 8400 2850 8950 2850
+Wire Wire Line
+ 8950 2850 8950 2500
+Wire Wire Line
+ 11150 4450 1300 4450
+Wire Wire Line
+ 1300 4450 1300 6150
+Wire Wire Line
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+Wire Wire Line
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+Connection ~ 2800 6150
+Wire Wire Line
+ 4600 5850 4600 6150
+Wire Wire Line
+ 4600 6150 4150 6150
+Wire Wire Line
+ 850 3950 10950 3950
+Wire Wire Line
+ 5050 1400 5050 4100
+Wire Wire Line
+ 10950 3950 10950 1500
+Connection ~ 5050 3950
+Wire Wire Line
+ 6600 4850 6600 4100
+Wire Wire Line
+ 6600 4100 5050 4100
+Wire Wire Line
+ 850 4300 10250 4300
+Wire Wire Line
+ 4350 2750 4350 5000
+Wire Wire Line
+ 10250 4300 10250 2850
+Connection ~ 4350 4300
+Wire Wire Line
+ 6050 6200 6050 5000
+Wire Wire Line
+ 6050 5000 4350 5000
+Wire Wire Line
+ 7100 6450 5300 6450
+Wire Wire Line
+ 5300 6450 5300 6600
+Wire Wire Line
+ 5300 6600 4700 6600
+Connection ~ 4700 6600
+Wire Wire Line
+ 7100 6750 4250 6750
+Wire Wire Line
+ 4250 6750 4250 4950
+Wire Wire Line
+ 4250 4950 4100 4950
+Connection ~ 4100 4950
+Wire Wire Line
+ 5950 5750 6700 5750
+Wire Wire Line
+ 6700 5750 6700 5800
+Wire Wire Line
+ 6700 5800 7100 5800
+Wire Wire Line
+ 2300 6250 2350 6250
+Wire Wire Line
+ 3750 6250 3800 6250
+Wire Wire Line
+ 6550 2950 6600 2950
+Wire Wire Line
+ 8000 2950 8050 2950
+Wire Wire Line
+ 1650 3100 1700 3100
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413.sub b/library/SubcircuitLibrary/MAX7413/MAX7413.sub
new file mode 100644
index 00000000..711ea0cd
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413.sub
@@ -0,0 +1,41 @@
+* Subcircuit MAX7413
+.subckt MAX7413 ? net-_m1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_c8-pad1_ ? gnd gnd
+* e:\esim\fossee\esim\library\subcircuitlibrary\max7413\max7413.cir
+.include lm_741.sub
+.include NMOS-180nm.lib
+x2 ? net-_c3-pad1_ net-_c4-pad1_ net-_u1-pad4_ ? net-_c5-pad1_ net-_u1-pad3_ ? lm_741
+r7 net-_c3-pad1_ net-_c5-pad1_ 9.089k
+r6 net-_c3-pad1_ gnd 10k
+c4 net-_c4-pad1_ gnd 0.05n
+c3 net-_c3-pad1_ gnd 0.0099u
+c5 net-_c5-pad1_ net-_c5-pad2_ 0.05n
+x3 ? net-_c6-pad1_ net-_c7-pad1_ net-_u1-pad4_ ? net-_c8-pad1_ net-_u1-pad3_ ? lm_741
+r11 net-_c6-pad1_ net-_c8-pad1_ 2.254k
+r10 net-_c6-pad1_ gnd 10k
+c7 net-_c7-pad1_ gnd 0.05n
+c6 net-_c6-pad1_ gnd 0.0199u
+c8 net-_c8-pad1_ net-_c8-pad2_ 0.05n
+x1 ? net-_c1-pad1_ net-_c2-pad1_ net-_u1-pad4_ ? net-_m7-pad2_ net-_u1-pad3_ ? lm_741
+r1 net-_m2-pad1_ net-_c2-pad1_ 3.4k
+r3 net-_c1-pad1_ net-_m7-pad2_ 10k
+r2 net-_c1-pad1_ gnd 10k
+c2 net-_c2-pad1_ gnd 0.05n
+c1 net-_c1-pad1_ gnd 0.001u
+m1 net-_c9-pad1_ net-_m1-pad2_ net-_m1-pad2_ net-_m1-pad2_ CMOSN W=100u L=100u M=1
+m2 net-_m2-pad1_ net-_m1-pad2_ net-_c9-pad1_ net-_m1-pad2_ CMOSN W=100u L=100u M=1
+c9 net-_c9-pad1_ gnd 0.05n
+m7 net-_c12-pad1_ net-_m7-pad2_ net-_m7-pad2_ net-_m7-pad2_ CMOSN W=100u L=100u M=1
+m8 net-_c5-pad2_ net-_m7-pad2_ net-_c12-pad1_ net-_m7-pad2_ CMOSN W=100u L=100u M=1
+c12 net-_c12-pad1_ gnd 0.005n
+m9 net-_c13-pad1_ net-_c5-pad2_ net-_c5-pad2_ net-_c5-pad2_ CMOSN W=100u L=100u M=1
+m10 net-_c4-pad1_ net-_c5-pad2_ net-_c13-pad1_ net-_c5-pad2_ CMOSN W=100u L=100u M=1
+c13 net-_c13-pad1_ gnd 0.005n
+m3 net-_c10-pad1_ net-_c5-pad1_ net-_c5-pad1_ net-_c5-pad1_ CMOSN W=100u L=100u M=1
+m4 net-_c8-pad2_ net-_c5-pad1_ net-_c10-pad1_ net-_c5-pad1_ CMOSN W=100u L=100u M=1
+c10 net-_c10-pad1_ gnd 0.05n
+m5 net-_c11-pad1_ net-_c8-pad2_ net-_c8-pad2_ net-_c8-pad2_ CMOSN W=100u L=100u M=1
+m6 net-_c7-pad1_ net-_c8-pad2_ net-_c11-pad1_ net-_c8-pad2_ CMOSN W=100u L=100u M=1
+c11 net-_c11-pad1_ gnd 0.05n
+* Control Statements
+
+.ends MAX7413 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/MAX7413_Previous_Values.xml b/library/SubcircuitLibrary/MAX7413/MAX7413_Previous_Values.xml
new file mode 100644
index 00000000..2c053ff6
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/MAX7413_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><m1><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m7><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m7><m8><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m8><m9><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m9><m10><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m10><m3><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m4><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m5><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>E:\ESIM\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m6></devicemodel><subcircuit><x2><field>E:\ESIM\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x2><x3><field>E:\ESIM\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x3><x1><field>E:\ESIM\FOSSEE\eSim\library\SubcircuitLibrary\lm_741</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/NMOS-180nm.lib b/library/SubcircuitLibrary/MAX7413/NMOS-180nm.lib
new file mode 100644
index 00000000..51e9b119
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/NMOS-180nm.lib
@@ -0,0 +1,13 @@
+.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697
++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0
++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18
++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4
++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0
++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0
++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3
++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1
++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1
++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12
++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286
++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078
++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3)
diff --git a/library/SubcircuitLibrary/MAX7413/NPN.lib b/library/SubcircuitLibrary/MAX7413/NPN.lib
new file mode 100644
index 00000000..6509fe7a
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=.3416 Vjc=.75 Fc=.5 Cje=22.01p Mje=.377 Vje=.75 Tr=46.91n Tf=411.1p
++ Itf=.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/MAX7413/PNP.lib b/library/SubcircuitLibrary/MAX7413/PNP.lib
new file mode 100644
index 00000000..7edda0ea
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/PNP.lib
@@ -0,0 +1,4 @@
+.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829
++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715
++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75
++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10)
diff --git a/library/SubcircuitLibrary/MAX7413/analysis b/library/SubcircuitLibrary/MAX7413/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741-cache.lib b/library/SubcircuitLibrary/MAX7413/lm_741-cache.lib
new file mode 100644
index 00000000..04e3fecd
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741-cache.lib
@@ -0,0 +1,119 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_C
+#
+DEF eSim_C C 0 10 N Y 1 F N
+F0 "C" 25 100 50 H V L CNN
+F1 "eSim_C" 25 -100 50 H V L CNN
+F2 "" 38 -150 30 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ C_*
+$ENDFPLIST
+DRAW
+P 2 0 1 20 -80 -30 80 -30 N
+P 2 0 1 20 -80 30 80 30 N
+X ~ 1 0 150 110 D 40 40 1 1 P
+X ~ 2 0 -150 110 U 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_PNP
+#
+DEF eSim_PNP Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_PNP" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F
+X C 1 100 200 100 D 50 50 1 1 C
+X B 2 -200 0 225 R 50 50 1 1 I
+X E 3 100 -200 100 U 50 50 1 1 E
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741.cir b/library/SubcircuitLibrary/MAX7413/lm_741.cir
new file mode 100644
index 00000000..4a5917ea
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741.cir
@@ -0,0 +1,43 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\lm_741\lm_741.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/25/19 19:37:28
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+Q2 Net-_Q1-Pad1_ Net-_Q2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q6 Net-_Q3-Pad2_ Net-_Q13-Pad1_ Net-_Q1-Pad3_ eSim_PNP
+Q5 Net-_C1-Pad2_ Net-_Q13-Pad1_ Net-_Q2-Pad3_ eSim_PNP
+Q3 Net-_Q10-Pad3_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+Q4 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q9 Net-_Q13-Pad1_ Net-_Q1-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q8 Net-_C1-Pad2_ Net-_Q3-Pad3_ Net-_Q8-Pad3_ eSim_NPN
+Q7 Net-_Q3-Pad2_ Net-_Q3-Pad3_ Net-_Q7-Pad3_ eSim_NPN
+R1 Net-_Q7-Pad3_ Net-_Q12-Pad3_ 1k
+R2 Net-_Q3-Pad3_ Net-_Q12-Pad3_ 50k
+R3 Net-_Q8-Pad3_ Net-_Q12-Pad3_ 1k
+Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN
+Q13 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q13-Pad3_ eSim_NPN
+R4 Net-_Q13-Pad3_ Net-_Q12-Pad3_ 5k
+R11 Net-_Q10-Pad1_ Net-_Q12-Pad1_ 39k
+Q10 Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q11 Net-_C1-Pad1_ Net-_Q10-Pad1_ Net-_Q10-Pad3_ eSim_PNP
+Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_NPN
+R8 Net-_C1-Pad1_ Net-_Q14-Pad2_ 4.5k
+R7 Net-_Q14-Pad3_ Net-_Q14-Pad2_ 7.5k
+C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p
+Q16 Net-_Q14-Pad3_ Net-_C1-Pad2_ Net-_Q15-Pad2_ eSim_NPN
+Q15 Net-_Q14-Pad3_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN
+R5 Net-_Q15-Pad2_ Net-_Q12-Pad3_ 50k
+R6 Net-_Q15-Pad3_ Net-_Q12-Pad3_ 50
+Q17 Net-_C1-Pad2_ Net-_Q15-Pad3_ Net-_Q12-Pad3_ eSim_NPN
+Q18 Net-_Q10-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad3_ eSim_NPN
+Q20 Net-_C1-Pad1_ Net-_Q18-Pad3_ Net-_Q20-Pad3_ eSim_NPN
+R9 Net-_Q18-Pad3_ Net-_Q20-Pad3_ 25
+R10 Net-_Q20-Pad3_ Net-_Q19-Pad3_ 50
+Q19 Net-_Q12-Pad3_ Net-_Q14-Pad3_ Net-_Q19-Pad3_ eSim_PNP
+U1 Net-_Q7-Pad3_ Net-_Q2-Pad2_ Net-_Q1-Pad2_ Net-_Q12-Pad3_ Net-_Q8-Pad3_ Net-_Q20-Pad3_ Net-_Q10-Pad3_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741.cir.out b/library/SubcircuitLibrary/MAX7413/lm_741.cir.out
new file mode 100644
index 00000000..a00bd86a
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741.cir.out
@@ -0,0 +1,46 @@
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1 net-_q7-pad3_ net-_q12-pad3_ 1k
+r2 net-_q3-pad3_ net-_q12-pad3_ 50k
+r3 net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4 net-_q13-pad3_ net-_q12-pad3_ 5k
+r11 net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5 net-_q15-pad2_ net-_q12-pad3_ 50k
+r6 net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9 net-_q18-pad3_ net-_q20-pad3_ 25
+r10 net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* u1 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ? port
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741.pro b/library/SubcircuitLibrary/MAX7413/lm_741.pro
new file mode 100644
index 00000000..b56de1b0
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741.pro
@@ -0,0 +1,44 @@
+update=Fri Jun 7 21:53:51 2019
+version=1
+last_client=eeschema
+[general]
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+RootSch=
+BoardNm=
+[pcbnew]
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+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
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+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_User
+LibName10=eSim_Sources
+LibName11=eSim_Subckt
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741.sch b/library/SubcircuitLibrary/MAX7413/lm_741.sch
new file mode 100644
index 00000000..b017fd2b
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741.sch
@@ -0,0 +1,697 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:lm_741-cache
+EELAYER 25 0
+EELAYER END
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+encoding utf-8
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diff --git a/library/SubcircuitLibrary/MAX7413/lm_741.sub b/library/SubcircuitLibrary/MAX7413/lm_741.sub
new file mode 100644
index 00000000..fa8d27b1
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741.sub
@@ -0,0 +1,40 @@
+* Subcircuit lm_741
+.subckt lm_741 net-_q7-pad3_ net-_q2-pad2_ net-_q1-pad2_ net-_q12-pad3_ net-_q8-pad3_ net-_q20-pad3_ net-_q10-pad3_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\lm_741\lm_741.cir
+.include npn_1.lib
+.include pnp_1.lib
+q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ npn_1
+q2 net-_q1-pad1_ net-_q2-pad2_ net-_q2-pad3_ npn_1
+q6 net-_q3-pad2_ net-_q13-pad1_ net-_q1-pad3_ pnp_1
+q5 net-_c1-pad2_ net-_q13-pad1_ net-_q2-pad3_ pnp_1
+q3 net-_q10-pad3_ net-_q3-pad2_ net-_q3-pad3_ npn_1
+q4 net-_q1-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q9 net-_q13-pad1_ net-_q1-pad1_ net-_q10-pad3_ pnp_1
+q8 net-_c1-pad2_ net-_q3-pad3_ net-_q8-pad3_ npn_1
+q7 net-_q3-pad2_ net-_q3-pad3_ net-_q7-pad3_ npn_1
+r1 net-_q7-pad3_ net-_q12-pad3_ 1k
+r2 net-_q3-pad3_ net-_q12-pad3_ 50k
+r3 net-_q8-pad3_ net-_q12-pad3_ 1k
+q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ npn_1
+q13 net-_q13-pad1_ net-_q12-pad1_ net-_q13-pad3_ npn_1
+r4 net-_q13-pad3_ net-_q12-pad3_ 5k
+r11 net-_q10-pad1_ net-_q12-pad1_ 39k
+q10 net-_q10-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q11 net-_c1-pad1_ net-_q10-pad1_ net-_q10-pad3_ pnp_1
+q14 net-_c1-pad1_ net-_q14-pad2_ net-_q14-pad3_ npn_1
+r8 net-_c1-pad1_ net-_q14-pad2_ 4.5k
+r7 net-_q14-pad3_ net-_q14-pad2_ 7.5k
+c1 net-_c1-pad1_ net-_c1-pad2_ 30p
+q16 net-_q14-pad3_ net-_c1-pad2_ net-_q15-pad2_ npn_1
+q15 net-_q14-pad3_ net-_q15-pad2_ net-_q15-pad3_ npn_1
+r5 net-_q15-pad2_ net-_q12-pad3_ 50k
+r6 net-_q15-pad3_ net-_q12-pad3_ 50
+q17 net-_c1-pad2_ net-_q15-pad3_ net-_q12-pad3_ npn_1
+q18 net-_q10-pad3_ net-_c1-pad1_ net-_q18-pad3_ npn_1
+q20 net-_c1-pad1_ net-_q18-pad3_ net-_q20-pad3_ npn_1
+r9 net-_q18-pad3_ net-_q20-pad3_ 25
+r10 net-_q20-pad3_ net-_q19-pad3_ 50
+q19 net-_q12-pad3_ net-_q14-pad3_ net-_q19-pad3_ pnp_1
+* Control Statements
+
+.ends lm_741 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/lm_741_Previous_Values.xml b/library/SubcircuitLibrary/MAX7413/lm_741_Previous_Values.xml
new file mode 100644
index 00000000..b61322bb
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/lm_741_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model /><devicemodel><q1><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q1><q20><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q20><q3><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q3><q2><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q2><q5><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q5><q4><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q4><q7><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q7><q6><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q6><q9><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q9><q8><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q8><q15><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q15><q14><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q14><q17><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q17><q16><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q16><q11><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q11><q10><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q10><q13><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q13><q12><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q12><q19><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/pnp_1.lib</field></q19><q18><field>C:/Users/malli/eSim/src/deviceModelLibrary/Transistor/npn_1.lib</field></q18></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/npn_1.lib b/library/SubcircuitLibrary/MAX7413/npn_1.lib
new file mode 100644
index 00000000..a1818ed8
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/npn_1.lib
@@ -0,0 +1,29 @@
+.model npn_1 NPN(
++ Vtf=1.7
++ Cjc=0.5p
++ Nc=2
++ Tr=46.91n
++ Ne=1.307
++ Cje=0.5p
++ Isc=0
++ Xtb=1.5
++ Rb=500
++ Rc=1
++ Tf=411.1p
++ Xti=3
++ Ikr=0
++ Bf=125
++ Fc=.5
++ Ise=14.34f
++ Br=6.092
++ Ikf=.2847
++ Mje=.377
++ Mjc=.3416
++ Vaf=74.03
++ Vjc=.75
++ Vje=.75
++ Xtf=3
++ Itf=.6
++ Is=14.34f
++ Eg=1.11
+) \ No newline at end of file
diff --git a/library/SubcircuitLibrary/MAX7413/pnp_1.lib b/library/SubcircuitLibrary/MAX7413/pnp_1.lib
new file mode 100644
index 00000000..a4ee06da
--- /dev/null
+++ b/library/SubcircuitLibrary/MAX7413/pnp_1.lib
@@ -0,0 +1,29 @@
+.model pnp_1 PNP(
++ Vtf=1.7
++ Cjc=1.5p
++ Nc=2
++ Tr=46.91n
++ Ne=1.307
++ Cje=0.3p
++ Isc=0
++ Xtb=1.5
++ Rb=250
++ Rc=1
++ Tf=411.1p
++ Xti=3
++ Ikr=0
++ Bf=25
++ Fc=.5
++ Ise=14.34f
++ Br=6.092
++ Ikf=.2847
++ Mje=.377
++ Mjc=.3416
++ Vaf=74.03
++ Vjc=.75
++ Vje=.75
++ Xtf=3
++ Itf=.6
++ Is=14.34f
++ Eg=1.11
+) \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-06-30 08:06:26 +0000