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-rw-r--r--library/SubcircuitLibrary/L601/D.lib2
-rw-r--r--library/SubcircuitLibrary/L601/L601-cache.lib107
-rw-r--r--library/SubcircuitLibrary/L601/L601.cir67
-rw-r--r--library/SubcircuitLibrary/L601/L601.cir.out70
-rw-r--r--library/SubcircuitLibrary/L601/L601.pro73
-rw-r--r--library/SubcircuitLibrary/L601/L601.sch1267
-rw-r--r--library/SubcircuitLibrary/L601/L601.sub64
-rw-r--r--library/SubcircuitLibrary/L601/L601_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/L601/NPN.lib4
-rw-r--r--library/SubcircuitLibrary/L601/analysis1
10 files changed, 1656 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/L601/D.lib b/library/SubcircuitLibrary/L601/D.lib
new file mode 100644
index 00000000..f53bf3e0
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/D.lib
@@ -0,0 +1,2 @@
+.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/library/SubcircuitLibrary/L601/L601-cache.lib b/library/SubcircuitLibrary/L601/L601-cache.lib
new file mode 100644
index 00000000..2a23e8a6
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601-cache.lib
@@ -0,0 +1,107 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# eSim_Diode
+#
+DEF eSim_Diode D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "eSim_Diode" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ TO-???*
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+ D_*
+$ENDFPLIST
+DRAW
+T 0 -100 50 60 0 0 0 A Normal 0 C C
+T 0 100 50 60 0 0 0 K Normal 0 C C
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_NPN
+#
+DEF eSim_NPN Q 0 0 Y N 1 F N
+F0 "Q" -100 50 50 H V R CNN
+F1 "eSim_NPN" -50 150 50 H V R CNN
+F2 "" 200 100 29 H V C CNN
+F3 "" 0 0 60 H V C CNN
+ALIAS BC547 Q2N2222
+DRAW
+C 50 0 111 0 1 10 N
+P 2 0 1 0 25 25 100 100 N
+P 3 0 1 0 25 -25 100 -100 100 -100 N
+P 3 0 1 20 25 75 25 -75 25 -75 N
+P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F
+X C 1 100 200 100 D 50 50 1 1 P
+X B 2 -200 0 225 R 50 50 1 1 P
+X E 3 100 -200 100 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# eSim_R
+#
+DEF eSim_R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "eSim_R" 50 -50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+ALIAS resistor
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/L601/L601.cir b/library/SubcircuitLibrary/L601/L601.cir
new file mode 100644
index 00000000..a0321006
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601.cir
@@ -0,0 +1,67 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\L601\L601.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 02/03/25 18:35:59
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+Q2 Net-_D8-Pad2_ Net-_D2-Pad2_ Net-_Q2-Pad3_ eSim_NPN
+Q5 Net-_D5-Pad1_ Net-_Q2-Pad3_ GND eSim_NPN
+R2 Net-_D2-Pad2_ Net-_Q2-Pad3_ 7.2k
+R5 Net-_Q2-Pad3_ GND 3k
+D8 GND Net-_D8-Pad2_ eSim_Diode
+D2 GND Net-_D2-Pad2_ eSim_Diode
+D5 Net-_D5-Pad1_ COM eSim_Diode
+Q3 Net-_D9-Pad2_ Net-_D3-Pad2_ Net-_Q3-Pad3_ eSim_NPN
+Q6 Net-_D6-Pad1_ Net-_Q3-Pad3_ GND eSim_NPN
+R3 Net-_D3-Pad2_ Net-_Q3-Pad3_ 7.2k
+R6 Net-_Q3-Pad3_ GND 3k
+D9 GND Net-_D9-Pad2_ eSim_Diode
+D3 GND Net-_D3-Pad2_ eSim_Diode
+D6 Net-_D6-Pad1_ COM eSim_Diode
+Q1 Net-_D7-Pad2_ Net-_D1-Pad2_ Net-_Q1-Pad3_ eSim_NPN
+Q4 Net-_D4-Pad1_ Net-_Q1-Pad3_ GND eSim_NPN
+R1 Net-_D1-Pad2_ Net-_Q1-Pad3_ 7.2k
+R4 Net-_Q1-Pad3_ GND 3k
+D7 GND Net-_D7-Pad2_ eSim_Diode
+D1 GND Net-_D1-Pad2_ eSim_Diode
+D4 Net-_D4-Pad1_ COM eSim_Diode
+Q11 Net-_D21-Pad2_ Net-_D16-Pad2_ Net-_Q11-Pad3_ eSim_NPN
+Q14 Net-_D19-Pad1_ Net-_Q11-Pad3_ GND eSim_NPN
+R11 Net-_D16-Pad2_ Net-_Q11-Pad3_ 7.2k
+R14 Net-_Q11-Pad3_ GND 3k
+D21 GND Net-_D21-Pad2_ eSim_Diode
+D16 GND Net-_D16-Pad2_ eSim_Diode
+D19 Net-_D19-Pad1_ COM eSim_Diode
+Q12 Net-_D23-Pad2_ Net-_D17-Pad2_ Net-_Q12-Pad3_ eSim_NPN
+Q15 Net-_D20-Pad1_ Net-_Q12-Pad3_ GND eSim_NPN
+R12 Net-_D17-Pad2_ Net-_Q12-Pad3_ 7.2k
+R15 Net-_Q12-Pad3_ GND 3k
+D23 GND Net-_D23-Pad2_ eSim_Diode
+D17 GND Net-_D17-Pad2_ eSim_Diode
+D20 Net-_D20-Pad1_ COM eSim_Diode
+Q7 Net-_D14-Pad2_ Net-_D10-Pad2_ Net-_Q7-Pad3_ eSim_NPN
+Q9 Net-_D12-Pad1_ Net-_Q7-Pad3_ GND eSim_NPN
+R7 Net-_D10-Pad2_ Net-_Q7-Pad3_ 7.2k
+R9 Net-_Q7-Pad3_ GND 3k
+D14 GND Net-_D14-Pad2_ eSim_Diode
+D10 GND Net-_D10-Pad2_ eSim_Diode
+D12 Net-_D12-Pad1_ COM eSim_Diode
+Q13 Net-_D24-Pad2_ Net-_D18-Pad2_ Net-_Q13-Pad3_ eSim_NPN
+Q16 Net-_D22-Pad1_ Net-_Q13-Pad3_ GND eSim_NPN
+R13 Net-_D18-Pad2_ Net-_Q13-Pad3_ 7.2k
+R16 Net-_Q13-Pad3_ GND 3k
+D24 GND Net-_D24-Pad2_ eSim_Diode
+D18 GND Net-_D18-Pad2_ eSim_Diode
+D22 Net-_D22-Pad1_ COM eSim_Diode
+Q8 Net-_D15-Pad2_ Net-_D11-Pad2_ Net-_Q10-Pad2_ eSim_NPN
+Q10 Net-_D13-Pad1_ Net-_Q10-Pad2_ GND eSim_NPN
+R8 Net-_D11-Pad2_ Net-_Q10-Pad2_ 7.2k
+R10 Net-_Q10-Pad2_ GND 3k
+D15 GND Net-_D15-Pad2_ eSim_Diode
+D11 GND Net-_D11-Pad2_ eSim_Diode
+D13 Net-_D13-Pad1_ COM eSim_Diode
+U1 Net-_D2-Pad2_ Net-_D3-Pad2_ Net-_D1-Pad2_ Net-_D11-Pad2_ Net-_D10-Pad2_ Net-_D16-Pad2_ Net-_D17-Pad2_ Net-_D18-Pad2_ GND COM Net-_D24-Pad2_ Net-_D23-Pad2_ Net-_D21-Pad2_ Net-_D14-Pad2_ Net-_D15-Pad2_ Net-_D7-Pad2_ Net-_D9-Pad2_ Net-_D8-Pad2_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/L601/L601.cir.out b/library/SubcircuitLibrary/L601/L601.cir.out
new file mode 100644
index 00000000..07ca3f73
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601.cir.out
@@ -0,0 +1,70 @@
+* c:\fossee\esim\library\subcircuitlibrary\l601\l601.cir
+
+.include D.lib
+.include NPN.lib
+q2 net-_d8-pad2_ net-_d2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_d5-pad1_ net-_q2-pad3_ gnd Q2N2222
+r2 net-_d2-pad2_ net-_q2-pad3_ 7.2k
+r5 net-_q2-pad3_ gnd 3k
+d8 gnd net-_d8-pad2_ 1N4148
+d2 gnd net-_d2-pad2_ 1N4148
+d5 net-_d5-pad1_ com 1N4148
+q3 net-_d9-pad2_ net-_d3-pad2_ net-_q3-pad3_ Q2N2222
+q6 net-_d6-pad1_ net-_q3-pad3_ gnd Q2N2222
+r3 net-_d3-pad2_ net-_q3-pad3_ 7.2k
+r6 net-_q3-pad3_ gnd 3k
+d9 gnd net-_d9-pad2_ 1N4148
+d3 gnd net-_d3-pad2_ 1N4148
+d6 net-_d6-pad1_ com 1N4148
+q1 net-_d7-pad2_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222
+q4 net-_d4-pad1_ net-_q1-pad3_ gnd Q2N2222
+r1 net-_d1-pad2_ net-_q1-pad3_ 7.2k
+r4 net-_q1-pad3_ gnd 3k
+d7 gnd net-_d7-pad2_ 1N4148
+d1 gnd net-_d1-pad2_ 1N4148
+d4 net-_d4-pad1_ com 1N4148
+q11 net-_d21-pad2_ net-_d16-pad2_ net-_q11-pad3_ Q2N2222
+q14 net-_d19-pad1_ net-_q11-pad3_ gnd Q2N2222
+r11 net-_d16-pad2_ net-_q11-pad3_ 7.2k
+r14 net-_q11-pad3_ gnd 3k
+d21 gnd net-_d21-pad2_ 1N4148
+d16 gnd net-_d16-pad2_ 1N4148
+d19 net-_d19-pad1_ com 1N4148
+q12 net-_d23-pad2_ net-_d17-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_d20-pad1_ net-_q12-pad3_ gnd Q2N2222
+r12 net-_d17-pad2_ net-_q12-pad3_ 7.2k
+r15 net-_q12-pad3_ gnd 3k
+d23 gnd net-_d23-pad2_ 1N4148
+d17 gnd net-_d17-pad2_ 1N4148
+d20 net-_d20-pad1_ com 1N4148
+q7 net-_d14-pad2_ net-_d10-pad2_ net-_q7-pad3_ Q2N2222
+q9 net-_d12-pad1_ net-_q7-pad3_ gnd Q2N2222
+r7 net-_d10-pad2_ net-_q7-pad3_ 7.2k
+r9 net-_q7-pad3_ gnd 3k
+d14 gnd net-_d14-pad2_ 1N4148
+d10 gnd net-_d10-pad2_ 1N4148
+d12 net-_d12-pad1_ com 1N4148
+q13 net-_d24-pad2_ net-_d18-pad2_ net-_q13-pad3_ Q2N2222
+q16 net-_d22-pad1_ net-_q13-pad3_ gnd Q2N2222
+r13 net-_d18-pad2_ net-_q13-pad3_ 7.2k
+r16 net-_q13-pad3_ gnd 3k
+d24 gnd net-_d24-pad2_ 1N4148
+d18 gnd net-_d18-pad2_ 1N4148
+d22 net-_d22-pad1_ com 1N4148
+q8 net-_d15-pad2_ net-_d11-pad2_ net-_q10-pad2_ Q2N2222
+q10 net-_d13-pad1_ net-_q10-pad2_ gnd Q2N2222
+r8 net-_d11-pad2_ net-_q10-pad2_ 7.2k
+r10 net-_q10-pad2_ gnd 3k
+d15 gnd net-_d15-pad2_ 1N4148
+d11 gnd net-_d11-pad2_ 1N4148
+d13 net-_d13-pad1_ com 1N4148
+* u1 net-_d2-pad2_ net-_d3-pad2_ net-_d1-pad2_ net-_d11-pad2_ net-_d10-pad2_ net-_d16-pad2_ net-_d17-pad2_ net-_d18-pad2_ gnd com net-_d24-pad2_ net-_d23-pad2_ net-_d21-pad2_ net-_d14-pad2_ net-_d15-pad2_ net-_d7-pad2_ net-_d9-pad2_ net-_d8-pad2_ port
+.tran 0.01e-00 0.1e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/L601/L601.pro b/library/SubcircuitLibrary/L601/L601.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/L601/L601.sch b/library/SubcircuitLibrary/L601/L601.sch
new file mode 100644
index 00000000..0d7febdd
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601.sch
@@ -0,0 +1,1267 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:L601-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L eSim_NPN Q2
+U 1 1 67A0CBB7
+P 2150 1100
+F 0 "Q2" H 2050 1150 50 0000 R CNN
+F 1 "eSim_NPN" H 2100 1250 50 0000 R CNN
+F 2 "" H 2350 1200 29 0000 C CNN
+F 3 "" H 2150 1100 60 0000 C CNN
+ 1 2150 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q5
+U 1 1 67A0CBB8
+P 3000 1350
+F 0 "Q5" H 2900 1400 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 1500 50 0000 R CNN
+F 2 "" H 3200 1450 29 0000 C CNN
+F 3 "" H 3000 1350 60 0000 C CNN
+ 1 3000 1350
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R2
+U 1 1 67A0CBB9
+P 1800 1750
+F 0 "R2" H 1850 1880 50 0000 C CNN
+F 1 "7.2k" H 1850 1700 50 0000 C CNN
+F 2 "" H 1850 1730 30 0000 C CNN
+F 3 "" V 1850 1800 30 0000 C CNN
+ 1 1800 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L resistor R5
+U 1 1 67A0CBBA
+P 2550 1750
+F 0 "R5" H 2600 1880 50 0000 C CNN
+F 1 "3k" H 2600 1700 50 0000 C CNN
+F 2 "" H 2600 1730 30 0000 C CNN
+F 3 "" V 2600 1800 30 0000 C CNN
+ 1 2550 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_Diode D8
+U 1 1 67A0CBBB
+P 3700 1650
+F 0 "D8" H 3700 1750 50 0000 C CNN
+F 1 "eSim_Diode" H 3700 1550 50 0000 C CNN
+F 2 "" H 3700 1650 60 0000 C CNN
+F 3 "" H 3700 1650 60 0000 C CNN
+ 1 3700 1650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_Diode D2
+U 1 1 67A0CBBC
+P 1950 2200
+F 0 "D2" H 1950 2300 50 0000 C CNN
+F 1 "eSim_Diode" H 1950 2100 50 0000 C CNN
+F 2 "" H 1950 2200 60 0000 C CNN
+F 3 "" H 1950 2200 60 0000 C CNN
+ 1 1950 2200
+ -1 0 0 1
+$EndComp
+$Comp
+L eSim_Diode D5
+U 1 1 67A0CBBD
+P 3300 600
+F 0 "D5" H 3300 700 50 0000 C CNN
+F 1 "eSim_Diode" H 3300 500 50 0000 C CNN
+F 2 "" H 3300 600 60 0000 C CNN
+F 3 "" H 3300 600 60 0000 C CNN
+ 1 3300 600
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 2100 2200 4000 2200
+Wire Wire Line
+ 3700 2200 3700 1800
+Wire Wire Line
+ 2000 1700 2450 1700
+Wire Wire Line
+ 3100 1150 3100 600
+Wire Wire Line
+ 3100 600 3150 600
+Wire Wire Line
+ 2250 900 3900 900
+Wire Wire Line
+ 3700 1500 3700 900
+Connection ~ 3700 900
+Wire Wire Line
+ 1950 1100 950 1100
+Wire Wire Line
+ 1700 1700 1500 1700
+Wire Wire Line
+ 1500 1700 1500 1100
+Connection ~ 1500 1100
+Wire Wire Line
+ 1800 2200 1100 2200
+Wire Wire Line
+ 1100 2200 1100 1100
+Connection ~ 1100 1100
+Wire Wire Line
+ 2250 1300 2250 1350
+Wire Wire Line
+ 2250 1350 2800 1350
+Wire Wire Line
+ 3100 1550 3100 2200
+Connection ~ 3100 2200
+Wire Wire Line
+ 2750 1700 3100 1700
+Connection ~ 3100 1700
+Wire Wire Line
+ 2350 1350 2350 1700
+Connection ~ 2350 1700
+Connection ~ 2350 1350
+Wire Wire Line
+ 3450 600 3850 600
+Text GLabel 3850 600 2 60 Input ~ 0
+COM
+Connection ~ 3700 2200
+Text GLabel 4000 2200 2 60 Input ~ 0
+GND
+$Comp
+L eSim_NPN Q3
+U 1 1 67A0CBBE
+P 2150 2950
+F 0 "Q3" H 2050 3000 50 0000 R CNN
+F 1 "eSim_NPN" H 2100 3100 50 0000 R CNN
+F 2 "" H 2350 3050 29 0000 C CNN
+F 3 "" H 2150 2950 60 0000 C CNN
+ 1 2150 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L eSim_NPN Q6
+U 1 1 67A0CBBF
+P 3000 3200
+F 0 "Q6" H 2900 3250 50 0000 R CNN
+F 1 "eSim_NPN" H 2950 3350 50 0000 R CNN
+F 2 "" H 3200 3300 29 0000 C CNN
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+U 1 1 67A0CBD3
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+U 1 1 67A0CBD6
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+U 1 1 67A0CBD9
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+U 1 1 67A0CBE8
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+U 1 1 67A0CBEE
+P 6700 3100
+F 0 "D13" H 6700 3200 50 0000 C CNN
+F 1 "eSim_Diode" H 6700 3000 50 0000 C CNN
+F 2 "" H 6700 3100 60 0000 C CNN
+F 3 "" H 6700 3100 60 0000 C CNN
+ 1 6700 3100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5500 4700 7400 4700
+Wire Wire Line
+ 7100 4700 7100 4300
+Wire Wire Line
+ 5400 4200 5850 4200
+Wire Wire Line
+ 6500 3650 6500 3100
+Wire Wire Line
+ 6500 3100 6550 3100
+Wire Wire Line
+ 5650 3400 7300 3400
+Wire Wire Line
+ 7100 4000 7100 3400
+Connection ~ 7100 3400
+Wire Wire Line
+ 5350 3600 4350 3600
+Wire Wire Line
+ 5100 4200 4900 4200
+Wire Wire Line
+ 4900 4200 4900 3600
+Connection ~ 4900 3600
+Wire Wire Line
+ 5200 4700 4500 4700
+Wire Wire Line
+ 4500 4700 4500 3600
+Connection ~ 4500 3600
+Wire Wire Line
+ 5650 3800 5650 3850
+Wire Wire Line
+ 5650 3850 6200 3850
+Wire Wire Line
+ 6500 4050 6500 4700
+Connection ~ 6500 4700
+Wire Wire Line
+ 6150 4200 6500 4200
+Connection ~ 6500 4200
+Wire Wire Line
+ 5750 3850 5750 4200
+Connection ~ 5750 4200
+Connection ~ 5750 3850
+Wire Wire Line
+ 6850 3100 7250 3100
+Text GLabel 7250 3100 2 60 Input ~ 0
+COM
+Connection ~ 7100 4700
+Text GLabel 7400 4700 2 60 Input ~ 0
+GND
+Text GLabel 5200 1500 0 60 Input ~ 0
+COM
+Text GLabel 5950 1350 0 60 Input ~ 0
+GND
+Wire Wire Line
+ 5200 1500 5400 1500
+Wire Wire Line
+ 5400 1500 5400 1950
+Wire Wire Line
+ 5950 1350 6150 1350
+Wire Wire Line
+ 6150 1350 6150 1750
+$Comp
+L PORT U1
+U 3 1 67A0CBEF
+P 650 4750
+F 0 "U1" H 700 4850 30 0000 C CNN
+F 1 "PORT" H 650 4750 30 0000 C CNN
+F 2 "" H 650 4750 60 0000 C CNN
+F 3 "" H 650 4750 60 0000 C CNN
+ 3 650 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 67A0CBF0
+P 700 1100
+F 0 "U1" H 750 1200 30 0000 C CNN
+F 1 "PORT" H 700 1100 30 0000 C CNN
+F 2 "" H 700 1100 60 0000 C CNN
+F 3 "" H 700 1100 60 0000 C CNN
+ 1 700 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 67A0CBF1
+P 700 2950
+F 0 "U1" H 750 3050 30 0000 C CNN
+F 1 "PORT" H 700 2950 30 0000 C CNN
+F 2 "" H 700 2950 60 0000 C CNN
+F 3 "" H 700 2950 60 0000 C CNN
+ 2 700 2950
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 67A0CBF2
+P 4100 3600
+F 0 "U1" H 4150 3700 30 0000 C CNN
+F 1 "PORT" H 4100 3600 30 0000 C CNN
+F 2 "" H 4100 3600 60 0000 C CNN
+F 3 "" H 4100 3600 60 0000 C CNN
+ 4 4100 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 67A0CBF3
+P 4000 5600
+F 0 "U1" H 4050 5700 30 0000 C CNN
+F 1 "PORT" H 4000 5600 30 0000 C CNN
+F 2 "" H 4000 5600 60 0000 C CNN
+F 3 "" H 4000 5600 60 0000 C CNN
+ 5 4000 5600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 67A0CBF4
+P 11100 4900
+F 0 "U1" H 11150 5000 30 0000 C CNN
+F 1 "PORT" H 11100 4900 30 0000 C CNN
+F 2 "" H 11100 4900 60 0000 C CNN
+F 3 "" H 11100 4900 60 0000 C CNN
+ 11 11100 4900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 67A0CBF5
+P 10700 900
+F 0 "U1" H 10750 1000 30 0000 C CNN
+F 1 "PORT" H 10700 900 30 0000 C CNN
+F 2 "" H 10700 900 60 0000 C CNN
+F 3 "" H 10700 900 60 0000 C CNN
+ 13 10700 900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 67A0CBF6
+P 7450 5400
+F 0 "U1" H 7500 5500 30 0000 C CNN
+F 1 "PORT" H 7450 5400 30 0000 C CNN
+F 2 "" H 7450 5400 60 0000 C CNN
+F 3 "" H 7450 5400 60 0000 C CNN
+ 14 7450 5400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 67A0CBF7
+P 7300 2900
+F 0 "U1" H 7350 3000 30 0000 C CNN
+F 1 "PORT" H 7300 2900 30 0000 C CNN
+F 2 "" H 7300 2900 60 0000 C CNN
+F 3 "" H 7300 2900 60 0000 C CNN
+ 7 7300 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 67A0CBF8
+P 7250 1100
+F 0 "U1" H 7300 1200 30 0000 C CNN
+F 1 "PORT" H 7250 1100 30 0000 C CNN
+F 2 "" H 7250 1100 60 0000 C CNN
+F 3 "" H 7250 1100 60 0000 C CNN
+ 6 7250 1100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 67A0CBF9
+P 4150 2750
+F 0 "U1" H 4200 2850 30 0000 C CNN
+F 1 "PORT" H 4150 2750 30 0000 C CNN
+F 2 "" H 4150 2750 60 0000 C CNN
+F 3 "" H 4150 2750 60 0000 C CNN
+ 17 4150 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 67A0CBFA
+P 4100 4550
+F 0 "U1" H 4150 4650 30 0000 C CNN
+F 1 "PORT" H 4100 4550 30 0000 C CNN
+F 2 "" H 4100 4550 60 0000 C CNN
+F 3 "" H 4100 4550 60 0000 C CNN
+ 16 4100 4550
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 67A0CBFB
+P 7550 3400
+F 0 "U1" H 7600 3500 30 0000 C CNN
+F 1 "PORT" H 7550 3400 30 0000 C CNN
+F 2 "" H 7550 3400 60 0000 C CNN
+F 3 "" H 7550 3400 60 0000 C CNN
+ 15 7550 3400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 67A0CBFC
+P 4150 900
+F 0 "U1" H 4200 1000 30 0000 C CNN
+F 1 "PORT" H 4150 900 30 0000 C CNN
+F 2 "" H 4150 900 60 0000 C CNN
+F 3 "" H 4150 900 60 0000 C CNN
+ 18 4150 900
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 67A0CBFD
+P 10750 2700
+F 0 "U1" H 10800 2800 30 0000 C CNN
+F 1 "PORT" H 10750 2700 30 0000 C CNN
+F 2 "" H 10750 2700 60 0000 C CNN
+F 3 "" H 10750 2700 60 0000 C CNN
+ 12 10750 2700
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 67A0CBFE
+P 5400 2200
+F 0 "U1" H 5450 2300 30 0000 C CNN
+F 1 "PORT" H 5400 2200 30 0000 C CNN
+F 2 "" H 5400 2200 60 0000 C CNN
+F 3 "" H 5400 2200 60 0000 C CNN
+ 10 5400 2200
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 9 1 67A0CBFF
+P 6150 2000
+F 0 "U1" H 6200 2100 30 0000 C CNN
+F 1 "PORT" H 6150 2000 30 0000 C CNN
+F 2 "" H 6150 2000 60 0000 C CNN
+F 3 "" H 6150 2000 60 0000 C CNN
+ 9 6150 2000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 8 1 67A0CC00
+P 7650 5100
+F 0 "U1" H 7700 5200 30 0000 C CNN
+F 1 "PORT" H 7650 5100 30 0000 C CNN
+F 2 "" H 7650 5100 60 0000 C CNN
+F 3 "" H 7650 5100 60 0000 C CNN
+ 8 7650 5100
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/L601/L601.sub b/library/SubcircuitLibrary/L601/L601.sub
new file mode 100644
index 00000000..bb2bc010
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601.sub
@@ -0,0 +1,64 @@
+* Subcircuit L601
+.subckt L601 net-_d2-pad2_ net-_d3-pad2_ net-_d1-pad2_ net-_d11-pad2_ net-_d10-pad2_ net-_d16-pad2_ net-_d17-pad2_ net-_d18-pad2_ gnd com net-_d24-pad2_ net-_d23-pad2_ net-_d21-pad2_ net-_d14-pad2_ net-_d15-pad2_ net-_d7-pad2_ net-_d9-pad2_ net-_d8-pad2_
+* c:\fossee\esim\library\subcircuitlibrary\l601\l601.cir
+.include D.lib
+.include NPN.lib
+q2 net-_d8-pad2_ net-_d2-pad2_ net-_q2-pad3_ Q2N2222
+q5 net-_d5-pad1_ net-_q2-pad3_ gnd Q2N2222
+r2 net-_d2-pad2_ net-_q2-pad3_ 7.2k
+r5 net-_q2-pad3_ gnd 3k
+d8 gnd net-_d8-pad2_ 1N4148
+d2 gnd net-_d2-pad2_ 1N4148
+d5 net-_d5-pad1_ com 1N4148
+q3 net-_d9-pad2_ net-_d3-pad2_ net-_q3-pad3_ Q2N2222
+q6 net-_d6-pad1_ net-_q3-pad3_ gnd Q2N2222
+r3 net-_d3-pad2_ net-_q3-pad3_ 7.2k
+r6 net-_q3-pad3_ gnd 3k
+d9 gnd net-_d9-pad2_ 1N4148
+d3 gnd net-_d3-pad2_ 1N4148
+d6 net-_d6-pad1_ com 1N4148
+q1 net-_d7-pad2_ net-_d1-pad2_ net-_q1-pad3_ Q2N2222
+q4 net-_d4-pad1_ net-_q1-pad3_ gnd Q2N2222
+r1 net-_d1-pad2_ net-_q1-pad3_ 7.2k
+r4 net-_q1-pad3_ gnd 3k
+d7 gnd net-_d7-pad2_ 1N4148
+d1 gnd net-_d1-pad2_ 1N4148
+d4 net-_d4-pad1_ com 1N4148
+q11 net-_d21-pad2_ net-_d16-pad2_ net-_q11-pad3_ Q2N2222
+q14 net-_d19-pad1_ net-_q11-pad3_ gnd Q2N2222
+r11 net-_d16-pad2_ net-_q11-pad3_ 7.2k
+r14 net-_q11-pad3_ gnd 3k
+d21 gnd net-_d21-pad2_ 1N4148
+d16 gnd net-_d16-pad2_ 1N4148
+d19 net-_d19-pad1_ com 1N4148
+q12 net-_d23-pad2_ net-_d17-pad2_ net-_q12-pad3_ Q2N2222
+q15 net-_d20-pad1_ net-_q12-pad3_ gnd Q2N2222
+r12 net-_d17-pad2_ net-_q12-pad3_ 7.2k
+r15 net-_q12-pad3_ gnd 3k
+d23 gnd net-_d23-pad2_ 1N4148
+d17 gnd net-_d17-pad2_ 1N4148
+d20 net-_d20-pad1_ com 1N4148
+q7 net-_d14-pad2_ net-_d10-pad2_ net-_q7-pad3_ Q2N2222
+q9 net-_d12-pad1_ net-_q7-pad3_ gnd Q2N2222
+r7 net-_d10-pad2_ net-_q7-pad3_ 7.2k
+r9 net-_q7-pad3_ gnd 3k
+d14 gnd net-_d14-pad2_ 1N4148
+d10 gnd net-_d10-pad2_ 1N4148
+d12 net-_d12-pad1_ com 1N4148
+q13 net-_d24-pad2_ net-_d18-pad2_ net-_q13-pad3_ Q2N2222
+q16 net-_d22-pad1_ net-_q13-pad3_ gnd Q2N2222
+r13 net-_d18-pad2_ net-_q13-pad3_ 7.2k
+r16 net-_q13-pad3_ gnd 3k
+d24 gnd net-_d24-pad2_ 1N4148
+d18 gnd net-_d18-pad2_ 1N4148
+d22 net-_d22-pad1_ com 1N4148
+q8 net-_d15-pad2_ net-_d11-pad2_ net-_q10-pad2_ Q2N2222
+q10 net-_d13-pad1_ net-_q10-pad2_ gnd Q2N2222
+r8 net-_d11-pad2_ net-_q10-pad2_ 7.2k
+r10 net-_q10-pad2_ gnd 3k
+d15 gnd net-_d15-pad2_ 1N4148
+d11 gnd net-_d11-pad2_ 1N4148
+d13 net-_d13-pad1_ com 1N4148
+* Control Statements
+
+.ends L601 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/L601/L601_Previous_Values.xml b/library/SubcircuitLibrary/L601/L601_Previous_Values.xml
new file mode 100644
index 00000000..fb6aeca0
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/L601_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0.01</field2><field3 name="Stop Time">0.1</field3><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model /><devicemodel><q2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q2><q5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q5><d8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d8><d2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d2><d5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d5><q3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q3><q6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q6><d9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d9><d3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d3><d6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d6><q1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q1><q4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q4><d7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d7><d1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d1><d4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d4><q11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q11><q14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q14><d21><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d21><d16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d16><d19><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d19><q12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q12><q15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q15><d23><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d23><d17><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d17><d20><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d20><q7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q7><q9><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q9><d14><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d14><d10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d10><d12><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d12><q13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q13><q16><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q16><d24><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d24><d18><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d18><d22><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d22><q8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q8><q10><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.lib</field></q10><d15><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d15><d11><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d11><d13><field>C:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.lib</field></d13></devicemodel><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/L601/NPN.lib b/library/SubcircuitLibrary/L601/NPN.lib
new file mode 100644
index 00000000..be5f3073
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/NPN.lib
@@ -0,0 +1,4 @@
+.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307
++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p
++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p
++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10)
diff --git a/library/SubcircuitLibrary/L601/analysis b/library/SubcircuitLibrary/L601/analysis
new file mode 100644
index 00000000..f709edd1
--- /dev/null
+++ b/library/SubcircuitLibrary/L601/analysis
@@ -0,0 +1 @@
+.tran 0.01e-00 0.1e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-07-01 01:08:58 +0000