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-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and-cache.lib61
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and.cir13
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and.cir.out20
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and.pro43
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and.sch130
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and.sub14
-rw-r--r--library/SubcircuitLibrary/DM74LS460/3_and_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and-cache.lib79
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and-rescue.lib22
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and.cir13
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and.cir.out18
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and.pro57
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and.sch151
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and.sub12
-rw-r--r--library/SubcircuitLibrary/DM74LS460/4_and_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460-cache.lib146
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.bak166
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.cir27
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.cir.out69
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.pro73
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.sch577
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460.sub63
-rw-r--r--library/SubcircuitLibrary/DM74LS460/DM74LS460_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/DM74LS460/SUB file1
-rw-r--r--library/SubcircuitLibrary/DM74LS460/analysis1
25 files changed, 1759 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and-cache.lib b/library/SubcircuitLibrary/DM74LS460/3_and-cache.lib
new file mode 100644
index 00000000..0a3ccf7f
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and.cir b/library/SubcircuitLibrary/DM74LS460/3_and.cir
new file mode 100644
index 00000000..15f8954d
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\3_and\3_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 03/26/19 18:42:57
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U2-Pad3_ d_and
+U3 Net-_U2-Pad3_ Net-_U1-Pad3_ Net-_U1-Pad4_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and.cir.out b/library/SubcircuitLibrary/DM74LS460/3_and.cir.out
new file mode 100644
index 00000000..e3c96645
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and.cir.out
@@ -0,0 +1,20 @@
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and.pro b/library/SubcircuitLibrary/DM74LS460/3_and.pro
new file mode 100644
index 00000000..a4cdec48
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and.pro
@@ -0,0 +1,43 @@
+update=05/31/19 15:26:09
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_User
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and.sch b/library/SubcircuitLibrary/DM74LS460/3_and.sch
new file mode 100644
index 00000000..c853bf49
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and.sch
@@ -0,0 +1,130 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:3_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_and U2
+U 1 1 5C9A24D8
+P 4250 2700
+F 0 "U2" H 4250 2700 60 0000 C CNN
+F 1 "d_and" H 4300 2800 60 0000 C CNN
+F 2 "" H 4250 2700 60 0000 C CNN
+F 3 "" H 4250 2700 60 0000 C CNN
+ 1 4250 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U3
+U 1 1 5C9A2538
+P 5150 2900
+F 0 "U3" H 5150 2900 60 0000 C CNN
+F 1 "d_and" H 5200 3000 60 0000 C CNN
+F 2 "" H 5150 2900 60 0000 C CNN
+F 3 "" H 5150 2900 60 0000 C CNN
+ 1 5150 2900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5C9A259A
+P 3050 2600
+F 0 "U1" H 3100 2700 30 0000 C CNN
+F 1 "PORT" H 3050 2600 30 0000 C CNN
+F 2 "" H 3050 2600 60 0000 C CNN
+F 3 "" H 3050 2600 60 0000 C CNN
+ 1 3050 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A25D9
+P 3050 2800
+F 0 "U1" H 3100 2900 30 0000 C CNN
+F 1 "PORT" H 3050 2800 30 0000 C CNN
+F 2 "" H 3050 2800 60 0000 C CNN
+F 3 "" H 3050 2800 60 0000 C CNN
+ 2 3050 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A260A
+P 3050 3100
+F 0 "U1" H 3100 3200 30 0000 C CNN
+F 1 "PORT" H 3050 3100 30 0000 C CNN
+F 2 "" H 3050 3100 60 0000 C CNN
+F 3 "" H 3050 3100 60 0000 C CNN
+ 3 3050 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2637
+P 6900 2850
+F 0 "U1" H 6950 2950 30 0000 C CNN
+F 1 "PORT" H 6900 2850 30 0000 C CNN
+F 2 "" H 6900 2850 60 0000 C CNN
+F 3 "" H 6900 2850 60 0000 C CNN
+ 4 6900 2850
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 4700 2650 4700 2800
+Wire Wire Line
+ 5600 2850 6650 2850
+Wire Wire Line
+ 3800 2600 3300 2600
+Wire Wire Line
+ 3800 2700 3300 2700
+Wire Wire Line
+ 3300 2700 3300 2800
+Wire Wire Line
+ 3300 3100 4700 3100
+Wire Wire Line
+ 4700 3100 4700 2900
+Text Notes 3500 2600 0 60 ~ 12
+in1
+Text Notes 3450 2800 0 60 ~ 12
+in2\n
+Text Notes 3500 3100 0 60 ~ 12
+in3
+Text Notes 6100 2850 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and.sub b/library/SubcircuitLibrary/DM74LS460/3_and.sub
new file mode 100644
index 00000000..b949ae4f
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and.sub
@@ -0,0 +1,14 @@
+* Subcircuit 3_and
+.subckt 3_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_
+* c:\users\malli\esim\src\subcircuitlibrary\3_and\3_and.cir
+* u2 net-_u1-pad1_ net-_u1-pad2_ net-_u2-pad3_ d_and
+* u3 net-_u2-pad3_ net-_u1-pad3_ net-_u1-pad4_ d_and
+a1 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u2-pad3_ u2
+a2 [net-_u2-pad3_ net-_u1-pad3_ ] net-_u1-pad4_ u3
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 3_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/3_and_Previous_Values.xml b/library/SubcircuitLibrary/DM74LS460/3_and_Previous_Values.xml
new file mode 100644
index 00000000..abc5faaa
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/3_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and-cache.lib b/library/SubcircuitLibrary/DM74LS460/4_and-cache.lib
new file mode 100644
index 00000000..cb84d8f2
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and-cache.lib
@@ -0,0 +1,79 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and-rescue.lib b/library/SubcircuitLibrary/DM74LS460/4_and-rescue.lib
new file mode 100644
index 00000000..6b2c17f7
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and-rescue.lib
@@ -0,0 +1,22 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and-RESCUE-4_and
+#
+DEF 3_and-RESCUE-4_and X 0 40 Y Y 1 F N
+F0 "X" 900 300 60 H V C CNN
+F1 "3_and-RESCUE-4_and" 950 500 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 950 400 158 716 -716 0 1 0 N 1000 550 1000 250
+P 2 0 1 0 650 550 1000 550 N
+P 3 0 1 0 650 550 650 250 1000 250 N
+X in1 1 450 500 200 R 50 50 1 1 I
+X in2 2 450 400 200 R 50 50 1 1 I
+X in3 3 450 300 200 R 50 50 1 1 I
+X out 4 1300 400 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and.cir b/library/SubcircuitLibrary/DM74LS460/4_and.cir
new file mode 100644
index 00000000..35e46097
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and.cir
@@ -0,0 +1,13 @@
+* C:\Users\malli\eSim\src\SubcircuitLibrary\4_and\4_and.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 13:09:58
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U2-Pad1_ 3_and
+U2 Net-_U2-Pad1_ Net-_U1-Pad4_ Net-_U1-Pad5_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ PORT
+
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and.cir.out b/library/SubcircuitLibrary/DM74LS460/4_and.cir.out
new file mode 100644
index 00000000..6e35b18a
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and.cir.out
@@ -0,0 +1,18 @@
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ port
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and.pro b/library/SubcircuitLibrary/DM74LS460/4_and.pro
new file mode 100644
index 00000000..673ae0ac
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and.pro
@@ -0,0 +1,57 @@
+update=Wed Mar 18 19:54:24 2020
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=4_and-rescue
+LibName2=texas
+LibName3=intel
+LibName4=audio
+LibName5=interface
+LibName6=digital-audio
+LibName7=philips
+LibName8=display
+LibName9=cypress
+LibName10=siliconi
+LibName11=opto
+LibName12=atmel
+LibName13=contrib
+LibName14=valves
+LibName15=eSim_Analog
+LibName16=eSim_Devices
+LibName17=eSim_Digital
+LibName18=eSim_Hybrid
+LibName19=eSim_Miscellaneous
+LibName20=eSim_Plot
+LibName21=eSim_Power
+LibName22=eSim_Sources
+LibName23=eSim_Subckt
+LibName24=eSim_User
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and.sch b/library/SubcircuitLibrary/DM74LS460/4_and.sch
new file mode 100644
index 00000000..2d8296d4
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and.sch
@@ -0,0 +1,151 @@
+EESchema Schematic File Version 2
+LIBS:4_and-rescue
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_PSpice
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:4_and-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 3_and-RESCUE-4_and X1
+U 1 1 5C9A2915
+P 3700 3500
+F 0 "X1" H 4600 3800 60 0000 C CNN
+F 1 "3_and" H 4650 4000 60 0000 C CNN
+F 2 "" H 3700 3500 60 0000 C CNN
+F 3 "" H 3700 3500 60 0000 C CNN
+ 1 3700 3500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U2
+U 1 1 5C9A2940
+P 5450 3400
+F 0 "U2" H 5450 3400 60 0000 C CNN
+F 1 "d_and" H 5500 3500 60 0000 C CNN
+F 2 "" H 5450 3400 60 0000 C CNN
+F 3 "" H 5450 3400 60 0000 C CNN
+ 1 5450 3400
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5000 3100 5000 3300
+Wire Wire Line
+ 4150 3000 4150 2700
+Wire Wire Line
+ 4150 2700 3200 2700
+Wire Wire Line
+ 4150 3100 4000 3100
+Wire Wire Line
+ 4000 3100 4000 3000
+Wire Wire Line
+ 4000 3000 3200 3000
+Wire Wire Line
+ 4150 3200 4150 3300
+Wire Wire Line
+ 4150 3300 3250 3300
+Wire Wire Line
+ 5000 3400 5000 3550
+Wire Wire Line
+ 5000 3550 3250 3550
+Wire Wire Line
+ 5900 3350 6500 3350
+$Comp
+L PORT U1
+U 1 1 5C9A29B1
+P 2950 2700
+F 0 "U1" H 3000 2800 30 0000 C CNN
+F 1 "PORT" H 2950 2700 30 0000 C CNN
+F 2 "" H 2950 2700 60 0000 C CNN
+F 3 "" H 2950 2700 60 0000 C CNN
+ 1 2950 2700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5C9A29E9
+P 2950 3000
+F 0 "U1" H 3000 3100 30 0000 C CNN
+F 1 "PORT" H 2950 3000 30 0000 C CNN
+F 2 "" H 2950 3000 60 0000 C CNN
+F 3 "" H 2950 3000 60 0000 C CNN
+ 2 2950 3000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5C9A2A0D
+P 3000 3300
+F 0 "U1" H 3050 3400 30 0000 C CNN
+F 1 "PORT" H 3000 3300 30 0000 C CNN
+F 2 "" H 3000 3300 60 0000 C CNN
+F 3 "" H 3000 3300 60 0000 C CNN
+ 3 3000 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5C9A2A3C
+P 3000 3550
+F 0 "U1" H 3050 3650 30 0000 C CNN
+F 1 "PORT" H 3000 3550 30 0000 C CNN
+F 2 "" H 3000 3550 60 0000 C CNN
+F 3 "" H 3000 3550 60 0000 C CNN
+ 4 3000 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 5C9A2A68
+P 6750 3350
+F 0 "U1" H 6800 3450 30 0000 C CNN
+F 1 "PORT" H 6750 3350 30 0000 C CNN
+F 2 "" H 6750 3350 60 0000 C CNN
+F 3 "" H 6750 3350 60 0000 C CNN
+ 5 6750 3350
+ -1 0 0 1
+$EndComp
+Text Notes 3450 2650 0 60 ~ 12
+in1
+Text Notes 3450 2950 0 60 ~ 12
+in2
+Text Notes 3500 3300 0 60 ~ 12
+in3
+Text Notes 3500 3550 0 60 ~ 12
+in4
+Text Notes 6150 3350 0 60 ~ 12
+out
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and.sub b/library/SubcircuitLibrary/DM74LS460/4_and.sub
new file mode 100644
index 00000000..bf20b628
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and.sub
@@ -0,0 +1,12 @@
+* Subcircuit 4_and
+.subckt 4_and net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_
+* c:\users\malli\esim\src\subcircuitlibrary\4_and\4_and.cir
+.include 3_and.sub
+x1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u2-pad1_ 3_and
+* u2 net-_u2-pad1_ net-_u1-pad4_ net-_u1-pad5_ d_and
+a1 [net-_u2-pad1_ net-_u1-pad4_ ] net-_u1-pad5_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4_and \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/4_and_Previous_Values.xml b/library/SubcircuitLibrary/DM74LS460/4_and_Previous_Values.xml
new file mode 100644
index 00000000..f2ba0130
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/4_and_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source /><model><u2 name="type">d_and<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\3_and</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460-cache.lib b/library/SubcircuitLibrary/DM74LS460/DM74LS460-cache.lib
new file mode 100644
index 00000000..035b734a
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460-cache.lib
@@ -0,0 +1,146 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 3_and
+#
+DEF 3_and X 0 40 Y Y 1 F N
+F0 "X" 100 -50 60 H V C CNN
+F1 "3_and" 150 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 150 50 158 716 -716 0 1 0 N 200 200 200 -100
+P 2 0 1 0 -150 200 200 200 N
+P 3 0 1 0 -150 200 -150 -100 200 -100 N
+X in1 1 -350 150 200 R 50 50 1 1 I
+X in2 2 -350 50 200 R 50 50 1 1 I
+X in3 3 -350 -50 200 R 50 50 1 1 I
+X out 4 500 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# 4_and
+#
+DEF 4_and X 0 40 Y Y 1 F N
+F0 "X" 50 -50 60 H V C CNN
+F1 "4_and" 100 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 100 0 206 760 -760 0 1 0 N 150 200 150 -200
+P 2 0 1 0 -200 200 150 200 N
+P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N
+X in1 1 -400 150 200 R 50 50 1 1 I
+X in2 2 -400 50 200 R 50 50 1 1 I
+X in3 3 -400 -50 200 R 50 50 1 1 I
+X in4 4 -400 -150 200 R 50 50 1 1 I
+X out 5 500 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_buffer
+#
+DEF d_buffer U 0 40 Y Y 1 F N
+F0 "U" 0 -50 60 H V C CNN
+F1 "d_buffer" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+P 4 0 1 0 -300 200 -300 -200 450 0 -300 200 N
+X IN 1 -500 0 200 R 50 50 1 1 I
+X OUT 2 650 0 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_xnor
+#
+DEF d_xnor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xnor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 150 -50 -200 -50 N
+P 2 0 1 0 150 150 -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 43 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.bak b/library/SubcircuitLibrary/DM74LS460/DM74LS460.bak
new file mode 100644
index 00000000..7425f63b
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.bak
@@ -0,0 +1,166 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xnor U?
+U 1 1 681F02AA
+P 3650 1750
+F 0 "U?" H 3650 1750 60 0000 C CNN
+F 1 "d_xnor" H 3700 1850 47 0000 C CNN
+F 2 "" H 3650 1750 60 0000 C CNN
+F 3 "" H 3650 1750 60 0000 C CNN
+ 1 3650 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F02FB
+P 3650 2200
+F 0 "U?" H 3650 2200 60 0000 C CNN
+F 1 "d_xnor" H 3700 2300 47 0000 C CNN
+F 2 "" H 3650 2200 60 0000 C CNN
+F 3 "" H 3650 2200 60 0000 C CNN
+ 1 3650 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F032F
+P 3700 2750
+F 0 "U?" H 3700 2750 60 0000 C CNN
+F 1 "d_xnor" H 3750 2850 47 0000 C CNN
+F 2 "" H 3700 2750 60 0000 C CNN
+F 3 "" H 3700 2750 60 0000 C CNN
+ 1 3700 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F0335
+P 3700 3200
+F 0 "U?" H 3700 3200 60 0000 C CNN
+F 1 "d_xnor" H 3750 3300 47 0000 C CNN
+F 2 "" H 3700 3200 60 0000 C CNN
+F 3 "" H 3700 3200 60 0000 C CNN
+ 1 3700 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F03BF
+P 3650 3700
+F 0 "U?" H 3650 3700 60 0000 C CNN
+F 1 "d_xnor" H 3700 3800 47 0000 C CNN
+F 2 "" H 3650 3700 60 0000 C CNN
+F 3 "" H 3650 3700 60 0000 C CNN
+ 1 3650 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F03C5
+P 3650 4150
+F 0 "U?" H 3650 4150 60 0000 C CNN
+F 1 "d_xnor" H 3700 4250 47 0000 C CNN
+F 2 "" H 3650 4150 60 0000 C CNN
+F 3 "" H 3650 4150 60 0000 C CNN
+ 1 3650 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F03CB
+P 3700 4700
+F 0 "U?" H 3700 4700 60 0000 C CNN
+F 1 "d_xnor" H 3750 4800 47 0000 C CNN
+F 2 "" H 3700 4700 60 0000 C CNN
+F 3 "" H 3700 4700 60 0000 C CNN
+ 1 3700 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F03D1
+P 3700 5150
+F 0 "U?" H 3700 5150 60 0000 C CNN
+F 1 "d_xnor" H 3750 5250 47 0000 C CNN
+F 2 "" H 3700 5150 60 0000 C CNN
+F 3 "" H 3700 5150 60 0000 C CNN
+ 1 3700 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F051F
+P 3650 5650
+F 0 "U?" H 3650 5650 60 0000 C CNN
+F 1 "d_xnor" H 3700 5750 47 0000 C CNN
+F 2 "" H 3650 5650 60 0000 C CNN
+F 3 "" H 3650 5650 60 0000 C CNN
+ 1 3650 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U?
+U 1 1 681F0525
+P 3650 6100
+F 0 "U?" H 3650 6100 60 0000 C CNN
+F 1 "d_xnor" H 3700 6200 47 0000 C CNN
+F 2 "" H 3650 6100 60 0000 C CNN
+F 3 "" H 3650 6100 60 0000 C CNN
+ 1 3650 6100
+ 1 0 0 -1
+$EndComp
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir b/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir
new file mode 100644
index 00000000..1e368475
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir
@@ -0,0 +1,27 @@
+* C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\DM74LS460\DM74LS460.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/17/25 16:37:47
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U2 Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U2-Pad3_ d_xnor
+U3 Net-_U1-Pad22_ Net-_U1-Pad23_ Net-_U3-Pad3_ d_xnor
+U8 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U8-Pad3_ d_xnor
+U9 Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U9-Pad3_ d_xnor
+U4 Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U4-Pad3_ d_xnor
+U5 Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U5-Pad3_ d_xnor
+U10 Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U10-Pad3_ d_xnor
+U11 Net-_U1-Pad11_ Net-_U1-Pad13_ Net-_U11-Pad3_ d_xnor
+U6 Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U12-Pad1_ d_xnor
+U7 Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U12-Pad2_ d_xnor
+X1 Net-_U2-Pad3_ Net-_U3-Pad3_ Net-_U8-Pad3_ Net-_U9-Pad3_ Net-_X1-Pad5_ 4_and
+X2 Net-_U4-Pad3_ Net-_U5-Pad3_ Net-_U10-Pad3_ Net-_U11-Pad3_ Net-_X2-Pad5_ 4_and
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ Net-_U12-Pad3_ d_and
+X3 Net-_X1-Pad5_ Net-_X2-Pad5_ Net-_U12-Pad3_ Net-_U13-Pad1_ 3_and
+U14 Net-_U13-Pad1_ Net-_U1-Pad18_ d_buffer
+U13 Net-_U13-Pad1_ Net-_U1-Pad19_ d_inverter
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_U1-Pad8_ Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ ? Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_U1-Pad16_ Net-_U1-Pad17_ Net-_U1-Pad18_ Net-_U1-Pad19_ Net-_U1-Pad20_ Net-_U1-Pad21_ Net-_U1-Pad22_ Net-_U1-Pad23_ ? PORT
+
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir.out b/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir.out
new file mode 100644
index 00000000..bad12c7b
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.cir.out
@@ -0,0 +1,69 @@
+* c:\users\public\music\fossee\esim\library\subcircuitlibrary\dm74ls460\dm74ls460.cir
+
+.include 4_and.sub
+.include 3_and.sub
+* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_xnor
+* u3 net-_u1-pad22_ net-_u1-pad23_ net-_u3-pad3_ d_xnor
+* u8 net-_u1-pad1_ net-_u1-pad2_ net-_u8-pad3_ d_xnor
+* u9 net-_u1-pad3_ net-_u1-pad4_ net-_u9-pad3_ d_xnor
+* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_xnor
+* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_xnor
+* u10 net-_u1-pad9_ net-_u1-pad10_ net-_u10-pad3_ d_xnor
+* u11 net-_u1-pad11_ net-_u1-pad13_ net-_u11-pad3_ d_xnor
+* u6 net-_u1-pad14_ net-_u1-pad15_ net-_u12-pad1_ d_xnor
+* u7 net-_u1-pad16_ net-_u1-pad17_ net-_u12-pad2_ d_xnor
+x1 net-_u2-pad3_ net-_u3-pad3_ net-_u8-pad3_ net-_u9-pad3_ net-_x1-pad5_ 4_and
+x2 net-_u4-pad3_ net-_u5-pad3_ net-_u10-pad3_ net-_u11-pad3_ net-_x2-pad5_ 4_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+x3 net-_x1-pad5_ net-_x2-pad5_ net-_u12-pad3_ net-_u13-pad1_ 3_and
+* u14 net-_u13-pad1_ net-_u1-pad18_ d_buffer
+* u13 net-_u13-pad1_ net-_u1-pad19_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ? port
+a1 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u8-pad3_ u8
+a4 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u9-pad3_ u9
+a5 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4
+a6 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5
+a7 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u10-pad3_ u10
+a8 [net-_u1-pad11_ net-_u1-pad13_ ] net-_u11-pad3_ u11
+a9 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u12-pad1_ u6
+a10 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u12-pad2_ u7
+a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a12 net-_u13-pad1_ net-_u1-pad18_ u14
+a13 net-_u13-pad1_ net-_u1-pad19_ u13
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u2 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u11 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.pro b/library/SubcircuitLibrary/DM74LS460/DM74LS460.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.sch b/library/SubcircuitLibrary/DM74LS460/DM74LS460.sch
new file mode 100644
index 00000000..5a9919c1
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.sch
@@ -0,0 +1,577 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xnor U2
+U 1 1 681F02AA
+P 3650 1750
+F 0 "U2" H 3650 1750 60 0000 C CNN
+F 1 "d_xnor" H 3700 1850 47 0000 C CNN
+F 2 "" H 3650 1750 60 0000 C CNN
+F 3 "" H 3650 1750 60 0000 C CNN
+ 1 3650 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U3
+U 1 1 681F02FB
+P 3650 2200
+F 0 "U3" H 3650 2200 60 0000 C CNN
+F 1 "d_xnor" H 3700 2300 47 0000 C CNN
+F 2 "" H 3650 2200 60 0000 C CNN
+F 3 "" H 3650 2200 60 0000 C CNN
+ 1 3650 2200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U8
+U 1 1 681F032F
+P 3700 2750
+F 0 "U8" H 3700 2750 60 0000 C CNN
+F 1 "d_xnor" H 3750 2850 47 0000 C CNN
+F 2 "" H 3700 2750 60 0000 C CNN
+F 3 "" H 3700 2750 60 0000 C CNN
+ 1 3700 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U9
+U 1 1 681F0335
+P 3700 3200
+F 0 "U9" H 3700 3200 60 0000 C CNN
+F 1 "d_xnor" H 3750 3300 47 0000 C CNN
+F 2 "" H 3700 3200 60 0000 C CNN
+F 3 "" H 3700 3200 60 0000 C CNN
+ 1 3700 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U4
+U 1 1 681F03BF
+P 3650 3700
+F 0 "U4" H 3650 3700 60 0000 C CNN
+F 1 "d_xnor" H 3700 3800 47 0000 C CNN
+F 2 "" H 3650 3700 60 0000 C CNN
+F 3 "" H 3650 3700 60 0000 C CNN
+ 1 3650 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U5
+U 1 1 681F03C5
+P 3650 4150
+F 0 "U5" H 3650 4150 60 0000 C CNN
+F 1 "d_xnor" H 3700 4250 47 0000 C CNN
+F 2 "" H 3650 4150 60 0000 C CNN
+F 3 "" H 3650 4150 60 0000 C CNN
+ 1 3650 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U10
+U 1 1 681F03CB
+P 3700 4700
+F 0 "U10" H 3700 4700 60 0000 C CNN
+F 1 "d_xnor" H 3750 4800 47 0000 C CNN
+F 2 "" H 3700 4700 60 0000 C CNN
+F 3 "" H 3700 4700 60 0000 C CNN
+ 1 3700 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U11
+U 1 1 681F03D1
+P 3700 5150
+F 0 "U11" H 3700 5150 60 0000 C CNN
+F 1 "d_xnor" H 3750 5250 47 0000 C CNN
+F 2 "" H 3700 5150 60 0000 C CNN
+F 3 "" H 3700 5150 60 0000 C CNN
+ 1 3700 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U6
+U 1 1 681F051F
+P 3650 5650
+F 0 "U6" H 3650 5650 60 0000 C CNN
+F 1 "d_xnor" H 3700 5750 47 0000 C CNN
+F 2 "" H 3650 5650 60 0000 C CNN
+F 3 "" H 3650 5650 60 0000 C CNN
+ 1 3650 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_xnor U7
+U 1 1 681F0525
+P 3650 6100
+F 0 "U7" H 3650 6100 60 0000 C CNN
+F 1 "d_xnor" H 3700 6200 47 0000 C CNN
+F 2 "" H 3650 6100 60 0000 C CNN
+F 3 "" H 3650 6100 60 0000 C CNN
+ 1 3650 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X1
+U 1 1 681F0816
+P 5650 3100
+F 0 "X1" H 5700 3050 60 0000 C CNN
+F 1 "4_and" H 5750 3200 60 0000 C CNN
+F 2 "" H 5650 3100 60 0000 C CNN
+F 3 "" H 5650 3100 60 0000 C CNN
+ 1 5650 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L 4_and X2
+U 1 1 681F0881
+P 5650 4000
+F 0 "X2" H 5700 3950 60 0000 C CNN
+F 1 "4_and" H 5750 4100 60 0000 C CNN
+F 2 "" H 5650 4000 60 0000 C CNN
+F 3 "" H 5650 4000 60 0000 C CNN
+ 1 5650 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U12
+U 1 1 681F08CC
+P 5650 5000
+F 0 "U12" H 5650 5000 60 0000 C CNN
+F 1 "d_and" H 5700 5100 60 0000 C CNN
+F 2 "" H 5650 5000 60 0000 C CNN
+F 3 "" H 5650 5000 60 0000 C CNN
+ 1 5650 5000
+ 1 0 0 -1
+$EndComp
+$Comp
+L 3_and X3
+U 1 1 681F0976
+P 7350 4000
+F 0 "X3" H 7450 3950 60 0000 C CNN
+F 1 "3_and" H 7500 4150 60 0000 C CNN
+F 2 "" H 7350 4000 60 0000 C CNN
+F 3 "" H 7350 4000 60 0000 C CNN
+ 1 7350 4000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_buffer U14
+U 1 1 681F09A7
+P 9100 3850
+F 0 "U14" H 9100 3800 60 0000 C CNN
+F 1 "d_buffer" H 9100 3900 60 0000 C CNN
+F 2 "" H 9100 3850 60 0000 C CNN
+F 3 "" H 9100 3850 60 0000 C CNN
+ 1 9100 3850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U13
+U 1 1 681F09FC
+P 8900 3450
+F 0 "U13" H 8900 3350 60 0000 C CNN
+F 1 "d_inverter" H 8900 3600 60 0000 C CNN
+F 2 "" H 8950 3400 60 0000 C CNN
+F 3 "" H 8950 3400 60 0000 C CNN
+ 1 8900 3450
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4100 1700 5250 1700
+Wire Wire Line
+ 5250 1700 5250 2950
+Wire Wire Line
+ 4100 2150 5000 2150
+Wire Wire Line
+ 5000 2150 5000 3050
+Wire Wire Line
+ 5000 3050 5250 3050
+Wire Wire Line
+ 4150 2700 4800 2700
+Wire Wire Line
+ 4800 2700 4800 3150
+Wire Wire Line
+ 4800 3150 5250 3150
+Wire Wire Line
+ 4150 3150 4650 3150
+Wire Wire Line
+ 4650 3150 4650 3300
+Wire Wire Line
+ 4650 3300 5250 3300
+Wire Wire Line
+ 5250 3300 5250 3250
+Wire Wire Line
+ 4100 3650 5250 3650
+Wire Wire Line
+ 5250 3650 5250 3850
+Wire Wire Line
+ 4100 4100 4100 3950
+Wire Wire Line
+ 4100 3950 5250 3950
+Wire Wire Line
+ 4150 4650 4150 4050
+Wire Wire Line
+ 4150 4050 5250 4050
+Wire Wire Line
+ 4150 5100 4750 5100
+Wire Wire Line
+ 4750 5100 4750 4150
+Wire Wire Line
+ 4750 4150 5250 4150
+Wire Wire Line
+ 4100 5600 5050 5600
+Wire Wire Line
+ 5050 5600 5050 4900
+Wire Wire Line
+ 5050 4900 5200 4900
+Wire Wire Line
+ 4100 6050 5200 6050
+Wire Wire Line
+ 5200 6050 5200 5000
+Wire Wire Line
+ 6100 4950 7000 4950
+Wire Wire Line
+ 7000 4950 7000 4050
+Wire Wire Line
+ 6150 4000 7000 4000
+Wire Wire Line
+ 7000 4000 7000 3950
+Wire Wire Line
+ 6150 3100 7000 3100
+Wire Wire Line
+ 7000 3100 7000 3850
+Wire Wire Line
+ 8600 3950 7850 3950
+Wire Wire Line
+ 8600 3450 8600 3950
+Connection ~ 8600 3850
+$Comp
+L PORT U1
+U 20 1 681F13CD
+P 2950 1650
+F 0 "U1" H 3000 1750 30 0000 C CNN
+F 1 "PORT" H 2950 1650 30 0000 C CNN
+F 2 "" H 2950 1650 60 0000 C CNN
+F 3 "" H 2950 1650 60 0000 C CNN
+ 20 2950 1650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 681F14F6
+P 2950 4050
+F 0 "U1" H 3000 4150 30 0000 C CNN
+F 1 "PORT" H 2950 4050 30 0000 C CNN
+F 2 "" H 2950 4050 60 0000 C CNN
+F 3 "" H 2950 4050 60 0000 C CNN
+ 7 2950 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 681F153F
+P 2950 5550
+F 0 "U1" H 3000 5650 30 0000 C CNN
+F 1 "PORT" H 2950 5550 30 0000 C CNN
+F 2 "" H 2950 5550 60 0000 C CNN
+F 3 "" H 2950 5550 60 0000 C CNN
+ 14 2950 5550
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 18 1 681F1592
+P 9750 4100
+F 0 "U1" H 9800 4200 30 0000 C CNN
+F 1 "PORT" H 9750 4100 30 0000 C CNN
+F 2 "" H 9750 4100 60 0000 C CNN
+F 3 "" H 9750 4100 60 0000 C CNN
+ 18 9750 4100
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 10 1 681F15EF
+P 3000 4700
+F 0 "U1" H 3050 4800 30 0000 C CNN
+F 1 "PORT" H 3000 4700 30 0000 C CNN
+F 2 "" H 3000 4700 60 0000 C CNN
+F 3 "" H 3000 4700 60 0000 C CNN
+ 10 3000 4700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 681F1642
+P 3000 5050
+F 0 "U1" H 3050 5150 30 0000 C CNN
+F 1 "PORT" H 3000 5050 30 0000 C CNN
+F 2 "" H 3000 5050 60 0000 C CNN
+F 3 "" H 3000 5050 60 0000 C CNN
+ 11 3000 5050
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 681F17E7
+P 4800 7100
+F 0 "U1" H 4850 7200 30 0000 C CNN
+F 1 "PORT" H 4800 7100 30 0000 C CNN
+F 2 "" H 4800 7100 60 0000 C CNN
+F 3 "" H 4800 7100 60 0000 C CNN
+ 12 4800 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 22 1 681F1836
+P 2950 2100
+F 0 "U1" H 3000 2200 30 0000 C CNN
+F 1 "PORT" H 2950 2100 30 0000 C CNN
+F 2 "" H 2950 2100 60 0000 C CNN
+F 3 "" H 2950 2100 60 0000 C CNN
+ 22 2950 2100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 681F1881
+P 3000 3100
+F 0 "U1" H 3050 3200 30 0000 C CNN
+F 1 "PORT" H 3000 3100 30 0000 C CNN
+F 2 "" H 3000 3100 60 0000 C CNN
+F 3 "" H 3000 3100 60 0000 C CNN
+ 3 3000 3100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 681F18D4
+P 3000 2650
+F 0 "U1" H 3050 2750 30 0000 C CNN
+F 1 "PORT" H 3000 2650 30 0000 C CNN
+F 2 "" H 3000 2650 60 0000 C CNN
+F 3 "" H 3000 2650 60 0000 C CNN
+ 1 3000 2650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 681F1927
+P 3000 2750
+F 0 "U1" H 3050 2850 30 0000 C CNN
+F 1 "PORT" H 3000 2750 30 0000 C CNN
+F 2 "" H 3000 2750 60 0000 C CNN
+F 3 "" H 3000 2750 60 0000 C CNN
+ 2 3000 2750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 17 1 681F1978
+P 2950 6100
+F 0 "U1" H 3000 6200 30 0000 C CNN
+F 1 "PORT" H 2950 6100 30 0000 C CNN
+F 2 "" H 2950 6100 60 0000 C CNN
+F 3 "" H 2950 6100 60 0000 C CNN
+ 17 2950 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 681F1A93
+P 2950 6000
+F 0 "U1" H 3000 6100 30 0000 C CNN
+F 1 "PORT" H 2950 6000 30 0000 C CNN
+F 2 "" H 2950 6000 60 0000 C CNN
+F 3 "" H 2950 6000 60 0000 C CNN
+ 16 2950 6000
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 21 1 681F1AF0
+P 2950 1750
+F 0 "U1" H 3000 1850 30 0000 C CNN
+F 1 "PORT" H 2950 1750 30 0000 C CNN
+F 2 "" H 2950 1750 60 0000 C CNN
+F 3 "" H 2950 1750 60 0000 C CNN
+ 21 2950 1750
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 681F1B49
+P 2950 3700
+F 0 "U1" H 3000 3800 30 0000 C CNN
+F 1 "PORT" H 2950 3700 30 0000 C CNN
+F 2 "" H 2950 3700 60 0000 C CNN
+F 3 "" H 2950 3700 60 0000 C CNN
+ 6 2950 3700
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 24 1 681F1BA6
+P 3800 7100
+F 0 "U1" H 3850 7200 30 0000 C CNN
+F 1 "PORT" H 3800 7100 30 0000 C CNN
+F 2 "" H 3800 7100 60 0000 C CNN
+F 3 "" H 3800 7100 60 0000 C CNN
+ 24 3800 7100
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 681F1C5F
+P 3000 4600
+F 0 "U1" H 3050 4700 30 0000 C CNN
+F 1 "PORT" H 3000 4600 30 0000 C CNN
+F 2 "" H 3000 4600 60 0000 C CNN
+F 3 "" H 3000 4600 60 0000 C CNN
+ 9 3000 4600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 19 1 681F1CC8
+P 9500 3700
+F 0 "U1" H 9550 3800 30 0000 C CNN
+F 1 "PORT" H 9500 3700 30 0000 C CNN
+F 2 "" H 9500 3700 60 0000 C CNN
+F 3 "" H 9500 3700 60 0000 C CNN
+ 19 9500 3700
+ 0 -1 -1 0
+$EndComp
+$Comp
+L PORT U1
+U 4 1 681F1D41
+P 3000 3200
+F 0 "U1" H 3050 3300 30 0000 C CNN
+F 1 "PORT" H 3000 3200 30 0000 C CNN
+F 2 "" H 3000 3200 60 0000 C CNN
+F 3 "" H 3000 3200 60 0000 C CNN
+ 4 3000 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 681F1DB2
+P 3000 5150
+F 0 "U1" H 3050 5250 30 0000 C CNN
+F 1 "PORT" H 3000 5150 30 0000 C CNN
+F 2 "" H 3000 5150 60 0000 C CNN
+F 3 "" H 3000 5150 60 0000 C CNN
+ 13 3000 5150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 681F1E33
+P 2950 5650
+F 0 "U1" H 3000 5750 30 0000 C CNN
+F 1 "PORT" H 2950 5650 30 0000 C CNN
+F 2 "" H 2950 5650 60 0000 C CNN
+F 3 "" H 2950 5650 60 0000 C CNN
+ 15 2950 5650
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 8 1 681F1EBA
+P 2950 4150
+F 0 "U1" H 3000 4250 30 0000 C CNN
+F 1 "PORT" H 2950 4150 30 0000 C CNN
+F 2 "" H 2950 4150 60 0000 C CNN
+F 3 "" H 2950 4150 60 0000 C CNN
+ 8 2950 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 5 1 681F1F41
+P 2950 3600
+F 0 "U1" H 3000 3700 30 0000 C CNN
+F 1 "PORT" H 2950 3600 30 0000 C CNN
+F 2 "" H 2950 3600 60 0000 C CNN
+F 3 "" H 2950 3600 60 0000 C CNN
+ 5 2950 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 23 1 681F1FD6
+P 2950 2200
+F 0 "U1" H 3000 2300 30 0000 C CNN
+F 1 "PORT" H 2950 2200 30 0000 C CNN
+F 2 "" H 2950 2200 60 0000 C CNN
+F 3 "" H 2950 2200 60 0000 C CNN
+ 23 2950 2200
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 9500 3450 9200 3450
+NoConn ~ 4300 7200
+NoConn ~ 5400 7150
+Wire Wire Line
+ 4050 7100 4300 7100
+Wire Wire Line
+ 4300 7100 4300 7200
+Wire Wire Line
+ 5050 7100 5400 7100
+Wire Wire Line
+ 5400 7100 5400 7150
+$EndSCHEMATC
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460.sub b/library/SubcircuitLibrary/DM74LS460/DM74LS460.sub
new file mode 100644
index 00000000..1a3a84f3
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460.sub
@@ -0,0 +1,63 @@
+* Subcircuit DM74LS460
+.subckt DM74LS460 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ ? net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ net-_u1-pad17_ net-_u1-pad18_ net-_u1-pad19_ net-_u1-pad20_ net-_u1-pad21_ net-_u1-pad22_ net-_u1-pad23_ ?
+* c:\users\public\music\fossee\esim\library\subcircuitlibrary\dm74ls460\dm74ls460.cir
+.include 4_and.sub
+.include 3_and.sub
+* u2 net-_u1-pad20_ net-_u1-pad21_ net-_u2-pad3_ d_xnor
+* u3 net-_u1-pad22_ net-_u1-pad23_ net-_u3-pad3_ d_xnor
+* u8 net-_u1-pad1_ net-_u1-pad2_ net-_u8-pad3_ d_xnor
+* u9 net-_u1-pad3_ net-_u1-pad4_ net-_u9-pad3_ d_xnor
+* u4 net-_u1-pad5_ net-_u1-pad6_ net-_u4-pad3_ d_xnor
+* u5 net-_u1-pad7_ net-_u1-pad8_ net-_u5-pad3_ d_xnor
+* u10 net-_u1-pad9_ net-_u1-pad10_ net-_u10-pad3_ d_xnor
+* u11 net-_u1-pad11_ net-_u1-pad13_ net-_u11-pad3_ d_xnor
+* u6 net-_u1-pad14_ net-_u1-pad15_ net-_u12-pad1_ d_xnor
+* u7 net-_u1-pad16_ net-_u1-pad17_ net-_u12-pad2_ d_xnor
+x1 net-_u2-pad3_ net-_u3-pad3_ net-_u8-pad3_ net-_u9-pad3_ net-_x1-pad5_ 4_and
+x2 net-_u4-pad3_ net-_u5-pad3_ net-_u10-pad3_ net-_u11-pad3_ net-_x2-pad5_ 4_and
+* u12 net-_u12-pad1_ net-_u12-pad2_ net-_u12-pad3_ d_and
+x3 net-_x1-pad5_ net-_x2-pad5_ net-_u12-pad3_ net-_u13-pad1_ 3_and
+* u14 net-_u13-pad1_ net-_u1-pad18_ d_buffer
+* u13 net-_u13-pad1_ net-_u1-pad19_ d_inverter
+a1 [net-_u1-pad20_ net-_u1-pad21_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad22_ net-_u1-pad23_ ] net-_u3-pad3_ u3
+a3 [net-_u1-pad1_ net-_u1-pad2_ ] net-_u8-pad3_ u8
+a4 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u9-pad3_ u9
+a5 [net-_u1-pad5_ net-_u1-pad6_ ] net-_u4-pad3_ u4
+a6 [net-_u1-pad7_ net-_u1-pad8_ ] net-_u5-pad3_ u5
+a7 [net-_u1-pad9_ net-_u1-pad10_ ] net-_u10-pad3_ u10
+a8 [net-_u1-pad11_ net-_u1-pad13_ ] net-_u11-pad3_ u11
+a9 [net-_u1-pad14_ net-_u1-pad15_ ] net-_u12-pad1_ u6
+a10 [net-_u1-pad16_ net-_u1-pad17_ ] net-_u12-pad2_ u7
+a11 [net-_u12-pad1_ net-_u12-pad2_ ] net-_u12-pad3_ u12
+a12 net-_u13-pad1_ net-_u1-pad18_ u14
+a13 net-_u13-pad1_ net-_u1-pad19_ u13
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u2 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u3 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u8 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u9 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u4 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u5 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u10 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u11 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u6 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_xnor, NgSpice Name: d_xnor
+.model u7 d_xnor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_buffer, NgSpice Name: d_buffer
+.model u14 d_buffer(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Control Statements
+
+.ends DM74LS460 \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/DM74LS460_Previous_Values.xml b/library/SubcircuitLibrary/DM74LS460/DM74LS460_Previous_Values.xml
new file mode 100644
index 00000000..4be3d4fc
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/DM74LS460_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source /><model><u2 name="type">d_xnor<field1 name="Enter Rise Delay (default=1.0e-9)" /><field2 name="Enter Fall Delay (default=1.0e-9)" /><field3 name="Enter Input Load (default=1.0e-12)" /></u2><u3 name="type">d_xnor<field4 name="Enter Rise Delay (default=1.0e-9)" /><field5 name="Enter Fall Delay (default=1.0e-9)" /><field6 name="Enter Input Load (default=1.0e-12)" /></u3><u8 name="type">d_xnor<field7 name="Enter Rise Delay (default=1.0e-9)" /><field8 name="Enter Fall Delay (default=1.0e-9)" /><field9 name="Enter Input Load (default=1.0e-12)" /></u8><u9 name="type">d_xnor<field10 name="Enter Rise Delay (default=1.0e-9)" /><field11 name="Enter Fall Delay (default=1.0e-9)" /><field12 name="Enter Input Load (default=1.0e-12)" /></u9><u4 name="type">d_xnor<field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Fall Delay (default=1.0e-9)" /><field15 name="Enter Input Load (default=1.0e-12)" /></u4><u5 name="type">d_xnor<field16 name="Enter Rise Delay (default=1.0e-9)" /><field17 name="Enter Fall Delay (default=1.0e-9)" /><field18 name="Enter Input Load (default=1.0e-12)" /></u5><u10 name="type">d_xnor<field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /><field21 name="Enter Input Load (default=1.0e-12)" /></u10><u11 name="type">d_xnor<field22 name="Enter Rise Delay (default=1.0e-9)" /><field23 name="Enter Fall Delay (default=1.0e-9)" /><field24 name="Enter Input Load (default=1.0e-12)" /></u11><u6 name="type">d_xnor<field25 name="Enter Rise Delay (default=1.0e-9)" /><field26 name="Enter Fall Delay (default=1.0e-9)" /><field27 name="Enter Input Load (default=1.0e-12)" /></u6><u7 name="type">d_xnor<field28 name="Enter Rise Delay (default=1.0e-9)" /><field29 name="Enter Fall Delay (default=1.0e-9)" /><field30 name="Enter Input Load (default=1.0e-12)" /></u7><u12 name="type">d_and<field31 name="Enter Rise Delay (default=1.0e-9)" /><field32 name="Enter Fall Delay (default=1.0e-9)" /><field33 name="Enter Input Load (default=1.0e-12)" /></u12><u14 name="type">d_buffer<field34 name="Enter Rise Delay (default=1.0e-9)" /><field35 name="Enter Fall Delay (default=1.0e-9)" /><field36 name="Enter Input Load (default=1.0e-12)" /></u14><u13 name="type">d_inverter<field37 name="Enter Rise Delay (default=1.0e-9)" /><field38 name="Enter Fall Delay (default=1.0e-9)" /><field39 name="Enter Input Load (default=1.0e-12)" /></u13></model><devicemodel /><subcircuit><x1><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x1><x2><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\4_and</field></x2><x3><field>C:\Users\Public\Music\FOSSEE\eSim\library\SubcircuitLibrary\3_and</field></x3></subcircuit></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/DM74LS460/SUB file b/library/SubcircuitLibrary/DM74LS460/SUB file
new file mode 100644
index 00000000..8b137891
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/SUB file
@@ -0,0 +1 @@
+
diff --git a/library/SubcircuitLibrary/DM74LS460/analysis b/library/SubcircuitLibrary/DM74LS460/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/DM74LS460/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file