diff options
Diffstat (limited to 'library/SubcircuitLibrary/DM74184/DM74184.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/DM74184/DM74184.cir.out | 91 |
1 files changed, 91 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/DM74184/DM74184.cir.out b/library/SubcircuitLibrary/DM74184/DM74184.cir.out new file mode 100644 index 00000000..e86da212 --- /dev/null +++ b/library/SubcircuitLibrary/DM74184/DM74184.cir.out @@ -0,0 +1,91 @@ +* c:\users\hp\onedrive\documents\fossee\esim\library\subcircuitlibrary\dm74184\dm74184.cir + +.include 4_OR.sub +.include 3_and.sub +* u3 /y6 net-_u3-pad2_ d_inverter +* u4 /y5 net-_u4-pad2_ d_inverter +* u5 /y3 net-_u5-pad2_ d_inverter +* u6 /y2 net-_u6-pad2_ d_inverter +* u2 /y1 /y1 /a d_or +* u1 /y6 /y5 /y4 /y3 /y2 /y1 ? ? ? /a /b /c /d /e port +x1 /y6 net-_u4-pad2_ /y2 net-_x1-pad4_ 3_and +x2 net-_u3-pad2_ net-_u4-pad2_ /y2 net-_x2-pad4_ 3_and +x4 net-_u3-pad2_ /y5 net-_u6-pad2_ net-_x3-pad3_ 3_and +* u7 /y6 /y5 net-_u7-pad3_ d_and +x3 net-_x1-pad4_ net-_x2-pad4_ net-_x3-pad3_ net-_u7-pad3_ /b 4_OR +x5 /y6 net-_u4-pad2_ net-_u5-pad2_ net-_x5-pad4_ 3_and +x7 net-_u3-pad2_ net-_u4-pad2_ /y3 net-_x6-pad2_ 3_and +* u8 /y3 /y2 net-_u8-pad3_ d_xor +x8 net-_u8-pad3_ /y5 net-_u3-pad2_ net-_x6-pad3_ 3_and +* u9 /y5 /y6 net-_u9-pad3_ d_and +x6 net-_x5-pad4_ net-_x6-pad2_ net-_x6-pad3_ net-_u9-pad3_ /c 4_OR +* u10 /y5 /y6 net-_u10-pad3_ d_and +* u11 /y4 /y3 net-_u11-pad3_ d_xor +x9 net-_u11-pad3_ net-_u4-pad2_ /y6 net-_x10-pad2_ 3_and +x11 net-_u3-pad2_ net-_u4-pad2_ /y4 net-_x10-pad3_ 3_and +* u12 /y2 /y3 net-_u12-pad3_ d_and +* u14 net-_u12-pad3_ /y4 net-_u13-pad1_ d_xor +x12 net-_u13-pad2_ /y5 net-_u3-pad2_ net-_x10-pad4_ 3_and +* u13 net-_u13-pad1_ net-_u13-pad2_ d_inverter +x10 net-_u10-pad3_ net-_x10-pad2_ net-_x10-pad3_ net-_x10-pad4_ /d 4_OR +* u15 /y2 /y3 net-_u15-pad3_ d_and +* u16 net-_u15-pad3_ /y4 net-_u16-pad3_ d_or +* u17 net-_u17-pad1_ /y6 /e d_or +x13 net-_u16-pad3_ /y5 net-_u3-pad2_ net-_u17-pad1_ 3_and +a1 /y6 net-_u3-pad2_ u3 +a2 /y5 net-_u4-pad2_ u4 +a3 /y3 net-_u5-pad2_ u5 +a4 /y2 net-_u6-pad2_ u6 +a5 [/y1 /y1 ] /a u2 +a6 [/y6 /y5 ] net-_u7-pad3_ u7 +a7 [/y3 /y2 ] net-_u8-pad3_ u8 +a8 [/y5 /y6 ] net-_u9-pad3_ u9 +a9 [/y5 /y6 ] net-_u10-pad3_ u10 +a10 [/y4 /y3 ] net-_u11-pad3_ u11 +a11 [/y2 /y3 ] net-_u12-pad3_ u12 +a12 [net-_u12-pad3_ /y4 ] net-_u13-pad1_ u14 +a13 net-_u13-pad1_ net-_u13-pad2_ u13 +a14 [/y2 /y3 ] net-_u15-pad3_ u15 +a15 [net-_u15-pad3_ /y4 ] net-_u16-pad3_ u16 +a16 [net-_u17-pad1_ /y6 ] /e u17 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u2 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u8 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u11 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u12 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_xor, NgSpice Name: d_xor +.model u14 d_xor(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u13 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u15 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u16 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u17 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |