diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4028_B')
25 files changed, 2215 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib b/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir new file mode 100644 index 00000000..17b9331f --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate\AND_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 14:03:16 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_N +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M3-Pad3_ Net-_M3-Pad3_ eSim_MOS_N +M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_P +U1 Net-_M5-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M3-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out new file mode 100644 index 00000000..bea80ad4 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\and_gate\and_gate.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +* u1 net-_m5-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m3-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro b/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch new file mode 100644 index 00000000..5f7950b3 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sch @@ -0,0 +1,250 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:AND_Gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M1 +U 1 1 62B6B95F +P 4550 1800 +F 0 "M1" H 4500 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 4600 1950 50 0000 R CNN +F 2 "" H 4800 1900 29 0000 C CNN +F 3 "" H 4600 1800 60 0000 C CNN + 1 4550 1800 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62B6B9AC +P 4700 2250 +F 0 "M2" H 4700 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 4800 2200 50 0000 R CNN +F 2 "" H 5000 1950 29 0000 C CNN +F 3 "" H 4800 2050 60 0000 C CNN + 1 4700 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M4 +U 1 1 62B6B9ED +P 5250 1800 +F 0 "M4" H 5200 1850 50 0000 R CNN +F 1 "eSim_MOS_P" H 5300 1950 50 0000 R CNN +F 2 "" H 5500 1900 29 0000 C CNN +F 3 "" H 5300 1800 60 0000 C CNN + 1 5250 1800 + -1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 62B6BA57 +P 4700 2750 +F 0 "M3" H 4700 2600 50 0000 R CNN +F 1 "eSim_MOS_N" H 4800 2700 50 0000 R CNN +F 2 "" H 5000 2450 29 0000 C CNN +F 3 "" H 4800 2550 60 0000 C CNN + 1 4700 2750 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4700 1600 6000 1600 +Wire Wire Line + 5000 1650 5000 1600 +Connection ~ 5000 1600 +Wire Wire Line + 4800 1650 4800 1600 +Connection ~ 4800 1600 +Wire Wire Line + 4700 2000 5100 2000 +Wire Wire Line + 4900 2250 4900 2000 +Connection ~ 4900 2000 +Wire Wire Line + 4900 2650 4900 2750 +Wire Wire Line + 5000 2600 5000 2700 +Wire Wire Line + 5000 2700 4900 2700 +Connection ~ 4900 2700 +Wire Wire Line + 5000 3400 5000 3100 +Wire Wire Line + 4900 3150 6000 3150 +Wire Wire Line + 4900 2150 5650 2150 +Connection ~ 4900 2150 +$Comp +L eSim_MOS_N M5 +U 1 1 62B6BB39 +P 5750 2250 +F 0 "M5" H 5750 2100 50 0000 R CNN +F 1 "eSim_MOS_N" H 5850 2200 50 0000 R CNN +F 2 "" H 6050 1950 29 0000 C CNN +F 3 "" H 5850 2050 60 0000 C CNN + 1 5750 2250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62B6BB82 +P 5800 1900 +F 0 "M6" H 5750 1950 50 0000 R CNN +F 1 "eSim_MOS_P" H 5850 2050 50 0000 R CNN +F 2 "" H 6050 2000 29 0000 C CNN +F 3 "" H 5850 1900 60 0000 C CNN + 1 5800 1900 + 1 0 0 1 +$EndComp +Wire Wire Line + 5950 1700 6050 1700 +Wire Wire Line + 6050 1700 6050 1750 +Wire Wire Line + 6050 2600 6050 2650 +Wire Wire Line + 6050 2650 5950 2650 +Wire Wire Line + 5950 2100 5950 2250 +Wire Wire Line + 5650 1900 5650 2450 +Connection ~ 5650 2150 +Wire Wire Line + 5950 2150 6300 2150 +Connection ~ 5950 2150 +Wire Wire Line + 6000 1600 6000 1700 +Connection ~ 5100 1600 +Connection ~ 6000 1700 +Wire Wire Line + 6000 3150 6000 2650 +Connection ~ 5000 3150 +Connection ~ 6000 2650 +Wire Wire Line + 4400 1800 4400 2450 +Wire Wire Line + 4400 2450 4600 2450 +Wire Wire Line + 5400 1800 5400 2800 +Wire Wire Line + 5400 2800 4600 2800 +Wire Wire Line + 4600 2800 4600 2950 +Wire Wire Line + 4400 2100 3950 2100 +Connection ~ 4400 2100 +Wire Wire Line + 4600 2850 3950 2850 +Connection ~ 4600 2850 +$Comp +L PORT U1 +U 3 1 62B6BDF0 +P 3700 2850 +F 0 "U1" H 3750 2950 30 0000 C CNN +F 1 "PORT" H 3700 2850 30 0000 C CNN +F 2 "" H 3700 2850 60 0000 C CNN +F 3 "" H 3700 2850 60 0000 C CNN + 3 3700 2850 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B6BE6B +P 6550 2150 +F 0 "U1" H 6600 2250 30 0000 C CNN +F 1 "PORT" H 6550 2150 30 0000 C CNN +F 2 "" H 6550 2150 60 0000 C CNN +F 3 "" H 6550 2150 60 0000 C CNN + 1 6550 2150 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62B6BEC8 +P 3700 2100 +F 0 "U1" H 3750 2200 30 0000 C CNN +F 1 "PORT" H 3700 2100 30 0000 C CNN +F 2 "" H 3700 2100 60 0000 C CNN +F 3 "" H 3700 2100 60 0000 C CNN + 2 3700 2100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B6BF63 +P 3750 1300 +F 0 "U1" H 3800 1400 30 0000 C CNN +F 1 "PORT" H 3750 1300 30 0000 C CNN +F 2 "" H 3750 1300 60 0000 C CNN +F 3 "" H 3750 1300 60 0000 C CNN + 4 3750 1300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62B6BF90 +P 3800 3400 +F 0 "U1" H 3850 3500 30 0000 C CNN +F 1 "PORT" H 3800 3400 30 0000 C CNN +F 2 "" H 3800 3400 60 0000 C CNN +F 3 "" H 3800 3400 60 0000 C CNN + 5 3800 3400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4000 1300 4900 1300 +Wire Wire Line + 4900 1300 4900 1600 +Connection ~ 4900 1600 +Wire Wire Line + 4050 3400 5000 3400 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub new file mode 100644 index 00000000..ad6e1a1e --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate.sub @@ -0,0 +1,14 @@ +* Subcircuit AND_Gate +.subckt AND_Gate net-_m5-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m3-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\and_gate\and_gate.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m3-pad3_ net-_m3-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +* Control Statements + +.ends AND_Gate
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml new file mode 100644 index 00000000..eabe321b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/AND_Gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m4><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib b/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib new file mode 100644 index 00000000..972525a2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# AND_gate +# +DEF AND_gate X 0 40 Y Y 1 F N +F0 "X" 150 50 60 H V C CNN +F1 "AND_gate" 150 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 300 -25 202 603 -603 0 1 0 N 400 150 400 -200 +P 4 0 1 0 400 150 -300 150 -300 -200 400 -200 N +X OUT 1 700 -50 200 L 50 50 1 1 O +X A 2 -500 100 200 R 50 50 1 1 I +X B 3 -500 -100 200 R 50 50 1 1 I +X VDD 4 -50 350 200 D 50 50 1 1 I +X GND 5 -150 -400 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# NOR +# +DEF NOR X 0 40 Y Y 1 F N +F0 "X" 100 100 60 H V C CNN +F1 "NOR" 150 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 50 0 1 0 N +P 6 0 1 0 -250 150 250 150 350 0 250 -150 -250 -150 -250 150 N +X OUT 1 650 0 200 L 50 50 1 1 O +X A 2 -450 100 200 R 50 50 1 1 I +X B 3 -450 -100 200 R 50 50 1 1 I +X VDD 4 -100 350 200 D 50 50 1 1 I +X GND 5 0 -350 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir new file mode 100644 index 00000000..530338ba --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir @@ -0,0 +1,36 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CD4028_B\CD4028_B.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 16:06:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X5 Net-_X12-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X6 Net-_X13-Pad2_ Net-_M4-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X7 Net-_X10-Pad2_ Net-_M4-Pad2_ Net-_M1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X2 Net-_X11-Pad2_ Net-_M4-Pad1_ Net-_M1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X1 Net-_X1-Pad1_ Net-_M2-Pad2_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X3 Net-_X12-Pad3_ Net-_M2-Pad1_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X4 Net-_X16-Pad3_ Net-_M2-Pad2_ Net-_M3-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ NOR +X8 Net-_U1-Pad3_ Net-_X12-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X9 Net-_U1-Pad14_ Net-_X13-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X10 Net-_U1-Pad2_ Net-_X10-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X11 Net-_U1-Pad15_ Net-_X11-Pad2_ Net-_X1-Pad1_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X12 Net-_U1-Pad1_ Net-_X12-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X13 Net-_U1-Pad6_ Net-_X13-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X14 Net-_U1-Pad7_ Net-_X10-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X15 Net-_U1-Pad4_ Net-_X11-Pad2_ Net-_X12-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X16 Net-_U1-Pad9_ Net-_X12-Pad2_ Net-_X16-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +X17 Net-_U1-Pad5_ Net-_X13-Pad2_ Net-_X16-Pad3_ Net-_M5-Pad3_ Net-_M1-Pad3_ AND_gate +M8 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M4 Net-_M4-Pad1_ Net-_M4-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M5 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M6 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M2 Net-_M2-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M7 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M5-Pad3_ Net-_M5-Pad3_ eSim_MOS_P +M3 Net-_M3-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ Net-_M1-Pad3_ Net-_U1-Pad9_ Net-_M4-Pad2_ Net-_M3-Pad2_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_U1-Pad14_ Net-_U1-Pad15_ Net-_M5-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out new file mode 100644 index 00000000..69859b03 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.cir.out @@ -0,0 +1,41 @@ +* c:\fossee\esim\library\subcircuitlibrary\cd4028_b\cd4028_b.cir + +.include AND_Gate.sub +.include NOR_Gate.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x5 net-_x12-pad2_ net-_m4-pad2_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x6 net-_x13-pad2_ net-_m4-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x7 net-_x10-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x2 net-_x11-pad2_ net-_m4-pad1_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x1 net-_x1-pad1_ net-_m2-pad2_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x3 net-_x12-pad3_ net-_m2-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x4 net-_x16-pad3_ net-_m2-pad2_ net-_m3-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x8 net-_u1-pad3_ net-_x12-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x9 net-_u1-pad14_ net-_x13-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x10 net-_u1-pad2_ net-_x10-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x11 net-_u1-pad15_ net-_x11-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x12 net-_u1-pad1_ net-_x12-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x13 net-_u1-pad6_ net-_x13-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x14 net-_u1-pad7_ net-_x10-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x15 net-_u1-pad4_ net-_x11-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x16 net-_u1-pad9_ net-_x12-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x17 net-_u1-pad5_ net-_x13-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_m4-pad2_ net-_m3-pad2_ net-_m2-pad2_ net-_m1-pad2_ net-_u1-pad14_ net-_u1-pad15_ net-_m5-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro b/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch new file mode 100644 index 00000000..bf06b0df --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sch @@ -0,0 +1,942 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD4028_B-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L NOR X5 +U 1 1 62B82191 +P 2900 1500 +F 0 "X5" H 3000 1600 60 0000 C CNN +F 1 "NOR" H 3050 1450 60 0000 C CNN +F 2 "" H 2900 1500 60 0001 C CNN +F 3 "" H 2900 1500 60 0001 C CNN + 1 2900 1500 + 1 0 0 -1 +$EndComp +$Comp +L NOR X6 +U 1 1 62B821F6 +P 2900 2400 +F 0 "X6" H 3000 2500 60 0000 C CNN +F 1 "NOR" H 3050 2350 60 0000 C CNN +F 2 "" H 2900 2400 60 0001 C CNN +F 3 "" H 2900 2400 60 0001 C CNN + 1 2900 2400 + 1 0 0 -1 +$EndComp +$Comp +L NOR X7 +U 1 1 62B82225 +P 2900 3250 +F 0 "X7" H 3000 3350 60 0000 C CNN +F 1 "NOR" H 3050 3200 60 0000 C CNN +F 2 "" H 2900 3250 60 0001 C CNN +F 3 "" H 2900 3250 60 0001 C CNN + 1 2900 3250 + 1 0 0 -1 +$EndComp +$Comp +L NOR X2 +U 1 1 62B8225C +P 2850 4050 +F 0 "X2" H 2950 4150 60 0000 C CNN +F 1 "NOR" H 3000 4000 60 0000 C CNN +F 2 "" H 2850 4050 60 0001 C CNN +F 3 "" H 2850 4050 60 0001 C CNN + 1 2850 4050 + 1 0 0 -1 +$EndComp +$Comp +L NOR X1 +U 1 1 62B822A5 +P 2800 4950 +F 0 "X1" H 2900 5050 60 0000 C CNN +F 1 "NOR" H 2950 4900 60 0000 C CNN +F 2 "" H 2800 4950 60 0001 C CNN +F 3 "" H 2800 4950 60 0001 C CNN + 1 2800 4950 + 1 0 0 -1 +$EndComp +$Comp +L NOR X3 +U 1 1 62B8239B +P 2850 5850 +F 0 "X3" H 2950 5950 60 0000 C CNN +F 1 "NOR" H 3000 5800 60 0000 C CNN +F 2 "" H 2850 5850 60 0001 C CNN +F 3 "" H 2850 5850 60 0001 C CNN + 1 2850 5850 + 1 0 0 -1 +$EndComp +$Comp +L NOR X4 +U 1 1 62B82472 +P 2850 6650 +F 0 "X4" H 2950 6750 60 0000 C CNN +F 1 "NOR" H 3000 6600 60 0000 C CNN +F 2 "" H 2850 6650 60 0001 C CNN +F 3 "" H 2850 6650 60 0001 C CNN + 1 2850 6650 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X8 +U 1 1 62B829B4 +P 4950 1050 +F 0 "X8" H 5100 1100 60 0000 C CNN +F 1 "AND_gate" H 5100 950 60 0000 C CNN +F 2 "" H 4950 1050 60 0001 C CNN +F 3 "" H 4950 1050 60 0001 C CNN + 1 4950 1050 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X9 +U 1 1 62B82D5D +P 4950 1900 +F 0 "X9" H 5100 1950 60 0000 C CNN +F 1 "AND_gate" H 5100 1800 60 0000 C CNN +F 2 "" H 4950 1900 60 0001 C CNN +F 3 "" H 4950 1900 60 0001 C CNN + 1 4950 1900 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X10 +U 1 1 62B82D9A +P 4950 2650 +F 0 "X10" H 5100 2700 60 0000 C CNN +F 1 "AND_gate" H 5100 2550 60 0000 C CNN +F 2 "" H 4950 2650 60 0001 C CNN +F 3 "" H 4950 2650 60 0001 C CNN + 1 4950 2650 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X11 +U 1 1 62B82DFB +P 4950 3450 +F 0 "X11" H 5100 3500 60 0000 C CNN +F 1 "AND_gate" H 5100 3350 60 0000 C CNN +F 2 "" H 4950 3450 60 0001 C CNN +F 3 "" H 4950 3450 60 0001 C CNN + 1 4950 3450 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X12 +U 1 1 62B82E50 +P 4950 4200 +F 0 "X12" H 5100 4250 60 0000 C CNN +F 1 "AND_gate" H 5100 4100 60 0000 C CNN +F 2 "" H 4950 4200 60 0001 C CNN +F 3 "" H 4950 4200 60 0001 C CNN + 1 4950 4200 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X13 +U 1 1 62B82FFD +P 4950 5000 +F 0 "X13" H 5100 5050 60 0000 C CNN +F 1 "AND_gate" H 5100 4900 60 0000 C CNN +F 2 "" H 4950 5000 60 0001 C CNN +F 3 "" H 4950 5000 60 0001 C CNN + 1 4950 5000 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X14 +U 1 1 62B83048 +P 4950 5750 +F 0 "X14" H 5100 5800 60 0000 C CNN +F 1 "AND_gate" H 5100 5650 60 0000 C CNN +F 2 "" H 4950 5750 60 0001 C CNN +F 3 "" H 4950 5750 60 0001 C CNN + 1 4950 5750 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X15 +U 1 1 62B83307 +P 4950 6550 +F 0 "X15" H 5100 6600 60 0000 C CNN +F 1 "AND_gate" H 5100 6450 60 0000 C CNN +F 2 "" H 4950 6550 60 0001 C CNN +F 3 "" H 4950 6550 60 0001 C CNN + 1 4950 6550 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X16 +U 1 1 62B83368 +P 7600 5150 +F 0 "X16" H 7750 5200 60 0000 C CNN +F 1 "AND_gate" H 7750 5050 60 0000 C CNN +F 2 "" H 7600 5150 60 0001 C CNN +F 3 "" H 7600 5150 60 0001 C CNN + 1 7600 5150 + 1 0 0 -1 +$EndComp +$Comp +L AND_gate X17 +U 1 1 62B83411 +P 7600 5950 +F 0 "X17" H 7750 6000 60 0000 C CNN +F 1 "AND_gate" H 7750 5850 60 0000 C CNN +F 2 "" H 7600 5950 60 0001 C CNN +F 3 "" H 7600 5950 60 0001 C CNN + 1 7600 5950 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M8 +U 1 1 62B84DD0 +P 1500 1650 +F 0 "M8" H 1450 1700 50 0000 R CNN +F 1 "eSim_MOS_P" H 1550 1800 50 0000 R CNN +F 2 "" H 1750 1750 29 0000 C CNN +F 3 "" H 1550 1650 60 0000 C CNN + 1 1500 1650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 62B84E21 +P 1450 2000 +F 0 "M4" H 1450 1850 50 0000 R CNN +F 1 "eSim_MOS_N" H 1550 1950 50 0000 R CNN +F 2 "" H 1750 1700 29 0000 C CNN +F 3 "" H 1550 1800 60 0000 C CNN + 1 1450 2000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M5 +U 1 1 62B853D4 +P 1450 3200 +F 0 "M5" H 1400 3250 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 3350 50 0000 R CNN +F 2 "" H 1700 3300 29 0000 C CNN +F 3 "" H 1500 3200 60 0000 C CNN + 1 1450 3200 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62B853DA +P 1400 3550 +F 0 "M1" H 1400 3400 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 3500 50 0000 R CNN +F 2 "" H 1700 3250 29 0000 C CNN +F 3 "" H 1500 3350 60 0000 C CNN + 1 1400 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M6 +U 1 1 62B8576A +P 1450 4650 +F 0 "M6" H 1400 4700 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 4800 50 0000 R CNN +F 2 "" H 1700 4750 29 0000 C CNN +F 3 "" H 1500 4650 60 0000 C CNN + 1 1450 4650 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M2 +U 1 1 62B85770 +P 1400 5000 +F 0 "M2" H 1400 4850 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 4950 50 0000 R CNN +F 2 "" H 1700 4700 29 0000 C CNN +F 3 "" H 1500 4800 60 0000 C CNN + 1 1400 5000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M7 +U 1 1 62B857E4 +P 1450 6000 +F 0 "M7" H 1400 6050 50 0000 R CNN +F 1 "eSim_MOS_P" H 1500 6150 50 0000 R CNN +F 2 "" H 1700 6100 29 0000 C CNN +F 3 "" H 1500 6000 60 0000 C CNN + 1 1450 6000 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M3 +U 1 1 62B857EA +P 1400 6350 +F 0 "M3" H 1400 6200 50 0000 R CNN +F 1 "eSim_MOS_N" H 1500 6300 50 0000 R CNN +F 2 "" H 1700 6050 29 0000 C CNN +F 3 "" H 1500 6150 60 0000 C CNN + 1 1400 6350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 1650 1350 2200 +Wire Wire Line + 1650 1450 1750 1450 +Wire Wire Line + 1750 1450 1750 1500 +Wire Wire Line + 1750 2350 1750 2400 +Wire Wire Line + 1650 2400 1800 2400 +Wire Wire Line + 1650 1850 1650 2000 +Wire Wire Line + 1300 3200 1300 3750 +Wire Wire Line + 1600 3000 1900 3000 +Wire Wire Line + 1700 3000 1700 3050 +Wire Wire Line + 1700 3900 1700 3950 +Wire Wire Line + 1600 3950 1800 3950 +Wire Wire Line + 1600 3400 1600 3550 +Wire Wire Line + 1300 4650 1300 5200 +Wire Wire Line + 1600 4450 1700 4450 +Wire Wire Line + 1700 4450 1700 4500 +Wire Wire Line + 1700 5350 1700 5400 +Wire Wire Line + 1600 5400 1800 5400 +Wire Wire Line + 1600 4850 1600 5000 +Wire Wire Line + 1300 6000 1300 6550 +Wire Wire Line + 1600 5800 1700 5800 +Wire Wire Line + 1700 5800 1700 5850 +Wire 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7150 2700 60 0000 C CNN +F 3 "" H 7150 2700 60 0000 C CNN + 2 7150 2700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B8A7E0 +P 7150 4250 +F 0 "U1" H 7200 4350 30 0000 C CNN +F 1 "PORT" H 7150 4250 30 0000 C CNN +F 2 "" H 7150 4250 60 0000 C CNN +F 3 "" H 7150 4250 60 0000 C CNN + 1 7150 4250 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62B8AE80 +P 7150 1100 +F 0 "U1" H 7200 1200 30 0000 C CNN +F 1 "PORT" H 7150 1100 30 0000 C CNN +F 2 "" H 7150 1100 60 0000 C CNN +F 3 "" H 7150 1100 60 0000 C CNN + 3 7150 1100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B8AFD9 +P 9150 4750 +F 0 "U1" H 9200 4850 30 0000 C CNN +F 1 "PORT" H 9150 4750 30 0000 C CNN +F 2 "" H 9150 4750 60 0000 C CNN +F 3 "" H 9150 4750 60 0000 C CNN + 4 9150 4750 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 62B8B2B9 +P 9200 6000 +F 0 "U1" H 9250 6100 30 0000 C CNN +F 1 "PORT" H 9200 6000 30 0000 C CNN +F 2 "" H 9200 6000 60 0000 C CNN +F 3 "" H 9200 6000 60 0000 C CNN + 5 9200 6000 + -1 0 0 -1 +$EndComp +$Comp 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0000 C CNN +F 2 "" H 800 1900 60 0000 C CNN +F 3 "" H 800 1900 60 0000 C CNN + 10 800 1900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 11 1 62B8CC31 +P 900 6300 +F 0 "U1" H 950 6400 30 0000 C CNN +F 1 "PORT" H 900 6300 30 0000 C CNN +F 2 "" H 900 6300 60 0000 C CNN +F 3 "" H 900 6300 60 0000 C CNN + 11 900 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 62B8CCFC +P 850 4900 +F 0 "U1" H 900 5000 30 0000 C CNN +F 1 "PORT" H 850 4900 30 0000 C CNN +F 2 "" H 850 4900 60 0000 C CNN +F 3 "" H 850 4900 60 0000 C CNN + 12 850 4900 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 13 1 62B8CDE1 +P 850 3450 +F 0 "U1" H 900 3550 30 0000 C CNN +F 1 "PORT" H 850 3450 30 0000 C CNN +F 2 "" H 850 3450 60 0000 C CNN +F 3 "" H 850 3450 60 0000 C CNN + 13 850 3450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 14 1 62B8D384 +P 7150 1950 +F 0 "U1" H 7200 2050 30 0000 C CNN +F 1 "PORT" H 7150 1950 30 0000 C CNN +F 2 "" H 7150 1950 60 0000 C CNN +F 3 "" H 7150 1950 60 0000 C CNN + 14 7150 1950 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 15 1 62B8D53F +P 7150 3500 +F 0 "U1" H 7200 3600 30 0000 C CNN +F 1 "PORT" H 7150 3500 30 0000 C CNN +F 2 "" H 7150 3500 60 0000 C CNN +F 3 "" H 7150 3500 60 0000 C CNN + 15 7150 3500 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 16 1 62B8D8EA +P 850 700 +F 0 "U1" H 900 800 30 0000 C CNN +F 1 "PORT" H 850 700 30 0000 C CNN +F 2 "" H 850 700 60 0000 C CNN +F 3 "" H 850 700 60 0000 C CNN + 16 850 700 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub new file mode 100644 index 00000000..f43f7ea9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B.sub @@ -0,0 +1,35 @@ +* Subcircuit CD4028_B +.subckt CD4028_B net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_m1-pad3_ net-_u1-pad9_ net-_m4-pad2_ net-_m3-pad2_ net-_m2-pad2_ net-_m1-pad2_ net-_u1-pad14_ net-_u1-pad15_ net-_m5-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cd4028_b\cd4028_b.cir +.include AND_Gate.sub +.include NOR_Gate.sub +.include NMOS-180nm.lib +.include PMOS-180nm.lib +x5 net-_x12-pad2_ net-_m4-pad2_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x6 net-_x13-pad2_ net-_m4-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x7 net-_x10-pad2_ net-_m4-pad2_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x2 net-_x11-pad2_ net-_m4-pad1_ net-_m1-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x1 net-_x1-pad1_ net-_m2-pad2_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x3 net-_x12-pad3_ net-_m2-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x4 net-_x16-pad3_ net-_m2-pad2_ net-_m3-pad1_ net-_m5-pad3_ net-_m1-pad3_ NOR_Gate +x8 net-_u1-pad3_ net-_x12-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x9 net-_u1-pad14_ net-_x13-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x10 net-_u1-pad2_ net-_x10-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x11 net-_u1-pad15_ net-_x11-pad2_ net-_x1-pad1_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x12 net-_u1-pad1_ net-_x12-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x13 net-_u1-pad6_ net-_x13-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x14 net-_u1-pad7_ net-_x10-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x15 net-_u1-pad4_ net-_x11-pad2_ net-_x12-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x16 net-_u1-pad9_ net-_x12-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +x17 net-_u1-pad5_ net-_x13-pad2_ net-_x16-pad3_ net-_m5-pad3_ net-_m1-pad3_ AND_Gate +m8 net-_m4-pad1_ net-_m4-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m4-pad1_ net-_m4-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m5 net-_m1-pad1_ net-_m1-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m2-pad1_ net-_m2-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m2-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m7 net-_m3-pad1_ net-_m3-pad2_ net-_m5-pad3_ net-_m5-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CD4028_B
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml new file mode 100644 index 00000000..d5185cb2 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/CD4028_B_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model /><devicemodel><m8><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m8><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m5><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m6><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m2><m7><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m7><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m3></devicemodel><subcircuit><x5><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x5><x6><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x6><x7><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x7><x2><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x2><x1><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x1><x3><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x3><x4><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate</field></x4><x8><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x8><x9><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x9><x10><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x10><x11><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x11><x12><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x12><x13><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x13><x14><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x14><x15><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x15><x16><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x16><x17><field>C:\FOSSEE\eSim\library\SubcircuitLibrary\AND_Gate</field></x17></subcircuit></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib b/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib b/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir new file mode 100644 index 00000000..51675c6f --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\NOR_Gate\NOR_Gate.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 06/26/22 11:08:33 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ eSim_MOS_P +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ eSim_MOS_N +U1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ PORT + +.end diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out new file mode 100644 index 00000000..9bf686dc --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\nor_gate\nor_gate.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m2-pad3_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch new file mode 100644 index 00000000..e1d72f85 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:NOR_Gate-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_MOS_P M2 +U 1 1 62B6BCF2 +P 4800 2350 +F 0 "M2" H 4750 2400 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 2500 50 0000 R CNN +F 2 "" H 5050 2450 29 0000 C CNN +F 3 "" H 4850 2350 60 0000 C CNN + 1 4800 2350 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M1 +U 1 1 62B6BD21 +P 4500 3350 +F 0 "M1" H 4500 3200 50 0000 R CNN +F 1 "eSim_MOS_N" H 4600 3300 50 0000 R CNN +F 2 "" H 4800 3050 29 0000 C CNN +F 3 "" H 4600 3150 60 0000 C CNN + 1 4500 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M3 +U 1 1 62B6BD52 +P 4800 2850 +F 0 "M3" H 4750 2900 50 0000 R CNN +F 1 "eSim_MOS_P" H 4850 3000 50 0000 R CNN +F 2 "" H 5050 2950 29 0000 C CNN +F 3 "" H 4850 2850 60 0000 C CNN + 1 4800 2850 + 1 0 0 1 +$EndComp +$Comp +L eSim_MOS_N M4 +U 1 1 62B6BE27 +P 5350 3350 +F 0 "M4" H 5350 3200 50 0000 R CNN +F 1 "eSim_MOS_N" H 5450 3300 50 0000 R CNN +F 2 "" H 5650 3050 29 0000 C CNN +F 3 "" H 5450 3150 60 0000 C CNN + 1 5350 3350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4950 2550 4950 2650 +Wire Wire Line + 4950 3050 4950 3250 +Wire Wire Line + 4700 3350 4700 3250 +Wire Wire Line + 4700 3250 5150 3250 +Wire Wire Line + 5150 3250 5150 3350 +Connection ~ 4950 3250 +Wire Wire Line + 4800 3700 4800 3750 +Wire Wire Line + 4700 3750 5150 3750 +Wire Wire Line + 5050 3750 5050 3700 +Wire Wire Line + 5050 2200 5050 2150 +Wire Wire Line + 5050 2150 4950 2150 +Wire Wire Line + 5050 2700 5050 2650 +Wire Wire Line + 5050 2650 4950 2650 +Connection ~ 5050 3750 +Connection ~ 4800 3750 +Wire Wire Line + 4650 2350 4250 2350 +Wire Wire Line + 4250 2350 4250 3550 +Wire Wire Line + 4250 3550 4400 3550 +Wire Wire Line + 5450 3550 5450 3200 +Wire Wire Line + 5450 3200 4650 3200 +Wire Wire Line + 4650 3200 4650 2850 +Wire Wire Line + 4950 3050 5800 3050 +Wire Wire Line + 4250 2450 4000 2450 +Connection ~ 4250 2450 +Wire Wire Line + 4650 2950 4000 2950 +Connection ~ 4650 2950 +Wire Wire Line + 5000 2150 5000 2100 +Wire Wire Line + 5000 2100 4000 2100 +Connection ~ 5000 2150 +Wire Wire Line + 4950 3750 4950 3850 +Wire Wire Line + 4950 3850 4050 3850 +Connection ~ 4950 3750 +$Comp +L PORT U1 +U 5 1 62B6C047 +P 3800 3850 +F 0 "U1" H 3850 3950 30 0000 C CNN +F 1 "PORT" H 3800 3850 30 0000 C CNN +F 2 "" H 3800 3850 60 0000 C CNN +F 3 "" H 3800 3850 60 0000 C CNN + 5 3800 3850 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 62B6C0A2 +P 3750 2450 +F 0 "U1" H 3800 2550 30 0000 C CNN +F 1 "PORT" H 3750 2450 30 0000 C CNN +F 2 "" H 3750 2450 60 0000 C CNN +F 3 "" H 3750 2450 60 0000 C CNN + 2 3750 2450 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62B6C0DB +P 3750 2950 +F 0 "U1" H 3800 3050 30 0000 C CNN +F 1 "PORT" H 3750 2950 30 0000 C CNN +F 2 "" H 3750 2950 60 0000 C CNN +F 3 "" H 3750 2950 60 0000 C CNN + 3 3750 2950 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62B6C112 +P 6050 3050 +F 0 "U1" H 6100 3150 30 0000 C CNN +F 1 "PORT" H 6050 3050 30 0000 C CNN +F 2 "" H 6050 3050 60 0000 C CNN +F 3 "" H 6050 3050 60 0000 C CNN + 1 6050 3050 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62B6C165 +P 3750 2100 +F 0 "U1" H 3800 2200 30 0000 C CNN +F 1 "PORT" H 3750 2100 30 0000 C CNN +F 2 "" H 3750 2100 60 0000 C CNN +F 3 "" H 3750 2100 60 0000 C CNN + 4 3750 2100 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub new file mode 100644 index 00000000..7ce33167 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate.sub @@ -0,0 +1,12 @@ +* Subcircuit NOR_Gate +.subckt NOR_Gate net-_m1-pad1_ net-_m1-pad2_ net-_m3-pad2_ net-_m2-pad3_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\nor_gate\nor_gate.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends NOR_Gate
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml b/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml new file mode 100644 index 00000000..31ba7357 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/NOR_Gate_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m2><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m1><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field /><field /><field /></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field /><field /><field /></m4></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib b/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/CD4028_B/README.md b/library/SubcircuitLibrary/CD4028_B/README.md new file mode 100644 index 00000000..2a53ca39 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/README.md @@ -0,0 +1,27 @@ + +# CD4028 IC + +It is BCD to Decimal converter IC. CD4028 IC is designed with 180nm CMOS technology in eSim. It is 16 pin IC. +## Usage/Examples + +Code Conversion + +Indication-Tube Decoder + +Address Decoding + +Memory Selection Control +## Documentation + +To know the details of CD4028 IC please go through with the documentation : [CD4028_datasheet](https://www.ti.com/lit/gpn/cd4028b) + +## Comments/Notes + +Please note this is a complete digital IC. It works fine at the time of simulation. + +## Contributer + +Name: Ankush Mondal +Email: mondalankush369@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellow 2022
\ No newline at end of file diff --git a/library/SubcircuitLibrary/CD4028_B/analysis b/library/SubcircuitLibrary/CD4028_B/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/CD4028_B/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |