diff options
Diffstat (limited to 'library/SubcircuitLibrary/CD4020/tff.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/CD4020/tff.cir.out | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/CD4020/tff.cir.out b/library/SubcircuitLibrary/CD4020/tff.cir.out new file mode 100644 index 00000000..8f3c42f5 --- /dev/null +++ b/library/SubcircuitLibrary/CD4020/tff.cir.out @@ -0,0 +1,31 @@ +* c:\fossee\esim\library\subcircuitlibrary\tff\tff.cir + +* u3 net-_u1-pad5_ net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad8_ a1 net-_u3-pad6_ d_tff +* u1 t clk gnd reset net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ adc_bridge_4 +* u5 a1 q dac_bridge_1 +* u4 net-_u3-pad6_ qb dac_bridge_1 +* u2 net-_u1-pad6_ net-_u2-pad2_ d_inverter +a1 net-_u1-pad5_ net-_u2-pad2_ net-_u1-pad7_ net-_u1-pad8_ a1 net-_u3-pad6_ u3 +a2 [t clk gnd reset ] [net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ ] u1 +a3 [a1 ] [q ] u5 +a4 [net-_u3-pad6_ ] [qb ] u4 +a5 net-_u1-pad6_ net-_u2-pad2_ u2 +* Schematic Name: d_tff, NgSpice Name: d_tff +.model u3 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge +.model u1 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u5 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u4 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end |