diff options
Diffstat (limited to 'library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub')
| -rw-r--r-- | library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub new file mode 100644 index 00000000..042fec69 --- /dev/null +++ b/library/SubcircuitLibrary/74LVC1G57/74LVC1G57.sub @@ -0,0 +1,38 @@ +* Subcircuit 74LVC1G57 +.subckt 74LVC1G57 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ +* c:\users\senba\desktop\fossee\esim\library\subcircuitlibrary\74lvc1g57\74lvc1g57.cir +* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter +* u3 net-_u1-pad2_ net-_u3-pad2_ d_inverter +* u4 net-_u1-pad3_ net-_u4-pad2_ d_inverter +* u7 net-_u2-pad2_ net-_u4-pad2_ net-_u7-pad3_ d_and +* u5 net-_u3-pad2_ net-_u5-pad2_ d_inverter +* u6 net-_u4-pad2_ net-_u6-pad2_ d_inverter +* u8 net-_u5-pad2_ net-_u6-pad2_ net-_u8-pad3_ d_and +* u9 net-_u7-pad3_ net-_u8-pad3_ net-_u1-pad4_ d_or +a1 net-_u1-pad1_ net-_u2-pad2_ u2 +a2 net-_u1-pad2_ net-_u3-pad2_ u3 +a3 net-_u1-pad3_ net-_u4-pad2_ u4 +a4 [net-_u2-pad2_ net-_u4-pad2_ ] net-_u7-pad3_ u7 +a5 net-_u3-pad2_ net-_u5-pad2_ u5 +a6 net-_u4-pad2_ net-_u6-pad2_ u6 +a7 [net-_u5-pad2_ net-_u6-pad2_ ] net-_u8-pad3_ u8 +a8 [net-_u7-pad3_ net-_u8-pad3_ ] net-_u1-pad4_ u9 +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u3 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u4 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u5 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_inverter, NgSpice Name: d_inverter +.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_and, NgSpice Name: d_and +.model u8 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: d_or, NgSpice Name: d_or +.model u9 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) +* Control Statements + +.ends 74LVC1G57
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