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-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib139
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020.cir28
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020.cir.out77
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020.pro73
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020.sch630
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020.sub71
-rw-r--r--library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml1
-rw-r--r--library/SubcircuitLibrary/74HC4020/analysis1
8 files changed, 1020 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib b/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib
new file mode 100644
index 00000000..41a77822
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020-cache.lib
@@ -0,0 +1,139 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 75 50 H I C CNN
+F1 "PWR_FLAG" 0 150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+X pwr 1 0 0 0 U 50 50 0 0 w
+P 6 0 1 0 0 0 0 50 -40 75 0 100 40 75 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_1
+#
+DEF adc_bridge_1 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_1" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -50 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X OUT1 2 550 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_tff
+#
+DEF d_tff U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_tff" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 350 450 -350 -400 0 1 0 N
+X T 1 -550 350 200 R 50 50 1 1 I
+X Clk 2 -550 -300 200 R 50 50 1 1 I C
+X Set 3 0 650 200 D 50 50 1 1 I
+X Reset 4 0 -600 200 U 50 50 1 1 I
+X Out 5 550 350 200 L 50 50 1 1 O
+X Nout 6 550 -300 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# pulse
+#
+DEF pulse v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "pulse" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -25 -450 501 928 871 0 1 0 N -50 50 0 50
+A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50
+A 75 600 551 -926 -873 0 1 0 N 50 50 100 50
+A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50
+A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50
+A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.cir b/library/SubcircuitLibrary/74HC4020/74HC4020.cir
new file mode 100644
index 00000000..aed99954
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020.cir
@@ -0,0 +1,28 @@
+* C:\FOSSEE\eSim\library\SubcircuitLibrary\Asynch_counter_sub\Asynch_counter_sub.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 4/20/2025 7:24:35 PM
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U4 Net-_U10-Pad1_ Net-_U1-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad4_ Net-_U4-Pad6_ d_tff
+U6 Net-_U10-Pad1_ Net-_U4-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ ? Net-_U6-Pad6_ d_tff
+U8 Net-_U10-Pad1_ Net-_U6-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ ? Net-_U10-Pad2_ d_tff
+U10 Net-_U10-Pad1_ Net-_U10-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U10-Pad5_ Net-_U10-Pad6_ d_tff
+U12 Net-_U10-Pad1_ Net-_U10-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U12-Pad5_ Net-_U12-Pad6_ d_tff
+U14 Net-_U10-Pad1_ Net-_U12-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U14-Pad5_ Net-_U14-Pad6_ d_tff
+U16 Net-_U10-Pad1_ Net-_U14-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U16-Pad5_ Net-_U16-Pad6_ d_tff
+U5 Net-_U10-Pad1_ Net-_U16-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad5_ Net-_U5-Pad6_ d_tff
+U7 Net-_U10-Pad1_ Net-_U5-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad6_ Net-_U7-Pad6_ d_tff
+U9 Net-_U10-Pad1_ Net-_U7-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U3-Pad7_ Net-_U11-Pad2_ d_tff
+U11 Net-_U10-Pad1_ Net-_U11-Pad2_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ d_tff
+U13 Net-_U10-Pad1_ Net-_U11-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U13-Pad5_ Net-_U13-Pad6_ d_tff
+U15 Net-_U10-Pad1_ Net-_U13-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U15-Pad5_ Net-_U15-Pad6_ d_tff
+U17 Net-_U10-Pad1_ Net-_U15-Pad6_ Net-_U10-Pad3_ Net-_U10-Pad4_ Net-_U17-Pad5_ ? d_tff
+U3 Net-_U10-Pad3_ Net-_U1-Pad1_ Net-_U10-Pad4_ Net-_U3-Pad4_ Net-_U3-Pad5_ Net-_U3-Pad6_ Net-_U3-Pad7_ Net-_U10-Pad5_ Net-_U11-Pad5_ Net-_U12-Pad5_ Net-_U13-Pad5_ Net-_U14-Pad5_ Net-_U15-Pad5_ Net-_U16-Pad5_ Net-_U17-Pad5_ PORT
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ d_inverter
+U2 Net-_U2-Pad1_ Net-_U10-Pad1_ adc_bridge_1
+v1 Net-_U2-Pad1_ GND 5
+
+.end
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out b/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out
new file mode 100644
index 00000000..0671778f
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020.cir.out
@@ -0,0 +1,77 @@
+* c:\fossee\esim\library\subcircuitlibrary\asynch_counter_sub\asynch_counter_sub.cir
+
+* u4 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ d_tff
+* u6 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ d_tff
+* u8 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ d_tff
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ d_tff
+* u12 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_tff
+* u14 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ d_tff
+* u16 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ d_tff
+* u5 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ d_tff
+* u7 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ d_tff
+* u9 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ d_tff
+* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_tff
+* u13 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_tff
+* u15 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_tff
+* u17 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? d_tff
+* u3 net-_u10-pad3_ net-_u1-pad1_ net-_u10-pad4_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u10-pad5_ net-_u11-pad5_ net-_u12-pad5_ net-_u13-pad5_ net-_u14-pad5_ net-_u15-pad5_ net-_u16-pad5_ net-_u17-pad5_ port
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u10-pad1_ adc_bridge_1
+v1 net-_u2-pad1_ gnd 5
+a1 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ u4
+a2 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ u6
+a3 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ u8
+a4 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ u10
+a5 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12
+a6 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ u14
+a7 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ u16
+a8 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ u5
+a9 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ u7
+a10 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ u9
+a11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a12 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13
+a13 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a14 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? u17
+a15 net-_u1-pad1_ net-_u1-pad2_ u1
+a16 [net-_u2-pad1_ ] [net-_u10-pad1_ ] u2
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u4 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u5 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u17 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.pro b/library/SubcircuitLibrary/74HC4020/74HC4020.pro
new file mode 100644
index 00000000..e27a398b
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020.pro
@@ -0,0 +1,73 @@
+update=22/05/2015 07:44:53
+version=1
+last_client=kicad
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=adc-dac
+LibName2=memory
+LibName3=xilinx
+LibName4=microcontrollers
+LibName5=dsp
+LibName6=microchip
+LibName7=analog_switches
+LibName8=motorola
+LibName9=texas
+LibName10=intel
+LibName11=audio
+LibName12=interface
+LibName13=digital-audio
+LibName14=philips
+LibName15=display
+LibName16=cypress
+LibName17=siliconi
+LibName18=opto
+LibName19=atmel
+LibName20=contrib
+LibName21=power
+LibName22=eSim_Plot
+LibName23=transistors
+LibName24=conn
+LibName25=eSim_User
+LibName26=regul
+LibName27=74xx
+LibName28=cmos4000
+LibName29=eSim_Analog
+LibName30=eSim_Devices
+LibName31=eSim_Digital
+LibName32=eSim_Hybrid
+LibName33=eSim_Miscellaneous
+LibName34=eSim_Power
+LibName35=eSim_Sources
+LibName36=eSim_Subckt
+LibName37=eSim_Nghdl
+LibName38=eSim_Ngveri
+LibName39=eSim_SKY130
+LibName40=eSim_SKY130_Subckts
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.sch b/library/SubcircuitLibrary/74HC4020/74HC4020.sch
new file mode 100644
index 00000000..1cc3a953
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020.sch
@@ -0,0 +1,630 @@
+EESchema Schematic File Version 2
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:eSim_Plot
+LIBS:transistors
+LIBS:conn
+LIBS:eSim_User
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_Nghdl
+LIBS:eSim_Ngveri
+LIBS:eSim_SKY130
+LIBS:eSim_SKY130_Subckts
+LIBS:Asynch_counter_sub-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
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diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020.sub b/library/SubcircuitLibrary/74HC4020/74HC4020.sub
new file mode 100644
index 00000000..f0d95a49
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020.sub
@@ -0,0 +1,71 @@
+* Subcircuit Asynch_counter_sub
+.subckt Asynch_counter_sub net-_u10-pad3_ net-_u1-pad1_ net-_u10-pad4_ net-_u3-pad4_ net-_u3-pad5_ net-_u3-pad6_ net-_u3-pad7_ net-_u10-pad5_ net-_u11-pad5_ net-_u12-pad5_ net-_u13-pad5_ net-_u14-pad5_ net-_u15-pad5_ net-_u16-pad5_ net-_u17-pad5_
+* c:\fossee\esim\library\subcircuitlibrary\asynch_counter_sub\asynch_counter_sub.cir
+* u4 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ d_tff
+* u6 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ d_tff
+* u8 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ d_tff
+* u10 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ d_tff
+* u12 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ d_tff
+* u14 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ d_tff
+* u16 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ d_tff
+* u5 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ d_tff
+* u7 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ d_tff
+* u9 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ d_tff
+* u11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ d_tff
+* u13 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ d_tff
+* u15 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ d_tff
+* u17 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? d_tff
+* u1 net-_u1-pad1_ net-_u1-pad2_ d_inverter
+* u2 net-_u2-pad1_ net-_u10-pad1_ adc_bridge_1
+v1 net-_u2-pad1_ gnd 5
+a1 net-_u10-pad1_ net-_u1-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad4_ net-_u4-pad6_ u4
+a2 net-_u10-pad1_ net-_u4-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u6-pad6_ u6
+a3 net-_u10-pad1_ net-_u6-pad6_ net-_u10-pad3_ net-_u10-pad4_ ? net-_u10-pad2_ u8
+a4 net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ u10
+a5 net-_u10-pad1_ net-_u10-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u12-pad5_ net-_u12-pad6_ u12
+a6 net-_u10-pad1_ net-_u12-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u14-pad5_ net-_u14-pad6_ u14
+a7 net-_u10-pad1_ net-_u14-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u16-pad5_ net-_u16-pad6_ u16
+a8 net-_u10-pad1_ net-_u16-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad5_ net-_u5-pad6_ u5
+a9 net-_u10-pad1_ net-_u5-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad6_ net-_u7-pad6_ u7
+a10 net-_u10-pad1_ net-_u7-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u3-pad7_ net-_u11-pad2_ u9
+a11 net-_u10-pad1_ net-_u11-pad2_ net-_u10-pad3_ net-_u10-pad4_ net-_u11-pad5_ net-_u11-pad6_ u11
+a12 net-_u10-pad1_ net-_u11-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u13-pad5_ net-_u13-pad6_ u13
+a13 net-_u10-pad1_ net-_u13-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u15-pad5_ net-_u15-pad6_ u15
+a14 net-_u10-pad1_ net-_u15-pad6_ net-_u10-pad3_ net-_u10-pad4_ net-_u17-pad5_ ? u17
+a15 net-_u1-pad1_ net-_u1-pad2_ u1
+a16 [net-_u2-pad1_ ] [net-_u10-pad1_ ] u2
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u4 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u6 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u8 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u10 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u12 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u14 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u16 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u5 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u7 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u9 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u11 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u13 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u15 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_tff, NgSpice Name: d_tff
+.model u17 d_tff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 t_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u1 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge
+.model u2 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 )
+* Control Statements
+
+.ends Asynch_counter_sub \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml b/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml
new file mode 100644
index 00000000..26e2bb93
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/74HC4020_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">sec</field4><field5 name="Step Combo">sec</field5><field6 name="Stop Combo">sec</field6></tran></analysis><source><v1 name="Source type">5</v1></source><model><u4 name="type">d_tff<field1 name="Enter Clk Delay (default=1.0e-9)" /><field2 name="Enter Set Delay (default=1.0e-9)" /><field3 name="Enter Reset Delay (default=1.0)" /><field4 name="Enter IC (default=0)" /><field5 name="Enter value for T Load (default=1.0e-12)" /><field6 name="Enter value for Clk Load (default=1.0e-12)" /><field7 name="Enter value for Set Load (default=1.0e-12)" /><field8 name="Enter value for Reset Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /><field10 name="Enter Fall Delay (default=1.0e-9)" /></u4><u6 name="type">d_tff<field11 name="Enter Clk Delay (default=1.0e-9)" /><field12 name="Enter Set Delay (default=1.0e-9)" /><field13 name="Enter Reset Delay (default=1.0)" /><field14 name="Enter IC (default=0)" /><field15 name="Enter value for T Load (default=1.0e-12)" /><field16 name="Enter value for Clk Load (default=1.0e-12)" /><field17 name="Enter value for Set Load (default=1.0e-12)" /><field18 name="Enter value for Reset Load (default=1.0e-12)" /><field19 name="Enter Rise Delay (default=1.0e-9)" /><field20 name="Enter Fall Delay (default=1.0e-9)" /></u6><u8 name="type">d_tff<field21 name="Enter Clk Delay (default=1.0e-9)" /><field22 name="Enter Set Delay (default=1.0e-9)" /><field23 name="Enter Reset Delay (default=1.0)" /><field24 name="Enter IC (default=0)" /><field25 name="Enter value for T Load (default=1.0e-12)" /><field26 name="Enter value for Clk Load (default=1.0e-12)" /><field27 name="Enter value for Set Load (default=1.0e-12)" /><field28 name="Enter value for Reset Load (default=1.0e-12)" /><field29 name="Enter Rise Delay (default=1.0e-9)" /><field30 name="Enter Fall Delay (default=1.0e-9)" /></u8><u10 name="type">d_tff<field31 name="Enter Clk Delay (default=1.0e-9)" /><field32 name="Enter Set Delay (default=1.0e-9)" /><field33 name="Enter Reset Delay (default=1.0)" /><field34 name="Enter IC (default=0)" /><field35 name="Enter value for T Load (default=1.0e-12)" /><field36 name="Enter value for Clk Load (default=1.0e-12)" /><field37 name="Enter value for Set Load (default=1.0e-12)" /><field38 name="Enter value for Reset Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /><field40 name="Enter Fall Delay (default=1.0e-9)" /></u10><u12 name="type">d_tff<field41 name="Enter Clk Delay (default=1.0e-9)" /><field42 name="Enter Set Delay (default=1.0e-9)" /><field43 name="Enter Reset Delay (default=1.0)" /><field44 name="Enter IC (default=0)" /><field45 name="Enter value for T Load (default=1.0e-12)" /><field46 name="Enter value for Clk Load (default=1.0e-12)" /><field47 name="Enter value for Set Load (default=1.0e-12)" /><field48 name="Enter value for Reset Load (default=1.0e-12)" /><field49 name="Enter Rise Delay (default=1.0e-9)" /><field50 name="Enter Fall Delay (default=1.0e-9)" /></u12><u14 name="type">d_tff<field51 name="Enter Clk Delay (default=1.0e-9)" /><field52 name="Enter Set Delay (default=1.0e-9)" /><field53 name="Enter Reset Delay (default=1.0)" /><field54 name="Enter IC (default=0)" /><field55 name="Enter value for T Load (default=1.0e-12)" /><field56 name="Enter value for Clk Load (default=1.0e-12)" /><field57 name="Enter value for Set Load (default=1.0e-12)" /><field58 name="Enter value for Reset Load (default=1.0e-12)" /><field59 name="Enter Rise Delay (default=1.0e-9)" /><field60 name="Enter Fall Delay (default=1.0e-9)" /></u14><u16 name="type">d_tff<field61 name="Enter Clk Delay (default=1.0e-9)" /><field62 name="Enter Set Delay (default=1.0e-9)" /><field63 name="Enter Reset Delay (default=1.0)" /><field64 name="Enter IC (default=0)" /><field65 name="Enter value for T Load (default=1.0e-12)" /><field66 name="Enter value for Clk Load (default=1.0e-12)" /><field67 name="Enter value for Set Load (default=1.0e-12)" /><field68 name="Enter value for Reset Load (default=1.0e-12)" /><field69 name="Enter Rise Delay (default=1.0e-9)" /><field70 name="Enter Fall Delay (default=1.0e-9)" /></u16><u5 name="type">d_tff<field71 name="Enter Clk Delay (default=1.0e-9)" /><field72 name="Enter Set Delay (default=1.0e-9)" /><field73 name="Enter Reset Delay (default=1.0)" /><field74 name="Enter IC (default=0)" /><field75 name="Enter value for T Load (default=1.0e-12)" /><field76 name="Enter value for Clk Load (default=1.0e-12)" /><field77 name="Enter value for Set Load (default=1.0e-12)" /><field78 name="Enter value for Reset Load (default=1.0e-12)" /><field79 name="Enter Rise Delay (default=1.0e-9)" /><field80 name="Enter Fall Delay (default=1.0e-9)" /></u5><u7 name="type">d_tff<field81 name="Enter Clk Delay (default=1.0e-9)" /><field82 name="Enter Set Delay (default=1.0e-9)" /><field83 name="Enter Reset Delay (default=1.0)" /><field84 name="Enter IC (default=0)" /><field85 name="Enter value for T Load (default=1.0e-12)" /><field86 name="Enter value for Clk Load (default=1.0e-12)" /><field87 name="Enter value for Set Load (default=1.0e-12)" /><field88 name="Enter value for Reset Load (default=1.0e-12)" /><field89 name="Enter Rise Delay (default=1.0e-9)" /><field90 name="Enter Fall Delay (default=1.0e-9)" /></u7><u9 name="type">d_tff<field91 name="Enter Clk Delay (default=1.0e-9)" /><field92 name="Enter Set Delay (default=1.0e-9)" /><field93 name="Enter Reset Delay (default=1.0)" /><field94 name="Enter IC (default=0)" /><field95 name="Enter value for T Load (default=1.0e-12)" /><field96 name="Enter value for Clk Load (default=1.0e-12)" /><field97 name="Enter value for Set Load (default=1.0e-12)" /><field98 name="Enter value for Reset Load (default=1.0e-12)" /><field99 name="Enter Rise Delay (default=1.0e-9)" /><field100 name="Enter Fall Delay (default=1.0e-9)" /></u9><u11 name="type">d_tff<field101 name="Enter Clk Delay (default=1.0e-9)" /><field102 name="Enter Set Delay (default=1.0e-9)" /><field103 name="Enter Reset Delay (default=1.0)" /><field104 name="Enter IC (default=0)" /><field105 name="Enter value for T Load (default=1.0e-12)" /><field106 name="Enter value for Clk Load (default=1.0e-12)" /><field107 name="Enter value for Set Load (default=1.0e-12)" /><field108 name="Enter value for Reset Load (default=1.0e-12)" /><field109 name="Enter Rise Delay (default=1.0e-9)" /><field110 name="Enter Fall Delay (default=1.0e-9)" /></u11><u13 name="type">d_tff<field111 name="Enter Clk Delay (default=1.0e-9)" /><field112 name="Enter Set Delay (default=1.0e-9)" /><field113 name="Enter Reset Delay (default=1.0)" /><field114 name="Enter IC (default=0)" /><field115 name="Enter value for T Load (default=1.0e-12)" /><field116 name="Enter value for Clk Load (default=1.0e-12)" /><field117 name="Enter value for Set Load (default=1.0e-12)" /><field118 name="Enter value for Reset Load (default=1.0e-12)" /><field119 name="Enter Rise Delay (default=1.0e-9)" /><field120 name="Enter Fall Delay (default=1.0e-9)" /></u13><u15 name="type">d_tff<field121 name="Enter Clk Delay (default=1.0e-9)" /><field122 name="Enter Set Delay (default=1.0e-9)" /><field123 name="Enter Reset Delay (default=1.0)" /><field124 name="Enter IC (default=0)" /><field125 name="Enter value for T Load (default=1.0e-12)" /><field126 name="Enter value for Clk Load (default=1.0e-12)" /><field127 name="Enter value for Set Load (default=1.0e-12)" /><field128 name="Enter value for Reset Load (default=1.0e-12)" /><field129 name="Enter Rise Delay (default=1.0e-9)" /><field130 name="Enter Fall Delay (default=1.0e-9)" /></u15><u17 name="type">d_tff<field131 name="Enter Clk Delay (default=1.0e-9)" /><field132 name="Enter Set Delay (default=1.0e-9)" /><field133 name="Enter Reset Delay (default=1.0)" /><field134 name="Enter IC (default=0)" /><field135 name="Enter value for T Load (default=1.0e-12)" /><field136 name="Enter value for Clk Load (default=1.0e-12)" /><field137 name="Enter value for Set Load (default=1.0e-12)" /><field138 name="Enter value for Reset Load (default=1.0e-12)" /><field139 name="Enter Rise Delay (default=1.0e-9)" /><field140 name="Enter Fall Delay (default=1.0e-9)" /></u17><u1 name="type">d_inverter<field141 name="Enter Rise Delay (default=1.0e-9)" /><field142 name="Enter Fall Delay (default=1.0e-9)" /><field143 name="Enter Input Load (default=1.0e-12)" /></u1><u2 name="type">adc_bridge<field144 name="Enter value for in_low (default=1.0)" /><field145 name="Enter value for in_high (default=2.0)" /><field146 name="Enter Rise Delay (default=1.0e-9)" /><field147 name="Enter Fall Delay (default=1.0e-9)" /></u2></model><devicemodel /><subcircuit /></KicadtoNgspice> \ No newline at end of file
diff --git a/library/SubcircuitLibrary/74HC4020/analysis b/library/SubcircuitLibrary/74HC4020/analysis
new file mode 100644
index 00000000..ebd5c0a9
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC4020/analysis
@@ -0,0 +1 @@
+.tran 0e-00 0e-00 0e-00 \ No newline at end of file
generated by cgit (git 2.34.1) at 2025-06-30 08:23:07 +0000