1 files changed, 65 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC193/74HC193.cir.out b/library/SubcircuitLibrary/74HC193/74HC193.cir.out
new file mode 100644
index 00000000..8e47f1f8
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC193/74HC193.cir.out
@@ -0,0 +1,65 @@
+* c:\fossee\esim\library\subcircuitlibrary\4_bit_updown_counter\4_bit_updown_counter.cir
+
+.include jk_mux.sub
+x1 net-_u1-pad5_ net-_u1-pad3_ net-_u1-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad8_ net-_u4-pad1_ jk_mux
+x7 net-_u1-pad13_ net-_u11-pad3_ net-_u11-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad14_ net-_u13-pad1_ jk_mux
+x3 net-_u1-pad9_ net-_u5-pad3_ net-_u5-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad10_ net-_u7-pad2_ jk_mux
+x5 net-_u1-pad11_ net-_u8-pad3_ net-_u8-pad3_ net-_u1-pad7_ net-_u1-pad2_ net-_u1-pad4_ net-_u1-pad6_ net-_u1-pad12_ net-_u10-pad1_ jk_mux
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ net-_u1-pad16_ port
+* u2  net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u3  net-_u1-pad1_ net-_u1-pad8_ net-_u3-pad3_ d_and
+* u4  net-_u4-pad1_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5  net-_u3-pad3_ net-_u4-pad3_ net-_u5-pad3_ d_or
+* u6  net-_u3-pad3_ net-_u1-pad10_ net-_u6-pad3_ d_and
+* u7  net-_u4-pad3_ net-_u7-pad2_ net-_u10-pad2_ d_and
+* u8  net-_u6-pad3_ net-_u10-pad2_ net-_u8-pad3_ d_or
+* u9  net-_u6-pad3_ net-_u1-pad12_ net-_u11-pad1_ d_and
+* u10  net-_u10-pad1_ net-_u10-pad2_ net-_u10-pad3_ d_and
+* u11  net-_u11-pad1_ net-_u10-pad3_ net-_u11-pad3_ d_or
+* u12  net-_u11-pad1_ net-_u1-pad14_ net-_u1-pad15_ d_nand
+* u13  net-_u13-pad1_ net-_u10-pad3_ net-_u1-pad16_ d_nand
+a1 net-_u1-pad1_ net-_u2-pad2_ u2
+a2 [net-_u1-pad1_ net-_u1-pad8_ ] net-_u3-pad3_ u3
+a3 [net-_u4-pad1_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a4 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u5-pad3_ u5
+a5 [net-_u3-pad3_ net-_u1-pad10_ ] net-_u6-pad3_ u6
+a6 [net-_u4-pad3_ net-_u7-pad2_ ] net-_u10-pad2_ u7
+a7 [net-_u6-pad3_ net-_u10-pad2_ ] net-_u8-pad3_ u8
+a8 [net-_u6-pad3_ net-_u1-pad12_ ] net-_u11-pad1_ u9
+a9 [net-_u10-pad1_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a10 [net-_u11-pad1_ net-_u10-pad3_ ] net-_u11-pad3_ u11
+a11 [net-_u11-pad1_ net-_u1-pad14_ ] net-_u1-pad15_ u12
+a12 [net-_u13-pad1_ net-_u10-pad3_ ] net-_u1-pad16_ u13
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u6 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u7 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u8 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u9 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_and, NgSpice Name: d_and
+.model u10 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_or, NgSpice Name: d_or
+.model u11 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u12 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+* Schematic Name:                             d_nand, NgSpice Name: d_nand
+.model u13 d_nand(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end