1 files changed, 32 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC175/74HC175.cir.out b/library/SubcircuitLibrary/74HC175/74HC175.cir.out
new file mode 100644
index 00000000..4018e114
--- /dev/null
+++ b/library/SubcircuitLibrary/74HC175/74HC175.cir.out
@@ -0,0 +1,32 @@
+* c:\fossee\esim\library\subcircuitlibrary\74hc175\74hc175.cir
+
+* u2  net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ d_dff
+* u3  net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ d_dff
+* u4  net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ d_dff
+* u5  net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ d_dff
+* u1  net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ net-_u1-pad8_ net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ port
+* u6  net-_u1-pad2_ net-_u2-pad4_ d_inverter
+a1 net-_u1-pad3_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad5_ net-_u1-pad6_ u2
+a2 net-_u1-pad4_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad7_ net-_u1-pad8_ u3
+a3 net-_u1-pad9_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad11_ net-_u1-pad12_ u4
+a4 net-_u1-pad10_ net-_u1-pad1_ net-_u1-pad15_ net-_u2-pad4_ net-_u1-pad13_ net-_u1-pad14_ u5
+a5 net-_u1-pad2_ net-_u2-pad4_ u6
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u2 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u3 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u4 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_dff, NgSpice Name: d_dff
+.model u5 d_dff(clk_delay=1.0e-9 set_delay=1.0e-9 reset_delay=1.0 ic=0 data_load=1.0e-12 clk_load=1.0e-12 set_load=1.0e-12 reset_load=1.0e-12 rise_delay=1.0e-9 fall_delay=1.0e-9 ) 
+* Schematic Name:                             d_inverter, NgSpice Name: d_inverter
+.model u6 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 ) 
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end