diff options
Diffstat (limited to 'library/SubcircuitLibrary/74HC157/mux.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/74HC157/mux.cir.out | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74HC157/mux.cir.out b/library/SubcircuitLibrary/74HC157/mux.cir.out new file mode 100644 index 00000000..d23ed61f --- /dev/null +++ b/library/SubcircuitLibrary/74HC157/mux.cir.out @@ -0,0 +1,28 @@ +* c:\fossee\esim\library\subcircuitlibrary\mux\mux.cir
+
+* u3 net-_u1-pad1_ net-_u1-pad3_ net-_u3-pad3_ d_and
+* u4 net-_u1-pad2_ net-_u2-pad2_ net-_u4-pad3_ d_and
+* u5 net-_u3-pad3_ net-_u4-pad3_ net-_u1-pad4_ d_or
+* u2 net-_u1-pad1_ net-_u2-pad2_ d_inverter
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ port
+a1 [net-_u1-pad1_ net-_u1-pad3_ ] net-_u3-pad3_ u3
+a2 [net-_u1-pad2_ net-_u2-pad2_ ] net-_u4-pad3_ u4
+a3 [net-_u3-pad3_ net-_u4-pad3_ ] net-_u1-pad4_ u5
+a4 net-_u1-pad1_ net-_u2-pad2_ u2
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u4 d_and(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u5 d_or(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(rise_delay=1.0e-9 fall_delay=1.0e-9 input_load=1.0e-12 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
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