diff options
Diffstat (limited to 'library/SubcircuitLibrary/54act11030/54act11030.cir.out')
| -rw-r--r-- | library/SubcircuitLibrary/54act11030/54act11030.cir.out | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/54act11030/54act11030.cir.out b/library/SubcircuitLibrary/54act11030/54act11030.cir.out new file mode 100644 index 00000000..75b8bced --- /dev/null +++ b/library/SubcircuitLibrary/54act11030/54act11030.cir.out @@ -0,0 +1,39 @@ +* c:\users\shanthipriya\esim-workspace\030\030.cir + +.include 74_1030.sub +x1 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ net-_u10-pad1_ 74_1030 +* u9 a1 a2 a3 a4 a5 a6 a7 a8 net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ adc_bridge_8 +* u10 net-_u10-pad1_ out dac_bridge_1 +v1 a1 gnd pulse(0 5 0 1n 1n 2m 4m) +v2 a2 gnd pulse(0 5 0 1n 1n 4m 8m) +v3 a3 gnd pulse(0 5 0 1n 1n 8m 16m) +v4 a4 gnd pulse(0 5 0 1n 1n 16m 32m) +v5 a5 gnd pulse(0 5 0 1n 1n 32m 64m) +v6 a6 gnd pulse(0 5 0 1n 1n 64 128m) +v7 a7 gnd pulse(0 5 0 1n 1n 128m 256m) +v8 a8 gnd pulse(0 5 0 1n 1n 256m 512m) +* u11 out plot_v1 +* u1 a1 plot_v1 +* u2 a2 plot_v1 +* u3 a3 plot_v1 +* u4 a4 plot_v1 +* u5 a5 plot_v1 +* u6 a6 plot_v1 +* u7 a7 plot_v1 +* u8 a8 plot_v1 +a1 [a1 a2 a3 a4 a5 a6 a7 a8 ] [net-_u9-pad9_ net-_u9-pad10_ net-_u9-pad11_ net-_u9-pad12_ net-_u9-pad13_ net-_u9-pad14_ net-_u9-pad15_ net-_u9-pad16_ ] u9 +a2 [net-_u10-pad1_ ] [out ] u10 +* Schematic Name: adc_bridge_8, NgSpice Name: adc_bridge +.model u9 adc_bridge(in_low=1.0 in_high=2.0 rise_delay=1.0e-9 fall_delay=1.0e-9 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_low=0.0 out_high=5.0 out_undef=0.5 input_load=1.0e-12 t_rise=1.0e-9 t_fall=1.0e-9 ) +.tran 1e-03 300e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out)+6 v(a1)+12 v(a2)+18 v(a3)+24 v(a4)+30 v(a5)+36v(a6)+42 v(a7)+48 v(a8) +.endc +.end |