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-rw-r--r--code/maker/Appconfig.rst18
-rw-r--r--code/maker/Maker.rst19
-rw-r--r--code/maker/ModelGeneration.rst19
-rw-r--r--code/maker/NgVeri.rst21
-rw-r--r--code/maker/createkicad.rst18
-rw-r--r--code/maker/makerchip.rst19
6 files changed, 114 insertions, 0 deletions
diff --git a/code/maker/Appconfig.rst b/code/maker/Appconfig.rst
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+AppConfig Module
+================
+
+This module manages application configuration settings for the eSim Maker tools.
+
+**Features:**
+- Loads and saves user preferences and application settings.
+- Provides an interface for accessing and updating configuration values.
+
+**Usage:**
+Refer to the API documentation or user guide for instructions on modifying application settings.
+
+.. note::
+
+ Source : ``src/maker/Appconfig.py``
+
+.. automodule:: maker.Appconfig
+ :members: \ No newline at end of file
diff --git a/code/maker/Maker.rst b/code/maker/Maker.rst
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+Maker Module
+============
+
+The Maker module in eSim provides tools and utilities for creating, editing, and managing electronic design projects.
+
+**Features:**
+- Project creation and management.
+- Integration with schematic and PCB design tools.
+- Export options for various EDA formats.
+
+**Usage:**
+Refer to the user guide or API documentation for instructions on using the Maker module features.
+
+.. note::
+
+ Source : ``src/maker/Maker.py``
+
+.. automodule:: maker.Maker
+ :members: \ No newline at end of file
diff --git a/code/maker/ModelGeneration.rst b/code/maker/ModelGeneration.rst
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+ModelGeneration Module
+======================
+
+This module provides tools for generating simulation models within eSim Maker.
+
+**Features:**
+- Generates SPICE and behavioral models for components.
+- Supports parameterized model creation.
+- Integrates with other Maker modules for seamless workflow.
+
+**Usage:**
+Refer to the API documentation or user guide for instructions on generating and using models.
+
+.. note::
+
+ Source : ``src/maker/ModelGeneration.py``
+
+.. automodule:: maker.ModelGeneration
+ :members: \ No newline at end of file
diff --git a/code/maker/NgVeri.rst b/code/maker/NgVeri.rst
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+NgVeri Module
+=============
+
+This module defines all components of the NgVeri Tab in eSim Maker, enabling users to convert Verilog files to Ngspice-compatible models and manage related dependencies.
+
+**Features:**
+- Converts Verilog files to Ngspice code models.
+- Adds dependency files and folders required by the Verilog top module.
+- Provides a terminal interface for logs and messages.
+- Allows management of Verilog models and lint-off comments.
+- Integrates with Maker and ModelGeneration modules.
+
+**Usage:**
+Use the NgVeri tab in the eSim Maker interface to convert Verilog files, manage dependencies, and handle model/lint-off lists. Refer to the user guide for step-by-step instructions.
+
+.. note::
+
+ Source : ``src/maker/NgVeri.py``
+
+.. automodule:: maker.NgVeri
+ :members: \ No newline at end of file
diff --git a/code/maker/createkicad.rst b/code/maker/createkicad.rst
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+Create KiCad Module
+===================
+
+This module provides tools for creating and exporting KiCad-compatible files from eSim Maker.
+
+**Features:**
+- Generates KiCad schematic and symbol files.
+- Supports exporting projects and components in KiCad formats.
+
+**Usage:**
+Use the provided interface or scripts to generate KiCad files from your eSim Maker projects.
+
+.. note::
+
+ Source : ``src/maker/createkicad.py``
+
+.. automodule:: maker.createkicad
+ :members: \ No newline at end of file
diff --git a/code/maker/makerchip.rst b/code/maker/makerchip.rst
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+Makerchip Module
+================
+
+This module provides integration with Makerchip for digital design and simulation within eSim Maker.
+
+**Features:**
+- Supports digital circuit design using Makerchip.
+- Enables simulation and verification of digital designs.
+- Provides export and import options for Makerchip projects.
+
+**Usage:**
+Refer to the Makerchip integration guide or API documentation for instructions on using this module.
+
+.. note::
+
+ Source : ``src/maker/makerchip.py``
+
+.. automodule:: maker.makerchip
+ :members: \ No newline at end of file