diff options
Diffstat (limited to 'Windows/spice/examples/xspice/original-examples/digital_models4.deck')
| -rw-r--r-- | Windows/spice/examples/xspice/original-examples/digital_models4.deck | 91 |
1 files changed, 0 insertions, 91 deletions
diff --git a/Windows/spice/examples/xspice/original-examples/digital_models4.deck b/Windows/spice/examples/xspice/original-examples/digital_models4.deck deleted file mode 100644 index 6d18c98b..00000000 --- a/Windows/spice/examples/xspice/original-examples/digital_models4.deck +++ /dev/null @@ -1,91 +0,0 @@ -Code Model Test: State Machine, RAM -* -* -*** analysis type *** -.tran .01s 8s -* -*** input sources *** -* -vdata1 100 0 DC PWL( (0 0.0) (2 0.0) (2.0000000001 1.0) (3 1.0) -+ (3.5000000001 0.0) (4 0.0) ) -* -* -vdata2 200 0 DC PWL( (0 0.0) (1.0 0.0) (1.0000000001 1.0) (2 1.0) -+ (2.0000000001 0.0) (3 0.0) (3.0000000001 1.0) (4 1.0) ) -* -* -vclk 300 0 DC PWL( (0 0.0) (0.5 0.0) (0.50000000001 1.0) -+ (1.0 1.0) (1.00000000001 0.0) -+ (1.5 0.0) (1.50000000001 1.0) -+ (2.0 1.0) (2.00000000001 0.0) -+ (2.5 0.0) (2.50000000001 1.0) -+ (3.0 1.0) (3.00000000001 0.0) -+ (3.5 0.0) (3.50000000001 1.0) -+ (4.0 1.0) (4.00000000001 0.0) -+ (4.5 0.0) (4.50000000001 1.0) -+ (5.0 1.0) (5.00000000001 0.0) -+ (5.5 0.0) (5.50000000001 1.0) -+ (6.0 1.0) (6.00000000001 0.0) -+ (6.5 0.0) (6.50000000001 1.0) -+ (7.0 1.0) (7.00000000001 0.0) -+ (7.5 0.0) (7.50000000001 1.0) (8.0 1.0) ) -* -vaddr1 400 0 DC 0 -* -* -vaddr2 500 0 DC PWL( (0 0.0) (0.6 0.0) (0.60000000001 1.0) -+ (0.9 1.0) (0.90000000001 0.0) -+ (2.6 0.0) (2.60000000001 1.0) -+ (2.9 1.0) (2.90000000001 0.0) (3.0 0.0) ) -* -* -* -vselect 600 0 DC PWL( (0 0.0) (1.0 0.0) (2 1.0) (2.0000000001 1.0) ) -* -* -* -* -* -*** adc_bridge block *** -aconverter [100 200 300 400 500 600] [1 2 3 4 5 6] adc_bridge1 -.model adc_bridge1 adc_bridge (in_low=0.1 in_high=0.9 -+ rise_delay=1.0e-12 fall_delay=1.0e-12) -* -* -* -*** state machine block *** -*a1 [1 2] 3 4 [10 11] d_state1 -*.model d_state1 d_state (clk_delay=1.0e-6 reset_delay=2.0e-6 -*+ state_file="state.txt" reset_state=0 -*+ input_load=1.0e-12 clk_load=1.0e-12 -*+ reset_load=1.0e-12) -* -* -*** RAM block *** -a2 [1 2] [20 21] [3 4] 5 [6] d_ram1 -.model d_ram1 d_ram (select_value=1 ic=0 -+ read_delay=1.0e-6 data_load=1.0e-12 -+ address_load=1.0e-12 select_load=1.0e-12 -+ enable_load=1.0e-12) -* -* -* -* -* -*** resistors to ground *** -r1 100 0 10k -r2 200 0 10k -r3 300 0 10k -r4 400 0 10k -r5 500 0 10k -r6 600 0 10k -* -* -* -.end - - - - - - |