diff options
Diffstat (limited to 'Examples/NGHDL_Examples/Cmosinverter')
18 files changed, 1064 insertions, 0 deletions
diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib new file mode 100644 index 00000000..c6733b19 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter-cache.lib @@ -0,0 +1,75 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# INVCMOS +# +DEF INVCMOS X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "INVCMOS" -450 150 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +C 400 0 112 0 1 0 N +S -250 200 -250 -200 0 1 0 N +P 3 0 1 0 -250 200 300 0 -250 -200 N +X in 1 -450 0 200 R 50 50 1 1 P +X out 2 700 0 200 L 50 50 1 1 P +ENDDRAW +ENDDEF +# +# adc_bridge_1 +# +DEF adc_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "adc_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# dac_bridge_1 +# +DEF dac_bridge_1 U 0 40 Y Y 1 F N +F0 "U" 0 0 60 H V C CNN +F1 "dac_bridge_1" 0 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -400 200 350 -50 0 1 0 N +X IN1 1 -600 50 200 R 50 50 1 1 I +X OUT1 2 550 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# inverter +# +DEF inverter U 0 40 Y Y 1 F N +F0 "U" 2850 1800 60 H V C CNN +F1 "inverter" 2850 2000 60 H V C CNN +F2 "" 2850 1950 60 H V C CNN +F3 "" 2850 1950 60 H V C CNN +DRAW +S 2550 2100 3150 1700 0 1 0 N +X in1 1 2350 1900 200 R 50 50 1 1 I +X out1 2 3350 1900 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir new file mode 100644 index 00000000..7736c9d0 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir @@ -0,0 +1,26 @@ +* /home/saurabh/eSim-Workspace/Cmosinvertor/Cmosinvertor.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Nov 27 14:17:36 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U2 out1 plot_v1 +X1 out7 out1 INVCMOS +X2 out1 out2 INVCMOS +X3 out2 out3 INVCMOS +U3 out2 plot_v1 +U4 out3 plot_v1 +X4 out3 out4 INVCMOS +U5 out4 plot_v1 +X5 out4 out5 INVCMOS +U6 out5 plot_v1 +X6 out5 out6 INVCMOS +U7 out6 plot_v1 +U8 out7 plot_v1 +U9 out6 Net-_U1-Pad1_ adc_bridge_1 +U10 Net-_U1-Pad2_ out7 dac_bridge_1 +U1 Net-_U1-Pad1_ Net-_U1-Pad2_ inverter + +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out new file mode 100644 index 00000000..9cebe968 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.cir.out @@ -0,0 +1,45 @@ +* /home/saurabh/esim-workspace/cmosinvertor/cmosinvertor.cir + +.include INVCMOS.sub +* u2 out1 plot_v1 +x1 out7 out1 INVCMOS +x2 out1 out2 INVCMOS +x3 out2 out3 INVCMOS +* u3 out2 plot_v1 +* u4 out3 plot_v1 +x4 out3 out4 INVCMOS +* u5 out4 plot_v1 +x5 out4 out5 INVCMOS +* u6 out5 plot_v1 +x6 out5 out6 INVCMOS +* u7 out6 plot_v1 +* u8 out7 plot_v1 +* u9 out6 net-_u1-pad1_ adc_bridge_1 +* u10 net-_u1-pad2_ out7 dac_bridge_1 +* u1 net-_u1-pad1_ net-_u1-pad2_ inverter +a1 [out6 ] [net-_u1-pad1_ ] u9 +a2 [net-_u1-pad2_ ] [out7 ] u10 +a3 [net-_u1-pad1_ ] [net-_u1-pad2_ ] u1 +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u9 adc_bridge(fall_delay=1.0e-6 in_high=2.0 rise_delay=1.0e-6 in_low=1.0 ) +* Schematic Name: dac_bridge_1, NgSpice Name: dac_bridge +.model u10 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-6 t_fall=1.0e-6 input_load=1.0e-12 ) +* Schematic Name: inverter, NgSpice Name: inverter +.model u1 inverter(fall_delay=1.0e-6 input_load=1.0e-12 rise_delay=1.0e-6 instance_id=1 ) +.tran 1e-03 200e-03 0e-00 + +* Control Statements +.control +option noopalter +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(out1) +plot v(out2) +plot v(out3) +plot v(out4) +plot v(out5) +plot v(out6) +plot v(out7) +.endc +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro new file mode 100644 index 00000000..cb9e3c98 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.pro @@ -0,0 +1,74 @@ +update=Wed Nov 27 14:17:05 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt +LibName40=eSim_Nghdl + diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj new file mode 100644 index 00000000..851b8737 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.proj @@ -0,0 +1 @@ +schematicFile Cmosinvertor.sch diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch new file mode 100644 index 00000000..7abedbb2 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter.sch @@ -0,0 +1,303 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:Cmosinvertor-cache +EELAYER 25 0 +EELAYER END +$Descr A3 16535 11693 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L plot_v1 U2 +U 1 1 5D6266E9 +P 4350 1950 +F 0 "U2" H 4350 2450 60 0000 C CNN +F 1 "plot_v1" H 4550 2300 60 0000 C CNN +F 2 "" H 4350 1950 60 0000 C CNN +F 3 "" H 4350 1950 60 0000 C CNN + 1 4350 1950 + 1 0 0 -1 +$EndComp +Text GLabel 4350 2100 3 60 Input ~ 0 +out1 +$Comp +L INVCMOS X1 +U 1 1 5D626E20 +P 3200 1850 +F 0 "X1" H 3200 1850 60 0000 C CNN +F 1 "INVCMOS" H 2750 2000 60 0000 C CNN +F 2 "" H 3200 1850 60 0001 C CNN +F 3 "" H 3200 1850 60 0001 C CNN + 1 3200 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X2 +U 1 1 5D626E52 +P 5400 1850 +F 0 "X2" H 5400 1850 60 0000 C CNN +F 1 "INVCMOS" H 4950 2000 60 0000 C CNN +F 2 "" H 5400 1850 60 0001 C CNN +F 3 "" H 5400 1850 60 0001 C CNN + 1 5400 1850 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X3 +U 1 1 5D626EC9 +P 7000 1850 +F 0 "X3" H 7000 1850 60 0000 C CNN +F 1 "INVCMOS" H 6550 2000 60 0000 C CNN +F 2 "" H 7000 1850 60 0001 C CNN +F 3 "" H 7000 1850 60 0001 C CNN + 1 7000 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 5D626F62 +P 6200 1950 +F 0 "U3" H 6200 2450 60 0000 C CNN +F 1 "plot_v1" H 6400 2300 60 0000 C CNN +F 2 "" H 6200 1950 60 0000 C CNN +F 3 "" H 6200 1950 60 0000 C CNN + 1 6200 1950 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 5D626FB9 +P 8000 1950 +F 0 "U4" H 8000 2450 60 0000 C CNN +F 1 "plot_v1" H 8200 2300 60 0000 C CNN +F 2 "" H 8000 1950 60 0000 C CNN +F 3 "" H 8000 1950 60 0000 C CNN + 1 8000 1950 + 1 0 0 -1 +$EndComp +Text GLabel 6200 2150 3 60 Input ~ 0 +out2 +Text GLabel 8000 2150 3 60 Input ~ 0 +out3 +$Comp +L INVCMOS X4 +U 1 1 5D627966 +P 9050 1850 +F 0 "X4" H 9050 1850 60 0000 C CNN +F 1 "INVCMOS" H 8600 2000 60 0000 C CNN +F 2 "" H 9050 1850 60 0001 C CNN +F 3 "" H 9050 1850 60 0001 C CNN + 1 9050 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U5 +U 1 1 5D627A26 +P 9950 1950 +F 0 "U5" H 9950 2450 60 0000 C CNN +F 1 "plot_v1" H 10150 2300 60 0000 C CNN +F 2 "" H 9950 1950 60 0000 C CNN +F 3 "" H 9950 1950 60 0000 C CNN + 1 9950 1950 + 1 0 0 -1 +$EndComp +$Comp +L INVCMOS X5 +U 1 1 5D628061 +P 8200 3100 +F 0 "X5" H 8200 3100 60 0000 C CNN +F 1 "INVCMOS" H 7750 3250 60 0000 C CNN +F 2 "" H 8200 3100 60 0001 C CNN +F 3 "" H 8200 3100 60 0001 C CNN + 1 8200 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 5D628068 +P 9200 3200 +F 0 "U6" H 9200 3700 60 0000 C CNN +F 1 "plot_v1" H 9400 3550 60 0000 C CNN +F 2 "" H 9200 3200 60 0000 C CNN +F 3 "" H 9200 3200 60 0000 C CNN + 1 9200 3200 + 1 0 0 -1 +$EndComp +Text GLabel 9200 3400 3 60 Input ~ 0 +out5 +$Comp +L INVCMOS X6 +U 1 1 5D628071 +P 10250 3100 +F 0 "X6" H 10250 3100 60 0000 C CNN +F 1 "INVCMOS" H 9800 3250 60 0000 C CNN +F 2 "" H 10250 3100 60 0001 C CNN +F 3 "" H 10250 3100 60 0001 C CNN + 1 10250 3100 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 5D628079 +P 11150 3200 +F 0 "U7" H 11150 3700 60 0000 C CNN +F 1 "plot_v1" H 11350 3550 60 0000 C CNN +F 2 "" H 11150 3200 60 0000 C CNN +F 3 "" H 11150 3200 60 0000 C CNN + 1 11150 3200 + 1 0 0 -1 +$EndComp +Text GLabel 11150 3400 3 60 Input ~ 0 +out6 +Text GLabel 9950 2100 3 60 Input ~ 0 +out4 +$Comp +L plot_v1 U8 +U 1 1 5D636DDC +P 14550 4000 +F 0 "U8" H 14550 4500 60 0000 C CNN +F 1 "plot_v1" H 14750 4350 60 0000 C CNN +F 2 "" H 14550 4000 60 0000 C CNN +F 3 "" H 14550 4000 60 0000 C CNN + 1 14550 4000 + 0 -1 -1 0 +$EndComp +Text GLabel 14750 4000 2 60 Input ~ 0 +out7 +$Comp +L adc_bridge_1 U9 +U 1 1 5D67A9F3 +P 12300 3150 +F 0 "U9" H 12300 3150 60 0000 C CNN +F 1 "adc_bridge_1" H 12300 3300 60 0000 C CNN +F 2 "" H 12300 3150 60 0000 C CNN +F 3 "" H 12300 3150 60 0000 C CNN + 1 12300 3150 + 1 0 0 -1 +$EndComp +$Comp +L dac_bridge_1 U10 +U 1 1 5D67AA64 +P 14400 3000 +F 0 "U10" H 14400 3000 60 0000 C CNN +F 1 "dac_bridge_1" H 14400 3150 60 0000 C CNN +F 2 "" H 14400 3000 60 0000 C CNN +F 3 "" H 14400 3000 60 0000 C CNN + 1 14400 3000 + 0 1 1 0 +$EndComp +Wire Wire Line + 3900 1850 4950 1850 +Connection ~ 2550 1850 +Connection ~ 4350 1850 +Wire Wire Line + 6100 1850 6550 1850 +Wire Wire Line + 4350 1750 4350 2100 +Wire Wire Line + 6200 1750 6200 2150 +Connection ~ 6200 1850 +Wire Wire Line + 8000 1750 8000 2150 +Connection ~ 8000 1850 +Wire Wire Line + 7700 1850 8600 1850 +Connection ~ 9950 1850 +Wire Wire Line + 9950 1750 9950 2100 +Wire Wire Line + 7200 3100 7750 3100 +Wire Wire Line + 9200 3000 9200 3400 +Connection ~ 9200 3100 +Wire Wire Line + 8900 3100 9800 3100 +Wire Wire Line + 10950 3100 11700 3100 +Connection ~ 11150 3100 +Wire Wire Line + 11150 3000 11150 3400 +Wire Wire Line + 9750 1850 10400 1850 +Wire Wire Line + 10400 1850 10400 2500 +Wire Wire Line + 10400 2500 7200 2500 +Wire Wire Line + 7200 2500 7200 3100 +Wire Wire Line + 14350 4000 14750 4000 +Wire Wire Line + 14450 4950 14450 3550 +Connection ~ 14450 4000 +Wire Wire Line + 2550 4950 14450 4950 +Wire Wire Line + 2550 4950 2550 1850 +Wire Wire Line + 2550 1850 2750 1850 +Wire Wire Line + 13850 3100 14150 3100 +Wire Wire Line + 14150 3100 14150 2400 +Wire Wire Line + 14150 2400 14450 2400 +$Comp +L inverter U1 +U 1 1 5DDE38F5 +P 10500 5000 +F 0 "U1" H 13350 6800 60 0000 C CNN +F 1 "inverter" H 13350 7000 60 0000 C CNN +F 2 "" H 13350 6950 60 0000 C CNN +F 3 "" H 13350 6950 60 0000 C CNN + 1 10500 5000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml new file mode 100644 index 00000000..a1a22d60 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/Cmosinverter_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">pwl<field1 name="Enter in pwl format">0m 0 0.5m 5 50m 5 50.5m 0 100m 0 100.5m 5 150m 5 150.5m 0 200m 0</field1></v1><v1 name="Source type">dc<field1 name="Value">5</field1></v1></source><model><u9 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field1><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field3><field4 name="Enter value for in_low (default=1.0)" /></u9><u10 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u10><u1 name="type">inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)" /><field14 name="Enter Instance ID (Between 0-99)" /><field15 name="Enter the stop time to end the simulation (default=90e-9)" /></u1><u1 name="type">d_inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field13></u1><u27 name="type">inverter<field11 name="Enter Fall Delay (default=1.0e-9)">1.0e-3</field11><field12 name="Enter Input Load (default=1.0e-12)" /><field13 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field13><field14 name="Enter Instance ID (Between 0-99)" /><field15 name="Enter the stop time to end the simulation (default=90e-9)">200e-3</field15></u27><u35 name="type">inverter<field16 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field16><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field18><field19 name="Enter Instance ID (Between 0-99)" /><field20 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field20></u35><u26 name="type">inverter<field21 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field21><field22 name="Enter Input Load (default=1.0e-12)" /><field23 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field23><field24 name="Enter Instance ID (Between 0-99)" /><field25 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field25></u26><u19 name="type">inverter<field26 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field26><field27 name="Enter Input Load (default=1.0e-12)" /><field28 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field28><field29 name="Enter Instance ID (Between 0-99)" /><field30 name="Enter the stop time to end the simulation (default=90e-9)">50e-3</field30></u19><u13 name="type">inverter<field31 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field31><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field33><field34 name="Enter Instance ID (Between 0-99)" /><field35 name="Enter the stop time to end the simulation (default=90e-9)" /></u13><u11 name="type">adc_bridge<field41 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field41><field42 name="Enter value for in_high (default=2.0)" /><field43 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field43><field44 name="Enter value for in_low (default=1.0)" /></u11><u14 name="type">dac_bridge<field45 name="Enter value for input load (default=1.0e-12)" /><field46 name="Enter value for out_low (default=0.0)" /><field47 name="Enter value for out_high (default=5.0)" /><field48 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field48><field49 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field49><field50 name="Enter value for out_undef (default=0.5)" /></u14><u16 name="type">adc_bridge<field51 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field51><field52 name="Enter value for in_high (default=2.0)" /><field53 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field53><field54 name="Enter value for in_low (default=1.0)" /></u16><u20 name="type">dac_bridge<field55 name="Enter value for input load (default=1.0e-12)" /><field56 name="Enter value for out_low (default=0.0)" /><field57 name="Enter value for out_high (default=5.0)" /><field58 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field58><field59 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field59><field60 name="Enter value for out_undef (default=0.5)" /></u20><u22 name="type">adc_bridge<field61 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field61><field62 name="Enter value for in_high (default=2.0)" /><field63 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field63><field64 name="Enter value for in_low (default=1.0)" /></u22><u28 name="type">dac_bridge<field65 name="Enter value for input load (default=1.0e-12)" /><field66 name="Enter value for out_low (default=0.0)" /><field67 name="Enter value for out_high (default=5.0)" /><field68 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field68><field69 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field69><field70 name="Enter value for out_undef (default=0.5)" /></u28><u23 name="type">adc_bridge<field71 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field71><field72 name="Enter value for in_high (default=2.0)" /><field73 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field73><field74 name="Enter value for in_low (default=1.0)" /></u23><u18 name="type">dac_bridge<field75 name="Enter value for input load (default=1.0e-12)" /><field76 name="Enter value for out_low (default=0.0)" /><field77 name="Enter value for out_high (default=5.0)" /><field78 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field78><field79 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field79><field80 name="Enter value for out_undef (default=0.5)" /></u18><u31 name="type">adc_bridge<field81 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field81><field82 name="Enter value for in_high (default=2.0)" /><field83 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field83><field84 name="Enter value for in_low (default=1.0)" /></u31><u33 name="type">dac_bridge<field85 name="Enter value for input load (default=1.0e-12)" /><field86 name="Enter value for out_low (default=0.0)" /><field87 name="Enter value for out_high (default=5.0)" /><field88 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field88><field89 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field89><field90 name="Enter value for out_undef (default=0.5)" /></u33><u32 name="type">adc_bridge<field91 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field91><field92 name="Enter value for in_high (default=2.0)" /><field93 name="Enter Rise Delay (default=1.0e-9)">1.0e-6</field93><field94 name="Enter value for in_low (default=1.0)" /></u32><u29 name="type">dac_bridge<field95 name="Enter value for input load (default=1.0e-12)" /><field96 name="Enter value for out_low (default=0.0)" /><field97 name="Enter value for out_high (default=5.0)" /><field98 name="Enter the Rise Time (default=1.0e-9)">1.0e-6</field98><field99 name="Enter the Fall Time (default=1.0e-9)">1.0e-6</field99><field100 name="Enter value for out_undef (default=0.5)" /></u29><u25 name="type">test<field101 name="Enter Fall Delay (default=1.0e-9)">1.0e-6</field101><field102 name="Enter Input Load (default=1.0e-12)" /><field103 name="Enter Rise Delay (default=1.0e-9)" /><field104 name="Enter Instance ID (Between 0-99)" /><field105 name="Enter the stop time to end the simulation (default=90e-9)" /></u25></model><devicemodel /><subcircuit><x2><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x2><x3><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x3><x1><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x1><x6><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x6><x4><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x4><x5><field>/home/saurabh/Downloads/inverterCMOSsubcktFiles/INVCMOS</field></x5></subcircuit><analysis><ac><field1 name="Lin">false</field1><field2 name="Dec">true</field2><field3 name="Oct">false</field3><field4 name="Start Frequency">0</field4><field5 name="Stop Frequency">5k</field5><field6 name="No. of points">500</field6><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">200</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib new file mode 100644 index 00000000..cc25b0c9 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir new file mode 100644 index 00000000..44f1df81 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir @@ -0,0 +1,15 @@ +* /home/saurabh/Downloads/eSim-1.1.2/src/SubcircuitLibrary/INVCMOS/INVCMOS.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: Sun Aug 25 17:34:16 2019 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_M1-Pad2_ Net-_C1-Pad1_ PORT +M1 Net-_C1-Pad1_ Net-_M1-Pad2_ GND GND eSim_MOS_N +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_C1-Pad1_ Net-_M2-Pad1_ eSim_MOS_P +v1 Net-_M2-Pad1_ GND 5 +C1 Net-_C1-Pad1_ GND 1u + +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out new file mode 100644 index 00000000..cb2b6641 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.cir.out @@ -0,0 +1,18 @@ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +* u1 net-_m1-pad2_ net-_c1-pad1_ port +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +.tran 0e-03 0e-03 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro new file mode 100644 index 00000000..b3f410b6 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.pro @@ -0,0 +1,73 @@ +update=Sun Aug 25 15:54:56 2019 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=device +LibName23=transistors +LibName24=conn +LibName25=linear +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_User +LibName37=eSim_Plot +LibName38=eSim_PSpice +LibName39=/home/saurabh/Downloads/eSim-1.1.2/kicadSchematicLibrary/eSim_Subckt + diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch new file mode 100644 index 00000000..13a7fc09 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sch @@ -0,0 +1,189 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_User +LIBS:eSim_Plot +LIBS:eSim_PSpice +LIBS:eSim_Subckt +LIBS:INVCMOS-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 5900 4000 5900 4150 +Connection ~ 5800 2450 +Connection ~ 5800 4150 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5050 3350 +Wire Wire Line + 4000 3350 5050 3350 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 4200 3350 +$Comp +L PORT U1 +U 1 1 5D6263BC +P 3750 3350 +F 0 "U1" H 3800 3450 30 0000 C CNN +F 1 "PORT" H 3750 3350 30 0000 C CNN +F 2 "" H 3750 3350 60 0000 C CNN +F 3 "" H 3750 3350 60 0000 C CNN + 1 3750 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3250 5800 3250 +Connection ~ 5800 3250 +Wire Wire Line + 5800 4050 5800 4550 +$Comp +L eSim_MOS_N M1 +U 1 1 5D6265DB +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "eSim_MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_MOS_P M2 +U 1 1 5D626659 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "eSim_MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5900 2850 6050 2850 +Wire Wire Line + 6050 2850 6050 2450 +Wire Wire Line + 6050 2450 5800 2450 +Connection ~ 6000 3250 +Connection ~ 5800 4300 +$Comp +L GND #PWR1 +U 1 1 5D626C59 +P 5800 4550 +F 0 "#PWR1" H 5800 4300 50 0001 C CNN +F 1 "GND" H 5800 4400 50 0000 C CNN +F 2 "" H 5800 4550 50 0001 C CNN +F 3 "" H 5800 4550 50 0001 C CNN + 1 5800 4550 + 1 0 0 -1 +$EndComp +$Comp +L DC v1 +U 1 1 5D626C7F +P 6250 2300 +F 0 "v1" H 6050 2400 60 0000 C CNN +F 1 "5" H 6050 2250 60 0000 C CNN +F 2 "R1" H 5950 2300 60 0000 C CNN +F 3 "" H 6250 2300 60 0000 C CNN + 1 6250 2300 + 0 -1 -1 0 +$EndComp +$Comp +L GND #PWR2 +U 1 1 5D626CF6 +P 6850 2300 +F 0 "#PWR2" H 6850 2050 50 0001 C CNN +F 1 "GND" H 6850 2150 50 0000 C CNN +F 2 "" H 6850 2300 50 0001 C CNN +F 3 "" H 6850 2300 50 0001 C CNN + 1 6850 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6850 2300 6700 2300 +$Comp +L PORT U1 +U 2 1 5D626DCB +P 6300 3250 +F 0 "U1" H 6350 3350 30 0000 C CNN +F 1 "PORT" H 6300 3250 30 0000 C CNN +F 2 "" H 6300 3250 60 0000 C CNN +F 3 "" H 6300 3250 60 0000 C CNN + 2 6300 3250 + -1 0 0 1 +$EndComp +$Comp +L eSim_C C1 +U 1 1 5D62796C +P 6050 3850 +F 0 "C1" H 6075 3950 50 0000 L CNN +F 1 "1u" H 6075 3750 50 0000 L CNN +F 2 "" H 6088 3700 30 0000 C CNN +F 3 "" H 6050 3850 60 0000 C CNN + 1 6050 3850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6050 3700 6050 3400 +Wire Wire Line + 6050 3400 6000 3400 +Wire Wire Line + 6000 3400 6000 3250 +Wire Wire Line + 6050 4000 6050 4300 +Wire Wire Line + 6050 4300 5800 4300 +$EndSCHEMATC diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub new file mode 100644 index 00000000..2319995c --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS.sub @@ -0,0 +1,12 @@ +* Subcircuit INVCMOS +.subckt INVCMOS net-_m1-pad2_ net-_c1-pad1_ +* /home/saurabh/downloads/esim-1.1.2/src/subcircuitlibrary/invcmos/invcmos.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 net-_c1-pad1_ net-_m1-pad2_ gnd gnd CMOSN W=100u L=100u M=1 +m2 net-_m2-pad1_ net-_m1-pad2_ net-_c1-pad1_ net-_m2-pad1_ CMOSP W=100u L=100u M=1 +v1 net-_m2-pad1_ gnd 5 +c1 net-_c1-pad1_ gnd 1u +* Control Statements + +.ends INVCMOS
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml new file mode 100644 index 00000000..e5bb98c7 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/INVCMOS_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v1 name="Source type">5</v1></source><model /><devicemodel><m1><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/NMOS-180nm.lib</field><field /><field /><field /></m1><m2><field>/home/saurabh/Downloads/eSim-1.1.2/src/deviceModelLibrary/MOS/PMOS-180nm.lib</field><field /><field /><field /></m2></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">0</field2><field3 name="Stop Time">0</field3><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib b/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib b/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/Examples/NGHDL_Examples/Cmosinverter/analysis b/Examples/NGHDL_Examples/Cmosinverter/analysis new file mode 100644 index 00000000..a8e9dce2 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/analysis @@ -0,0 +1 @@ +.tran 10e-03 200e-03 0e-00
\ No newline at end of file diff --git a/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx b/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx new file mode 100644 index 00000000..15d7dd62 --- /dev/null +++ b/Examples/NGHDL_Examples/Cmosinverter/plot_data_i.tx @@ -0,0 +1,60 @@ + *for invcmos with delay 62000 nanosec, so cap should be 1nf + Transient Analysis Wed Oct 23 08:51:15 2019 +-------------------------------------------------------------------------------- +Index time a2#branch_1_0 v.x1.v1#branch v.x2.v1#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -8.10296e-12 -1.44365e-11 +1 1.000000e-09 -2.81078e-17 -8.10285e-12 -1.44365e-11 +2 1.002200e-09 2.173939e-01 -1.15227e-01 -2.74526e-05 +3 1.006600e-09 2.162815e-01 -1.13448e-01 -7.48490e-05 +4 1.010243e-09 2.184120e-01 -1.13038e-01 -1.11758e-04 +5 1.013853e-09 2.172991e-01 -1.11472e-01 -1.50114e-04 +6 1.021072e-09 2.204125e-01 -1.10247e-01 -2.25851e-04 +7 1.029746e-09 2.209561e-01 -1.07578e-01 -3.19174e-04 +8 1.037077e-09 2.251083e-01 -1.06654e-01 -4.00503e-04 +9 1.044524e-09 2.264092e-01 -1.04663e-01 -4.87674e-04 +10 1.052725e-09 2.323633e-01 -1.04138e-01 -5.90750e-04 +11 1.060435e-09 2.354511e-01 -1.02773e-01 -6.95387e-04 +12 1.069658e-09 2.439113e-01 -1.02939e-01 -8.29368e-04 +13 1.080335e-09 2.510799e-01 -1.02271e-01 -9.94574e-04 +14 1.094923e-09 2.663147e-01 -1.03510e-01 -1.23319e-03 +15 1.114447e-09 2.843269e-01 -1.04606e-01 -1.56812e-03 +16 1.144395e-09 3.179442e-01 -1.09102e-01 -2.10007e-03 +17 1.190797e-09 3.663899e-01 -1.15973e-01 -2.93245e-03 +18 1.283601e-09 5.487499e-01 -1.31536e-01 -4.33032e-03 +19 1.367572e-09 6.869171e-01 -1.43008e-01 -5.18245e-03 +20 1.468572e-09 6.638993e-01 -1.53553e-01 -5.94693e-03 +21 1.575043e-09 7.087558e-01 -1.61684e-01 -6.60929e-03 +22 1.744449e-09 7.155756e-01 -1.69761e-01 -7.32968e-03 +23 1.995252e-09 7.377316e-01 -1.76018e-01 -7.92003e-03 +24 2.000000e-09 7.498134e-01 -1.76074e-01 -7.92665e-03 +25 2.000968e-09 6.032277e-01 -1.20805e-01 -7.90845e-03 +26 2.002904e-09 5.301496e-01 -1.20018e-01 -7.87685e-03 +27 2.006775e-09 4.946923e-01 -1.18388e-01 -7.82068e-03 +28 2.014518e-09 4.093856e-01 -1.15275e-01 -7.72364e-03 +29 2.029459e-09 3.783576e-01 -1.09456e-01 -7.56518e-03 +30 2.047840e-09 3.325140e-01 -1.02789e-01 -7.38462e-03 +31 2.079088e-09 3.288911e-01 -9.24054e-02 -7.06326e-03 +32 2.128139e-09 2.842254e-01 -7.83721e-02 -6.48629e-03 +33 2.183865e-09 2.371959e-01 -6.50659e-02 -5.82424e-03 +34 2.248107e-09 1.818877e-01 -5.26591e-02 -5.10705e-03 +35 2.326304e-09 1.364069e-01 -4.06836e-02 -4.32089e-03 +36 2.396878e-09 9.925243e-02 -3.22625e-02 -3.68610e-03 +37 2.474793e-09 7.365848e-02 -2.49854e-02 -3.03297e-03 +38 2.547274e-09 4.389135e-02 -1.96751e-02 -2.45002e-03 +39 2.554737e-09 3.366325e-02 -1.91978e-02 -2.40654e-03 +40 2.565922e-09 4.044917e-02 -1.85142e-02 -2.34368e-03 +41 2.578642e-09 2.998465e-02 -1.77577e-02 -2.27518e-03 +42 2.604081e-09 3.565078e-02 -1.63497e-02 -2.14457e-03 +43 2.635687e-09 2.374005e-02 -1.47438e-02 -1.99289e-03 +44 2.690358e-09 2.761452e-02 -1.23454e-02 -1.75395e-03 +45 2.777848e-09 1.285724e-02 -9.27836e-03 -1.42710e-03 +46 2.952828e-09 1.360492e-02 -5.25991e-03 -9.35047e-04 +47 3.302787e-09 -2.04270e-03 -1.67270e-03 -3.75480e-04 +48 3.710524e-09 4.745747e-03 -7.00511e-04 -1.15819e-04 +49 4.291175e-09 -4.33351e-03 -4.91850e-04 -4.79768e-06 +50 4.826620e-09 4.345034e-03 -4.94953e-04 1.274213e-05 +51 5.608149e-09 -4.33393e-03 -4.92033e-04 1.737270e-05 +52 6.602216e-09 4.344829e-03 -4.94930e-04 1.719331e-05 +53 8.590352e-09 -4.33400e-03 -4.91980e-04 1.743737e-05 +54 1.256662e-08 4.344672e-03 -4.94826e-04 1.720508e-05 |