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-rwxr-xr-xExamples/Fullwavebridgerectifier/D.lib2
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier-cache.lib103
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.bak221
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir18
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir.out22
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro71
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.proj1
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.sch221
-rw-r--r--Examples/Fullwavebridgerectifier/Fullwavebridgerectifier_Previous_Values.xml1
-rw-r--r--Examples/Fullwavebridgerectifier/analysis1
-rw-r--r--Examples/Fullwavebridgerectifier/plot_data_i.txt75
-rw-r--r--Examples/Fullwavebridgerectifier/plot_data_v.txt75
12 files changed, 811 insertions, 0 deletions
diff --git a/Examples/Fullwavebridgerectifier/D.lib b/Examples/Fullwavebridgerectifier/D.lib
new file mode 100755
index 00000000..8a7fb4da
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/D.lib
@@ -0,0 +1,2 @@
+.model 1n4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04)
+
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier-cache.lib b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier-cache.lib
new file mode 100644
index 00000000..7f76da1a
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier-cache.lib
@@ -0,0 +1,103 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# D
+#
+DEF D D 0 40 N N 1 F N
+F0 "D" 0 100 50 H V C CNN
+F1 "D" 0 -100 50 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ Diode_*
+ D-Pak_TO252AA
+ *SingleDiode
+ *_Diode_*
+ *SingleDiode*
+$ENDFPLIST
+DRAW
+P 2 0 1 6 50 50 50 -50 N
+P 3 0 1 0 -50 50 50 0 -50 -50 F
+X A 1 -150 0 100 R 40 40 1 1 P
+X K 2 150 0 100 L 40 40 1 1 P
+ENDDRAW
+ENDDEF
+#
+# GND
+#
+DEF GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# R
+#
+DEF R R 0 0 N Y 1 F N
+F0 "R" 50 130 50 H V C CNN
+F1 "R" 50 50 50 H V C CNN
+F2 "" 50 -20 30 H V C CNN
+F3 "" 50 50 30 V V C CNN
+$FPLIST
+ R_*
+ Resistor_*
+$ENDFPLIST
+DRAW
+S 150 10 -50 90 0 1 10 N
+X ~ 1 -100 50 50 R 60 60 1 1 P
+X ~ 2 200 50 50 L 60 60 1 1 P
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# plot_v2
+#
+DEF plot_v2 U 0 40 Y Y 1 F N
+F0 "U" 0 400 60 H V C CNN
+F1 "plot_v2" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 250 100 0 1 0 N
+X + 1 -300 250 200 R 50 50 1 1 I
+X - 2 300 250 200 L 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+# sine
+#
+DEF sine v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "sine" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+A -50 0 50 1 1799 0 1 0 N 0 0 -100 0
+A 50 0 50 -1799 -1 0 1 0 N 0 0 100 0
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 0 1 1 I
+X - 2 0 -450 300 U 50 0 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.bak b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.bak
new file mode 100644
index 00000000..31e618c6
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.bak
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Plot
+LIBS:Fullwavebridgerectifier-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sine v1
+U 1 1 56A85DC5
+P 3400 3600
+F 0 "v1" H 3200 3700 60 0000 C CNN
+F 1 "sine" H 3200 3550 60 0000 C CNN
+F 2 "R1" H 3100 3600 60 0000 C CNN
+F 3 "" H 3400 3600 60 0000 C CNN
+ 1 3400 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L D D1
+U 1 1 56A85EED
+P 4200 2900
+F 0 "D1" H 4200 3000 50 0000 C CNN
+F 1 "D" H 4200 2800 50 0000 C CNN
+F 2 "" H 4200 2900 60 0000 C CNN
+F 3 "" H 4200 2900 60 0000 C CNN
+ 1 4200 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D3
+U 1 1 56A85F6E
+P 5000 2900
+F 0 "D3" H 5000 3000 50 0000 C CNN
+F 1 "D" H 5000 2800 50 0000 C CNN
+F 2 "" H 5000 2900 60 0000 C CNN
+F 3 "" H 5000 2900 60 0000 C CNN
+ 1 5000 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D2
+U 1 1 56A85FBD
+P 4200 4250
+F 0 "D2" H 4200 4350 50 0000 C CNN
+F 1 "D" H 4200 4150 50 0000 C CNN
+F 2 "" H 4200 4250 60 0000 C CNN
+F 3 "" H 4200 4250 60 0000 C CNN
+ 1 4200 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D4
+U 1 1 56A8602F
+P 5000 4250
+F 0 "D4" H 5000 4350 50 0000 C CNN
+F 1 "D" H 5000 4150 50 0000 C CNN
+F 2 "" H 5000 4250 60 0000 C CNN
+F 3 "" H 5000 4250 60 0000 C CNN
+ 1 5000 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L R R1
+U 1 1 56A860D7
+P 6050 3400
+F 0 "R1" H 6100 3530 50 0000 C CNN
+F 1 "1k" H 6100 3450 50 0000 C CNN
+F 2 "" H 6100 3380 30 0000 C CNN
+F 3 "" V 6100 3450 30 0000 C CNN
+ 1 6050 3400
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4200 2750 4200 2650
+Wire Wire Line
+ 4200 2650 6100 2650
+Wire Wire Line
+ 5000 2650 5000 2750
+Wire Wire Line
+ 4200 4100 4200 3050
+Wire Wire Line
+ 5000 4100 5000 3050
+Wire Wire Line
+ 4200 4400 4200 4500
+Wire Wire Line
+ 4200 4500 6100 4500
+Wire Wire Line
+ 5000 4500 5000 4400
+Wire Wire Line
+ 6100 2650 6100 3300
+Connection ~ 5000 2650
+Wire Wire Line
+ 6100 4500 6100 3600
+Connection ~ 5000 4500
+Wire Wire Line
+ 3400 3150 3700 3150
+Wire Wire Line
+ 3700 3150 3700 3400
+Wire Wire Line
+ 3700 3400 4200 3400
+Connection ~ 4200 3400
+Wire Wire Line
+ 3400 4050 3700 4050
+Wire Wire Line
+ 3700 4050 3700 3600
+Wire Wire Line
+ 3700 3600 5000 3600
+Connection ~ 5000 3600
+$Comp
+L GND #PWR1
+U 1 1 56A862E5
+P 5300 4650
+F 0 "#PWR1" H 5300 4400 50 0001 C CNN
+F 1 "GND" H 5300 4500 50 0000 C CNN
+F 2 "" H 5300 4650 50 0000 C CNN
+F 3 "" H 5300 4650 50 0000 C CNN
+ 1 5300 4650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 4650 5300 4500
+Connection ~ 5300 4500
+Text GLabel 3550 3050 1 60 Input ~ 0
+in1
+Text GLabel 3550 4150 3 60 Input ~ 0
+in2
+Text GLabel 5800 2500 2 60 Input ~ 0
+out
+Wire Wire Line
+ 3550 3050 3550 3150
+Connection ~ 3550 3150
+Wire Wire Line
+ 3550 4150 3550 4050
+Connection ~ 3550 4050
+Wire Wire Line
+ 5800 2500 5750 2500
+Wire Wire Line
+ 5750 2400 5750 2650
+Connection ~ 5750 2650
+Connection ~ 5750 2500
+Wire Wire Line
+ 2850 3250 2850 3100
+Wire Wire Line
+ 2850 3100 3550 3100
+Connection ~ 3550 3100
+Wire Wire Line
+ 2850 3850 2850 4100
+Wire Wire Line
+ 2850 4100 3550 4100
+Connection ~ 3550 4100
+$Comp
+L plot_v1 U2
+U 1 1 56D43D75
+P 5750 2600
+F 0 "U2" H 5750 3100 60 0000 C CNN
+F 1 "plot_v1" H 5950 2950 60 0000 C CNN
+F 2 "" H 5750 2600 60 0000 C CNN
+F 3 "" H 5750 2600 60 0000 C CNN
+ 1 5750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v2 U1
+U 1 1 56D43E45
+P 2600 3550
+F 0 "U1" H 2600 3950 60 0000 C CNN
+F 1 "plot_v2" H 2600 3650 60 0000 C CNN
+F 2 "" H 2600 3550 60 0000 C CNN
+F 3 "" H 2600 3550 60 0000 C CNN
+ 1 2600 3550
+ 0 1 1 0
+$EndComp
+$EndSCHEMATC
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir
new file mode 100644
index 00000000..6dacf87d
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir
@@ -0,0 +1,18 @@
+* /home/fossee/UpdatedExamples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 21:23:57 2016
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+v1 in1 in2 sine
+D1 in1 out D
+D3 in2 out D
+D2 GND in1 D
+D4 GND in2 D
+R1 out GND 1k
+U2 out plot_v1
+U1 in1 in2 plot_v2
+
+.end
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir.out b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir.out
new file mode 100644
index 00000000..d3cc7835
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.cir.out
@@ -0,0 +1,22 @@
+* /home/fossee/updatedexamples/fullwavebridgerectifier/fullwavebridgerectifier.cir
+
+.include D.lib
+v1 in1 in2 sine(0 5 50 0 0)
+d1 in1 out 1N4148
+d3 in2 out 1N4148
+d2 gnd in1 1N4148
+d4 gnd in2 1N4148
+r1 out gnd 1k
+* u2 out plot_v1
+* u1 in1 in2 plot_v2
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(out)
+plot v(in1,in2)
+.endc
+.end
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro
new file mode 100644
index 00000000..1dea64f7
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.pro
@@ -0,0 +1,71 @@
+update=Thu Jan 28 14:33:48 2016
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Power
+LibName7=eSim_Sources
+LibName8=eSim_Subckt
+LibName9=eSim_User
+LibName10=adc-dac
+LibName11=memory
+LibName12=xilinx
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=power
+LibName31=device
+LibName32=transistors
+LibName33=conn
+LibName34=linear
+LibName35=regul
+LibName36=74xx
+LibName37=cmos4000
+LibName38=/home/fossee/library/eSim_Plot
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.proj b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.proj
new file mode 100644
index 00000000..f7aed0bf
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.proj
@@ -0,0 +1 @@
+schematicFile Fullwavebridgerectifier.sch
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.sch b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.sch
new file mode 100644
index 00000000..d3840669
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier.sch
@@ -0,0 +1,221 @@
+EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:eSim_Plot
+LIBS:Fullwavebridgerectifier-cache
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L sine v1
+U 1 1 56A85DC5
+P 3400 3600
+F 0 "v1" H 3200 3700 60 0000 C CNN
+F 1 "sine" H 3200 3550 60 0000 C CNN
+F 2 "R1" H 3100 3600 60 0000 C CNN
+F 3 "" H 3400 3600 60 0000 C CNN
+ 1 3400 3600
+ 1 0 0 -1
+$EndComp
+$Comp
+L D D1
+U 1 1 56A85EED
+P 4200 2900
+F 0 "D1" H 4200 3000 50 0000 C CNN
+F 1 "D" H 4200 2800 50 0000 C CNN
+F 2 "" H 4200 2900 60 0000 C CNN
+F 3 "" H 4200 2900 60 0000 C CNN
+ 1 4200 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D3
+U 1 1 56A85F6E
+P 5000 2900
+F 0 "D3" H 5000 3000 50 0000 C CNN
+F 1 "D" H 5000 2800 50 0000 C CNN
+F 2 "" H 5000 2900 60 0000 C CNN
+F 3 "" H 5000 2900 60 0000 C CNN
+ 1 5000 2900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D2
+U 1 1 56A85FBD
+P 4200 4250
+F 0 "D2" H 4200 4350 50 0000 C CNN
+F 1 "D" H 4200 4150 50 0000 C CNN
+F 2 "" H 4200 4250 60 0000 C CNN
+F 3 "" H 4200 4250 60 0000 C CNN
+ 1 4200 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L D D4
+U 1 1 56A8602F
+P 5000 4250
+F 0 "D4" H 5000 4350 50 0000 C CNN
+F 1 "D" H 5000 4150 50 0000 C CNN
+F 2 "" H 5000 4250 60 0000 C CNN
+F 3 "" H 5000 4250 60 0000 C CNN
+ 1 5000 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L R R1
+U 1 1 56A860D7
+P 6050 3400
+F 0 "R1" H 6100 3530 50 0000 C CNN
+F 1 "1k" H 6100 3450 50 0000 C CNN
+F 2 "" H 6100 3380 30 0000 C CNN
+F 3 "" V 6100 3450 30 0000 C CNN
+ 1 6050 3400
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 4200 2750 4200 2650
+Wire Wire Line
+ 4200 2650 6100 2650
+Wire Wire Line
+ 5000 2650 5000 2750
+Wire Wire Line
+ 4200 4100 4200 3050
+Wire Wire Line
+ 5000 4100 5000 3050
+Wire Wire Line
+ 4200 4400 4200 4500
+Wire Wire Line
+ 4200 4500 6100 4500
+Wire Wire Line
+ 5000 4500 5000 4400
+Wire Wire Line
+ 6100 2650 6100 3300
+Connection ~ 5000 2650
+Wire Wire Line
+ 6100 4500 6100 3600
+Connection ~ 5000 4500
+Wire Wire Line
+ 3400 3150 3700 3150
+Wire Wire Line
+ 3700 3150 3700 3400
+Connection ~ 4200 3400
+Wire Wire Line
+ 3400 4050 3700 4050
+Wire Wire Line
+ 3700 4050 3700 3600
+Connection ~ 5000 3600
+$Comp
+L GND #PWR1
+U 1 1 56A862E5
+P 5300 4650
+F 0 "#PWR1" H 5300 4400 50 0001 C CNN
+F 1 "GND" H 5300 4500 50 0000 C CNN
+F 2 "" H 5300 4650 50 0000 C CNN
+F 3 "" H 5300 4650 50 0000 C CNN
+ 1 5300 4650
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 5300 4650 5300 4500
+Connection ~ 5300 4500
+Text GLabel 3550 3050 1 60 Input ~ 0
+in1
+Text GLabel 3550 4150 3 60 Input ~ 0
+in2
+Text GLabel 5800 2500 2 60 Input ~ 0
+out
+Wire Wire Line
+ 3550 3050 3550 3150
+Connection ~ 3550 3150
+Wire Wire Line
+ 3550 4150 3550 4050
+Connection ~ 3550 4050
+Wire Wire Line
+ 5800 2500 5750 2500
+Wire Wire Line
+ 5750 2400 5750 2650
+Connection ~ 5750 2650
+Connection ~ 5750 2500
+Wire Wire Line
+ 2850 3250 2850 3100
+Wire Wire Line
+ 2850 3100 3550 3100
+Connection ~ 3550 3100
+Wire Wire Line
+ 2850 3850 2850 4100
+Wire Wire Line
+ 2850 4100 3550 4100
+Connection ~ 3550 4100
+$Comp
+L plot_v1 U2
+U 1 1 56D43D75
+P 5750 2600
+F 0 "U2" H 5750 3100 60 0000 C CNN
+F 1 "plot_v1" H 5950 2950 60 0000 C CNN
+F 2 "" H 5750 2600 60 0000 C CNN
+F 3 "" H 5750 2600 60 0000 C CNN
+ 1 5750 2600
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v2 U1
+U 1 1 56D43E45
+P 2600 3550
+F 0 "U1" H 2600 3950 60 0000 C CNN
+F 1 "plot_v2" H 2600 3650 60 0000 C CNN
+F 2 "" H 2600 3550 60 0000 C CNN
+F 3 "" H 2600 3550 60 0000 C CNN
+ 1 2600 3550
+ 0 1 1 0
+$EndComp
+Wire Wire Line
+ 3700 3400 4200 3400
+Wire Wire Line
+ 3700 3600 5000 3600
+$EndSCHEMATC
diff --git a/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier_Previous_Values.xml b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier_Previous_Values.xml
new file mode 100644
index 00000000..3369ba77
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/Fullwavebridgerectifier_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><source><v1 name="Source type">sine<field1 name="Offset Value">0</field1><field2 name="Amplitude">5</field2><field3 name="Frequency">50</field3><field4 name="Delay Time">0</field4><field5 name="Damping Factor">0</field5></v1></source><model /><devicemodel><d4><field>/home/fossee/esim-updated/eSim/src/deviceModelLibrary/Diode/D.lib</field></d4><d2><field>/home/fossee/esim-updated/eSim/src/deviceModelLibrary/Diode/D.lib</field></d2><d3><field>/home/fossee/esim-updated/eSim/src/deviceModelLibrary/Diode/D.lib</field></d3><d1><field>/home/fossee/esim-updated/eSim/src/deviceModelLibrary/Diode/D.lib</field></d1></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice> \ No newline at end of file
diff --git a/Examples/Fullwavebridgerectifier/analysis b/Examples/Fullwavebridgerectifier/analysis
new file mode 100644
index 00000000..660a46cc
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/analysis
@@ -0,0 +1 @@
+.tran 10e-03 100e-03 0e-03 \ No newline at end of file
diff --git a/Examples/Fullwavebridgerectifier/plot_data_i.txt b/Examples/Fullwavebridgerectifier/plot_data_i.txt
new file mode 100644
index 00000000..3b1a6246
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/plot_data_i.txt
@@ -0,0 +1,75 @@
+* /home/fossee/updatedexamples/fullwavebridgerectifier/fullwavebridgerectifier.cir
+Transient Analysis Thu Mar 3 21:24:22 2016
+--------------------------------------------------------------------------------
+Index time alli
+--------------------------------------------------------------------------------
+0 0.000000e+00 -3.85186e-34
+1 1.000000e-05 -3.57806e-09
+2 2.000000e-05 -4.51526e-09
+3 4.000000e-05 -6.60386e-09
+4 8.000000e-05 -1.26852e-08
+5 1.600000e-04 -4.75219e-08
+6 3.200000e-04 -8.01226e-07
+7 6.400000e-04 -8.85271e-05
+8 1.026163e-03 -5.19805e-04
+9 1.655442e-03 -1.33749e-03
+10 2.298545e-03 -2.11673e-03
+11 3.584751e-03 -3.28650e-03
+12 5.584751e-03 -3.67800e-03
+13 7.584751e-03 -2.24626e-03
+14 9.584751e-03 -4.24121e-06
+15 1.109526e-02 6.082866e-04
+16 1.246929e-02 2.305998e-03
+17 1.410508e-02 3.568964e-03
+18 1.575154e-02 3.625220e-03
+19 1.775154e-02 2.059387e-03
+20 1.975154e-02 2.196050e-07
+21 2.099045e-02 -4.74545e-04
+22 2.218016e-02 -1.98045e-03
+23 2.350824e-02 -3.23506e-03
+24 2.499322e-02 -3.76069e-03
+25 2.699322e-02 -2.83716e-03
+26 2.899322e-02 -4.95271e-04
+27 3.067596e-02 1.184755e-04
+28 3.228544e-02 2.102320e-03
+29 3.393144e-02 3.488559e-03
+30 3.558694e-02 3.677814e-03
+31 3.758694e-02 2.244110e-03
+32 3.958694e-02 4.088871e-06
+33 4.065388e-02 -9.95947e-05
+34 4.167023e-02 -1.35614e-03
+35 4.280948e-02 -2.65330e-03
+36 4.407919e-02 -3.55777e-03
+37 4.607919e-02 -3.48280e-03
+38 4.807919e-02 -1.67071e-03
+39 5.007919e-02 1.505363e-08
+40 5.207919e-02 1.861636e-03
+41 5.407919e-02 3.558053e-03
+42 5.607919e-02 3.481944e-03
+43 5.807919e-02 1.670710e-03
+44 6.007919e-02 -1.40368e-08
+45 6.207919e-02 -1.86164e-03
+46 6.396337e-02 -3.50438e-03
+47 6.596337e-02 -3.53794e-03
+48 6.796337e-02 -1.81145e-03
+49 6.996337e-02 5.661852e-11
+50 7.161164e-02 1.281427e-03
+51 7.315451e-02 2.965167e-03
+52 7.515451e-02 3.755083e-03
+53 7.711563e-02 2.724870e-03
+54 7.911563e-02 3.433469e-04
+
+Index time alli
+--------------------------------------------------------------------------------
+55 8.075818e-02 -1.99167e-04
+56 8.231040e-02 -2.13032e-03
+57 8.403093e-02 -3.53596e-03
+58 8.572571e-02 -3.63420e-03
+59 8.772571e-02 -2.08887e-03
+60 8.972571e-02 -3.52804e-07
+61 9.134324e-02 9.317609e-04
+62 9.283257e-02 2.676375e-03
+63 9.462685e-02 3.727290e-03
+64 9.644440e-02 3.267211e-03
+65 9.844440e-02 1.209237e-03
+66 1.000000e-01 -6.09035e-09
diff --git a/Examples/Fullwavebridgerectifier/plot_data_v.txt b/Examples/Fullwavebridgerectifier/plot_data_v.txt
new file mode 100644
index 00000000..97711ed9
--- /dev/null
+++ b/Examples/Fullwavebridgerectifier/plot_data_v.txt
@@ -0,0 +1,75 @@
+* /home/fossee/updatedexamples/fullwavebridgerectifier/fullwavebridgerectifier.cir
+Transient Analysis Thu Mar 3 21:24:22 2016
+--------------------------------------------------------------------------------
+Index time in1 in2 out
+--------------------------------------------------------------------------------
+0 0.000000e+00 -1.02878e-18 -1.02878e-18 2.710884e-22
+1 1.000000e-05 7.854011e-03 -7.85393e-03 8.389384e-08
+2 2.000000e-05 1.570803e-02 -1.57077e-02 3.361913e-07
+3 4.000000e-05 3.141579e-02 -3.14144e-02 1.382156e-06
+4 8.000000e-05 6.282835e-02 -6.28221e-02 6.229084e-06
+5 1.600000e-04 1.256309e-01 -1.25591e-01 4.020326e-05
+6 3.200000e-04 2.513011e-01 -2.50507e-01 7.937111e-04
+7 6.400000e-04 5.435344e-01 -4.55016e-01 8.851888e-02
+8 1.026163e-03 1.051957e+00 -5.32161e-01 5.197952e-01
+9 1.655442e-03 1.911098e+00 -5.73617e-01 1.337482e+00
+10 2.298545e-03 2.710783e+00 -5.94062e-01 2.116720e+00
+11 3.584751e-03 3.900190e+00 -6.13695e-01 3.286495e+00
+12 5.584751e-03 4.296929e+00 -6.18939e-01 3.677991e+00
+13 7.584751e-03 2.843206e+00 -5.96950e-01 2.246256e+00
+14 9.584751e-03 3.273312e-01 -3.23091e-01 4.239839e-03
+15 1.109526e-02 -5.39198e-01 1.147479e+00 6.082813e-01
+16 1.246929e-02 -5.97639e-01 2.903625e+00 2.305986e+00
+17 1.410508e-02 -6.17364e-01 4.186325e+00 3.568962e+00
+18 1.575154e-02 -6.18036e-01 4.243248e+00 3.625212e+00
+19 1.775154e-02 -5.93004e-01 2.652393e+00 2.059389e+00
+20 1.975154e-02 -1.94832e-01 1.950470e-01 2.148331e-04
+21 2.099045e-02 1.002676e+00 -5.28139e-01 4.745379e-01
+22 2.218016e-02 2.571745e+00 -5.91301e-01 1.980444e+00
+23 2.350824e-02 3.847973e+00 -6.12922e-01 3.235052e+00
+24 2.499322e-02 4.380334e+00 -6.19655e-01 3.760679e+00
+25 2.699322e-02 3.444252e+00 -6.07088e-01 2.837164e+00
+26 2.899322e-02 1.025243e+00 -5.29974e-01 4.952690e-01
+27 3.067596e-02 -4.67681e-01 5.861527e-01 1.184713e-01
+28 3.228544e-02 -5.93533e-01 2.695840e+00 2.102307e+00
+29 3.393144e-02 -6.16172e-01 4.104730e+00 3.488558e+00
+30 3.558694e-02 -6.18717e-01 4.296522e+00 3.677805e+00
+31 3.758694e-02 -5.96775e-01 2.840888e+00 2.244113e+00
+32 3.958694e-02 -3.21466e-01 3.255492e-01 4.083027e-03
+33 4.065388e-02 5.597459e-01 -4.60158e-01 9.958758e-02
+34 4.167023e-02 1.930485e+00 -5.74358e-01 1.356126e+00
+35 4.280948e-02 3.257670e+00 -6.04371e-01 2.653299e+00
+36 4.407919e-02 4.175007e+00 -6.17241e-01 3.557766e+00
+37 4.607919e-02 4.099086e+00 -6.16287e-01 3.482799e+00
+38 4.807919e-02 2.254049e+00 -5.83338e-01 1.670711e+00
+39 5.007919e-02 -6.21896e-02 6.219594e-02 6.371741e-06
+40 5.207919e-02 -5.88509e-01 2.450138e+00 1.861629e+00
+41 5.407919e-02 -6.17101e-01 4.175147e+00 3.558045e+00
+42 5.607919e-02 -6.16716e-01 4.098657e+00 3.481941e+00
+43 5.807919e-02 -5.83340e-01 2.254047e+00 1.670707e+00
+44 6.007919e-02 6.219601e-02 -6.21895e-02 6.500126e-06
+45 6.207919e-02 2.450138e+00 -5.88509e-01 1.861629e+00
+46 6.396337e-02 4.120781e+00 -6.16404e-01 3.504378e+00
+47 6.596337e-02 4.155342e+00 -6.17408e-01 3.537935e+00
+48 6.796337e-02 2.398370e+00 -5.86917e-01 1.811453e+00
+49 6.996337e-02 2.877302e-02 -2.87718e-02 1.192263e-06
+50 7.161164e-02 -5.71682e-01 1.853100e+00 1.281418e+00
+51 7.315451e-02 -6.08881e-01 3.574041e+00 2.965160e+00
+52 7.515451e-02 -6.19516e-01 4.374595e+00 3.755079e+00
+53 7.711563e-02 -6.05406e-01 3.330273e+00 2.724867e+00
+54 7.911563e-02 -5.14007e-01 8.573536e-01 3.433465e-01
+
+Index time in1 in2 out
+--------------------------------------------------------------------------------
+55 8.075818e-02 6.894395e-01 -4.90276e-01 1.991635e-01
+56 8.231040e-02 2.724549e+00 -5.94243e-01 2.130306e+00
+57 8.403093e-02 4.153015e+00 -6.17057e-01 3.535959e+00
+58 8.572571e-02 4.252401e+00 -6.18214e-01 3.634187e+00
+59 8.772571e-02 2.682517e+00 -5.93640e-01 2.088877e+00
+60 8.972571e-02 2.153329e-01 -2.14987e-01 3.462796e-04
+61 9.134324e-02 -5.58069e-01 1.489819e+00 9.317501e-01
+62 9.283257e-02 -6.04304e-01 3.280673e+00 2.676369e+00
+63 9.462685e-02 -6.19200e-01 4.346483e+00 3.727283e+00
+64 9.644440e-02 -6.13397e-01 3.880607e+00 3.267209e+00
+65 9.844440e-02 -5.69096e-01 1.778330e+00 1.209234e+00
+66 1.000000e-01 -5.75202e-07 -5.75202e-07 -1.15031e-06