diff options
Diffstat (limited to 'Examples/CMOS_Inverter')
22 files changed, 1012 insertions, 0 deletions
diff --git a/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp b/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp Binary files differnew file mode 100644 index 00000000..f2abf69d --- /dev/null +++ b/Examples/CMOS_Inverter/.CMOS_Inverter.cir.out.swp diff --git a/Examples/CMOS_Inverter/CMOSN.lib b/Examples/CMOS_Inverter/CMOSN.lib new file mode 100644 index 00000000..93bdc23b --- /dev/null +++ b/Examples/CMOS_Inverter/CMOSN.lib @@ -0,0 +1,22 @@ +.model CMOSN NMOS( UB1=-7.61E-18 VSAT=9.366802E4 NFACTOR=2.4358891 CJSWG=3.3E-10 LINT=1.571424E-8 ++ WW=0 WR=1 WLN=1 PVAG=3.85243E-3 MJSW=0.1060414 ++ AGS=0.3939741 DSUB=0.0167075 LKETA=-0.0104078 LW=0 RDSW=105.5517558 ++ KETA=-5.180424E-4 CJSW=2.512138E-10 PRT=0 WL=0 LEVEL=8 ++ UA1=4.31E-9 XPART=0.5 PRDSW=-5 VERSION=3.2 VTH0=0.3823463 ++ B0=-6.413949E-9 B1=-1E-7 W0=1E-7 U0=280.633249 PRWG=0.5 ++ PRWB=-0.1998871 PVTH0=-1.192722E-3 VOFF=-0.0955434 DVT2W=0 NLX=1.910552E-7 ++ PB=0.8 LLN=1 PCLM=0.8073191 PK2=6.450505E-5 KT1L=0 ++ PVSAT=969.1480157 PETA0=1E-4 WINT=7.904732E-10 MJ=0.3864502 MOBMOD=1 ++ WWL=0 WWN=1 UA=-1.208537E-9 UC=5.342807E-11 DWG=1.297221E-9 ++ ETA0=3.104851E-3 TOX=4.1E-9 K3=0.0431669 K2=4.774618E-3 K1=0.5810697 ++ PDIBLCB=-0.1 CDSC=2.4E-4 PU0=6.3268729 DVT0W=0 CGBO=1E-12 ++ XJ=1E-7 CGDO=7.08E-10 XL=0 CF=0 PSCBE1=8E10 ++ CDSCB=0 CDSCD=0 XW=-1E-8 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PUA=2.226552E-11 PUB=0 ETAB=-2.512384E-5 TNOM=27 MJSWG=0.1060414 ++ CJ=9.68858E-4 WKETA=-4.27294E-4 CAPMOD=2 LWN=1 LWL=0 ++ CIT=0 PKETA=-1.049509E-3 CGSO=7.08E-10 LL=0 KT1=-0.11 ++ KT2=0.022 DROUT=0.7875618 A1=0 A0=1.7593146 A2=1 ++ UC1=-5.6E-11 UTE=-1.5 PBSWG=0.809286 K3B=1.1498346 DWB=1.479041E-9 ++ AT=3.3E4 PBSW=0.809286 UB=2.158625E-18 RSH=6.7 PSCBE2=9.213635E-10 ++ DVT1W=0 NCH=2.3549E17 DELTA=0.01 DVT2=0.0713729 DVT0=1.2894824 ++ DVT1=0.3622063 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/CMOSP.lib b/Examples/CMOS_Inverter/CMOSP.lib new file mode 100644 index 00000000..f2c89d2e --- /dev/null +++ b/Examples/CMOS_Inverter/CMOSP.lib @@ -0,0 +1,22 @@ +.model CMOSP PMOS( UB1=-7.61E-18 VSAT=1.329694E5 NFACTOR=1.9424315 CJSWG=4.22E-10 LINT=3.028832E-8 ++ WW=0 WR=1 WLN=1 PVAG=15 MJSW=0.3752089 ++ AGS=0.3641621 DSUB=0.7343015 LKETA=2.955547E-3 LW=0 RDSW=168.5705677 ++ KETA=0.0134667 CJSW=2.242609E-10 PRT=0 WL=0 LEVEL=8 ++ UA1=4.31E-9 XPART=0.5 PRDSW=11.5315407 VERSION=3.2 VTH0=-0.3938813 ++ B0=3.427126E-7 B1=1.062928E-6 W0=1E-6 U0=115.6852975 PRWG=0.5 ++ PRWB=-0.4987371 PVTH0=1.888482E-3 VOFF=-0.0994037 DVT2W=0 NLX=1.313191E-7 ++ PB=0.8421173 LLN=1 PCLM=3.2579974 PK2=1.559399E-3 KT1L=0 ++ PVSAT=50 PETA0=1E-4 WINT=0 MJ=0.4109788 MOBMOD=1 ++ WWL=0 WWN=1 UA=1.505832E-9 UC=-1E-10 DWG=-2.349633E-8 ++ ETA0=0.0608072 TOX=4.1E-9 K3=0.0993095 K2=0.0360586 K1=0.5479015 ++ PDIBLCB=-1E-3 CDSC=2.4E-4 PU0=-1.1105313 DVT0W=0 CGBO=1E-12 ++ XJ=1E-7 CGDO=6.32E-10 XL=0 CF=0 PSCBE1=1.454878E10 ++ CDSCB=0 CDSCD=0 XW=-1E-8 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 ++ PUA=-4.62102E-11 PUB=1E-21 ETAB=-0.0426148 TNOM=27 MJSWG=0.3752089 ++ CJ=1.172138E-3 WKETA=0.0319301 CAPMOD=2 LWN=1 LWL=0 ++ CIT=0 PKETA=-4.346368E-3 CGSO=6.32E-10 LL=0 KT1=-0.11 ++ KT2=0.022 DROUT=0 A1=0.6859506 A0=1.7590478 A2=0.3506788 ++ UC1=-5.6E-11 UTE=-1.5 PBSWG=0.8 K3B=5.7086622 DWB=-7.152486E-9 ++ AT=3.3E4 PBSW=0.8 UB=1E-21 RSH=7.8 PSCBE2=4.202027E-9 ++ DVT1W=0 NCH=4.1589E17 DELTA=0.01 DVT2=0.1 DVT0=0.4911363 ++ DVT1=0.2227356 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak b/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak new file mode 100644 index 00000000..40de879d --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter-cache.bak @@ -0,0 +1,118 @@ +EESchema-LIBRARY Version 2.3 Date: Tuesday 28 April 2015 10:53:44 PM IST +#encoding utf-8 +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 50 100 50 H V L CNN +F1 "C" 50 -100 50 H V L CNN +$FPLIST + SM* + C? + C1-1 +$ENDFPLIST +DRAW +P 2 0 1 10 -100 -30 100 -30 N +P 2 0 1 10 -100 30 100 30 N +X ~ 1 0 200 170 D 40 40 1 1 P +X ~ 2 0 -200 170 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N Q 0 0 N Y 1 F N +F0 "Q" 10 170 60 H V R CNN +F1 "MOS_N" 10 -150 60 H V R CNN +ALIAS MOSFET_N +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 8 100 -100 100 0 50 0 N +P 5 0 1 8 50 30 50 -30 0 0 50 30 50 30 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P Q 0 40 Y N 1 F N +F0 "Q" 0 190 60 H V R CNN +F1 "MOS_P" 0 -180 60 H V R CNN +ALIAS MOSFET_P +DRAW +P 2 0 1 8 -50 -100 -50 100 N +P 2 0 1 10 0 -150 0 150 N +P 2 0 1 8 30 0 0 0 N +P 2 0 1 0 100 -100 0 -100 N +P 2 0 1 0 100 100 0 100 N +P 3 0 1 0 80 0 100 0 100 -100 N +P 5 0 1 8 30 40 30 -30 80 0 30 40 30 40 N +X D D 100 200 100 D 40 40 1 1 P +X G G -200 0 150 R 40 40 1 1 I +X S S 100 -200 100 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 270 30 H I C CNN +F1 "PWR_FLAG" 0 230 30 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 3 0 1 0 0 0 0 100 0 100 N +P 5 0 1 0 0 100 -100 150 0 200 100 150 0 100 N +ENDDRAW +ENDDEF +# +# vplot8_1 +# +DEF vplot8_1 U 0 40 Y Y 8 F N +F0 "U" -150 100 50 H V C CNN +F1 "vplot8_1" 150 100 50 H V C CNN +DRAW +C 0 0 100 0 0 0 N +X + 1 0 -300 200 U 40 40 1 1 I +X + 2 0 -300 200 U 40 40 2 1 I +X + 3 0 -300 200 U 40 40 3 1 I +X + 4 0 -300 200 U 40 40 4 1 I +X + 5 0 -300 200 U 40 40 5 1 I +X + 6 0 -300 200 U 40 40 6 1 I +X + 7 0 -300 200 U 40 40 7 1 I +X + 8 0 -300 200 U 40 40 8 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib b/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib new file mode 100644 index 00000000..2c35750f --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter-cache.lib @@ -0,0 +1,136 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 0 +# +DEF 0 #GND 0 0 Y Y 1 F P +F0 "#GND" 0 -100 40 H I C CNN +F1 "0" 0 -70 40 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X 0 1 0 0 0 R 40 40 1 1 W N +ENDDRAW +ENDDEF +# +# C +# +DEF C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + C? + C_????_* + C_???? + SMD*_c + Capacitor* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# GND +# +DEF ~GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 0 30 H I C CNN +F1 "GND" 0 -70 30 H I C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +P 4 0 1 0 -50 0 0 -50 50 0 -50 0 N +X GND 1 0 0 0 U 30 30 1 1 W N +ENDDRAW +ENDDEF +# +# MOS_N +# +DEF MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 E +X G 2 -100 -200 210 R 50 50 1 1 I +X S 3 200 -400 100 U 50 50 1 1 C +X B 4 300 -350 98 U 47 47 1 1 I +ENDDRAW +ENDDEF +# +# MOS_P +# +DEF MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 C +X G 2 -150 0 210 R 50 50 1 1 I +X S 3 150 -200 100 U 50 50 1 1 E +X B 4 250 -150 100 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# PWR_FLAG +# +DEF PWR_FLAG #FLG 0 0 N N 1 F P +F0 "#FLG" 0 95 50 H I C CNN +F1 "PWR_FLAG" 0 180 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +X pwr 1 0 0 0 U 20 20 0 0 w +P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N +ENDDRAW +ENDDEF +# +# dc +# +DEF dc v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "dc" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.bak b/Examples/CMOS_Inverter/CMOS_Inverter.bak new file mode 100644 index 00000000..04c9e079 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.bak @@ -0,0 +1,208 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:sourcesSpice +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Devices +LIBS:CMOS_Inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5800 2400 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 4200 3350 +Wire Wire Line + 4200 3200 4200 3350 +Wire Wire Line + 6550 3300 6550 3550 +Wire Wire Line + 5800 1150 5800 1400 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 2900 3350 +Wire Wire Line + 2900 3100 2900 3550 +Wire Wire Line + 3100 3350 2900 3350 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 4000 3350 5050 3350 +Connection ~ 5050 3350 +Connection ~ 5800 3300 +Wire Wire Line + 6550 3850 6550 4400 +Wire Wire Line + 6550 4400 5800 4400 +Connection ~ 5800 4400 +Connection ~ 6300 3300 +Text GLabel 5900 2400 2 60 Input ~ 0 +vcc +Text GLabel 6300 3150 1 60 Input ~ 0 +out +Text GLabel 4200 3200 1 60 Input ~ 0 +in +$Comp +L C C1 +U 1 1 551BDFAE +P 6550 3700 +F 0 "C1" H 6600 3800 50 0000 L CNN +F 1 "1u" H 6600 3600 50 0000 L CNN +F 2 "" H 6550 3700 60 0001 C CNN +F 3 "" H 6550 3700 60 0001 C CNN + 1 6550 3700 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR01 +U 1 1 551BDA61 +P 5800 1150 +F 0 "#PWR01" H 5800 1150 30 0001 C CNN +F 1 "GND" H 5800 1080 30 0001 C CNN +F 2 "" H 5800 1150 60 0001 C CNN +F 3 "" H 5800 1150 60 0001 C CNN + 1 5800 1150 + -1 0 0 1 +$EndComp +$Comp +L GND #PWR02 +U 1 1 551BDA5A +P 5800 4700 +F 0 "#PWR02" H 5800 4700 30 0001 C CNN +F 1 "GND" H 5800 4630 30 0001 C CNN +F 2 "" H 5800 4700 60 0001 C CNN +F 3 "" H 5800 4700 60 0001 C CNN + 1 5800 4700 + 1 0 0 -1 +$EndComp +$Comp +L PWR_FLAG #FLG03 +U 1 1 54F86E05 +P 2900 3100 +F 0 "#FLG03" H 2900 3370 30 0001 C CNN +F 1 "PWR_FLAG" H 2900 3330 30 0000 C CNN +F 2 "" H 2900 3100 60 0001 C CNN +F 3 "" H 2900 3100 60 0001 C CNN + 1 2900 3100 + 1 0 0 -1 +$EndComp +$Comp +L GND #PWR04 +U 1 1 54F86DBA +P 2900 3550 +F 0 "#PWR04" H 2900 3550 30 0001 C CNN +F 1 "GND" H 2900 3480 30 0001 C CNN +F 2 "" H 2900 3550 60 0001 C CNN +F 3 "" H 2900 3550 60 0001 C CNN + 1 2900 3550 + 1 0 0 -1 +$EndComp +$Comp +L dc v1 +U 1 1 556C4B7E +P 3550 3350 +F 0 "v1" H 3350 3450 60 0000 C CNN +F 1 "dc" H 3350 3300 60 0000 C CNN +F 2 "R1" H 3250 3350 60 0000 C CNN +F 3 "" H 3550 3350 60 0000 C CNN + 1 3550 3350 + 0 1 1 0 +$EndComp +$Comp +L dc v2 +U 1 1 556C4BA7 +P 5800 1850 +F 0 "v2" H 5600 1950 60 0000 C CNN +F 1 "5" H 5600 1800 60 0000 C CNN +F 2 "R1" H 5500 1850 60 0000 C CNN +F 3 "" H 5800 1850 60 0000 C CNN + 1 5800 1850 + -1 0 0 1 +$EndComp +Wire Wire Line + 6300 3150 6300 3300 +Wire Wire Line + 5800 3300 6550 3300 +$Comp +L MOS_N M1 +U 1 1 556F0E6F +P 5600 3650 +F 0 "M1" H 5600 3500 50 0000 R CNN +F 1 "MOS_N" H 5700 3600 50 0000 R CNN +F 2 "" H 5900 3350 29 0000 C CNN +F 3 "" H 5700 3450 60 0000 C CNN + 1 5600 3650 + 1 0 0 -1 +$EndComp +$Comp +L MOS_P M2 +U 1 1 556F0EE6 +P 5650 2700 +F 0 "M2" H 5600 2750 50 0000 R CNN +F 1 "MOS_P" H 5700 2850 50 0000 R CNN +F 2 "" H 5900 2800 29 0000 C CNN +F 3 "" H 5700 2700 60 0000 C CNN + 1 5650 2700 + 1 0 0 1 +$EndComp +Wire Wire Line + 5800 4050 5800 4700 +Wire Wire Line + 5900 4150 5800 4150 +Connection ~ 5800 4150 +Connection ~ 5800 2450 +Wire Wire Line + 5900 4000 5900 4150 +Wire Wire Line + 5900 2550 5900 2450 +Wire Wire Line + 5900 2450 5800 2450 +$EndSCHEMATC diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir b/Examples/CMOS_Inverter/CMOS_Inverter.cir new file mode 100644 index 00000000..b435cd1c --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir @@ -0,0 +1,13 @@ +* EESchema Netlist Version 1.1 (Spice format) creation date: Fri Jun 12 12:25:06 2015 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +*Sheet Name:/ +C1 3 4 1u +v1 1 4 dc +v2 2 4 5 +M1 3 1 4 4 MOS_N +M2 3 1 2 2 MOS_P + +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt b/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt new file mode 100644 index 00000000..54d4aaa5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir.ckt @@ -0,0 +1,14 @@ +* eeschema netlist version 1.1 (spice format) creation date: wednesday 29 april 2015 05:48:14 pm ist +.include mos_n.lib +.include mos_p.lib + +v1 in gnd dc 5 +m2 out in gnd gnd mos_n M=100u L=100u W=100u +m1 out in vcc vcc mos_p M=100u L=100u W=100u +c1 out gnd 1u +v2 vcc gnd dc 5 +* Plotting option vplot8_1 + +.tran 10e-03 100e-03 0e-03 +.plot v(in) v(out) +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir.out b/Examples/CMOS_Inverter/CMOS_Inverter.cir.out new file mode 100644 index 00000000..318298d5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.cir.out @@ -0,0 +1,18 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 + +.include PMOS-5um.lib +.include NMOS-5um.lib +c1 out gnd 1u +v1 in gnd dc 5 +v2 vcc gnd 5 +m1 out in gnd gnd mos_n W=100u L=100u M=1 +m2 out in vcc vcc mos_p W=100u L=100u M=1 +.tran 10e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.pro b/Examples/CMOS_Inverter/CMOS_Inverter.pro new file mode 100644 index 00000000..2b819749 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.pro @@ -0,0 +1,42 @@ +update=Fri Jun 12 12:18:51 2015 +last_client=eeschema +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=power +LibName2=device +LibName3=transistors +LibName4=conn +LibName5=linear +LibName6=regul +LibName7=74xx +LibName8=cmos4000 +LibName9=adc-dac +LibName10=memory +LibName11=xilinx +LibName12=special +LibName13=microcontrollers +LibName14=dsp +LibName15=microchip +LibName16=analog_switches +LibName17=motorola +LibName18=texas +LibName19=intel +LibName20=audio +LibName21=interface +LibName22=digital-audio +LibName23=philips +LibName24=display +LibName25=cypress +LibName26=siliconi +LibName27=opto +LibName28=atmel +LibName29=contrib +LibName30=valves +LibName31=sourcesSpice +LibName32=/home/gaurav/Desktop/eSim Library/eSim_Analog +LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital +LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid +LibName35=/home/gaurav/Desktop/eSim Library/eSim_Devices +LibName36=/home/gaurav/pspice diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.proj b/Examples/CMOS_Inverter/CMOS_Inverter.proj new file mode 100644 index 00000000..f03822e4 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.proj @@ -0,0 +1 @@ +schematicFile CMOS_Inverter.sch diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.sch b/Examples/CMOS_Inverter/CMOS_Inverter.sch new file mode 100644 index 00000000..2829d5d5 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter.sch @@ -0,0 +1,249 @@ +EESchema Schematic File Version 2 +LIBS:power +LIBS:device +LIBS:transistors +LIBS:conn +LIBS:linear +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:special +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:valves +LIBS:sourcesSpice +LIBS:eSim_Analog +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Devices +LIBS:pspice +LIBS:CMOS_Inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "29 apr 2015" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Connection ~ 5800 2400 +Wire Wire Line + 5900 2400 5800 2400 +Connection ~ 4200 3350 +Wire Wire Line + 4200 3200 4200 3350 +Wire Wire Line + 6550 3300 6550 3550 +Wire Wire Line + 5800 1150 5800 1400 +Wire Wire Line + 5800 2500 5800 2300 +Connection ~ 2900 3350 +Wire Wire Line + 2900 3100 2900 3550 +Wire Wire Line + 3100 3350 2900 3350 +Wire Wire Line + 5800 3650 5800 2900 +Wire Wire Line + 5050 2700 5500 2700 +Wire Wire Line + 5050 2700 5050 3850 +Wire Wire Line + 5050 3850 5500 3850 +Wire Wire Line + 4000 3350 5050 3350 +Connection ~ 5050 3350 +Connection ~ 5800 3300 +Wire Wire Line + 6550 3850 6550 4400 +Wire Wire Line + 6550 4400 5800 4400 +Connection ~ 5800 4400 +Connection ~ 6300 3300 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"GND" H 5950 1230 30 0001 C CNN +F 2 "" H 5950 1300 60 0000 C CNN +F 3 "" H 5950 1300 60 0000 C CNN +F 4 "0" H 5950 1300 60 0001 C CNN "Value" + 1 5950 1300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5850 1300 5850 1250 +Wire Wire Line + 5850 1250 5950 1250 +Wire Wire Line + 5950 1250 5950 1300 +Wire Wire Line + 5850 1300 5800 1300 +$EndSCHEMATC diff --git a/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt b/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt new file mode 100644 index 00000000..5f3d6c29 --- /dev/null +++ b/Examples/CMOS_Inverter/CMOS_Inverter_last_input.txt @@ -0,0 +1,2 @@ +v1 in gnd dc 5 +v2 vcc gnd dc 5 diff --git a/Examples/CMOS_Inverter/NMOS-0.5um.lib b/Examples/CMOS_Inverter/NMOS-0.5um.lib new file mode 100755 index 00000000..2e6f4635 --- /dev/null +++ b/Examples/CMOS_Inverter/NMOS-0.5um.lib @@ -0,0 +1,6 @@ +.model mos_n NMOS( TPG=1 TOX=9.5n CJ=550u ETA=0.02125 VMAX=1.8E05 ++ GAMMA=0.62 CGSO=0.3n LD=50n MJSW=0.35 PB=1.1 ++ CGBO=0.45n XJ=0.2U CGDO=0.3n KAPPA=0.1 LEVEL=3 ++ VTO=0.6 NFS=7.20E11 THETA=0.23 CJSW=0.3n PHI=0.7 ++ RSH=2.0 MJ=0.6 UO=420 KP=156u DELTA=0.88 ++ NSUB=1.40E17 )
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/NMOS-5um.lib b/Examples/CMOS_Inverter/NMOS-5um.lib new file mode 100755 index 00000000..a237e1fe --- /dev/null +++ b/Examples/CMOS_Inverter/NMOS-5um.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/PMOS-5um.lib b/Examples/CMOS_Inverter/PMOS-5um.lib new file mode 100755 index 00000000..9c3ed976 --- /dev/null +++ b/Examples/CMOS_Inverter/PMOS-5um.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/analysis b/Examples/CMOS_Inverter/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/CMOS_Inverter/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file diff --git a/Examples/CMOS_Inverter/b3v3check.log b/Examples/CMOS_Inverter/b3v3check.log new file mode 100644 index 00000000..79783fe3 --- /dev/null +++ b/Examples/CMOS_Inverter/b3v3check.log @@ -0,0 +1,6 @@ +BSIM3 Model (Supports: v3.2, v3.2.2, v3.2.3, v3.2.4) +Parameter Checking. +Model = cmosn +W = 0.0001, L = 0.0001, M = 0.0001 +Warning: Pd = 0 is less than W. +Warning: Ps = 0 is less than W. diff --git a/Examples/CMOS_Inverter/mos_n.lib b/Examples/CMOS_Inverter/mos_n.lib new file mode 100644 index 00000000..a237e1fe --- /dev/null +++ b/Examples/CMOS_Inverter/mos_n.lib @@ -0,0 +1,5 @@ +* 5um technology + +.model mos_n NMOS( Cgso=0.4n Tox=85n Vto=1 phi=0.7 ++ Level=1 ++ Mj=.5 UO=750 Cgdo=0.4n Gamma=1.4 LAMBDA=0.01 LD=0.7u JS=1u CJ=0.4m CJSW=0.8n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/mos_p.lib b/Examples/CMOS_Inverter/mos_p.lib new file mode 100644 index 00000000..9c3ed976 --- /dev/null +++ b/Examples/CMOS_Inverter/mos_p.lib @@ -0,0 +1,5 @@ +*5um technology + +.model mos_p PMOS( Cgso=0.4n Tox=85n Vto=-1 phi=0.65 ++ Level=1 ++ Mj=.5 UO=250 Cgdo=0.4n Gamma=0.65 LAMBDA=0.03 LD=0.6u JS=1u CJ=0.18m CJSW=0.6n MJSW=0.5 PB=0.7 CGBO=0.2n ) diff --git a/Examples/CMOS_Inverter/plot_data_i.txt b/Examples/CMOS_Inverter/plot_data_i.txt new file mode 100644 index 00000000..d7d0eed7 --- /dev/null +++ b/Examples/CMOS_Inverter/plot_data_i.txt @@ -0,0 +1,67 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 +Transient Analysis Mon Jun 8 15:09:27 2015 +-------------------------------------------------------------------------------- +Index time v1#branch v2#branch +-------------------------------------------------------------------------------- +0 0.000000e+00 0.000000e+00 -5.01000e-12 +1 1.000000e-05 0.000000e+00 -5.01000e-12 +2 2.000000e-05 -3.65682e-22 -5.01000e-12 +3 4.000000e-05 -3.65269e-22 -5.01000e-12 +4 8.000000e-05 -1.82222e-22 -5.01000e-12 +5 1.600000e-04 -9.07020e-23 -5.01000e-12 +6 3.200000e-04 -4.49480e-23 -5.01000e-12 +7 6.400000e-04 -2.20827e-23 -5.01000e-12 +8 1.280000e-03 -1.06724e-23 -5.01000e-12 +9 2.560000e-03 -5.00782e-24 -5.01000e-12 +10 4.560000e-03 5.534460e-24 -5.01000e-12 +11 6.560000e-03 5.744371e-24 -5.01000e-12 +12 8.560000e-03 5.908101e-24 -5.01000e-12 +13 1.056000e-02 6.035806e-24 -5.01000e-12 +14 1.256000e-02 -4.82024e-25 -5.01000e-12 +15 1.456000e-02 2.904399e-24 -5.01000e-12 +16 1.656000e-02 2.965000e-24 -5.01000e-12 +17 1.856000e-02 3.012266e-24 -5.01000e-12 +18 2.056000e-02 3.049134e-24 -5.01000e-12 +19 2.256000e-02 3.077890e-24 -5.01000e-12 +20 2.456000e-02 3.100317e-24 -5.01000e-12 +21 2.656000e-02 3.117809e-24 -5.01000e-12 +22 2.856000e-02 3.131453e-24 -5.01000e-12 +23 3.056000e-02 3.142094e-24 -5.01000e-12 +24 3.256000e-02 3.150396e-24 -5.01000e-12 +25 3.456000e-02 3.156872e-24 -5.01000e-12 +26 3.656000e-02 3.161923e-24 -5.01000e-12 +27 3.856000e-02 3.165861e-24 -5.01000e-12 +28 4.056000e-02 3.168934e-24 -5.01000e-12 +29 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8.856000e-02 3.179802e-24 -5.01000e-12 +53 9.056000e-02 3.179808e-24 -5.01000e-12 +54 9.256000e-02 3.179811e-24 -5.01000e-12 + +Index time v1#branch v2#branch +-------------------------------------------------------------------------------- +55 9.456000e-02 3.179814e-24 -5.01000e-12 +56 9.656000e-02 3.179817e-24 -5.01000e-12 +57 9.856000e-02 3.179820e-24 -5.01000e-12 +58 1.000000e-01 3.129705e-24 -5.01000e-12 diff --git a/Examples/CMOS_Inverter/plot_data_v.txt b/Examples/CMOS_Inverter/plot_data_v.txt new file mode 100644 index 00000000..8c3925b3 --- /dev/null +++ b/Examples/CMOS_Inverter/plot_data_v.txt @@ -0,0 +1,67 @@ +* eeschema netlist version 1.1 (spice format) creation date: wed jun 3 14:55:15 2015 +Transient Analysis Mon Jun 8 15:09:27 2015 +-------------------------------------------------------------------------------- +Index time in out vcc +-------------------------------------------------------------------------------- +0 0.000000e+00 5.000000e+00 4.053196e-08 5.000000e+00 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4.053196e-08 5.000000e+00 + +Index time in out vcc +-------------------------------------------------------------------------------- +55 9.456000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +56 9.656000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +57 9.856000e-02 5.000000e+00 4.053196e-08 5.000000e+00 +58 1.000000e-01 5.000000e+00 4.053196e-08 5.000000e+00 |