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-rw-r--r--Examples/CMOS_Inverter/CMOS_Inverter.cir17
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diff --git a/Examples/CMOS_Inverter/CMOS_Inverter.cir b/Examples/CMOS_Inverter/CMOS_Inverter.cir
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--- a/Examples/CMOS_Inverter/CMOS_Inverter.cir
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-* /home/fossee/UpdatedExamples/CMOS_Inverter/CMOS_Inverter.cir
-
-* EESchema Netlist Version 1.1 (Spice format) creation date: Thu Mar 3 20:45:21 2016
-
-* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
-* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
-
-* Sheet Name: /
-v2 vcc GND 5
-M1 out in GND GND MOS_N
-M2 out in vcc vcc MOS_P
-U1 in plot_v1
-U2 out plot_v1
-C1 out GND 1u
-v1 in GND pwl
-
-.end