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-rw-r--r--Examples/BasicGates/BasicGates.cir.out44
1 files changed, 22 insertions, 22 deletions
diff --git a/Examples/BasicGates/BasicGates.cir.out b/Examples/BasicGates/BasicGates.cir.out
index 69c4d9ee..b0215f7b 100644
--- a/Examples/BasicGates/BasicGates.cir.out
+++ b/Examples/BasicGates/BasicGates.cir.out
@@ -1,26 +1,26 @@
-* eeschema netlist version 1.1 (spice format) creation date: mon jun 8 14:38:19 2015
+* /home/fossee/downloads/esim-master/examples/basicgates/basicgates.cir
-r3 8 0 1000
-r2 3 0 1000
-r1 7 0 1000
-* u2 12 6 5 d_and
-* u3 12 6 10 d_or
-* u4 5 10 1 d_nor
-* u5 5 10 9 d_nand
-* u6 1 11 d_inverter
-* u7 9 11 4 d_xor
-* u8 4 3 dac_bridge_1
-* u1 8 7 12 6 adc_bridge_2
-v2 8 0 pulse(0 5 0.1u 0.1u 0.1u 2u 20u)
-v1 7 0 pulse(5 0 0.1u 0.1u 0.1u 2u 20u)
-a1 [12 6 ] 5 u2
-a2 [12 6 ] 10 u3
-a3 [5 10 ] 1 u4
-a4 [5 10 ] 9 u5
-a5 1 11 u6
-a6 [9 11 ] 4 u7
-a7 [4 ] [3 ] u8
-a8 [8 7 ] [12 6 ] u1
+r3 in2 gnd 1000
+r2 out gnd 1000
+r1 in1 gnd 1000
+* u2 net-_u1-pad3_ net-_u1-pad4_ net-_u2-pad3_ d_and
+* u3 net-_u1-pad3_ net-_u1-pad4_ net-_u3-pad3_ d_or
+* u4 net-_u2-pad3_ net-_u3-pad3_ net-_u4-pad3_ d_nor
+* u5 net-_u2-pad3_ net-_u3-pad3_ net-_u5-pad3_ d_nand
+* u6 net-_u4-pad3_ net-_u6-pad2_ d_inverter
+* u7 net-_u5-pad3_ net-_u6-pad2_ net-_u7-pad3_ d_xor
+* u8 net-_u7-pad3_ out dac_bridge_1
+* u1 in2 in1 net-_u1-pad3_ net-_u1-pad4_ adc_bridge_2
+v2 in2 gnd pulse(0 5 0.1u 0.1u 0.1u 2u 20u)
+v1 in1 gnd pulse(5 0 0.1u 0.1u 0.1u 2u 20u)
+a1 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u2-pad3_ u2
+a2 [net-_u1-pad3_ net-_u1-pad4_ ] net-_u3-pad3_ u3
+a3 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u4-pad3_ u4
+a4 [net-_u2-pad3_ net-_u3-pad3_ ] net-_u5-pad3_ u5
+a5 net-_u4-pad3_ net-_u6-pad2_ u6
+a6 [net-_u5-pad3_ net-_u6-pad2_ ] net-_u7-pad3_ u7
+a7 [net-_u7-pad3_ ] [out ] u8
+a8 [in2 in1 ] [net-_u1-pad3_ net-_u1-pad4_ ] u1
* Schematic Name: d_and, NgSpice Name: d_and
.model u2 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
* Schematic Name: d_or, NgSpice Name: d_or