diff options
Diffstat (limited to 'Examples/Analysis_Of_Digital_IC/4028_test')
15 files changed, 1823 insertions, 0 deletions
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib new file mode 100644 index 00000000..4ba19fb8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028-cache.lib @@ -0,0 +1,94 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 26 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+X ~ 9 250 0 100 L 30 30 9 1 B
+X ~ 10 250 0 100 L 30 30 10 1 B
+X ~ 11 250 0 100 L 30 30 11 1 B
+X ~ 12 250 0 100 L 30 30 12 1 B
+X ~ 13 250 0 100 L 30 30 13 1 B
+X ~ 14 250 0 100 L 30 30 14 1 B
+X ~ 15 250 0 100 L 30 30 15 1 B
+X ~ 16 250 0 100 L 30 30 16 1 B
+X ~ 17 250 0 100 L 30 30 17 1 B
+X ~ 18 250 0 100 L 30 30 18 1 B
+X ~ 19 250 0 100 L 30 30 19 1 B
+X ~ 20 250 0 100 L 30 30 20 1 B
+X ~ 21 250 0 100 L 30 30 21 1 B
+X ~ 22 250 0 100 L 30 30 22 1 B
+X ~ 23 250 0 100 L 30 30 23 1 B
+X ~ 24 250 0 100 L 30 30 24 1 B
+X ~ 25 250 0 100 L 30 30 25 1 B
+X ~ 26 250 0 100 L 30 30 26 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0 150 -50 -250 -50 -250 150 150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_inverter
+#
+DEF d_inverter U 0 40 Y Y 1 F N
+F0 "U" 0 -100 60 H V C CNN
+F1 "d_inverter" 0 150 60 H V C CNN
+F2 "" 50 -50 60 H V C CNN
+F3 "" 50 -50 60 H V C CNN
+DRAW
+P 4 0 1 0 -100 50 -100 -50 100 0 -100 50 N
+X ~ 1 -300 0 200 R 50 50 1 1 I
+X ~ 2 300 0 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+# d_nor
+#
+DEF d_nor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_nor" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0 -250 -50 150 -50 N
+P 2 0 1 0 -250 150 150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir new file mode 100644 index 00000000..c13da65d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim\src\SubcircuitLibrary\4028\4028.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 05/31/19 16:24:30
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+U9 Net-_U1-Pad13_ Net-_U11-Pad1_ Net-_U16-Pad1_ d_nor
+U10 Net-_U1-Pad10_ Net-_U10-Pad2_ Net-_U10-Pad3_ d_nor
+U11 Net-_U11-Pad1_ Net-_U10-Pad2_ Net-_U11-Pad3_ d_nor
+U12 Net-_U1-Pad12_ Net-_U1-Pad11_ Net-_U12-Pad3_ d_nor
+U6 Net-_U4-Pad2_ Net-_U1-Pad11_ Net-_U13-Pad2_ d_nor
+U7 Net-_U1-Pad12_ Net-_U5-Pad2_ Net-_U14-Pad2_ d_nor
+U8 Net-_U1-Pad10_ Net-_U1-Pad13_ Net-_U14-Pad1_ d_nor
+U2 Net-_U1-Pad10_ Net-_U11-Pad1_ d_inverter
+U3 Net-_U1-Pad13_ Net-_U10-Pad2_ d_inverter
+U4 Net-_U1-Pad12_ Net-_U4-Pad2_ d_inverter
+U5 Net-_U1-Pad11_ Net-_U5-Pad2_ d_inverter
+U15 Net-_U14-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad3_ d_and
+U16 Net-_U16-Pad1_ Net-_U12-Pad3_ Net-_U1-Pad14_ d_and
+U17 Net-_U10-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad2_ d_and
+U18 Net-_U11-Pad3_ Net-_U12-Pad3_ Net-_U1-Pad15_ d_and
+U19 Net-_U14-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad1_ d_and
+U20 Net-_U16-Pad1_ Net-_U13-Pad2_ Net-_U1-Pad6_ d_and
+U21 Net-_U10-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad7_ d_and
+U13 Net-_U11-Pad3_ Net-_U13-Pad2_ Net-_U1-Pad4_ d_and
+U14 Net-_U14-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad9_ d_and
+U1 Net-_U1-Pad1_ Net-_U1-Pad2_ Net-_U1-Pad3_ Net-_U1-Pad4_ Net-_U1-Pad5_ Net-_U1-Pad6_ Net-_U1-Pad7_ ? Net-_U1-Pad9_ Net-_U1-Pad10_ Net-_U1-Pad11_ Net-_U1-Pad12_ Net-_U1-Pad13_ Net-_U1-Pad14_ Net-_U1-Pad15_ ? PORT
+U22 Net-_U16-Pad1_ Net-_U14-Pad2_ Net-_U1-Pad5_ d_and
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out new file mode 100644 index 00000000..93e14b93 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.cir.out @@ -0,0 +1,96 @@ +* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u1 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ? port
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+.tran 0e-00 0e-00 0e-00
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro new file mode 100644 index 00000000..6f7acdde --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.pro @@ -0,0 +1,43 @@ +update=05/31/19 15:43:40
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../../kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=eSim_Analog
+LibName2=eSim_Devices
+LibName3=eSim_Digital
+LibName4=eSim_Hybrid
+LibName5=eSim_Miscellaneous
+LibName6=eSim_Plot
+LibName7=eSim_Power
+LibName8=eSim_Sources
+LibName9=eSim_Subckt
+LibName10=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch new file mode 100644 index 00000000..a487c693 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sch @@ -0,0 +1,628 @@ +EESchema Schematic File Version 2
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_nor U9
+U 1 1 5CF0FE64
+P 3750 2500
+F 0 "U9" H 3750 2500 60 0000 C CNN
+F 1 "d_nor" H 3800 2600 60 0000 C CNN
+F 2 "" H 3750 2500 60 0000 C CNN
+F 3 "" H 3750 2500 60 0000 C CNN
+ 1 3750 2500
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U10
+U 1 1 5CF0FEA4
+P 3750 3050
+F 0 "U10" H 3750 3050 60 0000 C CNN
+F 1 "d_nor" H 3800 3150 60 0000 C CNN
+F 2 "" H 3750 3050 60 0000 C CNN
+F 3 "" H 3750 3050 60 0000 C CNN
+ 1 3750 3050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U11
+U 1 1 5CF0FECC
+P 3750 3550
+F 0 "U11" H 3750 3550 60 0000 C CNN
+F 1 "d_nor" H 3800 3650 60 0000 C CNN
+F 2 "" H 3750 3550 60 0000 C CNN
+F 3 "" H 3750 3550 60 0000 C CNN
+ 1 3750 3550
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U12
+U 1 1 5CF0FEF5
+P 3750 4150
+F 0 "U12" H 3750 4150 60 0000 C CNN
+F 1 "d_nor" H 3800 4250 60 0000 C CNN
+F 2 "" H 3750 4150 60 0000 C CNN
+F 3 "" H 3750 4150 60 0000 C CNN
+ 1 3750 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U6
+U 1 1 5CF0FF23
+P 3700 4750
+F 0 "U6" H 3700 4750 60 0000 C CNN
+F 1 "d_nor" H 3750 4850 60 0000 C CNN
+F 2 "" H 3700 4750 60 0000 C CNN
+F 3 "" H 3700 4750 60 0000 C CNN
+ 1 3700 4750
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U7
+U 1 1 5CF0FF59
+P 3700 5250
+F 0 "U7" H 3700 5250 60 0000 C CNN
+F 1 "d_nor" H 3750 5350 60 0000 C CNN
+F 2 "" H 3700 5250 60 0000 C CNN
+F 3 "" H 3700 5250 60 0000 C CNN
+ 1 3700 5250
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_nor U8
+U 1 1 5CF0FFA9
+P 3750 2000
+F 0 "U8" H 3750 2000 60 0000 C CNN
+F 1 "d_nor" H 3800 2100 60 0000 C CNN
+F 2 "" H 3750 2000 60 0000 C CNN
+F 3 "" H 3750 2000 60 0000 C CNN
+ 1 3750 2000
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U2
+U 1 1 5CF1003A
+P 2150 2400
+F 0 "U2" H 2150 2300 60 0000 C CNN
+F 1 "d_inverter" H 2150 2550 60 0000 C CNN
+F 2 "" H 2200 2350 60 0000 C CNN
+F 3 "" H 2200 2350 60 0000 C CNN
+ 1 2150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U3
+U 1 1 5CF1007F
+P 2150 3300
+F 0 "U3" H 2150 3200 60 0000 C CNN
+F 1 "d_inverter" H 2150 3450 60 0000 C CNN
+F 2 "" H 2200 3250 60 0000 C CNN
+F 3 "" H 2200 3250 60 0000 C CNN
+ 1 2150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U4
+U 1 1 5CF100CC
+P 2150 4150
+F 0 "U4" H 2150 4050 60 0000 C CNN
+F 1 "d_inverter" H 2150 4300 60 0000 C CNN
+F 2 "" H 2200 4100 60 0000 C CNN
+F 3 "" H 2200 4100 60 0000 C CNN
+ 1 2150 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_inverter U5
+U 1 1 5CF10114
+P 2150 4900
+F 0 "U5" H 2150 4800 60 0000 C CNN
+F 1 "d_inverter" H 2150 5050 60 0000 C CNN
+F 2 "" H 2200 4850 60 0000 C CNN
+F 3 "" H 2200 4850 60 0000 C CNN
+ 1 2150 4900
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 1400 2400 1850 2400
+Wire Wire Line
+ 1400 3300 1850 3300
+Wire Wire Line
+ 1450 4150 1850 4150
+Wire Wire Line
+ 1450 4900 1850 4900
+Wire Wire Line
+ 2450 4900 2500 4900
+Wire Wire Line
+ 2500 4900 2500 5250
+Wire Wire Line
+ 2500 5250 3250 5250
+Wire Wire Line
+ 2450 4150 2550 4150
+Wire Wire Line
+ 2550 4150 2550 4650
+Wire Wire Line
+ 2550 4650 3250 4650
+Wire Wire Line
+ 2450 3300 2550 3300
+Wire Wire Line
+ 2550 3300 2550 3550
+Wire Wire Line
+ 2550 3550 3300 3550
+Wire Wire Line
+ 2450 2400 2450 2500
+Wire Wire Line
+ 2450 2500 3300 2500
+Wire Wire Line
+ 2800 2500 2800 3450
+Wire Wire Line
+ 2800 3450 3300 3450
+Connection ~ 2800 2500
+Wire Wire Line
+ 1650 2400 1650 1900
+Wire Wire Line
+ 1650 1900 3300 1900
+Connection ~ 1650 2400
+Wire Wire Line
+ 3300 2000 2850 2000
+Wire Wire Line
+ 2850 2000 2850 3000
+Wire Wire Line
+ 2850 3000 1650 3000
+Wire Wire Line
+ 1650 3000 1650 3300
+Connection ~ 1650 3300
+Wire Wire Line
+ 2850 2400 3300 2400
+Connection ~ 2850 2400
+Wire Wire Line
+ 2950 1900 2950 2950
+Wire Wire Line
+ 2950 2950 3300 2950
+Connection ~ 2950 1900
+Wire Wire Line
+ 3100 3550 3100 3050
+Wire Wire Line
+ 3100 3050 3300 3050
+Connection ~ 3100 3550
+Wire Wire Line
+ 1650 3900 1650 4150
+Wire Wire Line
+ 1650 3900 3050 3900
+Wire Wire Line
+ 3050 3900 3050 5150
+Wire Wire Line
+ 3050 4050 3300 4050
+Connection ~ 1650 4150
+Wire Wire Line
+ 1750 4900 1750 5150
+Wire Wire Line
+ 1750 5150 2750 5150
+Connection ~ 1750 4900
+Wire Wire Line
+ 2750 5150 2750 4150
+Wire Wire Line
+ 2750 4150 3300 4150
+Wire Wire Line
+ 2750 4750 3250 4750
+Connection ~ 2750 4750
+Wire Wire Line
+ 3050 5150 3250 5150
+Connection ~ 3050 4050
+$Comp
+L d_and U15
+U 1 1 5CF106B1
+P 6600 1850
+F 0 "U15" H 6600 1850 60 0000 C CNN
+F 1 "d_and" H 6650 1950 60 0000 C CNN
+F 2 "" H 6600 1850 60 0000 C CNN
+F 3 "" H 6600 1850 60 0000 C CNN
+ 1 6600 1850
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U16
+U 1 1 5CF10756
+P 6600 2350
+F 0 "U16" H 6600 2350 60 0000 C CNN
+F 1 "d_and" H 6650 2450 60 0000 C CNN
+F 2 "" H 6600 2350 60 0000 C CNN
+F 3 "" H 6600 2350 60 0000 C CNN
+ 1 6600 2350
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U17
+U 1 1 5CF107A1
+P 6600 2800
+F 0 "U17" H 6600 2800 60 0000 C CNN
+F 1 "d_and" H 6650 2900 60 0000 C CNN
+F 2 "" H 6600 2800 60 0000 C CNN
+F 3 "" H 6600 2800 60 0000 C CNN
+ 1 6600 2800
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U18
+U 1 1 5CF107E9
+P 6600 3200
+F 0 "U18" H 6600 3200 60 0000 C CNN
+F 1 "d_and" H 6650 3300 60 0000 C CNN
+F 2 "" H 6600 3200 60 0000 C CNN
+F 3 "" H 6600 3200 60 0000 C CNN
+ 1 6600 3200
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U19
+U 1 1 5CF10834
+P 6600 3650
+F 0 "U19" H 6600 3650 60 0000 C CNN
+F 1 "d_and" H 6650 3750 60 0000 C CNN
+F 2 "" H 6600 3650 60 0000 C CNN
+F 3 "" H 6600 3650 60 0000 C CNN
+ 1 6600 3650
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U20
+U 1 1 5CF1087E
+P 6600 4050
+F 0 "U20" H 6600 4050 60 0000 C CNN
+F 1 "d_and" H 6650 4150 60 0000 C CNN
+F 2 "" H 6600 4050 60 0000 C CNN
+F 3 "" H 6600 4050 60 0000 C CNN
+ 1 6600 4050
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U21
+U 1 1 5CF108F9
+P 6600 4450
+F 0 "U21" H 6600 4450 60 0000 C CNN
+F 1 "d_and" H 6650 4550 60 0000 C CNN
+F 2 "" H 6600 4450 60 0000 C CNN
+F 3 "" H 6600 4450 60 0000 C CNN
+ 1 6600 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U13
+U 1 1 5CF1094D
+P 6550 4900
+F 0 "U13" H 6550 4900 60 0000 C CNN
+F 1 "d_and" H 6600 5000 60 0000 C CNN
+F 2 "" H 6550 4900 60 0000 C CNN
+F 3 "" H 6550 4900 60 0000 C CNN
+ 1 6550 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L d_and U14
+U 1 1 5CF109A6
+P 6550 5350
+F 0 "U14" H 6550 5350 60 0000 C CNN
+F 1 "d_and" H 6600 5450 60 0000 C CNN
+F 2 "" H 6550 5350 60 0000 C CNN
+F 3 "" H 6550 5350 60 0000 C CNN
+ 1 6550 5350
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 10 1 5CF11966
+P 1150 2400
+F 0 "U1" H 1200 2500 30 0000 C CNN
+F 1 "PORT" H 1150 2400 30 0000 C CNN
+F 2 "" H 1150 2400 60 0000 C CNN
+F 3 "" H 1150 2400 60 0000 C CNN
+ 10 1150 2400
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 13 1 5CF119D4
+P 1150 3300
+F 0 "U1" H 1200 3400 30 0000 C CNN
+F 1 "PORT" H 1150 3300 30 0000 C CNN
+F 2 "" H 1150 3300 60 0000 C CNN
+F 3 "" H 1150 3300 60 0000 C CNN
+ 13 1150 3300
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 12 1 5CF11AFC
+P 1200 4150
+F 0 "U1" H 1250 4250 30 0000 C CNN
+F 1 "PORT" H 1200 4150 30 0000 C CNN
+F 2 "" H 1200 4150 60 0000 C CNN
+F 3 "" H 1200 4150 60 0000 C CNN
+ 12 1200 4150
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 11 1 5CF11B6B
+P 1200 4900
+F 0 "U1" H 1250 5000 30 0000 C CNN
+F 1 "PORT" H 1200 4900 30 0000 C CNN
+F 2 "" H 1200 4900 60 0000 C CNN
+F 3 "" H 1200 4900 60 0000 C CNN
+ 11 1200 4900
+ 1 0 0 -1
+$EndComp
+$Comp
+L PORT U1
+U 3 1 5CF11BDB
+P 8000 1800
+F 0 "U1" H 8050 1900 30 0000 C CNN
+F 1 "PORT" H 8000 1800 30 0000 C CNN
+F 2 "" H 8000 1800 60 0000 C CNN
+F 3 "" H 8000 1800 60 0000 C CNN
+ 3 8000 1800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 14 1 5CF11F59
+P 8000 2300
+F 0 "U1" H 8050 2400 30 0000 C CNN
+F 1 "PORT" H 8000 2300 30 0000 C CNN
+F 2 "" H 8000 2300 60 0000 C CNN
+F 3 "" H 8000 2300 60 0000 C CNN
+ 14 8000 2300
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 2 1 5CF11FC5
+P 8000 2750
+F 0 "U1" H 8050 2850 30 0000 C CNN
+F 1 "PORT" H 8000 2750 30 0000 C CNN
+F 2 "" H 8000 2750 60 0000 C CNN
+F 3 "" H 8000 2750 60 0000 C CNN
+ 2 8000 2750
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 15 1 5CF1204F
+P 8000 3150
+F 0 "U1" H 8050 3250 30 0000 C CNN
+F 1 "PORT" H 8000 3150 30 0000 C CNN
+F 2 "" H 8000 3150 60 0000 C CNN
+F 3 "" H 8000 3150 60 0000 C CNN
+ 15 8000 3150
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 1 1 5CF120C5
+P 7950 3600
+F 0 "U1" H 8000 3700 30 0000 C CNN
+F 1 "PORT" H 7950 3600 30 0000 C CNN
+F 2 "" H 7950 3600 60 0000 C CNN
+F 3 "" H 7950 3600 60 0000 C CNN
+ 1 7950 3600
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 6 1 5CF1213C
+P 7950 4000
+F 0 "U1" H 8000 4100 30 0000 C CNN
+F 1 "PORT" H 7950 4000 30 0000 C CNN
+F 2 "" H 7950 4000 60 0000 C CNN
+F 3 "" H 7950 4000 60 0000 C CNN
+ 6 7950 4000
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 7 1 5CF121B2
+P 7900 4400
+F 0 "U1" H 7950 4500 30 0000 C CNN
+F 1 "PORT" H 7900 4400 30 0000 C CNN
+F 2 "" H 7900 4400 60 0000 C CNN
+F 3 "" H 7900 4400 60 0000 C CNN
+ 7 7900 4400
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 4 1 5CF1223D
+P 7900 4850
+F 0 "U1" H 7950 4950 30 0000 C CNN
+F 1 "PORT" H 7900 4850 30 0000 C CNN
+F 2 "" H 7900 4850 60 0000 C CNN
+F 3 "" H 7900 4850 60 0000 C CNN
+ 4 7900 4850
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 9 1 5CF1237B
+P 7900 5300
+F 0 "U1" H 7950 5400 30 0000 C CNN
+F 1 "PORT" H 7900 5300 30 0000 C CNN
+F 2 "" H 7900 5300 60 0000 C CNN
+F 3 "" H 7900 5300 60 0000 C CNN
+ 9 7900 5300
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7750 1800 7050 1800
+Wire Wire Line
+ 7050 2300 7750 2300
+Wire Wire Line
+ 7750 2750 7050 2750
+Wire Wire Line
+ 7050 3150 7750 3150
+Wire Wire Line
+ 7700 3600 7050 3600
+Wire Wire Line
+ 7050 4000 7700 4000
+Wire Wire Line
+ 7650 4400 7050 4400
+Wire Wire Line
+ 7000 4850 7650 4850
+Wire Wire Line
+ 7650 5300 7000 5300
+$Comp
+L d_and U22
+U 1 1 5CF14904
+P 6550 5800
+F 0 "U22" H 6550 5800 60 0000 C CNN
+F 1 "d_and" H 6600 5900 60 0000 C CNN
+F 2 "" H 6550 5800 60 0000 C CNN
+F 3 "" H 6550 5800 60 0000 C CNN
+ 1 6550 5800
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 4200 1950 4600 1950
+Wire Wire Line
+ 4600 1750 4600 5250
+Wire Wire Line
+ 4600 1750 6150 1750
+Wire Wire Line
+ 4600 5250 6100 5250
+Connection ~ 4600 1950
+Wire Wire Line
+ 6100 5800 5900 5800
+Wire Wire Line
+ 5900 5800 5900 5350
+Wire Wire Line
+ 5900 5350 6100 5350
+Wire Wire Line
+ 5850 4900 6100 4900
+Wire Wire Line
+ 5850 3650 5850 4900
+Wire Wire Line
+ 5850 4450 6150 4450
+Wire Wire Line
+ 5850 4050 6150 4050
+Connection ~ 5850 4450
+Wire Wire Line
+ 5850 3650 6150 3650
+Connection ~ 5850 4050
+Wire Wire Line
+ 5050 3200 6150 3200
+Wire Wire Line
+ 5850 1850 5850 3200
+Wire Wire Line
+ 5850 2800 6150 2800
+Wire Wire Line
+ 5850 2350 6150 2350
+Connection ~ 5850 2800
+Wire Wire Line
+ 5850 1850 6150 1850
+Connection ~ 5850 2350
+Wire Wire Line
+ 4200 2450 4700 2450
+Wire Wire Line
+ 4700 2250 4700 5700
+Wire Wire Line
+ 4700 2250 6150 2250
+Wire Wire Line
+ 4200 3000 4800 3000
+Wire Wire Line
+ 4800 2700 4800 4350
+Wire Wire Line
+ 4800 2700 6150 2700
+Wire Wire Line
+ 4700 5700 6100 5700
+Connection ~ 4700 2450
+Wire Wire Line
+ 6150 3550 4600 3550
+Connection ~ 4600 3550
+Wire Wire Line
+ 6150 3950 4700 3950
+Connection ~ 4700 3950
+Wire Wire Line
+ 4800 4350 6150 4350
+Connection ~ 4800 3000
+Wire Wire Line
+ 4200 3500 4900 3500
+Wire Wire Line
+ 4900 3100 4900 4800
+Wire Wire Line
+ 4900 3100 6150 3100
+Wire Wire Line
+ 4900 4800 6100 4800
+Connection ~ 4900 3500
+Wire Wire Line
+ 4200 4100 5050 4100
+Wire Wire Line
+ 5050 4100 5050 3200
+Connection ~ 5850 3200
+Wire Wire Line
+ 4150 4700 5850 4700
+Connection ~ 5850 4700
+Wire Wire Line
+ 4150 5200 4500 5200
+Wire Wire Line
+ 4500 5200 4500 5550
+Wire Wire Line
+ 4500 5550 5900 5550
+Connection ~ 5900 5550
+$Comp
+L PORT U1
+U 5 1 5CF1563E
+P 7950 5750
+F 0 "U1" H 8000 5850 30 0000 C CNN
+F 1 "PORT" H 7950 5750 30 0000 C CNN
+F 2 "" H 7950 5750 60 0000 C CNN
+F 3 "" H 7950 5750 60 0000 C CNN
+ 5 7950 5750
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 7700 5750 7000 5750
+$Comp
+L PORT U1
+U 8 1 5CF15953
+P 9550 4800
+F 0 "U1" H 9600 4900 30 0000 C CNN
+F 1 "PORT" H 9550 4800 30 0000 C CNN
+F 2 "" H 9550 4800 60 0000 C CNN
+F 3 "" H 9550 4800 60 0000 C CNN
+ 8 9550 4800
+ -1 0 0 1
+$EndComp
+$Comp
+L PORT U1
+U 16 1 5CF15A07
+P 9550 5250
+F 0 "U1" H 9600 5350 30 0000 C CNN
+F 1 "PORT" H 9550 5250 30 0000 C CNN
+F 2 "" H 9550 5250 60 0000 C CNN
+F 3 "" H 9550 5250 60 0000 C CNN
+ 16 9550 5250
+ -1 0 0 1
+$EndComp
+NoConn ~ 9300 4800
+NoConn ~ 9300 5250
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub new file mode 100644 index 00000000..5f9f3cf8 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028.sub @@ -0,0 +1,90 @@ +* Subcircuit 4028
+.subckt 4028 net-_u1-pad1_ net-_u1-pad2_ net-_u1-pad3_ net-_u1-pad4_ net-_u1-pad5_ net-_u1-pad6_ net-_u1-pad7_ ? net-_u1-pad9_ net-_u1-pad10_ net-_u1-pad11_ net-_u1-pad12_ net-_u1-pad13_ net-_u1-pad14_ net-_u1-pad15_ ?
+* c:\users\malli\esim\src\subcircuitlibrary\4028\4028.cir
+* u9 net-_u1-pad13_ net-_u11-pad1_ net-_u16-pad1_ d_nor
+* u10 net-_u1-pad10_ net-_u10-pad2_ net-_u10-pad3_ d_nor
+* u11 net-_u11-pad1_ net-_u10-pad2_ net-_u11-pad3_ d_nor
+* u12 net-_u1-pad12_ net-_u1-pad11_ net-_u12-pad3_ d_nor
+* u6 net-_u4-pad2_ net-_u1-pad11_ net-_u13-pad2_ d_nor
+* u7 net-_u1-pad12_ net-_u5-pad2_ net-_u14-pad2_ d_nor
+* u8 net-_u1-pad10_ net-_u1-pad13_ net-_u14-pad1_ d_nor
+* u2 net-_u1-pad10_ net-_u11-pad1_ d_inverter
+* u3 net-_u1-pad13_ net-_u10-pad2_ d_inverter
+* u4 net-_u1-pad12_ net-_u4-pad2_ d_inverter
+* u5 net-_u1-pad11_ net-_u5-pad2_ d_inverter
+* u15 net-_u14-pad1_ net-_u12-pad3_ net-_u1-pad3_ d_and
+* u16 net-_u16-pad1_ net-_u12-pad3_ net-_u1-pad14_ d_and
+* u17 net-_u10-pad3_ net-_u12-pad3_ net-_u1-pad2_ d_and
+* u18 net-_u11-pad3_ net-_u12-pad3_ net-_u1-pad15_ d_and
+* u19 net-_u14-pad1_ net-_u13-pad2_ net-_u1-pad1_ d_and
+* u20 net-_u16-pad1_ net-_u13-pad2_ net-_u1-pad6_ d_and
+* u21 net-_u10-pad3_ net-_u13-pad2_ net-_u1-pad7_ d_and
+* u13 net-_u11-pad3_ net-_u13-pad2_ net-_u1-pad4_ d_and
+* u14 net-_u14-pad1_ net-_u14-pad2_ net-_u1-pad9_ d_and
+* u22 net-_u16-pad1_ net-_u14-pad2_ net-_u1-pad5_ d_and
+a1 [net-_u1-pad13_ net-_u11-pad1_ ] net-_u16-pad1_ u9
+a2 [net-_u1-pad10_ net-_u10-pad2_ ] net-_u10-pad3_ u10
+a3 [net-_u11-pad1_ net-_u10-pad2_ ] net-_u11-pad3_ u11
+a4 [net-_u1-pad12_ net-_u1-pad11_ ] net-_u12-pad3_ u12
+a5 [net-_u4-pad2_ net-_u1-pad11_ ] net-_u13-pad2_ u6
+a6 [net-_u1-pad12_ net-_u5-pad2_ ] net-_u14-pad2_ u7
+a7 [net-_u1-pad10_ net-_u1-pad13_ ] net-_u14-pad1_ u8
+a8 net-_u1-pad10_ net-_u11-pad1_ u2
+a9 net-_u1-pad13_ net-_u10-pad2_ u3
+a10 net-_u1-pad12_ net-_u4-pad2_ u4
+a11 net-_u1-pad11_ net-_u5-pad2_ u5
+a12 [net-_u14-pad1_ net-_u12-pad3_ ] net-_u1-pad3_ u15
+a13 [net-_u16-pad1_ net-_u12-pad3_ ] net-_u1-pad14_ u16
+a14 [net-_u10-pad3_ net-_u12-pad3_ ] net-_u1-pad2_ u17
+a15 [net-_u11-pad3_ net-_u12-pad3_ ] net-_u1-pad15_ u18
+a16 [net-_u14-pad1_ net-_u13-pad2_ ] net-_u1-pad1_ u19
+a17 [net-_u16-pad1_ net-_u13-pad2_ ] net-_u1-pad6_ u20
+a18 [net-_u10-pad3_ net-_u13-pad2_ ] net-_u1-pad7_ u21
+a19 [net-_u11-pad3_ net-_u13-pad2_ ] net-_u1-pad4_ u13
+a20 [net-_u14-pad1_ net-_u14-pad2_ ] net-_u1-pad9_ u14
+a21 [net-_u16-pad1_ net-_u14-pad2_ ] net-_u1-pad5_ u22
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u9 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u10 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u11 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u12 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u6 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u7 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_nor, NgSpice Name: d_nor
+.model u8 d_nor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u2 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u3 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u4 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_inverter, NgSpice Name: d_inverter
+.model u5 d_inverter(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u15 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u16 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u17 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u18 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u19 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u20 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u21 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u13 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u14 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u22 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends 4028
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml new file mode 100644 index 00000000..189fb200 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u9 name="type">d_nor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u9><u10 name="type">d_nor<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u10><u11 name="type">d_nor<field7 name="Enter Fall Delay (default=1.0e-9)" /><field8 name="Enter Input Load (default=1.0e-12)" /><field9 name="Enter Rise Delay (default=1.0e-9)" /></u11><u12 name="type">d_nor<field10 name="Enter Fall Delay (default=1.0e-9)" /><field11 name="Enter Input Load (default=1.0e-12)" /><field12 name="Enter Rise Delay (default=1.0e-9)" /></u12><u6 name="type">d_nor<field13 name="Enter Fall Delay (default=1.0e-9)" /><field14 name="Enter Input Load (default=1.0e-12)" /><field15 name="Enter Rise Delay (default=1.0e-9)" /></u6><u7 name="type">d_nor<field16 name="Enter Fall Delay (default=1.0e-9)" /><field17 name="Enter Input Load (default=1.0e-12)" /><field18 name="Enter Rise Delay (default=1.0e-9)" /></u7><u8 name="type">d_nor<field19 name="Enter Fall Delay (default=1.0e-9)" /><field20 name="Enter Input Load (default=1.0e-12)" /><field21 name="Enter Rise Delay (default=1.0e-9)" /></u8><u2 name="type">d_inverter<field22 name="Enter Fall Delay (default=1.0e-9)" /><field23 name="Enter Input Load (default=1.0e-12)" /><field24 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_inverter<field25 name="Enter Fall Delay (default=1.0e-9)" /><field26 name="Enter Input Load (default=1.0e-12)" /><field27 name="Enter Rise Delay (default=1.0e-9)" /></u3><u4 name="type">d_inverter<field28 name="Enter Fall Delay (default=1.0e-9)" /><field29 name="Enter Input Load (default=1.0e-12)" /><field30 name="Enter Rise Delay (default=1.0e-9)" /></u4><u5 name="type">d_inverter<field31 name="Enter Fall Delay (default=1.0e-9)" /><field32 name="Enter Input Load (default=1.0e-12)" /><field33 name="Enter Rise Delay (default=1.0e-9)" /></u5><u15 name="type">d_and<field34 name="Enter Fall Delay (default=1.0e-9)" /><field35 name="Enter Input Load (default=1.0e-12)" /><field36 name="Enter Rise Delay (default=1.0e-9)" /></u15><u16 name="type">d_and<field37 name="Enter Fall Delay (default=1.0e-9)" /><field38 name="Enter Input Load (default=1.0e-12)" /><field39 name="Enter Rise Delay (default=1.0e-9)" /></u16><u17 name="type">d_and<field40 name="Enter Fall Delay (default=1.0e-9)" /><field41 name="Enter Input Load (default=1.0e-12)" /><field42 name="Enter Rise Delay (default=1.0e-9)" /></u17><u18 name="type">d_and<field43 name="Enter Fall Delay (default=1.0e-9)" /><field44 name="Enter Input Load (default=1.0e-12)" /><field45 name="Enter Rise Delay (default=1.0e-9)" /></u18><u19 name="type">d_and<field46 name="Enter Fall Delay (default=1.0e-9)" /><field47 name="Enter Input Load (default=1.0e-12)" /><field48 name="Enter Rise Delay (default=1.0e-9)" /></u19><u20 name="type">d_and<field49 name="Enter Fall Delay (default=1.0e-9)" /><field50 name="Enter Input Load (default=1.0e-12)" /><field51 name="Enter Rise Delay (default=1.0e-9)" /></u20><u21 name="type">d_and<field52 name="Enter Fall Delay (default=1.0e-9)" /><field53 name="Enter Input Load (default=1.0e-12)" /><field54 name="Enter Rise Delay (default=1.0e-9)" /></u21><u13 name="type">d_and<field55 name="Enter Fall Delay (default=1.0e-9)" /><field56 name="Enter Input Load (default=1.0e-12)" /><field57 name="Enter Rise Delay (default=1.0e-9)" /></u13><u14 name="type">d_and<field58 name="Enter Fall Delay (default=1.0e-9)" /><field59 name="Enter Input Load (default=1.0e-12)" /><field60 name="Enter Rise Delay (default=1.0e-9)" /></u14><u22 name="type">d_and<field61 name="Enter Fall Delay (default=1.0e-9)" /><field62 name="Enter Input Load (default=1.0e-12)" /><field63 name="Enter Rise Delay (default=1.0e-9)" /></u22></model><devicemodel /><subcircuit /></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib new file mode 100644 index 00000000..43241731 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test-cache.lib @@ -0,0 +1,152 @@ +EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# 4028
+#
+DEF 4028 X 0 40 Y Y 1 F N
+F0 "X" 0 -100 60 H V C CNN
+F1 "4028" 0 50 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -300 450 300 -450 0 1 0 N
+X Q4 1 -500 350 200 R 50 50 1 1 O
+X Q2 2 -500 250 200 R 50 50 1 1 O
+X Q0 3 -500 150 200 R 50 50 1 1 O
+X Q7 4 -500 50 200 R 50 50 1 1 O
+X Q9 5 -500 -50 200 R 50 50 1 1 O
+X Q5 6 -500 -150 200 R 50 50 1 1 O
+X Q6 7 -500 -250 200 R 50 50 1 1 O
+X Vss 8 -500 -350 200 R 50 50 1 1 I
+X Q8 9 500 -350 200 L 50 50 1 1 O
+X A0 10 500 -250 200 L 50 50 1 1 I
+X A3 11 500 -150 200 L 50 50 1 1 I
+X A2 12 500 -50 200 L 50 50 1 1 I
+X A1 13 500 50 200 L 50 50 1 1 I
+X Q1 14 500 150 200 L 50 50 1 1 O
+X Q3 15 500 250 200 L 50 50 1 1 O
+X Vdd 16 500 350 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# DC
+#
+DEF DC v 0 40 Y Y 1 F N
+F0 "v" -200 100 60 H V C CNN
+F1 "DC" -200 -50 60 H V C CNN
+F2 "R1" -300 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+$FPLIST
+ 1_pin
+$ENDFPLIST
+DRAW
+C 0 0 150 0 1 0 N
+X + 1 0 450 300 D 50 50 1 1 P
+X - 2 0 -450 300 U 50 50 1 1 P
+ENDDRAW
+ENDDEF
+#
+# PWR_FLAG
+#
+DEF PWR_FLAG #FLG 0 0 N N 1 F P
+F0 "#FLG" 0 95 50 H I C CNN
+F1 "PWR_FLAG" 0 180 50 H V C CNN
+F2 "" 0 0 50 H V C CNN
+F3 "" 0 0 50 H V C CNN
+DRAW
+X pwr 1 0 0 0 U 20 20 0 0 w
+P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
+ENDDRAW
+ENDDEF
+#
+# adc_bridge_4
+#
+DEF adc_bridge_4 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "adc_bridge_4" 0 300 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -350 350 350 -200 0 1 0 N
+X IN1 1 -550 200 200 R 50 50 1 1 I
+X IN2 2 -550 100 200 R 50 50 1 1 I
+X IN3 3 -550 0 200 R 50 50 1 1 I
+X IN4 4 -550 -100 200 R 50 50 1 1 I
+X OUT1 5 550 200 200 L 50 50 1 1 O
+X OUT2 6 550 100 200 L 50 50 1 1 O
+X OUT3 7 550 0 200 L 50 50 1 1 O
+X OUT4 8 550 -100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_2
+#
+DEF dac_bridge_2 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_2" 50 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -250 200 350 -100 0 1 0 N
+X IN1 1 -450 50 200 R 50 50 1 1 I
+X IN2 2 -450 -50 200 R 50 50 1 1 I
+X OUT1 3 550 50 200 L 50 50 1 1 O
+X OUT4 4 550 -50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# dac_bridge_8
+#
+DEF dac_bridge_8 U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "dac_bridge_8" 0 150 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S -400 200 350 -700 0 1 0 N
+X IN1 1 -600 50 200 R 50 50 1 1 I
+X IN2 2 -600 -50 200 R 50 50 1 1 I
+X IN3 3 -600 -150 200 R 50 50 1 1 I
+X IN4 4 -600 -250 200 R 50 50 1 1 I
+X IN5 5 -600 -350 200 R 50 50 1 1 I
+X IN6 6 -600 -450 200 R 50 50 1 1 I
+X IN7 7 -600 -550 200 R 50 50 1 1 I
+X IN8 8 -600 -650 200 R 50 50 1 1 I
+X OUT1 9 550 50 200 L 50 50 1 1 O
+X OUT2 10 550 -50 200 L 50 50 1 1 O
+X OUT3 11 550 -150 200 L 50 50 1 1 O
+X OUT4 12 550 -250 200 L 50 50 1 1 O
+X OUT5 13 550 -350 200 L 50 50 1 1 O
+X OUT6 14 550 -450 200 L 50 50 1 1 O
+X OUT7 15 550 -550 200 L 50 50 1 1 O
+X OUT8 16 550 -650 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# eSim_GND
+#
+DEF eSim_GND #PWR 0 0 Y Y 1 F P
+F0 "#PWR" 0 -250 50 H I C CNN
+F1 "eSim_GND" 0 -150 50 H V C CNN
+F2 "" 0 0 50 H I C CNN
+F3 "" 0 0 50 H I C CNN
+DRAW
+P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
+X GND 1 0 0 0 D 50 50 1 1 W N
+ENDDRAW
+ENDDEF
+#
+# plot_v1
+#
+DEF plot_v1 U 0 40 Y Y 1 F N
+F0 "U" 0 500 60 H V C CNN
+F1 "plot_v1" 200 350 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+C 0 500 100 0 1 0 N
+X ~ ~ 0 200 200 U 50 50 1 1 I
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir new file mode 100644 index 00000000..66fe8e03 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir @@ -0,0 +1,32 @@ +* C:\Users\malli\eSim-Workspace\4028_test\4028_test.cir
+
+* EESchema Netlist Version 1.1 (Spice format) creation date: 06/01/19 16:27:32
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+* Sheet Name: /
+X1 Net-_U11-Pad5_ Net-_U11-Pad3_ Net-_U11-Pad1_ Net-_U11-Pad8_ Net-_U12-Pad2_ Net-_U11-Pad6_ Net-_U11-Pad7_ ? Net-_U12-Pad1_ Net-_U13-Pad5_ Net-_U13-Pad8_ Net-_U13-Pad7_ Net-_U13-Pad6_ Net-_U11-Pad2_ Net-_U11-Pad4_ ? 4028
+U13 a0 a1 a2 a3 Net-_U13-Pad5_ Net-_U13-Pad6_ Net-_U13-Pad7_ Net-_U13-Pad8_ adc_bridge_4
+U11 Net-_U11-Pad1_ Net-_U11-Pad2_ Net-_U11-Pad3_ Net-_U11-Pad4_ Net-_U11-Pad5_ Net-_U11-Pad6_ Net-_U11-Pad7_ Net-_U11-Pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
+U12 Net-_U12-Pad1_ Net-_U12-Pad2_ q8 q9 dac_bridge_2
+v2 a1 GND DC
+v1 a0 GND DC
+v3 a2 GND DC
+v4 a3 GND DC
+U2 q1 plot_v1
+U3 q2 plot_v1
+U4 q3 plot_v1
+U5 q4 plot_v1
+U6 q5 plot_v1
+U7 q6 plot_v1
+U8 q7 plot_v1
+U9 q8 plot_v1
+U10 q9 plot_v1
+U1 q0 plot_v1
+U16 a1 plot_v1
+U15 a0 plot_v1
+U14 a3 plot_v1
+U17 a2 plot_v1
+
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out new file mode 100644 index 00000000..30ea7914 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.cir.out @@ -0,0 +1,57 @@ +* c:\users\malli\esim-workspace\4028_test\4028_test.cir
+
+.include 4028.sub
+x1 net-_u11-pad5_ net-_u11-pad3_ net-_u11-pad1_ net-_u11-pad8_ net-_u12-pad2_ net-_u11-pad6_ net-_u11-pad7_ ? net-_u12-pad1_ net-_u13-pad5_ net-_u13-pad8_ net-_u13-pad7_ net-_u13-pad6_ net-_u11-pad2_ net-_u11-pad4_ ? 4028
+* u13 a0 a1 a2 a3 net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ adc_bridge_4
+* u11 net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ q0 q1 q2 q3 q4 q5 q6 q7 dac_bridge_8
+* u12 net-_u12-pad1_ net-_u12-pad2_ q8 q9 dac_bridge_2
+v2 a1 gnd dc 0
+v1 a0 gnd dc 5
+v3 a2 gnd dc 5
+v4 a3 gnd dc 0
+* u2 q1 plot_v1
+* u3 q2 plot_v1
+* u4 q3 plot_v1
+* u5 q4 plot_v1
+* u6 q5 plot_v1
+* u7 q6 plot_v1
+* u8 q7 plot_v1
+* u9 q8 plot_v1
+* u10 q9 plot_v1
+* u1 q0 plot_v1
+* u16 a1 plot_v1
+* u15 a0 plot_v1
+* u14 a3 plot_v1
+* u17 a2 plot_v1
+a1 [a0 a1 a2 a3 ] [net-_u13-pad5_ net-_u13-pad6_ net-_u13-pad7_ net-_u13-pad8_ ] u13
+a2 [net-_u11-pad1_ net-_u11-pad2_ net-_u11-pad3_ net-_u11-pad4_ net-_u11-pad5_ net-_u11-pad6_ net-_u11-pad7_ net-_u11-pad8_ ] [q0 q1 q2 q3 q4 q5 q6 q7 ] u11
+a3 [net-_u12-pad1_ net-_u12-pad2_ ] [q8 q9 ] u12
+* Schematic Name: adc_bridge_4, NgSpice Name: adc_bridge
+.model u13 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 )
+* Schematic Name: dac_bridge_8, NgSpice Name: dac_bridge
+.model u11 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+* Schematic Name: dac_bridge_2, NgSpice Name: dac_bridge
+.model u12 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 )
+.tran 10e-03 100e-03 0e-03
+
+* Control Statements
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+plot v(q1)
+plot v(q2)
+plot v(q3)
+plot v(q4)
+plot v(q5)
+plot v(q6)
+plot v(q7)
+plot v(q8)
+plot v(q9)
+plot v(q0)
+plot v(a1)
+plot v(a0)
+plot v(a3)
+plot v(a2)
+.endc
+.end
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro new file mode 100644 index 00000000..dc708582 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.pro @@ -0,0 +1,44 @@ +update=06/01/19 16:07:13
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=../../eSim/kicadSchematicLibrary
+[eeschema/libraries]
+LibName1=power
+LibName2=eSim_Analog
+LibName3=eSim_Devices
+LibName4=eSim_Digital
+LibName5=eSim_Hybrid
+LibName6=eSim_Miscellaneous
+LibName7=eSim_Plot
+LibName8=eSim_Power
+LibName9=eSim_Sources
+LibName10=eSim_Subckt
+LibName11=eSim_User
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj new file mode 100644 index 00000000..fa2ce0cd --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.proj @@ -0,0 +1 @@ +schematicFile 4028_test.sch
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch new file mode 100644 index 00000000..53226145 --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test.sch @@ -0,0 +1,551 @@ +EESchema Schematic File Version 2
+LIBS:power
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Miscellaneous
+LIBS:eSim_Plot
+LIBS:eSim_Power
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+LIBS:eSim_User
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L 4028 X1
+U 1 1 5CF25569
+P 5600 4300
+F 0 "X1" H 5600 4200 60 0000 C CNN
+F 1 "4028" H 5600 4350 60 0000 C CNN
+F 2 "" H 5600 4300 60 0000 C CNN
+F 3 "" H 5600 4300 60 0000 C CNN
+ 1 5600 4300
+ 1 0 0 -1
+$EndComp
+$Comp
+L adc_bridge_4 U13
+U 1 1 5CF25781
+P 7300 4350
+F 0 "U13" H 7300 4350 60 0000 C CNN
+F 1 "adc_bridge_4" H 7300 4650 60 0000 C CNN
+F 2 "" H 7300 4350 60 0000 C CNN
+F 3 "" H 7300 4350 60 0000 C CNN
+ 1 7300 4350
+ -1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_8 U11
+U 1 1 5CF257F0
+P 3750 3950
+F 0 "U11" H 3750 3950 60 0000 C CNN
+F 1 "dac_bridge_8" H 3750 4100 60 0000 C CNN
+F 2 "" H 3750 3950 60 0000 C CNN
+F 3 "" H 3750 3950 60 0000 C CNN
+ 1 3750 3950
+ -1 0 0 -1
+$EndComp
+$Comp
+L dac_bridge_2 U12
+U 1 1 5CF258CD
+P 3800 5050
+F 0 "U12" H 3800 5050 60 0000 C CNN
+F 1 "dac_bridge_2" H 3850 5200 60 0000 C CNN
+F 2 "" H 3800 5050 60 0000 C CNN
+F 3 "" H 3800 5050 60 0000 C CNN
+ 1 3800 5050
+ -1 0 0 -1
+$EndComp
+$Comp
+L DC v2
+U 1 1 5CF25946
+P 9400 3950
+F 0 "v2" H 9200 4050 60 0000 C CNN
+F 1 "DC" H 9200 3900 60 0000 C CNN
+F 2 "R1" H 9100 3950 60 0000 C CNN
+F 3 "" H 9400 3950 60 0000 C CNN
+ 1 9400 3950
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v1
+U 1 1 5CF259A4
+P 9400 3400
+F 0 "v1" H 9200 3500 60 0000 C CNN
+F 1 "DC" H 9200 3350 60 0000 C CNN
+F 2 "R1" H 9100 3400 60 0000 C CNN
+F 3 "" H 9400 3400 60 0000 C CNN
+ 1 9400 3400
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v3
+U 1 1 5CF259F8
+P 9400 4500
+F 0 "v3" H 9200 4600 60 0000 C CNN
+F 1 "DC" H 9200 4450 60 0000 C CNN
+F 2 "R1" H 9100 4500 60 0000 C CNN
+F 3 "" H 9400 4500 60 0000 C CNN
+ 1 9400 4500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L DC v4
+U 1 1 5CF25A37
+P 9450 5000
+F 0 "v4" H 9250 5100 60 0000 C CNN
+F 1 "DC" H 9250 4950 60 0000 C CNN
+F 2 "R1" H 9150 5000 60 0000 C CNN
+F 3 "" H 9450 5000 60 0000 C CNN
+ 1 9450 5000
+ 0 -1 -1 0
+$EndComp
+$Comp
+L eSim_GND #PWR01
+U 1 1 5CF25C11
+P 10200 4450
+F 0 "#PWR01" H 10200 4200 50 0001 C CNN
+F 1 "eSim_GND" H 10200 4300 50 0000 C CNN
+F 2 "" H 10200 4450 50 0001 C CNN
+F 3 "" H 10200 4450 50 0001 C CNN
+ 1 10200 4450
+ 1 0 0 -1
+$EndComp
+$Comp
+L PWR_FLAG #FLG02
+U 1 1 5CF25C75
+P 10200 4100
+F 0 "#FLG02" H 10200 4195 50 0001 C CNN
+F 1 "PWR_FLAG" H 10200 4280 50 0000 C CNN
+F 2 "" H 10200 4100 50 0000 C CNN
+F 3 "" H 10200 4100 50 0000 C CNN
+ 1 10200 4100
+ 1 0 0 -1
+$EndComp
+Wire Wire Line
+ 8950 3400 8500 3400
+Wire Wire Line
+ 8500 3400 8500 4150
+Wire Wire Line
+ 8500 4150 7850 4150
+Wire Wire Line
+ 8600 4250 7850 4250
+Wire Wire Line
+ 8600 3050 8600 4250
+Wire Wire Line
+ 8600 3950 8950 3950
+Wire Wire Line
+ 8950 4500 8500 4500
+Wire Wire Line
+ 8500 4500 8500 4350
+Wire Wire Line
+ 8500 4350 7850 4350
+Wire Wire Line
+ 7850 4450 8200 4450
+Wire Wire Line
+ 8200 4450 8200 5000
+Wire Wire Line
+ 8200 5000 9000 5000
+Wire Wire Line
+ 9900 3400 9900 5000
+Wire Wire Line
+ 9900 3400 9850 3400
+Wire Wire Line
+ 9850 3950 9900 3950
+Connection ~ 9900 3950
+Wire Wire Line
+ 9850 4500 9900 4500
+Connection ~ 9900 4500
+Wire Wire Line
+ 9900 4200 10200 4200
+Wire Wire Line
+ 10200 4100 10200 4450
+Connection ~ 9900 4200
+Connection ~ 10200 4200
+Wire Wire Line
+ 5100 4150 4750 4150
+Wire Wire Line
+ 4750 4150 4750 3900
+Wire Wire Line
+ 4750 3900 4350 3900
+Wire Wire Line
+ 6100 4150 6200 4150
+Wire Wire Line
+ 6200 4150 6200 3700
+Wire Wire Line
+ 6200 3700 4400 3700
+Wire Wire Line
+ 4400 3700 4400 4000
+Wire Wire Line
+ 4400 4000 4350 4000
+Wire Wire Line
+ 4350 4050 5100 4050
+Wire Wire Line
+ 4350 4050 4350 4100
+Wire Wire Line
+ 6100 4050 6250 4050
+Wire Wire Line
+ 6250 4050 6250 3650
+Wire Wire Line
+ 6250 3650 4450 3650
+Wire Wire Line
+ 4450 3650 4450 4200
+Wire Wire Line
+ 4450 4200 4350 4200
+Wire Wire Line
+ 5100 3950 4500 3950
+Wire Wire Line
+ 4500 3950 4500 4300
+Wire Wire Line
+ 4500 4300 4350 4300
+Wire Wire Line
+ 5100 4450 4500 4450
+Wire Wire Line
+ 4500 4450 4500 4400
+Wire Wire Line
+ 4500 4400 4350 4400
+Wire Wire Line
+ 5100 4550 4450 4550
+Wire Wire Line
+ 4450 4550 4450 4500
+Wire Wire Line
+ 4450 4500 4350 4500
+Wire Wire Line
+ 4550 4250 5100 4250
+Wire Wire Line
+ 4550 4250 4550 4600
+Wire Wire Line
+ 4550 4600 4350 4600
+Wire Wire Line
+ 6100 4650 6150 4650
+Wire Wire Line
+ 6150 4650 6150 5000
+Wire Wire Line
+ 6150 5000 4250 5000
+Wire Wire Line
+ 4250 5100 4650 5100
+Wire Wire Line
+ 4650 5100 4650 4350
+Wire Wire Line
+ 4650 4350 5100 4350
+Wire Wire Line
+ 6100 4550 6350 4550
+Wire Wire Line
+ 6350 4550 6350 4150
+Wire Wire Line
+ 6350 4150 6750 4150
+Wire Wire Line
+ 6100 4250 6750 4250
+Wire Wire Line
+ 6100 4350 6750 4350
+Wire Wire Line
+ 6750 4450 6100 4450
+$Comp
+L plot_v1 U2
+U 1 1 5CF261D1
+P 1700 2550
+F 0 "U2" H 1700 3050 60 0000 C CNN
+F 1 "plot_v1" H 1900 2900 60 0000 C CNN
+F 2 "" H 1700 2550 60 0000 C CNN
+F 3 "" H 1700 2550 60 0000 C CNN
+ 1 1700 2550
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U3
+U 1 1 5CF262A9
+P 1700 3050
+F 0 "U3" H 1700 3550 60 0000 C CNN
+F 1 "plot_v1" H 1900 3400 60 0000 C CNN
+F 2 "" H 1700 3050 60 0000 C CNN
+F 3 "" H 1700 3050 60 0000 C CNN
+ 1 1700 3050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U4
+U 1 1 5CF262EF
+P 1700 3450
+F 0 "U4" H 1700 3950 60 0000 C CNN
+F 1 "plot_v1" H 1900 3800 60 0000 C CNN
+F 2 "" H 1700 3450 60 0000 C CNN
+F 3 "" H 1700 3450 60 0000 C CNN
+ 1 1700 3450
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U5
+U 1 1 5CF2632C
+P 1700 3850
+F 0 "U5" H 1700 4350 60 0000 C CNN
+F 1 "plot_v1" H 1900 4200 60 0000 C CNN
+F 2 "" H 1700 3850 60 0000 C CNN
+F 3 "" H 1700 3850 60 0000 C CNN
+ 1 1700 3850
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U6
+U 1 1 5CF26370
+P 1700 4250
+F 0 "U6" H 1700 4750 60 0000 C CNN
+F 1 "plot_v1" H 1900 4600 60 0000 C CNN
+F 2 "" H 1700 4250 60 0000 C CNN
+F 3 "" H 1700 4250 60 0000 C CNN
+ 1 1700 4250
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U7
+U 1 1 5CF263B7
+P 1700 4650
+F 0 "U7" H 1700 5150 60 0000 C CNN
+F 1 "plot_v1" H 1900 5000 60 0000 C CNN
+F 2 "" H 1700 4650 60 0000 C CNN
+F 3 "" H 1700 4650 60 0000 C CNN
+ 1 1700 4650
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U8
+U 1 1 5CF263FD
+P 1700 5050
+F 0 "U8" H 1700 5550 60 0000 C CNN
+F 1 "plot_v1" H 1900 5400 60 0000 C CNN
+F 2 "" H 1700 5050 60 0000 C CNN
+F 3 "" H 1700 5050 60 0000 C CNN
+ 1 1700 5050
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U9
+U 1 1 5CF26446
+P 1700 5500
+F 0 "U9" H 1700 6000 60 0000 C CNN
+F 1 "plot_v1" H 1900 5850 60 0000 C CNN
+F 2 "" H 1700 5500 60 0000 C CNN
+F 3 "" H 1700 5500 60 0000 C CNN
+ 1 1700 5500
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U10
+U 1 1 5CF2649A
+P 1700 5900
+F 0 "U10" H 1700 6400 60 0000 C CNN
+F 1 "plot_v1" H 1900 6250 60 0000 C CNN
+F 2 "" H 1700 5900 60 0000 C CNN
+F 3 "" H 1700 5900 60 0000 C CNN
+ 1 1700 5900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U1
+U 1 1 5CF26545
+P 1700 2100
+F 0 "U1" H 1700 2600 60 0000 C CNN
+F 1 "plot_v1" H 1900 2450 60 0000 C CNN
+F 2 "" H 1700 2100 60 0000 C CNN
+F 3 "" H 1700 2100 60 0000 C CNN
+ 1 1700 2100
+ 0 -1 -1 0
+$EndComp
+Wire Wire Line
+ 3200 3900 2900 3900
+Wire Wire Line
+ 2900 3900 2900 2100
+Wire Wire Line
+ 2900 2100 1500 2100
+Wire Wire Line
+ 1500 2550 2850 2550
+Wire Wire Line
+ 2850 2550 2850 4000
+Wire Wire Line
+ 2850 4000 3200 4000
+Wire Wire Line
+ 3200 4100 2700 4100
+Wire Wire Line
+ 2700 4100 2700 3050
+Wire Wire Line
+ 2700 3050 1500 3050
+Wire Wire Line
+ 1500 3450 2650 3450
+Wire Wire Line
+ 2650 3450 2650 4200
+Wire Wire Line
+ 2650 4200 3200 4200
+Wire Wire Line
+ 3200 4300 2600 4300
+Wire Wire Line
+ 2600 4300 2600 3850
+Wire Wire Line
+ 2600 3850 1500 3850
+Wire Wire Line
+ 1500 4250 2550 4250
+Wire Wire Line
+ 2550 4250 2550 4400
+Wire Wire Line
+ 2550 4400 3200 4400
+Wire Wire Line
+ 2450 4500 3200 4500
+Wire Wire Line
+ 2450 4500 2450 4650
+Wire Wire Line
+ 2450 4650 1500 4650
+Wire Wire Line
+ 1500 5050 2600 5050
+Wire Wire Line
+ 2600 5050 2600 4600
+Wire Wire Line
+ 2600 4600 3200 4600
+Wire Wire Line
+ 3250 5000 2650 5000
+Wire Wire Line
+ 2650 5000 2650 5500
+Wire Wire Line
+ 2650 5500 1500 5500
+Wire Wire Line
+ 3250 5100 2700 5100
+Wire Wire Line
+ 2700 5100 2700 5900
+Wire Wire Line
+ 2700 5900 1500 5900
+$Comp
+L plot_v1 U16
+U 1 1 5CF26B3C
+P 8600 3250
+F 0 "U16" H 8600 3750 60 0000 C CNN
+F 1 "plot_v1" H 8800 3600 60 0000 C CNN
+F 2 "" H 8600 3250 60 0000 C CNN
+F 3 "" H 8600 3250 60 0000 C CNN
+ 1 8600 3250
+ 1 0 0 -1
+$EndComp
+$Comp
+L plot_v1 U15
+U 1 1 5CF26C0A
+P 8250 3750
+F 0 "U15" H 8250 4250 60 0000 C CNN
+F 1 "plot_v1" H 8450 4100 60 0000 C CNN
+F 2 "" H 8250 3750 60 0000 C CNN
+F 3 "" H 8250 3750 60 0000 C CNN
+ 1 8250 3750
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U14
+U 1 1 5CF26C90
+P 8150 4900
+F 0 "U14" H 8150 5400 60 0000 C CNN
+F 1 "plot_v1" H 8350 5250 60 0000 C CNN
+F 2 "" H 8150 4900 60 0000 C CNN
+F 3 "" H 8150 4900 60 0000 C CNN
+ 1 8150 4900
+ 0 -1 -1 0
+$EndComp
+$Comp
+L plot_v1 U17
+U 1 1 5CF26D07
+P 8750 5150
+F 0 "U17" H 8750 5650 60 0000 C CNN
+F 1 "plot_v1" H 8950 5500 60 0000 C CNN
+F 2 "" H 8750 5150 60 0000 C CNN
+F 3 "" H 8750 5150 60 0000 C CNN
+ 1 8750 5150
+ -1 0 0 1
+$EndComp
+Wire Wire Line
+ 8750 5350 8750 4500
+Connection ~ 8750 4500
+Wire Wire Line
+ 7950 4900 8200 4900
+Connection ~ 8200 4900
+Wire Wire Line
+ 8050 3750 8500 3750
+Connection ~ 8500 3750
+Connection ~ 8600 3950
+Text GLabel 8450 3250 0 60 Input ~ 0
+a1
+Text GLabel 8250 3850 3 60 Input ~ 0
+a0
+Text GLabel 8600 4750 0 60 Input ~ 0
+a2
+Text GLabel 8050 5050 3 60 Input ~ 0
+a3
+Wire Wire Line
+ 8050 5050 8050 4900
+Connection ~ 8050 4900
+Wire Wire Line
+ 8600 4750 8750 4750
+Connection ~ 8750 4750
+Wire Wire Line
+ 8250 3850 8250 3750
+Connection ~ 8250 3750
+Wire Wire Line
+ 8450 3250 8600 3250
+Connection ~ 8600 3250
+NoConn ~ 6100 3950
+NoConn ~ 5100 4650
+Text GLabel 2000 1950 1 60 Output ~ 0
+q0
+Text GLabel 2000 2450 1 60 Output ~ 0
+q1
+Text GLabel 1900 2900 1 60 Output ~ 0
+q2
+Text GLabel 1850 3350 1 60 Output ~ 0
+q3
+Text GLabel 1850 3750 1 60 Output ~ 0
+q4
+Text GLabel 1850 4150 1 60 Output ~ 0
+q5
+Text GLabel 1800 4550 1 60 Output ~ 0
+q6
+Text GLabel 1800 4950 1 60 Output ~ 0
+q7
+Text GLabel 1800 5400 1 60 Output ~ 0
+q8
+Text GLabel 1800 5800 1 60 Output ~ 0
+q9
+Wire Wire Line
+ 1800 5800 1800 5900
+Connection ~ 1800 5900
+Wire Wire Line
+ 1800 5400 1800 5500
+Connection ~ 1800 5500
+Wire Wire Line
+ 1800 4950 1800 5050
+Connection ~ 1800 5050
+Wire Wire Line
+ 1800 4550 1800 4650
+Connection ~ 1800 4650
+Wire Wire Line
+ 1850 4150 1850 4250
+Connection ~ 1850 4250
+Wire Wire Line
+ 1850 3750 1850 3850
+Connection ~ 1850 3850
+Wire Wire Line
+ 1850 3350 1850 3450
+Connection ~ 1850 3450
+Wire Wire Line
+ 1900 2900 1900 3050
+Connection ~ 1900 3050
+Wire Wire Line
+ 2000 2450 2000 2550
+Connection ~ 2000 2550
+Wire Wire Line
+ 2000 1950 2000 2100
+Connection ~ 2000 2100
+$EndSCHEMATC
diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml new file mode 100644 index 00000000..4156779d --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/4028_test_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source><v2 name="Source type">dc<field1 name="Value">5</field1></v2><v1 name="Source type">dc<field1 name="Value">0</field1></v1><v3 name="Source type">dc<field1 name="Value">0</field1></v3><v4 name="Source type">dc<field1 name="Value">0</field1></v4></source><model><u13 name="type">adc_bridge<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter value for in_high (default=2.0)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /><field4 name="Enter value for in_low (default=1.0)" /></u13><u11 name="type">dac_bridge<field5 name="Enter value for input load (default=1.0e-12)" /><field6 name="Enter value for out_low (default=0.0)" /><field7 name="Enter value for out_high (default=5.0)" /><field8 name="Enter the Rise Time (default=1.0e-9)" /><field9 name="Enter the Fall Time (default=1.0e-9)" /><field10 name="Enter value for out_undef (default=0.5)" /></u11><u12 name="type">dac_bridge<field11 name="Enter value for input load (default=1.0e-12)" /><field12 name="Enter value for out_low (default=0.0)" /><field13 name="Enter value for out_high (default=5.0)" /><field14 name="Enter the Rise Time (default=1.0e-9)" /><field15 name="Enter the Fall Time (default=1.0e-9)" /><field16 name="Enter value for out_undef (default=0.5)" /></u12></model><devicemodel /><subcircuit><x1><field>C:\Users\malli\eSim\src\SubcircuitLibrary\4028</field></x1></subcircuit><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time">0</field1><field2 name="Step Time">10</field2><field3 name="Stop Time">100</field3><field4 name="Start Combo">ms</field4><field5 name="Step Combo">ms</field5><field6 name="Stop Combo">ms</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/Examples/Analysis_Of_Digital_IC/4028_test/analysis b/Examples/Analysis_Of_Digital_IC/4028_test/analysis new file mode 100644 index 00000000..660a46cc --- /dev/null +++ b/Examples/Analysis_Of_Digital_IC/4028_test/analysis @@ -0,0 +1 @@ +.tran 10e-03 100e-03 0e-03
\ No newline at end of file |