diff options
Diffstat (limited to 'Examples/3_Input_NOR_Characteristics/3_Input_NOR_Characteristics.cir.out')
| -rw-r--r-- | Examples/3_Input_NOR_Characteristics/3_Input_NOR_Characteristics.cir.out | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/Examples/3_Input_NOR_Characteristics/3_Input_NOR_Characteristics.cir.out b/Examples/3_Input_NOR_Characteristics/3_Input_NOR_Characteristics.cir.out new file mode 100644 index 00000000..af0715b1 --- /dev/null +++ b/Examples/3_Input_NOR_Characteristics/3_Input_NOR_Characteristics.cir.out @@ -0,0 +1,66 @@ +* /home/bhargav/esim-workspace/3_input_nor_characteristics/3_input_nor_characteristics.cir + +.include 4025.sub +* u6 v1 v2 v3 net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ adc_bridge_3 +* u10 v9 v8 v7 net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ adc_bridge_3 +v3 v1 gnd dc 0 +v4 v2 gnd dc 0 +v5 v3 gnd dc 0 +* u3 v1 plot_v1 +* u4 v2 plot_v1 +* u5 v3 plot_v1 +v1 v4 gnd dc 0 +v2 v5 gnd dc 0 +* u1 v4 plot_v1 +* u2 v5 plot_v1 +v6 v6 gnd dc 0 +* u14 v6 plot_v1 +v7 v7 gnd dc 0 +v8 v8 gnd dc 0 +v9 v9 gnd dc 0 +* u15 v7 plot_v1 +* u16 v8 plot_v1 +* u17 v9 plot_v1 +* u8 net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ o1 o2 o3 dac_bridge_3 +* u7 v4 v5 net-_u7-pad3_ net-_u7-pad4_ adc_bridge_2 +* u11 v6 net-_u11-pad2_ adc_bridge_1 +* u9 o1 plot_v1 +* u12 o2 plot_v1 +* u13 o3 plot_v1 +x1 net-_u7-pad3_ net-_u7-pad4_ net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ net-_u8-pad1_ ? net-_u11-pad2_ net-_u8-pad2_ net-_u8-pad3_ net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ? 4025 +a1 [v1 v2 v3 ] [net-_u6-pad4_ net-_u6-pad5_ net-_u6-pad6_ ] u6 +a2 [v9 v8 v7 ] [net-_u10-pad4_ net-_u10-pad5_ net-_u10-pad6_ ] u10 +a3 [net-_u8-pad1_ net-_u8-pad2_ net-_u8-pad3_ ] [o1 o2 o3 ] u8 +a4 [v4 v5 ] [net-_u7-pad3_ net-_u7-pad4_ ] u7 +a5 [v6 ] [net-_u11-pad2_ ] u11 +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u6 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_3, NgSpice Name: adc_bridge +.model u10 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: dac_bridge_3, NgSpice Name: dac_bridge +.model u8 dac_bridge(out_undef=0.5 out_low=0.0 out_high=5.0 t_rise=1.0e-9 t_fall=1.0e-9 input_load=1.0e-12 ) +* Schematic Name: adc_bridge_2, NgSpice Name: adc_bridge +.model u7 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +* Schematic Name: adc_bridge_1, NgSpice Name: adc_bridge +.model u11 adc_bridge(fall_delay=1.0e-9 in_high=2.0 rise_delay=1.0e-9 in_low=1.0 ) +.tran 1e-03 100e-03 0e-03 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(v1) +plot v(v2) +plot v(v3) +plot v(v4) +plot v(v5) +plot v(v6) +plot v(v7) +plot v(v8) +plot v(v9) +plot v(o1) +plot v(o2) +plot v(o3) +.endc +.end |