diff options
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib | 100 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14.cir | 17 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14.cir.out | 20 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14.pro | 71 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14.sch | 278 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14.sub | 14 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml | 1 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib | 13 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib | 11 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/README.md | 24 | ||||
| -rw-r--r-- | library/SubcircuitLibrary/74V1G14/analysis | 1 |
11 files changed, 550 insertions, 0 deletions
diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib new file mode 100644 index 00000000..6c512720 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir b/library/SubcircuitLibrary/74V1G14/74V1G14.cir new file mode 100644 index 00000000..58637c1a --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\74V1G14\74V1G14.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 8/3/2022 1:17:12 AM + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 /Vout /Inp Net-_M1-Pad3_ /GND mosfet_n +M2 Net-_M1-Pad3_ /Inp /GND /GND mosfet_n +M3 /Vcc /Inp Net-_M3-Pad3_ /Vcc mosfet_p +M4 Net-_M3-Pad3_ /Inp /Vout /Vcc mosfet_p +M5 /GND /Vout Net-_M3-Pad3_ /Vcc mosfet_p +M6 /Vcc /Vout Net-_M1-Pad3_ /GND mosfet_n +U1 ? /Inp /GND /Vout /Vcc PORT + +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out new file mode 100644 index 00000000..43a6987d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir + +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* u1 ? /inp /gnd /vout /vcc port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.pro b/library/SubcircuitLibrary/74V1G14/74V1G14.pro new file mode 100644 index 00000000..d7f78c3b --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sch b/library/SubcircuitLibrary/74V1G14/74V1G14.sch new file mode 100644 index 00000000..3cab975e --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sch @@ -0,0 +1,278 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:74V1G14-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_n M1 +U 1 1 62E8D877 +P 3550 3950 +F 0 "M1" H 3550 3800 50 0000 R CNN +F 1 "mosfet_n" H 3650 3900 50 0000 R CNN +F 2 "" H 3850 3650 29 0000 C CNN +F 3 "" H 3650 3750 60 0000 C CNN + 1 3550 3950 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62E8D878 +P 3550 5300 +F 0 "M2" H 3550 5150 50 0000 R CNN +F 1 "mosfet_n" H 3650 5250 50 0000 R CNN +F 2 "" H 3850 5000 29 0000 C CNN +F 3 "" H 3650 5100 60 0000 C CNN + 1 3550 5300 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62E8D879 +P 3650 1600 +F 0 "M3" H 3600 1650 50 0000 R CNN +F 1 "mosfet_p" H 3700 1750 50 0000 R CNN +F 2 "" H 3900 1700 29 0000 C CNN +F 3 "" H 3700 1600 60 0000 C CNN + 1 3650 1600 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62E8D87A +P 3650 2650 +F 0 "M4" H 3600 2700 50 0000 R CNN +F 1 "mosfet_p" H 3700 2800 50 0000 R CNN +F 2 "" H 3900 2750 29 0000 C CNN +F 3 "" H 3700 2650 60 0000 C CNN + 1 3650 2650 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_p M5 +U 1 1 62E8D87B +P 7250 2100 +F 0 "M5" H 7200 2150 50 0000 R CNN +F 1 "mosfet_p" H 7300 2250 50 0000 R CNN +F 2 "" H 7500 2200 29 0000 C CNN +F 3 "" H 7300 2100 60 0000 C CNN + 1 7250 2100 + 0 1 -1 0 +$EndComp +$Comp +L mosfet_n M6 +U 1 1 62E8D87C +P 7450 4850 +F 0 "M6" H 7450 4700 50 0000 R CNN +F 1 "mosfet_n" H 7550 4800 50 0000 R CNN +F 2 "" H 7750 4550 29 0000 C CNN +F 3 "" H 7550 4650 60 0000 C CNN + 1 7450 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 3800 1800 3800 2450 +Wire Wire Line + 3800 2850 3800 3950 +Wire Wire Line + 3800 3950 3750 3950 +Wire Wire Line + 3750 4350 3750 5300 +Wire Wire Line + 7050 1950 3800 1950 +Connection ~ 3800 1950 +Wire Wire Line + 7100 1750 7100 1850 +Wire Wire Line + 3800 850 3800 1400 +Wire Wire Line + 3800 1300 4550 1300 +Wire Wire Line + 4550 1300 4550 2900 +Wire Wire Line + 4550 2900 3900 2900 +Wire Wire Line + 3900 2900 3900 2800 +Connection ~ 3800 1300 +Wire Wire Line + 3900 1750 7100 1750 +Connection ~ 4550 1750 +Wire Wire Line + 3750 5700 3750 6200 +Wire Wire Line + 3850 5650 3850 5850 +Wire Wire Line + 3850 5850 3750 5850 +Connection ~ 3750 5850 +Wire Wire Line + 3850 5700 4150 5700 +Wire Wire Line + 4150 5700 4150 4300 +Wire Wire Line + 4150 4300 3850 4300 +Connection ~ 3850 5700 +Wire Wire Line + 4150 5250 7100 5250 +Wire Wire Line + 7100 5250 7100 5150 +Connection ~ 4150 5250 +Wire Wire Line + 7050 5050 3750 5050 +Connection ~ 3750 5050 +Wire Wire Line + 7450 5050 9450 5050 +Wire Wire Line + 3800 3350 9200 3350 +Connection ~ 3800 3350 +Wire Wire Line + 2750 1600 2750 5500 +Wire Wire Line + 2750 5500 3450 5500 +Wire Wire Line + 3500 2650 3500 2550 +Wire Wire Line + 3500 2550 2750 2550 +Connection ~ 2750 2550 +Connection ~ 2750 4150 +Wire Wire Line + 2100 3300 2750 3300 +Connection ~ 2750 3300 +Wire Wire Line + 7450 1950 9700 1950 +Wire Wire Line + 9700 1950 9700 6050 +Wire Wire Line + 9700 6050 3750 6050 +Connection ~ 3750 6050 +Wire Wire Line + 3500 1600 2750 1600 +Wire Wire Line + 3450 4150 2750 4150 +Wire Wire Line + 3600 850 9450 850 +Wire Wire Line + 9450 850 9450 5050 +Connection ~ 3800 850 +Text Label 3600 850 0 60 ~ 0 +Vcc +Text Label 9100 3350 0 60 ~ 0 +Vout +Text Label 3750 6150 0 60 ~ 0 +GND +Text Label 2300 3300 0 60 ~ 0 +Inp +Text Label 2300 4100 0 60 ~ 0 +NC +NoConn ~ 2300 4100 +$Comp +L PORT U1 +U 2 1 62E8E2E7 +P 1850 3300 +F 0 "U1" H 1900 3400 30 0000 C CNN +F 1 "PORT" H 1850 3300 30 0000 C CNN +F 2 "" H 1850 3300 60 0000 C CNN +F 3 "" H 1850 3300 60 0000 C CNN + 2 1850 3300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62E8E33C +P 2050 4100 +F 0 "U1" H 2100 4200 30 0000 C CNN +F 1 "PORT" H 2050 4100 30 0000 C CNN +F 2 "" H 2050 4100 60 0000 C CNN +F 3 "" H 2050 4100 60 0000 C CNN + 1 2050 4100 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62E8E47F +P 9450 3350 +F 0 "U1" H 9500 3450 30 0000 C CNN +F 1 "PORT" H 9450 3350 30 0000 C CNN +F 2 "" H 9450 3350 60 0000 C CNN +F 3 "" H 9450 3350 60 0000 C CNN + 4 9450 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62E8E9EE +P 3350 850 +F 0 "U1" H 3400 950 30 0000 C CNN +F 1 "PORT" H 3350 850 30 0000 C CNN +F 2 "" H 3350 850 60 0000 C CNN +F 3 "" H 3350 850 60 0000 C CNN + 5 3350 850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62E8ECBB +P 3500 6200 +F 0 "U1" H 3550 6300 30 0000 C CNN +F 1 "PORT" H 3500 6200 30 0000 C CNN +F 2 "" H 3500 6200 60 0000 C CNN +F 3 "" H 3500 6200 60 0000 C CNN + 3 3500 6200 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7250 2250 6900 2250 +Wire Wire Line + 6900 2250 6900 3350 +Connection ~ 6900 3350 +Wire Wire Line + 7250 4750 7250 3350 +Connection ~ 7250 3350 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14.sub b/library/SubcircuitLibrary/74V1G14/74V1G14.sub new file mode 100644 index 00000000..37c8151d --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14.sub @@ -0,0 +1,14 @@ +* Subcircuit 74V1G14 +.subckt 74V1G14 ? /inp /gnd /vout /vcc +* c:\fossee\esim\library\subcircuitlibrary\74v1g14\74v1g14.cir +.include NMOS-180nm.lib +.include PMOS-180nm.lib +m1 /vout /inp net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +m2 net-_m1-pad3_ /inp /gnd /gnd CMOSN W=25u L=0.25u M=1 +m3 /vcc /inp net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m4 net-_m3-pad3_ /inp /vout /vcc CMOSP W=25u L=0.25u M=1 +m5 /gnd /vout net-_m3-pad3_ /vcc CMOSP W=25u L=0.25u M=1 +m6 /vcc /vout net-_m1-pad3_ /gnd CMOSN W=25u L=0.25u M=1 +* Control Statements + +.ends 74V1G14
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml new file mode 100644 index 00000000..b08ed607 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/74V1G14_Previous_Values.xml @@ -0,0 +1 @@ +<KicadtoNgspice><source /><model /><devicemodel><m1><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m1><m2><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m2><m3><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m3><m4><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m4><m5><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.lib</field><field>75u</field><field>0.25u</field><field>1</field></m5><m6><field>C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.lib</field><field>25u</field><field>0.25u</field><field>1</field></m6></devicemodel><subcircuit /><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source 1" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">0</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8><field9 name="Source 2" /><field10 name="Start" /><field11 name="Increment" /><field12 name="Stop" /><field13 name="Start Combo">Volts or Amperes</field13><field14 name="Increment Combo">Volts or Amperes</field14><field15 name="Stop Combo">Volts or Amperes</field15></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis></KicadtoNgspice>
\ No newline at end of file diff --git a/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib new file mode 100644 index 00000000..51e9b119 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib new file mode 100644 index 00000000..032b5b95 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/library/SubcircuitLibrary/74V1G14/README.md b/library/SubcircuitLibrary/74V1G14/README.md new file mode 100644 index 00000000..6d0656e5 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/README.md @@ -0,0 +1,24 @@ +# Sch_trig IC + +Schmitt trigger is a general purpose IC. It is the circuit that is used to convert any type of input signal into a square waveform + +## Usage/Examples + +It is used in simple oscillators. + +It is used in Switch Debouncing. + +## Documentation + +To know the details of 74V1G14 IC please refer to this link [74V1G14_datasheet.](https://www.st.com/resource/en/datasheet/74v1g14.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Vanshika Tanwar +Email: vanshikatanwar30@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/74V1G14/analysis b/library/SubcircuitLibrary/74V1G14/analysis new file mode 100644 index 00000000..ebd5c0a9 --- /dev/null +++ b/library/SubcircuitLibrary/74V1G14/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00
\ No newline at end of file |