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| author | fahim-oscad | 2016-04-18 12:41:02 +0530 |
|---|---|---|
| committer | fahim-oscad | 2016-04-18 12:41:02 +0530 |
| commit | c7283f5300b5c8704c8a7866bd9b4b2bb8ce169b (patch) | |
| tree | 6cfadaa26f411715fae35eafa54d5a1dadca6540 /src | |
| parent | f9f323cb8f895dd7e1378b8c97ced398ad472b4a (diff) | |
| download | eSim-c7283f5300b5c8704c8a7866bd9b4b2bb8ce169b.tar.gz eSim-c7283f5300b5c8704c8a7866bd9b4b2bb8ce169b.tar.bz2 eSim-c7283f5300b5c8704c8a7866bd9b4b2bb8ce169b.zip | |
Remove Zero Voltage condition as It is now working in OpenModelica OMEdit
Diffstat (limited to 'src')
| -rw-r--r-- | src/ngspicetoModelica/NgspicetoModelica.py | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/src/ngspicetoModelica/NgspicetoModelica.py b/src/ngspicetoModelica/NgspicetoModelica.py index 0aaf7936..169c382a 100644 --- a/src/ngspicetoModelica/NgspicetoModelica.py +++ b/src/ngspicetoModelica/NgspicetoModelica.py @@ -70,11 +70,7 @@ class NgMoConverter: self.subCktDetail.append(eachline) elif eachline[0]=='v' or eachline[0]=='V': schematicInfo.append(eachline) - #Removing zero voltage source as it is not require in Modelica - if eachline.split()[-1]=='0': - continue - else: - self.sourceDetail.append(eachline) + self.sourceDetail.append(eachline) else: schematicInfo.append(eachline) ##No need of making it lower case as netlist is already converted to ngspice |