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authorEyantra698Sumanto2022-08-06 02:22:29 +0530
committerEyantra698Sumanto2022-08-06 02:22:29 +0530
commitbfca7d1f0bea171ab467f0a704274e29d440dd80 (patch)
tree38dd498c58464d1418e82f33caf186b04b750d63 /src
parent749a7284f2e8837e50edb1ad9aa381ebb388317c (diff)
downloadeSim-bfca7d1f0bea171ab467f0a704274e29d440dd80.tar.gz
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Fixed pep8 issues
Diffstat (limited to 'src')
-rwxr-xr-xsrc/kicadtoNgspice/DeviceModel.py8
1 files changed, 5 insertions, 3 deletions
diff --git a/src/kicadtoNgspice/DeviceModel.py b/src/kicadtoNgspice/DeviceModel.py
index 550f9d3c..5b2ea20e 100755
--- a/src/kicadtoNgspice/DeviceModel.py
+++ b/src/kicadtoNgspice/DeviceModel.py
@@ -89,7 +89,8 @@ class DeviceModel(QtWidgets.QWidget):
self.SOCbtn = QtWidgets.QPushButton("Generate SoC")
self.SOCbtn.clicked.connect(self.GenerateSOCbutton)
sky130grid.addWidget(self.SOCbtn, self.row, 2)
- self.SOCbtn.setToolTip('''This is the Generate SoC option to convert SPICE to verilog.
+ self.SOCbtn.setToolTip('''This is the Generate SoC \
+option to convert SPICE to verilog.
Naming convention should be strictly:
IP for Analog Design: IPAD
IP for Digital Design: IPDD
@@ -195,8 +196,9 @@ sky130_fd_pr/models/sky130.lib.spice")
if eachline[0:2] != 'sc' and eachline[0] != 'u' \
and eachline[0] != 'x' and eachline[0] != '*'\
and eachline[0] != 'v' and eachline[0] != 'i'\
- and eachline[0] != 'a':
- print("Only components with designators 'sc', 'u', 'x', 'v', 'i', 'a'\
+ and eachline[0] != 'a' :
+ print("Only components with designators 'sc', 'u', \
+'x', 'v', 'i', 'a'\
can be used with sky130 mode")
print("Please remove other components")
self.msg = QtWidgets.QErrorMessage()