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| author | rahulp13 | 2022-02-22 01:07:20 +0530 |
|---|---|---|
| committer | rahulp13 | 2022-02-22 01:07:20 +0530 |
| commit | 1b42df112e9d13afd092d9f415e7e446a2102e85 (patch) | |
| tree | 10caef51545fbbf7ee8ab43f02bc1a2650090c30 /src/maker/Maker.py | |
| parent | faadcb72916d269aeabbaa23f799962b6b99c45c (diff) | |
| download | eSim-1b42df112e9d13afd092d9f415e7e446a2102e85.tar.gz eSim-1b42df112e9d13afd092d9f415e7e446a2102e85.tar.bz2 eSim-1b42df112e9d13afd092d9f415e7e446a2102e85.zip | |
Restructured config paths and other path issues
Diffstat (limited to 'src/maker/Maker.py')
| -rwxr-xr-x | src/maker/Maker.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/maker/Maker.py b/src/maker/Maker.py index 78fd13b2..60087018 100755 --- a/src/maker/Maker.py +++ b/src/maker/Maker.py @@ -82,7 +82,7 @@ class Maker(QtWidgets.QWidget): # This function is to Add new verilog file def addverilog(self): - init_path = '../../../' + init_path = '../../' if os.name == 'nt': init_path = '' self.verilogfile = QtCore.QDir.toNativeSeparators( |