Subject: Added subcircuit for Half Adder and Full Adder.

Description: Added subcircuit for Half Adder and Full Adder.

23 files changed, 1017 insertions, 0 deletions

diff --git a/src/SubcircuitLibrary/full_adder/analysis b/src/SubcircuitLibrary/full_adder/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder-cache.lib b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
new file mode 100644
index 00000000..623a7f41
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder-cache.lib
@@ -0,0 +1,61 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_or
+#
+DEF d_or U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_or" 0 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  -250 -50  150 -50 N
+P 2 0 1 0  -250 150  150 150 N
+X IN1 1 -450 100 215 R 50 50 1 1 I
+X IN2 2 -450 0 215 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# half_adder
+#
+DEF half_adder X 0 40 Y Y 1 F N
+F0 "X" 900 500 60 H V C CNN
+F1 "half_adder" 900 400 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+S 500 800 1250 0 0 1 0 N
+X IN1 1 300 700 200 R 50 50 1 1 I
+X IN2 2 300 100 200 R 50 50 1 1 I
+X SUM 3 1450 700 200 L 50 50 1 1 O
+X COUT 4 1450 100 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir b/src/SubcircuitLibrary/full_adder/full_adder.cir
new file mode 100644
index 00000000..6461b5b6
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder.cir
@@ -0,0 +1,12 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 12:24:33 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+X1  8 7 6 2 half_adder		
+X2  5 6 4 3 half_adder		
+U1  8 7 5 4 1 PORT		
+U2  3 2 1 d_or		
+
+.end
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.cir.out b/src/SubcircuitLibrary/full_adder/full_adder.cir.out
new file mode 100644
index 00000000..b90ce70d
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder.cir.out
@@ -0,0 +1,19 @@
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
+
+.include half_adder.sub
+x1 8 7 6 2 half_adder
+x2 5 6 4 3 half_adder
+* u1  8 7 5 4 1 port
+* u2  3 2 1 d_or
+a1 [3 2 ] 1 u2
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.pro b/src/SubcircuitLibrary/full_adder/full_adder.pro
new file mode 100644
index 00000000..c0db0775
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder.pro
@@ -0,0 +1,69 @@
+update=Wed Jun 24 12:19:16 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sch b/src/SubcircuitLibrary/full_adder/full_adder.sch
new file mode 100644
index 00000000..8bd400f2
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder.sch
@@ -0,0 +1,180 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L half_adder X1
+U 1 1 558AA064
+P 3800 3350
+F 0 "X1" H 4700 3850 60  0000 C CNN
+F 1 "half_adder" H 4700 3750 60  0000 C CNN
+F 2 "" H 3800 3350 60  0000 C CNN
+F 3 "" H 3800 3350 60  0000 C CNN
+	1    3800 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L half_adder X2
+U 1 1 558AA0C1
+P 5700 3350
+F 0 "X2" H 6600 3850 60  0000 C CNN
+F 1 "half_adder" H 6600 3750 60  0000 C CNN
+F 2 "" H 5700 3350 60  0000 C CNN
+F 3 "" H 5700 3350 60  0000 C CNN
+	1    5700 3350
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558AA277
+P 3450 2650
+F 0 "U1" H 3500 2750 30  0000 C CNN
+F 1 "PORT" H 3450 2650 30  0000 C CNN
+F 2 "" H 3450 2650 60  0000 C CNN
+F 3 "" H 3450 2650 60  0000 C CNN
+	1    3450 2650
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 558AA29E
+P 3450 3250
+F 0 "U1" H 3500 3350 30  0000 C CNN
+F 1 "PORT" H 3450 3250 30  0000 C CNN
+F 2 "" H 3450 3250 60  0000 C CNN
+F 3 "" H 3450 3250 60  0000 C CNN
+	2    3450 3250
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 558AA2D8
+P 5650 2300
+F 0 "U1" H 5700 2400 30  0000 C CNN
+F 1 "PORT" H 5650 2300 30  0000 C CNN
+F 2 "" H 5650 2300 60  0000 C CNN
+F 3 "" H 5650 2300 60  0000 C CNN
+	3    5650 2300
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558AA378
+P 7900 2650
+F 0 "U1" H 7950 2750 30  0000 C CNN
+F 1 "PORT" H 7900 2650 30  0000 C CNN
+F 2 "" H 7900 2650 60  0000 C CNN
+F 3 "" H 7900 2650 60  0000 C CNN
+	4    7900 2650
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 5 1 558AA3E0
+P 8700 3400
+F 0 "U1" H 8750 3500 30  0000 C CNN
+F 1 "PORT" H 8700 3400 30  0000 C CNN
+F 2 "" H 8700 3400 60  0000 C CNN
+F 3 "" H 8700 3400 60  0000 C CNN
+	5    8700 3400
+	-1   0    0    1   
+$EndComp
+$Comp
+L d_or U2
+U 1 1 558AA43B
+P 7900 3450
+F 0 "U2" H 7900 3450 60  0000 C CNN
+F 1 "d_or" H 7900 3550 60  0000 C CNN
+F 2 "" H 7900 3450 60  0000 C CNN
+F 3 "" H 7900 3450 60  0000 C CNN
+	1    7900 3450
+	1    0    0    -1  
+$EndComp
+Wire Wire Line
+	3700 2650 4100 2650
+Wire Wire Line
+	3700 3250 4100 3250
+Wire Wire Line
+	5250 2650 5650 2650
+Wire Wire Line
+	5650 2650 5650 3250
+Wire Wire Line
+	5650 3250 6000 3250
+Wire Wire Line
+	5900 2300 5900 2650
+Wire Wire Line
+	5900 2650 6000 2650
+Wire Wire Line
+	7150 2650 7650 2650
+Wire Wire Line
+	7150 3250 7350 3250
+Wire Wire Line
+	7350 3250 7350 3350
+Wire Wire Line
+	7350 3350 7450 3350
+Wire Wire Line
+	5250 3250 5400 3250
+Wire Wire Line
+	5400 3250 5400 3450
+Wire Wire Line
+	5400 3450 7450 3450
+Wire Wire Line
+	8350 3400 8450 3400
+Text Notes 3850 2500 0    60   ~ 0
+IN1
+Text Notes 3850 3150 0    60   ~ 0
+IN2
+Text Notes 6000 2350 0    60   ~ 0
+CIN
+Text Notes 7350 2550 0    60   ~ 0
+SUM
+Text Notes 8300 3200 0    60   ~ 0
+COUT
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_adder/full_adder.sub b/src/SubcircuitLibrary/full_adder/full_adder.sub
new file mode 100644
index 00000000..5f261f78
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder.sub
@@ -0,0 +1,13 @@
+* Subcircuit full_adder
+.subckt full_adder 8 7 5 4 1 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 12:24:33 2015
+.include half_adder.sub
+x1 8 7 6 2 half_adder
+x2 5 6 4 3 half_adder
+* u2  3 2 1 d_or
+a1 [3 2 ] 1 u2
+* Schematic Name: d_or, NgSpice Name: d_or
+.model u2 d_or(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends full_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml
new file mode 100644
index 00000000..b63184d6
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/full_adder_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_or<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/half_adder-cache.lib b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
new file mode 100644
index 00000000..68785220
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  150 -50  -200 -50 N
+P 2 0 1 0  150 150  -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir b/src/SubcircuitLibrary/full_adder/half_adder.cir
new file mode 100644
index 00000000..8b2e7e06
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2  1 4 3 d_xor		
+U3  1 4 2 d_and		
+U1  1 4 3 2 PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.cir.out b/src/SubcircuitLibrary/full_adder/half_adder.cir.out
new file mode 100644
index 00000000..b1b6b1e7
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder.cir.out
@@ -0,0 +1,20 @@
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+* u1  1 4 3 2 port
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.pro b/src/SubcircuitLibrary/full_adder/half_adder.pro
new file mode 100644
index 00000000..695ae0f6
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder.pro
@@ -0,0 +1,69 @@
+update=Wed Jun 24 11:27:22 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sch b/src/SubcircuitLibrary/full_adder/half_adder.sch
new file mode 100644
index 00000000..bf9bcbf0
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder.sch
@@ -0,0 +1,152 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U2
+U 1 1 558A946A
+P 5650 3050
+F 0 "U2" H 5650 3050 60  0000 C CNN
+F 1 "d_xor" H 5700 3150 47  0000 C CNN
+F 2 "" H 5650 3050 60  0000 C CNN
+F 3 "" H 5650 3050 60  0000 C CNN
+	1    5650 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 558A94D5
+P 5700 3800
+F 0 "U3" H 5700 3800 60  0000 C CNN
+F 1 "d_and" H 5750 3900 60  0000 C CNN
+F 2 "" H 5700 3800 60  0000 C CNN
+F 3 "" H 5700 3800 60  0000 C CNN
+	1    5700 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558A94F6
+P 4150 3000
+F 0 "U1" H 4200 3100 30  0000 C CNN
+F 1 "PORT" H 4150 3000 30  0000 C CNN
+F 2 "" H 4150 3000 60  0000 C CNN
+F 3 "" H 4150 3000 60  0000 C CNN
+	1    4150 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 558A9543
+P 4150 3450
+F 0 "U1" H 4200 3550 30  0000 C CNN
+F 1 "PORT" H 4150 3450 30  0000 C CNN
+F 2 "" H 4150 3450 60  0000 C CNN
+F 3 "" H 4150 3450 60  0000 C CNN
+	2    4150 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 558A9573
+P 6650 3000
+F 0 "U1" H 6700 3100 30  0000 C CNN
+F 1 "PORT" H 6650 3000 30  0000 C CNN
+F 2 "" H 6650 3000 60  0000 C CNN
+F 3 "" H 6650 3000 60  0000 C CNN
+	3    6650 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558A9606
+P 6700 3750
+F 0 "U1" H 6750 3850 30  0000 C CNN
+F 1 "PORT" H 6700 3750 30  0000 C CNN
+F 2 "" H 6700 3750 60  0000 C CNN
+F 3 "" H 6700 3750 60  0000 C CNN
+	4    6700 3750
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5200 2950 4450 2950
+Wire Wire Line
+	4450 2950 4450 3000
+Wire Wire Line
+	4450 3000 4400 3000
+Wire Wire Line
+	4400 3450 4550 3450
+Wire Wire Line
+	4550 3450 4550 3050
+Wire Wire Line
+	4550 3050 5200 3050
+Wire Wire Line
+	5250 3700 5000 3700
+Wire Wire Line
+	5000 3700 5000 2950
+Connection ~ 5000 2950
+Wire Wire Line
+	5250 3800 4850 3800
+Wire Wire Line
+	4850 3800 4850 3050
+Connection ~ 4850 3050
+Wire Wire Line
+	6100 3000 6400 3000
+Wire Wire Line
+	6150 3750 6450 3750
+Text Notes 4550 2950 0    60   ~ 0
+IN1\n\n
+Text Notes 4600 3150 0    60   ~ 0
+IN2
+Text Notes 6200 2950 0    60   ~ 0
+SUM\n
+Text Notes 6200 3650 0    60   ~ 0
+COUT\n
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/full_adder/half_adder.sub b/src/SubcircuitLibrary/full_adder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml
new file mode 100644
index 00000000..b915f0da
--- /dev/null
+++ b/src/SubcircuitLibrary/full_adder/half_adder_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/analysis b/src/SubcircuitLibrary/half_adder/analysis
new file mode 100644
index 00000000..52ccc5ec
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/analysis
@@ -0,0 +1 @@
+.ac lin 0 0Hz 0Hz
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/half_adder-cache.lib b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
new file mode 100644
index 00000000..68785220
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder-cache.lib
@@ -0,0 +1,63 @@
+EESchema-LIBRARY Version 2.3
+#encoding utf-8
+#
+# PORT
+#
+DEF PORT U 0 40 Y Y 8 F N
+F0 "U" 50 100 30 H V C CNN
+F1 "PORT" 0 0 30 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0
+A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50
+S -100 50 100 -50 0 1 0 N
+X ~ 1 250 0 100 L 30 30 1 1 B
+X ~ 2 250 0 100 L 30 30 2 1 B
+X ~ 3 250 0 100 L 30 30 3 1 B
+X ~ 4 250 0 100 L 30 30 4 1 B
+X ~ 5 250 0 100 L 30 30 5 1 B
+X ~ 6 250 0 100 L 30 30 6 1 B
+X ~ 7 250 0 100 L 30 30 7 1 B
+X ~ 8 250 0 100 L 30 30 8 1 B
+ENDDRAW
+ENDDEF
+#
+# d_and
+#
+DEF d_and U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_and" 50 100 60 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A 149 50 100 -894 0 0 1 0 N 150 -50 250 50
+A 150 49 100 6 900 0 1 0 N 250 50 150 150
+P 4 0 1 0  150 -50  -250 -50  -250 150  150 150 N
+X IN1 1 -450 100 200 R 50 50 1 1 I
+X IN2 2 -450 0 200 R 50 50 1 1 I
+X OUT 3 450 50 200 L 50 50 1 1 O
+ENDDRAW
+ENDDEF
+#
+# d_xor
+#
+DEF d_xor U 0 40 Y Y 1 F N
+F0 "U" 0 0 60 H V C CNN
+F1 "d_xor" 50 100 47 H V C CNN
+F2 "" 0 0 60 H V C CNN
+F3 "" 0 0 60 H V C CNN
+DRAW
+A -450 50 224 266 -266 0 1 0 N -250 150 -250 -50
+A -350 50 180 -337 337 0 1 0 N -200 -50 -200 150
+A -25 -124 325 574 323 0 1 0 N 150 150 250 50
+A 74 125 191 -665 -231 0 1 0 N 150 -50 250 50
+P 2 0 1 0  150 -50  -200 -50 N
+P 2 0 1 0  150 150  -200 150 N
+X IN1 1 -450 100 215 R 50 43 1 1 I
+X IN2 2 -450 0 215 R 50 43 1 1 I
+X OUT 3 450 50 200 L 50 39 1 1 O
+ENDDRAW
+ENDDEF
+#
+#End Library
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir b/src/SubcircuitLibrary/half_adder/half_adder.cir
new file mode 100644
index 00000000..8b2e7e06
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder.cir
@@ -0,0 +1,11 @@
+* EESchema Netlist Version 1.1 (Spice format) creation date: Wed Jun 24 11:31:48 2015
+
+* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N
+* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0
+
+*Sheet Name:/
+U2  1 4 3 d_xor		
+U3  1 4 2 d_and		
+U1  1 4 3 2 PORT		
+
+.end
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.cir.out b/src/SubcircuitLibrary/half_adder/half_adder.cir.out
new file mode 100644
index 00000000..b1b6b1e7
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder.cir.out
@@ -0,0 +1,20 @@
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+* u1  1 4 3 2 port
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 ) 
+.ac lin 0 0Hz 0Hz
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.pro b/src/SubcircuitLibrary/half_adder/half_adder.pro
new file mode 100644
index 00000000..695ae0f6
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder.pro
@@ -0,0 +1,69 @@
+update=Wed Jun 24 11:27:22 2015
+version=1
+last_client=eeschema
+[general]
+version=1
+RootSch=
+BoardNm=
+[pcbnew]
+version=1
+LastNetListRead=
+UseCmpFile=1
+PadDrill=0.600000000000
+PadDrillOvalY=0.600000000000
+PadSizeH=1.500000000000
+PadSizeV=1.500000000000
+PcbTextSizeV=1.500000000000
+PcbTextSizeH=1.500000000000
+PcbTextThickness=0.300000000000
+ModuleTextSizeV=1.000000000000
+ModuleTextSizeH=1.000000000000
+ModuleTextSizeThickness=0.150000000000
+SolderMaskClearance=0.000000000000
+SolderMaskMinWidth=0.000000000000
+DrawSegmentWidth=0.200000000000
+BoardOutlineThickness=0.100000000000
+ModuleOutlineThickness=0.150000000000
+[cvpcb]
+version=1
+NetIExt=net
+[eeschema]
+version=1
+LibDir=
+[eeschema/libraries]
+LibName1=power
+LibName2=device
+LibName3=transistors
+LibName4=conn
+LibName5=linear
+LibName6=regul
+LibName7=74xx
+LibName8=cmos4000
+LibName9=adc-dac
+LibName10=memory
+LibName11=xilinx
+LibName12=special
+LibName13=microcontrollers
+LibName14=dsp
+LibName15=microchip
+LibName16=analog_switches
+LibName17=motorola
+LibName18=texas
+LibName19=intel
+LibName20=audio
+LibName21=interface
+LibName22=digital-audio
+LibName23=philips
+LibName24=display
+LibName25=cypress
+LibName26=siliconi
+LibName27=opto
+LibName28=atmel
+LibName29=contrib
+LibName30=valves
+LibName31=/home/gaurav/Desktop/eSim Library/eSim_Analog
+LibName32=/home/gaurav/Desktop/eSim Library/eSim_Devices
+LibName33=/home/gaurav/Desktop/eSim Library/eSim_Digital
+LibName34=/home/gaurav/Desktop/eSim Library/eSim_Hybrid
+LibName35=/home/gaurav/Desktop/eSim Library/eSim_Sources
+LibName36=/home/gaurav/Desktop/eSim Library/eSim_Subckt
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sch b/src/SubcircuitLibrary/half_adder/half_adder.sch
new file mode 100644
index 00000000..bf9bcbf0
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder.sch
@@ -0,0 +1,152 @@
+EESchema Schematic File Version 2
+LIBS:power
+LIBS:device
+LIBS:transistors
+LIBS:conn
+LIBS:linear
+LIBS:regul
+LIBS:74xx
+LIBS:cmos4000
+LIBS:adc-dac
+LIBS:memory
+LIBS:xilinx
+LIBS:special
+LIBS:microcontrollers
+LIBS:dsp
+LIBS:microchip
+LIBS:analog_switches
+LIBS:motorola
+LIBS:texas
+LIBS:intel
+LIBS:audio
+LIBS:interface
+LIBS:digital-audio
+LIBS:philips
+LIBS:display
+LIBS:cypress
+LIBS:siliconi
+LIBS:opto
+LIBS:atmel
+LIBS:contrib
+LIBS:valves
+LIBS:eSim_Analog
+LIBS:eSim_Devices
+LIBS:eSim_Digital
+LIBS:eSim_Hybrid
+LIBS:eSim_Sources
+LIBS:eSim_Subckt
+EELAYER 25 0
+EELAYER END
+$Descr A4 11693 8268
+encoding utf-8
+Sheet 1 1
+Title ""
+Date ""
+Rev ""
+Comp ""
+Comment1 ""
+Comment2 ""
+Comment3 ""
+Comment4 ""
+$EndDescr
+$Comp
+L d_xor U2
+U 1 1 558A946A
+P 5650 3050
+F 0 "U2" H 5650 3050 60  0000 C CNN
+F 1 "d_xor" H 5700 3150 47  0000 C CNN
+F 2 "" H 5650 3050 60  0000 C CNN
+F 3 "" H 5650 3050 60  0000 C CNN
+	1    5650 3050
+	1    0    0    -1  
+$EndComp
+$Comp
+L d_and U3
+U 1 1 558A94D5
+P 5700 3800
+F 0 "U3" H 5700 3800 60  0000 C CNN
+F 1 "d_and" H 5750 3900 60  0000 C CNN
+F 2 "" H 5700 3800 60  0000 C CNN
+F 3 "" H 5700 3800 60  0000 C CNN
+	1    5700 3800
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 1 1 558A94F6
+P 4150 3000
+F 0 "U1" H 4200 3100 30  0000 C CNN
+F 1 "PORT" H 4150 3000 30  0000 C CNN
+F 2 "" H 4150 3000 60  0000 C CNN
+F 3 "" H 4150 3000 60  0000 C CNN
+	1    4150 3000
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 2 1 558A9543
+P 4150 3450
+F 0 "U1" H 4200 3550 30  0000 C CNN
+F 1 "PORT" H 4150 3450 30  0000 C CNN
+F 2 "" H 4150 3450 60  0000 C CNN
+F 3 "" H 4150 3450 60  0000 C CNN
+	2    4150 3450
+	1    0    0    -1  
+$EndComp
+$Comp
+L PORT U1
+U 3 1 558A9573
+P 6650 3000
+F 0 "U1" H 6700 3100 30  0000 C CNN
+F 1 "PORT" H 6650 3000 30  0000 C CNN
+F 2 "" H 6650 3000 60  0000 C CNN
+F 3 "" H 6650 3000 60  0000 C CNN
+	3    6650 3000
+	-1   0    0    1   
+$EndComp
+$Comp
+L PORT U1
+U 4 1 558A9606
+P 6700 3750
+F 0 "U1" H 6750 3850 30  0000 C CNN
+F 1 "PORT" H 6700 3750 30  0000 C CNN
+F 2 "" H 6700 3750 60  0000 C CNN
+F 3 "" H 6700 3750 60  0000 C CNN
+	4    6700 3750
+	-1   0    0    1   
+$EndComp
+Wire Wire Line
+	5200 2950 4450 2950
+Wire Wire Line
+	4450 2950 4450 3000
+Wire Wire Line
+	4450 3000 4400 3000
+Wire Wire Line
+	4400 3450 4550 3450
+Wire Wire Line
+	4550 3450 4550 3050
+Wire Wire Line
+	4550 3050 5200 3050
+Wire Wire Line
+	5250 3700 5000 3700
+Wire Wire Line
+	5000 3700 5000 2950
+Connection ~ 5000 2950
+Wire Wire Line
+	5250 3800 4850 3800
+Wire Wire Line
+	4850 3800 4850 3050
+Connection ~ 4850 3050
+Wire Wire Line
+	6100 3000 6400 3000
+Wire Wire Line
+	6150 3750 6450 3750
+Text Notes 4550 2950 0    60   ~ 0
+IN1\n\n
+Text Notes 4600 3150 0    60   ~ 0
+IN2
+Text Notes 6200 2950 0    60   ~ 0
+SUM\n
+Text Notes 6200 3650 0    60   ~ 0
+COUT\n
+$EndSCHEMATC
diff --git a/src/SubcircuitLibrary/half_adder/half_adder.sub b/src/SubcircuitLibrary/half_adder/half_adder.sub
new file mode 100644
index 00000000..e9f92223
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder.sub
@@ -0,0 +1,14 @@
+* Subcircuit half_adder
+.subckt half_adder 1 4 3 2 
+* eeschema netlist version 1.1 (spice format) creation date: wed jun 24 11:31:48 2015
+* u2  1 4 3 d_xor
+* u3  1 4 2 d_and
+a1 [1 4 ] 3 u2
+a2 [1 4 ] 2 u3
+* Schematic Name: d_xor, NgSpice Name: d_xor
+.model u2 d_xor(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Schematic Name: d_and, NgSpice Name: d_and
+.model u3 d_and(fall_delay=1.0e-9 input_load=1.0e-12 rise_delay=1.0e-9 )
+* Control Statements
+
+.ends half_adder
\ No newline at end of file
diff --git a/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml
new file mode 100644
index 00000000..b915f0da
--- /dev/null
+++ b/src/SubcircuitLibrary/half_adder/half_adder_Previous_Values.xml
@@ -0,0 +1 @@
+<KicadtoNgspice><analysis><ac><field1 name="Lin">true</field1><field2 name="Dec">false</field2><field3 name="Oct">false</field3><field4 name="Start Frequency" /><field5 name="Stop Frequency" /><field6 name="No. of points" /><field7 name="Start Fre Combo">Hz</field7><field8 name="Stop Fre Combo">Hz</field8></ac><dc><field1 name="Source Name" /><field2 name="Start" /><field3 name="Increment" /><field4 name="Stop" /><field5 name="Operating Point">False</field5><field6 name="Start Combo">Volts or Amperes</field6><field7 name="Increment Combo">Volts or Amperes</field7><field8 name="Stop Combo">Volts or Amperes</field8></dc><tran><field1 name="Start Time" /><field2 name="Step Time" /><field3 name="Stop Time" /><field4 name="Start Combo">Sec</field4><field5 name="Step Combo">Sec</field5><field6 name="Stop Combo">Sec</field6></tran></analysis><source /><model><u2 name="type">d_xor<field1 name="Enter Fall Delay (default=1.0e-9)" /><field2 name="Enter Input Load (default=1.0e-12)" /><field3 name="Enter Rise Delay (default=1.0e-9)" /></u2><u3 name="type">d_and<field4 name="Enter Fall Delay (default=1.0e-9)" /><field5 name="Enter Input Load (default=1.0e-12)" /><field6 name="Enter Rise Delay (default=1.0e-9)" /></u3></model><devicemodel /></KicadtoNgspice>
\ No newline at end of file