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authorFahim2015-12-30 12:20:39 +0530
committerFahim2015-12-30 12:20:39 +0530
commit5c21ac87792c7eee763afcd6df80fc0bb8524b6c (patch)
tree385a811388f218bc5ebd798a7b9bbbdfda537d1a /src/SubcircuitLibrary/triac/triac.sub~
parente4b74bcbaa07bfe96f808db4d9fe6e05c6cde87d (diff)
downloadeSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.gz
eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.tar.bz2
eSim-5c21ac87792c7eee763afcd6df80fc0bb8524b6c.zip
Added :
1. Power Examples 2. eSim_Power.lib 3. Subcircuit for diac, scr, triac 4. Device model for Power Diode
Diffstat (limited to 'src/SubcircuitLibrary/triac/triac.sub~')
-rw-r--r--src/SubcircuitLibrary/triac/triac.sub~35
1 files changed, 35 insertions, 0 deletions
diff --git a/src/SubcircuitLibrary/triac/triac.sub~ b/src/SubcircuitLibrary/triac/triac.sub~
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+* Subcircuit triac
+.subckt triac 8 11 10
+* /opt/esim/src/subcircuitlibrary/triac/triac.cir
+.include PowerDiode.lib
+* f3
+v3 7 2 dc 0
+* f2
+v2 6 3 dc 0
+c1 8 9 10u
+* f1
+v1 10 4 dc 0
+* u1 9 11 6 aswitch
+* u2 9 2 11 aswitch
+r1 8 9 1
+d1 5 8 PowerDiode
+d2 1 7 PowerDiode
+Vf3 1 8 0
+f3 8 9 Vf3 10
+Vf2 3 5 0
+f2 8 9 Vf2 10
+Vf1 4 8 0
+f1 8 9 Vf1 100
+a1 9 [11 6 ] u1
+a2 9 [2 11 ] u2
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u1 aswitch(log=TRUE cntl_off=0.1 cntl_on=1 r_on=0.0125 r_off=1000000 )
+* Schematic Name: aswitch, NgSpice Name: aswitch
+.model u2 aswitch(log=TRUE cntl_off=-0.1 cntl_on=-1 r_on=0.0125 r_off=1000000 )
+* Control Statements
+
+.ends triac \ No newline at end of file